2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/usb.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/slab.h>
18 #include <linux/omap-dma.h>
20 #include "musb_core.h"
23 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
25 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
27 #define OMAP24XX_DMA_EXT_DMAREQ0 2
28 #define OMAP24XX_DMA_EXT_DMAREQ1 3
29 #define OMAP242X_DMA_EXT_DMAREQ2 14
30 #define OMAP242X_DMA_EXT_DMAREQ3 15
31 #define OMAP242X_DMA_EXT_DMAREQ4 16
32 #define OMAP242X_DMA_EXT_DMAREQ5 64
34 struct tusb_omap_dma_ch
{
37 unsigned long phys_offset
;
40 struct musb_hw_ep
*hw_ep
;
46 struct tusb_omap_dma
*tusb_dma
;
52 u16 transfer_packet_sz
;
57 struct tusb_omap_dma
{
58 struct dma_controller controller
;
64 unsigned multichannel
:1;
68 * Allocate dmareq0 to the current channel unless it's already taken
70 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch
*chdat
)
72 u32 reg
= musb_readl(chdat
->tbase
, TUSB_DMA_EP_MAP
);
75 dev_dbg(chdat
->musb
->controller
, "ep%i dmareq0 is busy for ep%i\n",
76 chdat
->epnum
, reg
& 0xf);
81 reg
= (1 << 4) | chdat
->epnum
;
85 musb_writel(chdat
->tbase
, TUSB_DMA_EP_MAP
, reg
);
90 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch
*chdat
)
92 u32 reg
= musb_readl(chdat
->tbase
, TUSB_DMA_EP_MAP
);
94 if ((reg
& 0xf) != chdat
->epnum
) {
95 printk(KERN_ERR
"ep%i trying to release dmareq0 for ep%i\n",
96 chdat
->epnum
, reg
& 0xf);
99 musb_writel(chdat
->tbase
, TUSB_DMA_EP_MAP
, 0);
103 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
106 static void tusb_omap_dma_cb(int lch
, u16 ch_status
, void *data
)
108 struct dma_channel
*channel
= (struct dma_channel
*)data
;
109 struct tusb_omap_dma_ch
*chdat
= to_chdat(channel
);
110 struct tusb_omap_dma
*tusb_dma
= chdat
->tusb_dma
;
111 struct musb
*musb
= chdat
->musb
;
112 struct device
*dev
= musb
->controller
;
113 struct musb_hw_ep
*hw_ep
= chdat
->hw_ep
;
114 void __iomem
*ep_conf
= hw_ep
->conf
;
115 void __iomem
*mbase
= musb
->mregs
;
116 unsigned long remaining
, flags
, pio
;
119 spin_lock_irqsave(&musb
->lock
, flags
);
121 if (tusb_dma
->multichannel
)
126 if (ch_status
!= OMAP_DMA_BLOCK_IRQ
)
127 printk(KERN_ERR
"TUSB DMA error status: %i\n", ch_status
);
129 dev_dbg(musb
->controller
, "ep%i %s dma callback ch: %i status: %x\n",
130 chdat
->epnum
, chdat
->tx
? "tx" : "rx",
134 remaining
= musb_readl(ep_conf
, TUSB_EP_TX_OFFSET
);
136 remaining
= musb_readl(ep_conf
, TUSB_EP_RX_OFFSET
);
138 remaining
= TUSB_EP_CONFIG_XFR_SIZE(remaining
);
140 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
141 if (unlikely(remaining
> chdat
->transfer_len
)) {
142 dev_dbg(musb
->controller
, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
143 chdat
->tx
? "tx" : "rx", chdat
->ch
,
148 channel
->actual_len
= chdat
->transfer_len
- remaining
;
149 pio
= chdat
->len
- channel
->actual_len
;
151 dev_dbg(musb
->controller
, "DMA remaining %lu/%u\n", remaining
, chdat
->transfer_len
);
153 /* Transfer remaining 1 - 31 bytes */
154 if (pio
> 0 && pio
< 32) {
157 dev_dbg(musb
->controller
, "Using PIO for remaining %lu bytes\n", pio
);
158 buf
= phys_to_virt((u32
)chdat
->dma_addr
) + chdat
->transfer_len
;
160 dma_unmap_single(dev
, chdat
->dma_addr
,
163 musb_write_fifo(hw_ep
, pio
, buf
);
165 dma_unmap_single(dev
, chdat
->dma_addr
,
168 musb_read_fifo(hw_ep
, pio
, buf
);
170 channel
->actual_len
+= pio
;
173 if (!tusb_dma
->multichannel
)
174 tusb_omap_free_shared_dmareq(chdat
);
176 channel
->status
= MUSB_DMA_STATUS_FREE
;
178 /* Handle only RX callbacks here. TX callbacks must be handled based
179 * on the TUSB DMA status interrupt.
180 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
181 * interrupt for RX and TX.
184 musb_dma_completion(musb
, chdat
->epnum
, chdat
->tx
);
186 /* We must terminate short tx transfers manually by setting TXPKTRDY.
187 * REVISIT: This same problem may occur with other MUSB dma as well.
188 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
190 if ((chdat
->transfer_len
< chdat
->packet_sz
)
191 || (chdat
->transfer_len
% chdat
->packet_sz
!= 0)) {
195 dev_dbg(musb
->controller
, "terminating short tx packet\n");
196 musb_ep_select(mbase
, chdat
->epnum
);
197 csr
= musb_readw(hw_ep
->regs
, MUSB_TXCSR
);
198 csr
|= MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY
199 | MUSB_TXCSR_P_WZC_BITS
;
200 musb_writew(hw_ep
->regs
, MUSB_TXCSR
, csr
);
204 spin_unlock_irqrestore(&musb
->lock
, flags
);
207 static int tusb_omap_dma_program(struct dma_channel
*channel
, u16 packet_sz
,
208 u8 rndis_mode
, dma_addr_t dma_addr
, u32 len
)
210 struct tusb_omap_dma_ch
*chdat
= to_chdat(channel
);
211 struct tusb_omap_dma
*tusb_dma
= chdat
->tusb_dma
;
212 struct musb
*musb
= chdat
->musb
;
213 struct device
*dev
= musb
->controller
;
214 struct musb_hw_ep
*hw_ep
= chdat
->hw_ep
;
215 void __iomem
*mbase
= musb
->mregs
;
216 void __iomem
*ep_conf
= hw_ep
->conf
;
217 dma_addr_t fifo
= hw_ep
->fifo_sync
;
218 struct omap_dma_channel_params dma_params
;
220 int src_burst
, dst_burst
;
226 if (unlikely(dma_addr
& 0x1) || (len
< 32) || (len
> packet_sz
))
230 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
231 * register which will cause missed DMA interrupt. We could try to
232 * use a timer for the callback, but it is unsafe as the XFR_SIZE
233 * register is corrupt, and we won't know if the DMA worked.
239 * Because of HW issue #10, it seems like mixing sync DMA and async
240 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
241 * using the channel for DMA.
244 dma_remaining
= musb_readl(ep_conf
, TUSB_EP_TX_OFFSET
);
246 dma_remaining
= musb_readl(ep_conf
, TUSB_EP_RX_OFFSET
);
248 dma_remaining
= TUSB_EP_CONFIG_XFR_SIZE(dma_remaining
);
250 dev_dbg(musb
->controller
, "Busy %s dma ch%i, not using: %08x\n",
251 chdat
->tx
? "tx" : "rx", chdat
->ch
,
256 chdat
->transfer_len
= len
& ~0x1f;
259 chdat
->transfer_packet_sz
= chdat
->transfer_len
;
261 chdat
->transfer_packet_sz
= packet_sz
;
263 if (tusb_dma
->multichannel
) {
265 dmareq
= chdat
->dmareq
;
266 sync_dev
= chdat
->sync_dev
;
268 if (tusb_omap_use_shared_dmareq(chdat
) != 0) {
269 dev_dbg(musb
->controller
, "could not get dma for ep%i\n", chdat
->epnum
);
272 if (tusb_dma
->ch
< 0) {
273 /* REVISIT: This should get blocked earlier, happens
274 * with MSC ErrorRecoveryTest
281 dmareq
= tusb_dma
->dmareq
;
282 sync_dev
= tusb_dma
->sync_dev
;
283 omap_set_dma_callback(ch
, tusb_omap_dma_cb
, channel
);
286 chdat
->packet_sz
= packet_sz
;
288 channel
->actual_len
= 0;
289 chdat
->dma_addr
= dma_addr
;
290 channel
->status
= MUSB_DMA_STATUS_BUSY
;
292 /* Since we're recycling dma areas, we need to clean or invalidate */
294 dma_map_single(dev
, phys_to_virt(dma_addr
), len
,
297 dma_map_single(dev
, phys_to_virt(dma_addr
), len
,
300 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
301 if ((dma_addr
& 0x3) == 0) {
302 dma_params
.data_type
= OMAP_DMA_DATA_TYPE_S32
;
303 dma_params
.elem_count
= 8; /* Elements in frame */
305 dma_params
.data_type
= OMAP_DMA_DATA_TYPE_S16
;
306 dma_params
.elem_count
= 16; /* Elements in frame */
307 fifo
= hw_ep
->fifo_async
;
310 dma_params
.frame_count
= chdat
->transfer_len
/ 32; /* Burst sz frame */
312 dev_dbg(musb
->controller
, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
313 chdat
->epnum
, chdat
->tx
? "tx" : "rx",
314 ch
, &dma_addr
, chdat
->transfer_len
, len
,
315 chdat
->transfer_packet_sz
, packet_sz
);
318 * Prepare omap DMA for transfer
321 dma_params
.src_amode
= OMAP_DMA_AMODE_POST_INC
;
322 dma_params
.src_start
= (unsigned long)dma_addr
;
323 dma_params
.src_ei
= 0;
324 dma_params
.src_fi
= 0;
326 dma_params
.dst_amode
= OMAP_DMA_AMODE_DOUBLE_IDX
;
327 dma_params
.dst_start
= (unsigned long)fifo
;
328 dma_params
.dst_ei
= 1;
329 dma_params
.dst_fi
= -31; /* Loop 32 byte window */
331 dma_params
.trigger
= sync_dev
;
332 dma_params
.sync_mode
= OMAP_DMA_SYNC_FRAME
;
333 dma_params
.src_or_dst_synch
= 0; /* Dest sync */
335 src_burst
= OMAP_DMA_DATA_BURST_16
; /* 16x32 read */
336 dst_burst
= OMAP_DMA_DATA_BURST_8
; /* 8x32 write */
338 dma_params
.src_amode
= OMAP_DMA_AMODE_DOUBLE_IDX
;
339 dma_params
.src_start
= (unsigned long)fifo
;
340 dma_params
.src_ei
= 1;
341 dma_params
.src_fi
= -31; /* Loop 32 byte window */
343 dma_params
.dst_amode
= OMAP_DMA_AMODE_POST_INC
;
344 dma_params
.dst_start
= (unsigned long)dma_addr
;
345 dma_params
.dst_ei
= 0;
346 dma_params
.dst_fi
= 0;
348 dma_params
.trigger
= sync_dev
;
349 dma_params
.sync_mode
= OMAP_DMA_SYNC_FRAME
;
350 dma_params
.src_or_dst_synch
= 1; /* Source sync */
352 src_burst
= OMAP_DMA_DATA_BURST_8
; /* 8x32 read */
353 dst_burst
= OMAP_DMA_DATA_BURST_16
; /* 16x32 write */
356 dev_dbg(musb
->controller
, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
357 chdat
->epnum
, chdat
->tx
? "tx" : "rx",
358 (dma_params
.data_type
== OMAP_DMA_DATA_TYPE_S32
) ? 32 : 16,
359 ((dma_addr
& 0x3) == 0) ? "sync" : "async",
360 dma_params
.src_start
, dma_params
.dst_start
);
362 omap_set_dma_params(ch
, &dma_params
);
363 omap_set_dma_src_burst_mode(ch
, src_burst
);
364 omap_set_dma_dest_burst_mode(ch
, dst_burst
);
365 omap_set_dma_write_mode(ch
, OMAP_DMA_WRITE_LAST_NON_POSTED
);
368 * Prepare MUSB for DMA transfer
371 musb_ep_select(mbase
, chdat
->epnum
);
372 csr
= musb_readw(hw_ep
->regs
, MUSB_TXCSR
);
373 csr
|= (MUSB_TXCSR_AUTOSET
| MUSB_TXCSR_DMAENAB
374 | MUSB_TXCSR_DMAMODE
| MUSB_TXCSR_MODE
);
375 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
376 musb_writew(hw_ep
->regs
, MUSB_TXCSR
, csr
);
378 musb_ep_select(mbase
, chdat
->epnum
);
379 csr
= musb_readw(hw_ep
->regs
, MUSB_RXCSR
);
380 csr
|= MUSB_RXCSR_DMAENAB
;
381 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
| MUSB_RXCSR_DMAMODE
);
382 musb_writew(hw_ep
->regs
, MUSB_RXCSR
,
383 csr
| MUSB_RXCSR_P_WZC_BITS
);
392 /* Send transfer_packet_sz packets at a time */
393 musb_writel(ep_conf
, TUSB_EP_MAX_PACKET_SIZE_OFFSET
,
394 chdat
->transfer_packet_sz
);
396 musb_writel(ep_conf
, TUSB_EP_TX_OFFSET
,
397 TUSB_EP_CONFIG_XFR_SIZE(chdat
->transfer_len
));
399 /* Receive transfer_packet_sz packets at a time */
400 musb_writel(ep_conf
, TUSB_EP_MAX_PACKET_SIZE_OFFSET
,
401 chdat
->transfer_packet_sz
<< 16);
403 musb_writel(ep_conf
, TUSB_EP_RX_OFFSET
,
404 TUSB_EP_CONFIG_XFR_SIZE(chdat
->transfer_len
));
410 static int tusb_omap_dma_abort(struct dma_channel
*channel
)
412 struct tusb_omap_dma_ch
*chdat
= to_chdat(channel
);
413 struct tusb_omap_dma
*tusb_dma
= chdat
->tusb_dma
;
415 if (!tusb_dma
->multichannel
) {
416 if (tusb_dma
->ch
>= 0) {
417 omap_stop_dma(tusb_dma
->ch
);
418 omap_free_dma(tusb_dma
->ch
);
422 tusb_dma
->dmareq
= -1;
423 tusb_dma
->sync_dev
= -1;
426 channel
->status
= MUSB_DMA_STATUS_FREE
;
431 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch
*chdat
)
433 u32 reg
= musb_readl(chdat
->tbase
, TUSB_DMA_EP_MAP
);
434 int i
, dmareq_nr
= -1;
436 const int sync_dev
[6] = {
437 OMAP24XX_DMA_EXT_DMAREQ0
,
438 OMAP24XX_DMA_EXT_DMAREQ1
,
439 OMAP242X_DMA_EXT_DMAREQ2
,
440 OMAP242X_DMA_EXT_DMAREQ3
,
441 OMAP242X_DMA_EXT_DMAREQ4
,
442 OMAP242X_DMA_EXT_DMAREQ5
,
445 for (i
= 0; i
< MAX_DMAREQ
; i
++) {
446 int cur
= (reg
& (0xf << (i
* 5))) >> (i
* 5);
456 reg
|= (chdat
->epnum
<< (dmareq_nr
* 5));
458 reg
|= ((1 << 4) << (dmareq_nr
* 5));
459 musb_writel(chdat
->tbase
, TUSB_DMA_EP_MAP
, reg
);
461 chdat
->dmareq
= dmareq_nr
;
462 chdat
->sync_dev
= sync_dev
[chdat
->dmareq
];
467 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch
*chdat
)
471 if (!chdat
|| chdat
->dmareq
< 0)
474 reg
= musb_readl(chdat
->tbase
, TUSB_DMA_EP_MAP
);
475 reg
&= ~(0x1f << (chdat
->dmareq
* 5));
476 musb_writel(chdat
->tbase
, TUSB_DMA_EP_MAP
, reg
);
479 chdat
->sync_dev
= -1;
482 static struct dma_channel
*dma_channel_pool
[MAX_DMAREQ
];
484 static struct dma_channel
*
485 tusb_omap_dma_allocate(struct dma_controller
*c
,
486 struct musb_hw_ep
*hw_ep
,
490 const char *dev_name
;
491 struct tusb_omap_dma
*tusb_dma
;
494 struct dma_channel
*channel
= NULL
;
495 struct tusb_omap_dma_ch
*chdat
= NULL
;
498 tusb_dma
= container_of(c
, struct tusb_omap_dma
, controller
);
499 musb
= tusb_dma
->controller
.musb
;
500 tbase
= musb
->ctrl_base
;
502 reg
= musb_readl(tbase
, TUSB_DMA_INT_MASK
);
504 reg
&= ~(1 << hw_ep
->epnum
);
506 reg
&= ~(1 << (hw_ep
->epnum
+ 15));
507 musb_writel(tbase
, TUSB_DMA_INT_MASK
, reg
);
509 /* REVISIT: Why does dmareq5 not work? */
510 if (hw_ep
->epnum
== 0) {
511 dev_dbg(musb
->controller
, "Not allowing DMA for ep0 %s\n", tx
? "tx" : "rx");
515 for (i
= 0; i
< MAX_DMAREQ
; i
++) {
516 struct dma_channel
*ch
= dma_channel_pool
[i
];
517 if (ch
->status
== MUSB_DMA_STATUS_UNKNOWN
) {
518 ch
->status
= MUSB_DMA_STATUS_FREE
;
520 chdat
= ch
->private_data
;
530 dev_name
= "TUSB transmit";
533 dev_name
= "TUSB receive";
536 chdat
->musb
= tusb_dma
->controller
.musb
;
537 chdat
->tbase
= tusb_dma
->tbase
;
538 chdat
->hw_ep
= hw_ep
;
539 chdat
->epnum
= hw_ep
->epnum
;
541 chdat
->completed_len
= 0;
542 chdat
->tusb_dma
= tusb_dma
;
544 channel
->max_len
= 0x7fffffff;
545 channel
->desired_mode
= 0;
546 channel
->actual_len
= 0;
548 if (tusb_dma
->multichannel
) {
549 ret
= tusb_omap_dma_allocate_dmareq(chdat
);
553 ret
= omap_request_dma(chdat
->sync_dev
, dev_name
,
554 tusb_omap_dma_cb
, channel
, &chdat
->ch
);
557 } else if (tusb_dma
->ch
== -1) {
558 tusb_dma
->dmareq
= 0;
559 tusb_dma
->sync_dev
= OMAP24XX_DMA_EXT_DMAREQ0
;
561 /* Callback data gets set later in the shared dmareq case */
562 ret
= omap_request_dma(tusb_dma
->sync_dev
, "TUSB shared",
563 tusb_omap_dma_cb
, NULL
, &tusb_dma
->ch
);
571 dev_dbg(musb
->controller
, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
573 chdat
->tx
? "tx" : "rx",
574 chdat
->ch
>= 0 ? "dedicated" : "shared",
575 chdat
->ch
>= 0 ? chdat
->ch
: tusb_dma
->ch
,
576 chdat
->dmareq
>= 0 ? chdat
->dmareq
: tusb_dma
->dmareq
,
577 chdat
->sync_dev
>= 0 ? chdat
->sync_dev
: tusb_dma
->sync_dev
);
582 tusb_omap_dma_free_dmareq(chdat
);
584 dev_dbg(musb
->controller
, "ep%i: Could not get a DMA channel\n", chdat
->epnum
);
585 channel
->status
= MUSB_DMA_STATUS_UNKNOWN
;
590 static void tusb_omap_dma_release(struct dma_channel
*channel
)
592 struct tusb_omap_dma_ch
*chdat
= to_chdat(channel
);
593 struct musb
*musb
= chdat
->musb
;
594 void __iomem
*tbase
= musb
->ctrl_base
;
597 dev_dbg(musb
->controller
, "ep%i ch%i\n", chdat
->epnum
, chdat
->ch
);
599 reg
= musb_readl(tbase
, TUSB_DMA_INT_MASK
);
601 reg
|= (1 << chdat
->epnum
);
603 reg
|= (1 << (chdat
->epnum
+ 15));
604 musb_writel(tbase
, TUSB_DMA_INT_MASK
, reg
);
606 reg
= musb_readl(tbase
, TUSB_DMA_INT_CLEAR
);
608 reg
|= (1 << chdat
->epnum
);
610 reg
|= (1 << (chdat
->epnum
+ 15));
611 musb_writel(tbase
, TUSB_DMA_INT_CLEAR
, reg
);
613 channel
->status
= MUSB_DMA_STATUS_UNKNOWN
;
615 if (chdat
->ch
>= 0) {
616 omap_stop_dma(chdat
->ch
);
617 omap_free_dma(chdat
->ch
);
621 if (chdat
->dmareq
>= 0)
622 tusb_omap_dma_free_dmareq(chdat
);
627 void tusb_dma_controller_destroy(struct dma_controller
*c
)
629 struct tusb_omap_dma
*tusb_dma
;
632 tusb_dma
= container_of(c
, struct tusb_omap_dma
, controller
);
633 for (i
= 0; i
< MAX_DMAREQ
; i
++) {
634 struct dma_channel
*ch
= dma_channel_pool
[i
];
636 kfree(ch
->private_data
);
641 if (tusb_dma
&& !tusb_dma
->multichannel
&& tusb_dma
->ch
>= 0)
642 omap_free_dma(tusb_dma
->ch
);
646 EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy
);
648 struct dma_controller
*
649 tusb_dma_controller_create(struct musb
*musb
, void __iomem
*base
)
651 void __iomem
*tbase
= musb
->ctrl_base
;
652 struct tusb_omap_dma
*tusb_dma
;
655 /* REVISIT: Get dmareq lines used from board-*.c */
657 musb_writel(musb
->ctrl_base
, TUSB_DMA_INT_MASK
, 0x7fffffff);
658 musb_writel(musb
->ctrl_base
, TUSB_DMA_EP_MAP
, 0);
660 musb_writel(tbase
, TUSB_DMA_REQ_CONF
,
661 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
662 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
663 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
665 tusb_dma
= kzalloc(sizeof(struct tusb_omap_dma
), GFP_KERNEL
);
669 tusb_dma
->controller
.musb
= musb
;
670 tusb_dma
->tbase
= musb
->ctrl_base
;
673 tusb_dma
->dmareq
= -1;
674 tusb_dma
->sync_dev
= -1;
676 tusb_dma
->controller
.channel_alloc
= tusb_omap_dma_allocate
;
677 tusb_dma
->controller
.channel_release
= tusb_omap_dma_release
;
678 tusb_dma
->controller
.channel_program
= tusb_omap_dma_program
;
679 tusb_dma
->controller
.channel_abort
= tusb_omap_dma_abort
;
681 if (musb
->tusb_revision
>= TUSB_REV_30
)
682 tusb_dma
->multichannel
= 1;
684 for (i
= 0; i
< MAX_DMAREQ
; i
++) {
685 struct dma_channel
*ch
;
686 struct tusb_omap_dma_ch
*chdat
;
688 ch
= kzalloc(sizeof(struct dma_channel
), GFP_KERNEL
);
692 dma_channel_pool
[i
] = ch
;
694 chdat
= kzalloc(sizeof(struct tusb_omap_dma_ch
), GFP_KERNEL
);
698 ch
->status
= MUSB_DMA_STATUS_UNKNOWN
;
699 ch
->private_data
= chdat
;
702 return &tusb_dma
->controller
;
705 musb_dma_controller_destroy(&tusb_dma
->controller
);
709 EXPORT_SYMBOL_GPL(tusb_dma_controller_create
);