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[mirror_ubuntu-zesty-kernel.git] / drivers / usb / phy / phy-msm-usb.c
1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/usb.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/usb/msm_hsusb.h>
40 #include <linux/usb/msm_hsusb_hw.h>
41 #include <linux/regulator/consumer.h>
42
43 #define MSM_USB_BASE (motg->regs)
44 #define DRIVER_NAME "msm_otg"
45
46 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
47
48 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
49 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
50 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
51 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
52
53 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
54 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
55 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
56 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
57
58 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
59 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
60
61 static struct regulator *hsusb_3p3;
62 static struct regulator *hsusb_1p8;
63 static struct regulator *hsusb_vddcx;
64
65 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
66 {
67 int ret = 0;
68
69 if (init) {
70 hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX");
71 if (IS_ERR(hsusb_vddcx)) {
72 dev_err(motg->phy.dev, "unable to get hsusb vddcx\n");
73 return PTR_ERR(hsusb_vddcx);
74 }
75
76 ret = regulator_set_voltage(hsusb_vddcx,
77 USB_PHY_VDD_DIG_VOL_MIN,
78 USB_PHY_VDD_DIG_VOL_MAX);
79 if (ret) {
80 dev_err(motg->phy.dev, "unable to set the voltage "
81 "for hsusb vddcx\n");
82 regulator_put(hsusb_vddcx);
83 return ret;
84 }
85
86 ret = regulator_enable(hsusb_vddcx);
87 if (ret) {
88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
89 regulator_put(hsusb_vddcx);
90 }
91 } else {
92 ret = regulator_set_voltage(hsusb_vddcx, 0,
93 USB_PHY_VDD_DIG_VOL_MAX);
94 if (ret)
95 dev_err(motg->phy.dev, "unable to set the voltage "
96 "for hsusb vddcx\n");
97 ret = regulator_disable(hsusb_vddcx);
98 if (ret)
99 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
100
101 regulator_put(hsusb_vddcx);
102 }
103
104 return ret;
105 }
106
107 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
108 {
109 int rc = 0;
110
111 if (init) {
112 hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3");
113 if (IS_ERR(hsusb_3p3)) {
114 dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
115 return PTR_ERR(hsusb_3p3);
116 }
117
118 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
119 USB_PHY_3P3_VOL_MAX);
120 if (rc) {
121 dev_err(motg->phy.dev, "unable to set voltage level "
122 "for hsusb 3p3\n");
123 goto put_3p3;
124 }
125 rc = regulator_enable(hsusb_3p3);
126 if (rc) {
127 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
128 goto put_3p3;
129 }
130 hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8");
131 if (IS_ERR(hsusb_1p8)) {
132 dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
133 rc = PTR_ERR(hsusb_1p8);
134 goto disable_3p3;
135 }
136 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
137 USB_PHY_1P8_VOL_MAX);
138 if (rc) {
139 dev_err(motg->phy.dev, "unable to set voltage level "
140 "for hsusb 1p8\n");
141 goto put_1p8;
142 }
143 rc = regulator_enable(hsusb_1p8);
144 if (rc) {
145 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
146 goto put_1p8;
147 }
148
149 return 0;
150 }
151
152 regulator_disable(hsusb_1p8);
153 put_1p8:
154 regulator_put(hsusb_1p8);
155 disable_3p3:
156 regulator_disable(hsusb_3p3);
157 put_3p3:
158 regulator_put(hsusb_3p3);
159 return rc;
160 }
161
162 static int msm_hsusb_ldo_set_mode(int on)
163 {
164 int ret = 0;
165
166 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
167 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
168 return -ENODEV;
169 }
170
171 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
172 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
173 return -ENODEV;
174 }
175
176 if (on) {
177 ret = regulator_set_optimum_mode(hsusb_1p8,
178 USB_PHY_1P8_HPM_LOAD);
179 if (ret < 0) {
180 pr_err("%s: Unable to set HPM of the regulator "
181 "HSUSB_1p8\n", __func__);
182 return ret;
183 }
184 ret = regulator_set_optimum_mode(hsusb_3p3,
185 USB_PHY_3P3_HPM_LOAD);
186 if (ret < 0) {
187 pr_err("%s: Unable to set HPM of the regulator "
188 "HSUSB_3p3\n", __func__);
189 regulator_set_optimum_mode(hsusb_1p8,
190 USB_PHY_1P8_LPM_LOAD);
191 return ret;
192 }
193 } else {
194 ret = regulator_set_optimum_mode(hsusb_1p8,
195 USB_PHY_1P8_LPM_LOAD);
196 if (ret < 0)
197 pr_err("%s: Unable to set LPM of the regulator "
198 "HSUSB_1p8\n", __func__);
199 ret = regulator_set_optimum_mode(hsusb_3p3,
200 USB_PHY_3P3_LPM_LOAD);
201 if (ret < 0)
202 pr_err("%s: Unable to set LPM of the regulator "
203 "HSUSB_3p3\n", __func__);
204 }
205
206 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
207 return ret < 0 ? ret : 0;
208 }
209
210 static int ulpi_read(struct usb_phy *phy, u32 reg)
211 {
212 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
213 int cnt = 0;
214
215 /* initiate read operation */
216 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
217 USB_ULPI_VIEWPORT);
218
219 /* wait for completion */
220 while (cnt < ULPI_IO_TIMEOUT_USEC) {
221 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
222 break;
223 udelay(1);
224 cnt++;
225 }
226
227 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
228 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
229 readl(USB_ULPI_VIEWPORT));
230 return -ETIMEDOUT;
231 }
232 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
233 }
234
235 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
236 {
237 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
238 int cnt = 0;
239
240 /* initiate write operation */
241 writel(ULPI_RUN | ULPI_WRITE |
242 ULPI_ADDR(reg) | ULPI_DATA(val),
243 USB_ULPI_VIEWPORT);
244
245 /* wait for completion */
246 while (cnt < ULPI_IO_TIMEOUT_USEC) {
247 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
248 break;
249 udelay(1);
250 cnt++;
251 }
252
253 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
254 dev_err(phy->dev, "ulpi_write: timeout\n");
255 return -ETIMEDOUT;
256 }
257 return 0;
258 }
259
260 static struct usb_phy_io_ops msm_otg_io_ops = {
261 .read = ulpi_read,
262 .write = ulpi_write,
263 };
264
265 static void ulpi_init(struct msm_otg *motg)
266 {
267 struct msm_otg_platform_data *pdata = motg->pdata;
268 int *seq = pdata->phy_init_seq;
269
270 if (!seq)
271 return;
272
273 while (seq[0] >= 0) {
274 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
275 seq[0], seq[1]);
276 ulpi_write(&motg->phy, seq[0], seq[1]);
277 seq += 2;
278 }
279 }
280
281 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
282 {
283 int ret = 0;
284
285 if (!motg->pdata->link_clk_reset)
286 return ret;
287
288 ret = motg->pdata->link_clk_reset(motg->clk, assert);
289 if (ret)
290 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
291 assert ? "assert" : "deassert");
292
293 return ret;
294 }
295
296 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
297 {
298 int ret = 0;
299
300 if (!motg->pdata->phy_clk_reset)
301 return ret;
302
303 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
304 if (ret)
305 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
306
307 return ret;
308 }
309
310 static int msm_otg_phy_reset(struct msm_otg *motg)
311 {
312 u32 val;
313 int ret;
314 int retries;
315
316 ret = msm_otg_link_clk_reset(motg, 1);
317 if (ret)
318 return ret;
319 ret = msm_otg_phy_clk_reset(motg);
320 if (ret)
321 return ret;
322 ret = msm_otg_link_clk_reset(motg, 0);
323 if (ret)
324 return ret;
325
326 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
327 writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
328
329 for (retries = 3; retries > 0; retries--) {
330 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
331 ULPI_CLR(ULPI_FUNC_CTRL));
332 if (!ret)
333 break;
334 ret = msm_otg_phy_clk_reset(motg);
335 if (ret)
336 return ret;
337 }
338 if (!retries)
339 return -ETIMEDOUT;
340
341 /* This reset calibrates the phy, if the above write succeeded */
342 ret = msm_otg_phy_clk_reset(motg);
343 if (ret)
344 return ret;
345
346 for (retries = 3; retries > 0; retries--) {
347 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
348 if (ret != -ETIMEDOUT)
349 break;
350 ret = msm_otg_phy_clk_reset(motg);
351 if (ret)
352 return ret;
353 }
354 if (!retries)
355 return -ETIMEDOUT;
356
357 dev_info(motg->phy.dev, "phy_reset: success\n");
358 return 0;
359 }
360
361 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
362 static int msm_otg_reset(struct usb_phy *phy)
363 {
364 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
365 struct msm_otg_platform_data *pdata = motg->pdata;
366 int cnt = 0;
367 int ret;
368 u32 val = 0;
369 u32 ulpi_val = 0;
370
371 ret = msm_otg_phy_reset(motg);
372 if (ret) {
373 dev_err(phy->dev, "phy_reset failed\n");
374 return ret;
375 }
376
377 ulpi_init(motg);
378
379 writel(USBCMD_RESET, USB_USBCMD);
380 while (cnt < LINK_RESET_TIMEOUT_USEC) {
381 if (!(readl(USB_USBCMD) & USBCMD_RESET))
382 break;
383 udelay(1);
384 cnt++;
385 }
386 if (cnt >= LINK_RESET_TIMEOUT_USEC)
387 return -ETIMEDOUT;
388
389 /* select ULPI phy */
390 writel(0x80000000, USB_PORTSC);
391
392 msleep(100);
393
394 writel(0x0, USB_AHBBURST);
395 writel(0x00, USB_AHBMODE);
396
397 if (pdata->otg_control == OTG_PHY_CONTROL) {
398 val = readl(USB_OTGSC);
399 if (pdata->mode == USB_OTG) {
400 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
401 val |= OTGSC_IDIE | OTGSC_BSVIE;
402 } else if (pdata->mode == USB_PERIPHERAL) {
403 ulpi_val = ULPI_INT_SESS_VALID;
404 val |= OTGSC_BSVIE;
405 }
406 writel(val, USB_OTGSC);
407 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
408 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
409 }
410
411 return 0;
412 }
413
414 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
415 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
416
417 #ifdef CONFIG_PM
418
419 #define USB_PHY_SUSP_DIG_VOL 500000
420 static int msm_hsusb_config_vddcx(int high)
421 {
422 int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
423 int min_vol;
424 int ret;
425
426 if (high)
427 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
428 else
429 min_vol = USB_PHY_SUSP_DIG_VOL;
430
431 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
432 if (ret) {
433 pr_err("%s: unable to set the voltage for regulator "
434 "HSUSB_VDDCX\n", __func__);
435 return ret;
436 }
437
438 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
439
440 return ret;
441 }
442
443 static int msm_otg_suspend(struct msm_otg *motg)
444 {
445 struct usb_phy *phy = &motg->phy;
446 struct usb_bus *bus = phy->otg->host;
447 struct msm_otg_platform_data *pdata = motg->pdata;
448 int cnt = 0;
449
450 if (atomic_read(&motg->in_lpm))
451 return 0;
452
453 disable_irq(motg->irq);
454 /*
455 * Chipidea 45-nm PHY suspend sequence:
456 *
457 * Interrupt Latch Register auto-clear feature is not present
458 * in all PHY versions. Latch register is clear on read type.
459 * Clear latch register to avoid spurious wakeup from
460 * low power mode (LPM).
461 *
462 * PHY comparators are disabled when PHY enters into low power
463 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
464 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
465 * PHY comparators. This save significant amount of power.
466 *
467 * PLL is not turned off when PHY enters into low power mode (LPM).
468 * Disable PLL for maximum power savings.
469 */
470
471 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
472 ulpi_read(phy, 0x14);
473 if (pdata->otg_control == OTG_PHY_CONTROL)
474 ulpi_write(phy, 0x01, 0x30);
475 ulpi_write(phy, 0x08, 0x09);
476 }
477
478 /*
479 * PHY may take some time or even fail to enter into low power
480 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
481 * in failure case.
482 */
483 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
484 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
485 if (readl(USB_PORTSC) & PORTSC_PHCD)
486 break;
487 udelay(1);
488 cnt++;
489 }
490
491 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
492 dev_err(phy->dev, "Unable to suspend PHY\n");
493 msm_otg_reset(phy);
494 enable_irq(motg->irq);
495 return -ETIMEDOUT;
496 }
497
498 /*
499 * PHY has capability to generate interrupt asynchronously in low
500 * power mode (LPM). This interrupt is level triggered. So USB IRQ
501 * line must be disabled till async interrupt enable bit is cleared
502 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
503 * block data communication from PHY.
504 */
505 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
506
507 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
508 motg->pdata->otg_control == OTG_PMIC_CONTROL)
509 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
510
511 clk_disable_unprepare(motg->pclk);
512 clk_disable_unprepare(motg->clk);
513 if (motg->core_clk)
514 clk_disable_unprepare(motg->core_clk);
515
516 if (!IS_ERR(motg->pclk_src))
517 clk_disable_unprepare(motg->pclk_src);
518
519 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
520 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
521 msm_hsusb_ldo_set_mode(0);
522 msm_hsusb_config_vddcx(0);
523 }
524
525 if (device_may_wakeup(phy->dev))
526 enable_irq_wake(motg->irq);
527 if (bus)
528 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
529
530 atomic_set(&motg->in_lpm, 1);
531 enable_irq(motg->irq);
532
533 dev_info(phy->dev, "USB in low power mode\n");
534
535 return 0;
536 }
537
538 static int msm_otg_resume(struct msm_otg *motg)
539 {
540 struct usb_phy *phy = &motg->phy;
541 struct usb_bus *bus = phy->otg->host;
542 int cnt = 0;
543 unsigned temp;
544
545 if (!atomic_read(&motg->in_lpm))
546 return 0;
547
548 if (!IS_ERR(motg->pclk_src))
549 clk_prepare_enable(motg->pclk_src);
550
551 clk_prepare_enable(motg->pclk);
552 clk_prepare_enable(motg->clk);
553 if (motg->core_clk)
554 clk_prepare_enable(motg->core_clk);
555
556 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
557 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
558 msm_hsusb_ldo_set_mode(1);
559 msm_hsusb_config_vddcx(1);
560 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
561 }
562
563 temp = readl(USB_USBCMD);
564 temp &= ~ASYNC_INTR_CTRL;
565 temp &= ~ULPI_STP_CTRL;
566 writel(temp, USB_USBCMD);
567
568 /*
569 * PHY comes out of low power mode (LPM) in case of wakeup
570 * from asynchronous interrupt.
571 */
572 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
573 goto skip_phy_resume;
574
575 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
576 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
577 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
578 break;
579 udelay(1);
580 cnt++;
581 }
582
583 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
584 /*
585 * This is a fatal error. Reset the link and
586 * PHY. USB state can not be restored. Re-insertion
587 * of USB cable is the only way to get USB working.
588 */
589 dev_err(phy->dev, "Unable to resume USB."
590 "Re-plugin the cable\n");
591 msm_otg_reset(phy);
592 }
593
594 skip_phy_resume:
595 if (device_may_wakeup(phy->dev))
596 disable_irq_wake(motg->irq);
597 if (bus)
598 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
599
600 atomic_set(&motg->in_lpm, 0);
601
602 if (motg->async_int) {
603 motg->async_int = 0;
604 pm_runtime_put(phy->dev);
605 enable_irq(motg->irq);
606 }
607
608 dev_info(phy->dev, "USB exited from low power mode\n");
609
610 return 0;
611 }
612 #endif
613
614 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
615 {
616 if (motg->cur_power == mA)
617 return;
618
619 /* TODO: Notify PMIC about available current */
620 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
621 motg->cur_power = mA;
622 }
623
624 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
625 {
626 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
627
628 /*
629 * Gadget driver uses set_power method to notify about the
630 * available current based on suspend/configured states.
631 *
632 * IDEV_CHG can be drawn irrespective of suspend/un-configured
633 * states when CDP/ACA is connected.
634 */
635 if (motg->chg_type == USB_SDP_CHARGER)
636 msm_otg_notify_charger(motg, mA);
637
638 return 0;
639 }
640
641 static void msm_otg_start_host(struct usb_phy *phy, int on)
642 {
643 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
644 struct msm_otg_platform_data *pdata = motg->pdata;
645 struct usb_hcd *hcd;
646
647 if (!phy->otg->host)
648 return;
649
650 hcd = bus_to_hcd(phy->otg->host);
651
652 if (on) {
653 dev_dbg(phy->dev, "host on\n");
654
655 if (pdata->vbus_power)
656 pdata->vbus_power(1);
657 /*
658 * Some boards have a switch cotrolled by gpio
659 * to enable/disable internal HUB. Enable internal
660 * HUB before kicking the host.
661 */
662 if (pdata->setup_gpio)
663 pdata->setup_gpio(OTG_STATE_A_HOST);
664 #ifdef CONFIG_USB
665 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
666 device_wakeup_enable(hcd->self.controller);
667 #endif
668 } else {
669 dev_dbg(phy->dev, "host off\n");
670
671 #ifdef CONFIG_USB
672 usb_remove_hcd(hcd);
673 #endif
674 if (pdata->setup_gpio)
675 pdata->setup_gpio(OTG_STATE_UNDEFINED);
676 if (pdata->vbus_power)
677 pdata->vbus_power(0);
678 }
679 }
680
681 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
682 {
683 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
684 struct usb_hcd *hcd;
685
686 /*
687 * Fail host registration if this board can support
688 * only peripheral configuration.
689 */
690 if (motg->pdata->mode == USB_PERIPHERAL) {
691 dev_info(otg->phy->dev, "Host mode is not supported\n");
692 return -ENODEV;
693 }
694
695 if (!host) {
696 if (otg->phy->state == OTG_STATE_A_HOST) {
697 pm_runtime_get_sync(otg->phy->dev);
698 msm_otg_start_host(otg->phy, 0);
699 otg->host = NULL;
700 otg->phy->state = OTG_STATE_UNDEFINED;
701 schedule_work(&motg->sm_work);
702 } else {
703 otg->host = NULL;
704 }
705
706 return 0;
707 }
708
709 hcd = bus_to_hcd(host);
710 hcd->power_budget = motg->pdata->power_budget;
711
712 otg->host = host;
713 dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
714
715 /*
716 * Kick the state machine work, if peripheral is not supported
717 * or peripheral is already registered with us.
718 */
719 if (motg->pdata->mode == USB_HOST || otg->gadget) {
720 pm_runtime_get_sync(otg->phy->dev);
721 schedule_work(&motg->sm_work);
722 }
723
724 return 0;
725 }
726
727 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
728 {
729 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
730 struct msm_otg_platform_data *pdata = motg->pdata;
731
732 if (!phy->otg->gadget)
733 return;
734
735 if (on) {
736 dev_dbg(phy->dev, "gadget on\n");
737 /*
738 * Some boards have a switch cotrolled by gpio
739 * to enable/disable internal HUB. Disable internal
740 * HUB before kicking the gadget.
741 */
742 if (pdata->setup_gpio)
743 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
744 usb_gadget_vbus_connect(phy->otg->gadget);
745 } else {
746 dev_dbg(phy->dev, "gadget off\n");
747 usb_gadget_vbus_disconnect(phy->otg->gadget);
748 if (pdata->setup_gpio)
749 pdata->setup_gpio(OTG_STATE_UNDEFINED);
750 }
751
752 }
753
754 static int msm_otg_set_peripheral(struct usb_otg *otg,
755 struct usb_gadget *gadget)
756 {
757 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
758
759 /*
760 * Fail peripheral registration if this board can support
761 * only host configuration.
762 */
763 if (motg->pdata->mode == USB_HOST) {
764 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
765 return -ENODEV;
766 }
767
768 if (!gadget) {
769 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
770 pm_runtime_get_sync(otg->phy->dev);
771 msm_otg_start_peripheral(otg->phy, 0);
772 otg->gadget = NULL;
773 otg->phy->state = OTG_STATE_UNDEFINED;
774 schedule_work(&motg->sm_work);
775 } else {
776 otg->gadget = NULL;
777 }
778
779 return 0;
780 }
781 otg->gadget = gadget;
782 dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
783
784 /*
785 * Kick the state machine work, if host is not supported
786 * or host is already registered with us.
787 */
788 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
789 pm_runtime_get_sync(otg->phy->dev);
790 schedule_work(&motg->sm_work);
791 }
792
793 return 0;
794 }
795
796 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
797 {
798 struct usb_phy *phy = &motg->phy;
799 u32 chg_det;
800 bool ret = false;
801
802 switch (motg->pdata->phy_type) {
803 case CI_45NM_INTEGRATED_PHY:
804 chg_det = ulpi_read(phy, 0x34);
805 ret = chg_det & (1 << 4);
806 break;
807 case SNPS_28NM_INTEGRATED_PHY:
808 chg_det = ulpi_read(phy, 0x87);
809 ret = chg_det & 1;
810 break;
811 default:
812 break;
813 }
814 return ret;
815 }
816
817 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
818 {
819 struct usb_phy *phy = &motg->phy;
820 u32 chg_det;
821
822 switch (motg->pdata->phy_type) {
823 case CI_45NM_INTEGRATED_PHY:
824 chg_det = ulpi_read(phy, 0x34);
825 /* Turn off charger block */
826 chg_det |= ~(1 << 1);
827 ulpi_write(phy, chg_det, 0x34);
828 udelay(20);
829 /* control chg block via ULPI */
830 chg_det &= ~(1 << 3);
831 ulpi_write(phy, chg_det, 0x34);
832 /* put it in host mode for enabling D- source */
833 chg_det &= ~(1 << 2);
834 ulpi_write(phy, chg_det, 0x34);
835 /* Turn on chg detect block */
836 chg_det &= ~(1 << 1);
837 ulpi_write(phy, chg_det, 0x34);
838 udelay(20);
839 /* enable chg detection */
840 chg_det &= ~(1 << 0);
841 ulpi_write(phy, chg_det, 0x34);
842 break;
843 case SNPS_28NM_INTEGRATED_PHY:
844 /*
845 * Configure DM as current source, DP as current sink
846 * and enable battery charging comparators.
847 */
848 ulpi_write(phy, 0x8, 0x85);
849 ulpi_write(phy, 0x2, 0x85);
850 ulpi_write(phy, 0x1, 0x85);
851 break;
852 default:
853 break;
854 }
855 }
856
857 static bool msm_chg_check_primary_det(struct msm_otg *motg)
858 {
859 struct usb_phy *phy = &motg->phy;
860 u32 chg_det;
861 bool ret = false;
862
863 switch (motg->pdata->phy_type) {
864 case CI_45NM_INTEGRATED_PHY:
865 chg_det = ulpi_read(phy, 0x34);
866 ret = chg_det & (1 << 4);
867 break;
868 case SNPS_28NM_INTEGRATED_PHY:
869 chg_det = ulpi_read(phy, 0x87);
870 ret = chg_det & 1;
871 break;
872 default:
873 break;
874 }
875 return ret;
876 }
877
878 static void msm_chg_enable_primary_det(struct msm_otg *motg)
879 {
880 struct usb_phy *phy = &motg->phy;
881 u32 chg_det;
882
883 switch (motg->pdata->phy_type) {
884 case CI_45NM_INTEGRATED_PHY:
885 chg_det = ulpi_read(phy, 0x34);
886 /* enable chg detection */
887 chg_det &= ~(1 << 0);
888 ulpi_write(phy, chg_det, 0x34);
889 break;
890 case SNPS_28NM_INTEGRATED_PHY:
891 /*
892 * Configure DP as current source, DM as current sink
893 * and enable battery charging comparators.
894 */
895 ulpi_write(phy, 0x2, 0x85);
896 ulpi_write(phy, 0x1, 0x85);
897 break;
898 default:
899 break;
900 }
901 }
902
903 static bool msm_chg_check_dcd(struct msm_otg *motg)
904 {
905 struct usb_phy *phy = &motg->phy;
906 u32 line_state;
907 bool ret = false;
908
909 switch (motg->pdata->phy_type) {
910 case CI_45NM_INTEGRATED_PHY:
911 line_state = ulpi_read(phy, 0x15);
912 ret = !(line_state & 1);
913 break;
914 case SNPS_28NM_INTEGRATED_PHY:
915 line_state = ulpi_read(phy, 0x87);
916 ret = line_state & 2;
917 break;
918 default:
919 break;
920 }
921 return ret;
922 }
923
924 static void msm_chg_disable_dcd(struct msm_otg *motg)
925 {
926 struct usb_phy *phy = &motg->phy;
927 u32 chg_det;
928
929 switch (motg->pdata->phy_type) {
930 case CI_45NM_INTEGRATED_PHY:
931 chg_det = ulpi_read(phy, 0x34);
932 chg_det &= ~(1 << 5);
933 ulpi_write(phy, chg_det, 0x34);
934 break;
935 case SNPS_28NM_INTEGRATED_PHY:
936 ulpi_write(phy, 0x10, 0x86);
937 break;
938 default:
939 break;
940 }
941 }
942
943 static void msm_chg_enable_dcd(struct msm_otg *motg)
944 {
945 struct usb_phy *phy = &motg->phy;
946 u32 chg_det;
947
948 switch (motg->pdata->phy_type) {
949 case CI_45NM_INTEGRATED_PHY:
950 chg_det = ulpi_read(phy, 0x34);
951 /* Turn on D+ current source */
952 chg_det |= (1 << 5);
953 ulpi_write(phy, chg_det, 0x34);
954 break;
955 case SNPS_28NM_INTEGRATED_PHY:
956 /* Data contact detection enable */
957 ulpi_write(phy, 0x10, 0x85);
958 break;
959 default:
960 break;
961 }
962 }
963
964 static void msm_chg_block_on(struct msm_otg *motg)
965 {
966 struct usb_phy *phy = &motg->phy;
967 u32 func_ctrl, chg_det;
968
969 /* put the controller in non-driving mode */
970 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
971 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
972 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
973 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
974
975 switch (motg->pdata->phy_type) {
976 case CI_45NM_INTEGRATED_PHY:
977 chg_det = ulpi_read(phy, 0x34);
978 /* control chg block via ULPI */
979 chg_det &= ~(1 << 3);
980 ulpi_write(phy, chg_det, 0x34);
981 /* Turn on chg detect block */
982 chg_det &= ~(1 << 1);
983 ulpi_write(phy, chg_det, 0x34);
984 udelay(20);
985 break;
986 case SNPS_28NM_INTEGRATED_PHY:
987 /* Clear charger detecting control bits */
988 ulpi_write(phy, 0x3F, 0x86);
989 /* Clear alt interrupt latch and enable bits */
990 ulpi_write(phy, 0x1F, 0x92);
991 ulpi_write(phy, 0x1F, 0x95);
992 udelay(100);
993 break;
994 default:
995 break;
996 }
997 }
998
999 static void msm_chg_block_off(struct msm_otg *motg)
1000 {
1001 struct usb_phy *phy = &motg->phy;
1002 u32 func_ctrl, chg_det;
1003
1004 switch (motg->pdata->phy_type) {
1005 case CI_45NM_INTEGRATED_PHY:
1006 chg_det = ulpi_read(phy, 0x34);
1007 /* Turn off charger block */
1008 chg_det |= ~(1 << 1);
1009 ulpi_write(phy, chg_det, 0x34);
1010 break;
1011 case SNPS_28NM_INTEGRATED_PHY:
1012 /* Clear charger detecting control bits */
1013 ulpi_write(phy, 0x3F, 0x86);
1014 /* Clear alt interrupt latch and enable bits */
1015 ulpi_write(phy, 0x1F, 0x92);
1016 ulpi_write(phy, 0x1F, 0x95);
1017 break;
1018 default:
1019 break;
1020 }
1021
1022 /* put the controller in normal mode */
1023 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1024 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1025 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1026 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1027 }
1028
1029 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1030 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1031 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1032 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1033 static void msm_chg_detect_work(struct work_struct *w)
1034 {
1035 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1036 struct usb_phy *phy = &motg->phy;
1037 bool is_dcd, tmout, vout;
1038 unsigned long delay;
1039
1040 dev_dbg(phy->dev, "chg detection work\n");
1041 switch (motg->chg_state) {
1042 case USB_CHG_STATE_UNDEFINED:
1043 pm_runtime_get_sync(phy->dev);
1044 msm_chg_block_on(motg);
1045 msm_chg_enable_dcd(motg);
1046 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1047 motg->dcd_retries = 0;
1048 delay = MSM_CHG_DCD_POLL_TIME;
1049 break;
1050 case USB_CHG_STATE_WAIT_FOR_DCD:
1051 is_dcd = msm_chg_check_dcd(motg);
1052 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1053 if (is_dcd || tmout) {
1054 msm_chg_disable_dcd(motg);
1055 msm_chg_enable_primary_det(motg);
1056 delay = MSM_CHG_PRIMARY_DET_TIME;
1057 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1058 } else {
1059 delay = MSM_CHG_DCD_POLL_TIME;
1060 }
1061 break;
1062 case USB_CHG_STATE_DCD_DONE:
1063 vout = msm_chg_check_primary_det(motg);
1064 if (vout) {
1065 msm_chg_enable_secondary_det(motg);
1066 delay = MSM_CHG_SECONDARY_DET_TIME;
1067 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1068 } else {
1069 motg->chg_type = USB_SDP_CHARGER;
1070 motg->chg_state = USB_CHG_STATE_DETECTED;
1071 delay = 0;
1072 }
1073 break;
1074 case USB_CHG_STATE_PRIMARY_DONE:
1075 vout = msm_chg_check_secondary_det(motg);
1076 if (vout)
1077 motg->chg_type = USB_DCP_CHARGER;
1078 else
1079 motg->chg_type = USB_CDP_CHARGER;
1080 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1081 /* fall through */
1082 case USB_CHG_STATE_SECONDARY_DONE:
1083 motg->chg_state = USB_CHG_STATE_DETECTED;
1084 case USB_CHG_STATE_DETECTED:
1085 msm_chg_block_off(motg);
1086 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1087 schedule_work(&motg->sm_work);
1088 return;
1089 default:
1090 return;
1091 }
1092
1093 schedule_delayed_work(&motg->chg_work, delay);
1094 }
1095
1096 /*
1097 * We support OTG, Peripheral only and Host only configurations. In case
1098 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1099 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1100 * enabled when switch is controlled by user and default mode is supplied
1101 * by board file, which can be changed by userspace later.
1102 */
1103 static void msm_otg_init_sm(struct msm_otg *motg)
1104 {
1105 struct msm_otg_platform_data *pdata = motg->pdata;
1106 u32 otgsc = readl(USB_OTGSC);
1107
1108 switch (pdata->mode) {
1109 case USB_OTG:
1110 if (pdata->otg_control == OTG_PHY_CONTROL) {
1111 if (otgsc & OTGSC_ID)
1112 set_bit(ID, &motg->inputs);
1113 else
1114 clear_bit(ID, &motg->inputs);
1115
1116 if (otgsc & OTGSC_BSV)
1117 set_bit(B_SESS_VLD, &motg->inputs);
1118 else
1119 clear_bit(B_SESS_VLD, &motg->inputs);
1120 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1121 if (pdata->default_mode == USB_HOST) {
1122 clear_bit(ID, &motg->inputs);
1123 } else if (pdata->default_mode == USB_PERIPHERAL) {
1124 set_bit(ID, &motg->inputs);
1125 set_bit(B_SESS_VLD, &motg->inputs);
1126 } else {
1127 set_bit(ID, &motg->inputs);
1128 clear_bit(B_SESS_VLD, &motg->inputs);
1129 }
1130 }
1131 break;
1132 case USB_HOST:
1133 clear_bit(ID, &motg->inputs);
1134 break;
1135 case USB_PERIPHERAL:
1136 set_bit(ID, &motg->inputs);
1137 if (otgsc & OTGSC_BSV)
1138 set_bit(B_SESS_VLD, &motg->inputs);
1139 else
1140 clear_bit(B_SESS_VLD, &motg->inputs);
1141 break;
1142 default:
1143 break;
1144 }
1145 }
1146
1147 static void msm_otg_sm_work(struct work_struct *w)
1148 {
1149 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1150 struct usb_otg *otg = motg->phy.otg;
1151
1152 switch (otg->phy->state) {
1153 case OTG_STATE_UNDEFINED:
1154 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1155 msm_otg_reset(otg->phy);
1156 msm_otg_init_sm(motg);
1157 otg->phy->state = OTG_STATE_B_IDLE;
1158 /* FALL THROUGH */
1159 case OTG_STATE_B_IDLE:
1160 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1161 if (!test_bit(ID, &motg->inputs) && otg->host) {
1162 /* disable BSV bit */
1163 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1164 msm_otg_start_host(otg->phy, 1);
1165 otg->phy->state = OTG_STATE_A_HOST;
1166 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1167 switch (motg->chg_state) {
1168 case USB_CHG_STATE_UNDEFINED:
1169 msm_chg_detect_work(&motg->chg_work.work);
1170 break;
1171 case USB_CHG_STATE_DETECTED:
1172 switch (motg->chg_type) {
1173 case USB_DCP_CHARGER:
1174 msm_otg_notify_charger(motg,
1175 IDEV_CHG_MAX);
1176 break;
1177 case USB_CDP_CHARGER:
1178 msm_otg_notify_charger(motg,
1179 IDEV_CHG_MAX);
1180 msm_otg_start_peripheral(otg->phy, 1);
1181 otg->phy->state
1182 = OTG_STATE_B_PERIPHERAL;
1183 break;
1184 case USB_SDP_CHARGER:
1185 msm_otg_notify_charger(motg, IUNIT);
1186 msm_otg_start_peripheral(otg->phy, 1);
1187 otg->phy->state
1188 = OTG_STATE_B_PERIPHERAL;
1189 break;
1190 default:
1191 break;
1192 }
1193 break;
1194 default:
1195 break;
1196 }
1197 } else {
1198 /*
1199 * If charger detection work is pending, decrement
1200 * the pm usage counter to balance with the one that
1201 * is incremented in charger detection work.
1202 */
1203 if (cancel_delayed_work_sync(&motg->chg_work)) {
1204 pm_runtime_put_sync(otg->phy->dev);
1205 msm_otg_reset(otg->phy);
1206 }
1207 msm_otg_notify_charger(motg, 0);
1208 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1209 motg->chg_type = USB_INVALID_CHARGER;
1210 }
1211 pm_runtime_put_sync(otg->phy->dev);
1212 break;
1213 case OTG_STATE_B_PERIPHERAL:
1214 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1215 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1216 !test_bit(ID, &motg->inputs)) {
1217 msm_otg_notify_charger(motg, 0);
1218 msm_otg_start_peripheral(otg->phy, 0);
1219 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1220 motg->chg_type = USB_INVALID_CHARGER;
1221 otg->phy->state = OTG_STATE_B_IDLE;
1222 msm_otg_reset(otg->phy);
1223 schedule_work(w);
1224 }
1225 break;
1226 case OTG_STATE_A_HOST:
1227 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1228 if (test_bit(ID, &motg->inputs)) {
1229 msm_otg_start_host(otg->phy, 0);
1230 otg->phy->state = OTG_STATE_B_IDLE;
1231 msm_otg_reset(otg->phy);
1232 schedule_work(w);
1233 }
1234 break;
1235 default:
1236 break;
1237 }
1238 }
1239
1240 static irqreturn_t msm_otg_irq(int irq, void *data)
1241 {
1242 struct msm_otg *motg = data;
1243 struct usb_phy *phy = &motg->phy;
1244 u32 otgsc = 0;
1245
1246 if (atomic_read(&motg->in_lpm)) {
1247 disable_irq_nosync(irq);
1248 motg->async_int = 1;
1249 pm_runtime_get(phy->dev);
1250 return IRQ_HANDLED;
1251 }
1252
1253 otgsc = readl(USB_OTGSC);
1254 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1255 return IRQ_NONE;
1256
1257 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1258 if (otgsc & OTGSC_ID)
1259 set_bit(ID, &motg->inputs);
1260 else
1261 clear_bit(ID, &motg->inputs);
1262 dev_dbg(phy->dev, "ID set/clear\n");
1263 pm_runtime_get_noresume(phy->dev);
1264 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1265 if (otgsc & OTGSC_BSV)
1266 set_bit(B_SESS_VLD, &motg->inputs);
1267 else
1268 clear_bit(B_SESS_VLD, &motg->inputs);
1269 dev_dbg(phy->dev, "BSV set/clear\n");
1270 pm_runtime_get_noresume(phy->dev);
1271 }
1272
1273 writel(otgsc, USB_OTGSC);
1274 schedule_work(&motg->sm_work);
1275 return IRQ_HANDLED;
1276 }
1277
1278 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1279 {
1280 struct msm_otg *motg = s->private;
1281 struct usb_otg *otg = motg->phy.otg;
1282
1283 switch (otg->phy->state) {
1284 case OTG_STATE_A_HOST:
1285 seq_printf(s, "host\n");
1286 break;
1287 case OTG_STATE_B_PERIPHERAL:
1288 seq_printf(s, "peripheral\n");
1289 break;
1290 default:
1291 seq_printf(s, "none\n");
1292 break;
1293 }
1294
1295 return 0;
1296 }
1297
1298 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1299 {
1300 return single_open(file, msm_otg_mode_show, inode->i_private);
1301 }
1302
1303 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1304 size_t count, loff_t *ppos)
1305 {
1306 struct seq_file *s = file->private_data;
1307 struct msm_otg *motg = s->private;
1308 char buf[16];
1309 struct usb_otg *otg = motg->phy.otg;
1310 int status = count;
1311 enum usb_mode_type req_mode;
1312
1313 memset(buf, 0x00, sizeof(buf));
1314
1315 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1316 status = -EFAULT;
1317 goto out;
1318 }
1319
1320 if (!strncmp(buf, "host", 4)) {
1321 req_mode = USB_HOST;
1322 } else if (!strncmp(buf, "peripheral", 10)) {
1323 req_mode = USB_PERIPHERAL;
1324 } else if (!strncmp(buf, "none", 4)) {
1325 req_mode = USB_NONE;
1326 } else {
1327 status = -EINVAL;
1328 goto out;
1329 }
1330
1331 switch (req_mode) {
1332 case USB_NONE:
1333 switch (otg->phy->state) {
1334 case OTG_STATE_A_HOST:
1335 case OTG_STATE_B_PERIPHERAL:
1336 set_bit(ID, &motg->inputs);
1337 clear_bit(B_SESS_VLD, &motg->inputs);
1338 break;
1339 default:
1340 goto out;
1341 }
1342 break;
1343 case USB_PERIPHERAL:
1344 switch (otg->phy->state) {
1345 case OTG_STATE_B_IDLE:
1346 case OTG_STATE_A_HOST:
1347 set_bit(ID, &motg->inputs);
1348 set_bit(B_SESS_VLD, &motg->inputs);
1349 break;
1350 default:
1351 goto out;
1352 }
1353 break;
1354 case USB_HOST:
1355 switch (otg->phy->state) {
1356 case OTG_STATE_B_IDLE:
1357 case OTG_STATE_B_PERIPHERAL:
1358 clear_bit(ID, &motg->inputs);
1359 break;
1360 default:
1361 goto out;
1362 }
1363 break;
1364 default:
1365 goto out;
1366 }
1367
1368 pm_runtime_get_sync(otg->phy->dev);
1369 schedule_work(&motg->sm_work);
1370 out:
1371 return status;
1372 }
1373
1374 const struct file_operations msm_otg_mode_fops = {
1375 .open = msm_otg_mode_open,
1376 .read = seq_read,
1377 .write = msm_otg_mode_write,
1378 .llseek = seq_lseek,
1379 .release = single_release,
1380 };
1381
1382 static struct dentry *msm_otg_dbg_root;
1383 static struct dentry *msm_otg_dbg_mode;
1384
1385 static int msm_otg_debugfs_init(struct msm_otg *motg)
1386 {
1387 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1388
1389 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1390 return -ENODEV;
1391
1392 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1393 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1394 if (!msm_otg_dbg_mode) {
1395 debugfs_remove(msm_otg_dbg_root);
1396 msm_otg_dbg_root = NULL;
1397 return -ENODEV;
1398 }
1399
1400 return 0;
1401 }
1402
1403 static void msm_otg_debugfs_cleanup(void)
1404 {
1405 debugfs_remove(msm_otg_dbg_mode);
1406 debugfs_remove(msm_otg_dbg_root);
1407 }
1408
1409 static int __init msm_otg_probe(struct platform_device *pdev)
1410 {
1411 int ret = 0;
1412 struct resource *res;
1413 struct msm_otg *motg;
1414 struct usb_phy *phy;
1415
1416 dev_info(&pdev->dev, "msm_otg probe\n");
1417 if (!dev_get_platdata(&pdev->dev)) {
1418 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1419 return -ENODEV;
1420 }
1421
1422 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1423 if (!motg) {
1424 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1425 return -ENOMEM;
1426 }
1427
1428 motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
1429 if (!motg->phy.otg) {
1430 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1431 return -ENOMEM;
1432 }
1433
1434 motg->pdata = dev_get_platdata(&pdev->dev);
1435 phy = &motg->phy;
1436 phy->dev = &pdev->dev;
1437
1438 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1439 if (IS_ERR(motg->phy_reset_clk)) {
1440 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1441 ret = PTR_ERR(motg->phy_reset_clk);
1442 goto free_motg;
1443 }
1444
1445 motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1446 if (IS_ERR(motg->clk)) {
1447 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1448 ret = PTR_ERR(motg->clk);
1449 goto put_phy_reset_clk;
1450 }
1451 clk_set_rate(motg->clk, 60000000);
1452
1453 /*
1454 * If USB Core is running its protocol engine based on CORE CLK,
1455 * CORE CLK must be running at >55Mhz for correct HSUSB
1456 * operation and USB core cannot tolerate frequency changes on
1457 * CORE CLK. For such USB cores, vote for maximum clk frequency
1458 * on pclk source
1459 */
1460 if (motg->pdata->pclk_src_name) {
1461 motg->pclk_src = clk_get(&pdev->dev,
1462 motg->pdata->pclk_src_name);
1463 if (IS_ERR(motg->pclk_src))
1464 goto put_clk;
1465 clk_set_rate(motg->pclk_src, INT_MAX);
1466 clk_prepare_enable(motg->pclk_src);
1467 } else
1468 motg->pclk_src = ERR_PTR(-ENOENT);
1469
1470
1471 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1472 if (IS_ERR(motg->pclk)) {
1473 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1474 ret = PTR_ERR(motg->pclk);
1475 goto put_pclk_src;
1476 }
1477
1478 /*
1479 * USB core clock is not present on all MSM chips. This
1480 * clock is introduced to remove the dependency on AXI
1481 * bus frequency.
1482 */
1483 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1484 if (IS_ERR(motg->core_clk))
1485 motg->core_clk = NULL;
1486
1487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1488 if (!res) {
1489 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1490 ret = -ENODEV;
1491 goto put_core_clk;
1492 }
1493
1494 motg->regs = ioremap(res->start, resource_size(res));
1495 if (!motg->regs) {
1496 dev_err(&pdev->dev, "ioremap failed\n");
1497 ret = -ENOMEM;
1498 goto put_core_clk;
1499 }
1500 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1501
1502 motg->irq = platform_get_irq(pdev, 0);
1503 if (!motg->irq) {
1504 dev_err(&pdev->dev, "platform_get_irq failed\n");
1505 ret = -ENODEV;
1506 goto free_regs;
1507 }
1508
1509 clk_prepare_enable(motg->clk);
1510 clk_prepare_enable(motg->pclk);
1511
1512 ret = msm_hsusb_init_vddcx(motg, 1);
1513 if (ret) {
1514 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1515 goto free_regs;
1516 }
1517
1518 ret = msm_hsusb_ldo_init(motg, 1);
1519 if (ret) {
1520 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1521 goto vddcx_exit;
1522 }
1523 ret = msm_hsusb_ldo_set_mode(1);
1524 if (ret) {
1525 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1526 goto ldo_exit;
1527 }
1528
1529 if (motg->core_clk)
1530 clk_prepare_enable(motg->core_clk);
1531
1532 writel(0, USB_USBINTR);
1533 writel(0, USB_OTGSC);
1534
1535 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1536 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1537 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1538 "msm_otg", motg);
1539 if (ret) {
1540 dev_err(&pdev->dev, "request irq failed\n");
1541 goto disable_clks;
1542 }
1543
1544 phy->init = msm_otg_reset;
1545 phy->set_power = msm_otg_set_power;
1546
1547 phy->io_ops = &msm_otg_io_ops;
1548
1549 phy->otg->phy = &motg->phy;
1550 phy->otg->set_host = msm_otg_set_host;
1551 phy->otg->set_peripheral = msm_otg_set_peripheral;
1552
1553 ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1554 if (ret) {
1555 dev_err(&pdev->dev, "usb_add_phy failed\n");
1556 goto free_irq;
1557 }
1558
1559 platform_set_drvdata(pdev, motg);
1560 device_init_wakeup(&pdev->dev, 1);
1561
1562 if (motg->pdata->mode == USB_OTG &&
1563 motg->pdata->otg_control == OTG_USER_CONTROL) {
1564 ret = msm_otg_debugfs_init(motg);
1565 if (ret)
1566 dev_dbg(&pdev->dev, "mode debugfs file is"
1567 "not available\n");
1568 }
1569
1570 pm_runtime_set_active(&pdev->dev);
1571 pm_runtime_enable(&pdev->dev);
1572
1573 return 0;
1574 free_irq:
1575 free_irq(motg->irq, motg);
1576 disable_clks:
1577 clk_disable_unprepare(motg->pclk);
1578 clk_disable_unprepare(motg->clk);
1579 ldo_exit:
1580 msm_hsusb_ldo_init(motg, 0);
1581 vddcx_exit:
1582 msm_hsusb_init_vddcx(motg, 0);
1583 free_regs:
1584 iounmap(motg->regs);
1585 put_core_clk:
1586 if (motg->core_clk)
1587 clk_put(motg->core_clk);
1588 clk_put(motg->pclk);
1589 put_pclk_src:
1590 if (!IS_ERR(motg->pclk_src)) {
1591 clk_disable_unprepare(motg->pclk_src);
1592 clk_put(motg->pclk_src);
1593 }
1594 put_clk:
1595 clk_put(motg->clk);
1596 put_phy_reset_clk:
1597 clk_put(motg->phy_reset_clk);
1598 free_motg:
1599 kfree(motg->phy.otg);
1600 kfree(motg);
1601 return ret;
1602 }
1603
1604 static int msm_otg_remove(struct platform_device *pdev)
1605 {
1606 struct msm_otg *motg = platform_get_drvdata(pdev);
1607 struct usb_phy *phy = &motg->phy;
1608 int cnt = 0;
1609
1610 if (phy->otg->host || phy->otg->gadget)
1611 return -EBUSY;
1612
1613 msm_otg_debugfs_cleanup();
1614 cancel_delayed_work_sync(&motg->chg_work);
1615 cancel_work_sync(&motg->sm_work);
1616
1617 pm_runtime_resume(&pdev->dev);
1618
1619 device_init_wakeup(&pdev->dev, 0);
1620 pm_runtime_disable(&pdev->dev);
1621
1622 usb_remove_phy(phy);
1623 free_irq(motg->irq, motg);
1624
1625 /*
1626 * Put PHY in low power mode.
1627 */
1628 ulpi_read(phy, 0x14);
1629 ulpi_write(phy, 0x08, 0x09);
1630
1631 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1632 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1633 if (readl(USB_PORTSC) & PORTSC_PHCD)
1634 break;
1635 udelay(1);
1636 cnt++;
1637 }
1638 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1639 dev_err(phy->dev, "Unable to suspend PHY\n");
1640
1641 clk_disable_unprepare(motg->pclk);
1642 clk_disable_unprepare(motg->clk);
1643 if (motg->core_clk)
1644 clk_disable_unprepare(motg->core_clk);
1645 if (!IS_ERR(motg->pclk_src)) {
1646 clk_disable_unprepare(motg->pclk_src);
1647 clk_put(motg->pclk_src);
1648 }
1649 msm_hsusb_ldo_init(motg, 0);
1650
1651 iounmap(motg->regs);
1652 pm_runtime_set_suspended(&pdev->dev);
1653
1654 clk_put(motg->phy_reset_clk);
1655 clk_put(motg->pclk);
1656 clk_put(motg->clk);
1657 if (motg->core_clk)
1658 clk_put(motg->core_clk);
1659
1660 kfree(motg->phy.otg);
1661 kfree(motg);
1662
1663 return 0;
1664 }
1665
1666 #ifdef CONFIG_PM_RUNTIME
1667 static int msm_otg_runtime_idle(struct device *dev)
1668 {
1669 struct msm_otg *motg = dev_get_drvdata(dev);
1670 struct usb_otg *otg = motg->phy.otg;
1671
1672 dev_dbg(dev, "OTG runtime idle\n");
1673
1674 /*
1675 * It is observed some times that a spurious interrupt
1676 * comes when PHY is put into LPM immediately after PHY reset.
1677 * This 1 sec delay also prevents entering into LPM immediately
1678 * after asynchronous interrupt.
1679 */
1680 if (otg->phy->state != OTG_STATE_UNDEFINED)
1681 pm_schedule_suspend(dev, 1000);
1682
1683 return -EAGAIN;
1684 }
1685
1686 static int msm_otg_runtime_suspend(struct device *dev)
1687 {
1688 struct msm_otg *motg = dev_get_drvdata(dev);
1689
1690 dev_dbg(dev, "OTG runtime suspend\n");
1691 return msm_otg_suspend(motg);
1692 }
1693
1694 static int msm_otg_runtime_resume(struct device *dev)
1695 {
1696 struct msm_otg *motg = dev_get_drvdata(dev);
1697
1698 dev_dbg(dev, "OTG runtime resume\n");
1699 return msm_otg_resume(motg);
1700 }
1701 #endif
1702
1703 #ifdef CONFIG_PM_SLEEP
1704 static int msm_otg_pm_suspend(struct device *dev)
1705 {
1706 struct msm_otg *motg = dev_get_drvdata(dev);
1707
1708 dev_dbg(dev, "OTG PM suspend\n");
1709 return msm_otg_suspend(motg);
1710 }
1711
1712 static int msm_otg_pm_resume(struct device *dev)
1713 {
1714 struct msm_otg *motg = dev_get_drvdata(dev);
1715 int ret;
1716
1717 dev_dbg(dev, "OTG PM resume\n");
1718
1719 ret = msm_otg_resume(motg);
1720 if (ret)
1721 return ret;
1722
1723 /*
1724 * Runtime PM Documentation recommends bringing the
1725 * device to full powered state upon resume.
1726 */
1727 pm_runtime_disable(dev);
1728 pm_runtime_set_active(dev);
1729 pm_runtime_enable(dev);
1730
1731 return 0;
1732 }
1733 #endif
1734
1735 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1736 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1737 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1738 msm_otg_runtime_idle)
1739 };
1740
1741 static struct platform_driver msm_otg_driver = {
1742 .remove = msm_otg_remove,
1743 .driver = {
1744 .name = DRIVER_NAME,
1745 .owner = THIS_MODULE,
1746 .pm = &msm_otg_dev_pm_ops,
1747 },
1748 };
1749
1750 module_platform_driver_probe(msm_otg_driver, msm_otg_probe);
1751
1752 MODULE_LICENSE("GPL v2");
1753 MODULE_DESCRIPTION("MSM USB transceiver driver");
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