]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/usb/phy/phy-msm-usb.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'for-3.14-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / usb / phy / phy-msm-usb.c
1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/usb.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/usb/msm_hsusb.h>
40 #include <linux/usb/msm_hsusb_hw.h>
41 #include <linux/regulator/consumer.h>
42
43 #define MSM_USB_BASE (motg->regs)
44 #define DRIVER_NAME "msm_otg"
45
46 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
47
48 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
49 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
50 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
51 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
52
53 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
54 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
55 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
56 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
57
58 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
59 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
60
61 static struct regulator *hsusb_3p3;
62 static struct regulator *hsusb_1p8;
63 static struct regulator *hsusb_vddcx;
64
65 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
66 {
67 int ret = 0;
68
69 if (init) {
70 hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX");
71 if (IS_ERR(hsusb_vddcx)) {
72 dev_err(motg->phy.dev, "unable to get hsusb vddcx\n");
73 return PTR_ERR(hsusb_vddcx);
74 }
75
76 ret = regulator_set_voltage(hsusb_vddcx,
77 USB_PHY_VDD_DIG_VOL_MIN,
78 USB_PHY_VDD_DIG_VOL_MAX);
79 if (ret) {
80 dev_err(motg->phy.dev, "unable to set the voltage "
81 "for hsusb vddcx\n");
82 regulator_put(hsusb_vddcx);
83 return ret;
84 }
85
86 ret = regulator_enable(hsusb_vddcx);
87 if (ret) {
88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
89 regulator_put(hsusb_vddcx);
90 }
91 } else {
92 ret = regulator_set_voltage(hsusb_vddcx, 0,
93 USB_PHY_VDD_DIG_VOL_MAX);
94 if (ret)
95 dev_err(motg->phy.dev, "unable to set the voltage "
96 "for hsusb vddcx\n");
97 ret = regulator_disable(hsusb_vddcx);
98 if (ret)
99 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
100
101 regulator_put(hsusb_vddcx);
102 }
103
104 return ret;
105 }
106
107 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
108 {
109 int rc = 0;
110
111 if (init) {
112 hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3");
113 if (IS_ERR(hsusb_3p3)) {
114 dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
115 return PTR_ERR(hsusb_3p3);
116 }
117
118 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
119 USB_PHY_3P3_VOL_MAX);
120 if (rc) {
121 dev_err(motg->phy.dev, "unable to set voltage level "
122 "for hsusb 3p3\n");
123 goto put_3p3;
124 }
125 rc = regulator_enable(hsusb_3p3);
126 if (rc) {
127 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
128 goto put_3p3;
129 }
130 hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8");
131 if (IS_ERR(hsusb_1p8)) {
132 dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
133 rc = PTR_ERR(hsusb_1p8);
134 goto disable_3p3;
135 }
136 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
137 USB_PHY_1P8_VOL_MAX);
138 if (rc) {
139 dev_err(motg->phy.dev, "unable to set voltage level "
140 "for hsusb 1p8\n");
141 goto put_1p8;
142 }
143 rc = regulator_enable(hsusb_1p8);
144 if (rc) {
145 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
146 goto put_1p8;
147 }
148
149 return 0;
150 }
151
152 regulator_disable(hsusb_1p8);
153 put_1p8:
154 regulator_put(hsusb_1p8);
155 disable_3p3:
156 regulator_disable(hsusb_3p3);
157 put_3p3:
158 regulator_put(hsusb_3p3);
159 return rc;
160 }
161
162 #ifdef CONFIG_PM_SLEEP
163 #define USB_PHY_SUSP_DIG_VOL 500000
164 static int msm_hsusb_config_vddcx(int high)
165 {
166 int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
167 int min_vol;
168 int ret;
169
170 if (high)
171 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
172 else
173 min_vol = USB_PHY_SUSP_DIG_VOL;
174
175 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
176 if (ret) {
177 pr_err("%s: unable to set the voltage for regulator "
178 "HSUSB_VDDCX\n", __func__);
179 return ret;
180 }
181
182 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
183
184 return ret;
185 }
186 #endif
187
188 static int msm_hsusb_ldo_set_mode(int on)
189 {
190 int ret = 0;
191
192 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
193 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
194 return -ENODEV;
195 }
196
197 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
198 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
199 return -ENODEV;
200 }
201
202 if (on) {
203 ret = regulator_set_optimum_mode(hsusb_1p8,
204 USB_PHY_1P8_HPM_LOAD);
205 if (ret < 0) {
206 pr_err("%s: Unable to set HPM of the regulator "
207 "HSUSB_1p8\n", __func__);
208 return ret;
209 }
210 ret = regulator_set_optimum_mode(hsusb_3p3,
211 USB_PHY_3P3_HPM_LOAD);
212 if (ret < 0) {
213 pr_err("%s: Unable to set HPM of the regulator "
214 "HSUSB_3p3\n", __func__);
215 regulator_set_optimum_mode(hsusb_1p8,
216 USB_PHY_1P8_LPM_LOAD);
217 return ret;
218 }
219 } else {
220 ret = regulator_set_optimum_mode(hsusb_1p8,
221 USB_PHY_1P8_LPM_LOAD);
222 if (ret < 0)
223 pr_err("%s: Unable to set LPM of the regulator "
224 "HSUSB_1p8\n", __func__);
225 ret = regulator_set_optimum_mode(hsusb_3p3,
226 USB_PHY_3P3_LPM_LOAD);
227 if (ret < 0)
228 pr_err("%s: Unable to set LPM of the regulator "
229 "HSUSB_3p3\n", __func__);
230 }
231
232 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
233 return ret < 0 ? ret : 0;
234 }
235
236 static int ulpi_read(struct usb_phy *phy, u32 reg)
237 {
238 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
239 int cnt = 0;
240
241 /* initiate read operation */
242 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
243 USB_ULPI_VIEWPORT);
244
245 /* wait for completion */
246 while (cnt < ULPI_IO_TIMEOUT_USEC) {
247 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
248 break;
249 udelay(1);
250 cnt++;
251 }
252
253 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
254 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
255 readl(USB_ULPI_VIEWPORT));
256 return -ETIMEDOUT;
257 }
258 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
259 }
260
261 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
262 {
263 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
264 int cnt = 0;
265
266 /* initiate write operation */
267 writel(ULPI_RUN | ULPI_WRITE |
268 ULPI_ADDR(reg) | ULPI_DATA(val),
269 USB_ULPI_VIEWPORT);
270
271 /* wait for completion */
272 while (cnt < ULPI_IO_TIMEOUT_USEC) {
273 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
274 break;
275 udelay(1);
276 cnt++;
277 }
278
279 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
280 dev_err(phy->dev, "ulpi_write: timeout\n");
281 return -ETIMEDOUT;
282 }
283 return 0;
284 }
285
286 static struct usb_phy_io_ops msm_otg_io_ops = {
287 .read = ulpi_read,
288 .write = ulpi_write,
289 };
290
291 static void ulpi_init(struct msm_otg *motg)
292 {
293 struct msm_otg_platform_data *pdata = motg->pdata;
294 int *seq = pdata->phy_init_seq;
295
296 if (!seq)
297 return;
298
299 while (seq[0] >= 0) {
300 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
301 seq[0], seq[1]);
302 ulpi_write(&motg->phy, seq[0], seq[1]);
303 seq += 2;
304 }
305 }
306
307 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
308 {
309 int ret = 0;
310
311 if (!motg->pdata->link_clk_reset)
312 return ret;
313
314 ret = motg->pdata->link_clk_reset(motg->clk, assert);
315 if (ret)
316 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
317 assert ? "assert" : "deassert");
318
319 return ret;
320 }
321
322 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
323 {
324 int ret = 0;
325
326 if (!motg->pdata->phy_clk_reset)
327 return ret;
328
329 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
330 if (ret)
331 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
332
333 return ret;
334 }
335
336 static int msm_otg_phy_reset(struct msm_otg *motg)
337 {
338 u32 val;
339 int ret;
340 int retries;
341
342 ret = msm_otg_link_clk_reset(motg, 1);
343 if (ret)
344 return ret;
345 ret = msm_otg_phy_clk_reset(motg);
346 if (ret)
347 return ret;
348 ret = msm_otg_link_clk_reset(motg, 0);
349 if (ret)
350 return ret;
351
352 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
353 writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
354
355 for (retries = 3; retries > 0; retries--) {
356 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
357 ULPI_CLR(ULPI_FUNC_CTRL));
358 if (!ret)
359 break;
360 ret = msm_otg_phy_clk_reset(motg);
361 if (ret)
362 return ret;
363 }
364 if (!retries)
365 return -ETIMEDOUT;
366
367 /* This reset calibrates the phy, if the above write succeeded */
368 ret = msm_otg_phy_clk_reset(motg);
369 if (ret)
370 return ret;
371
372 for (retries = 3; retries > 0; retries--) {
373 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
374 if (ret != -ETIMEDOUT)
375 break;
376 ret = msm_otg_phy_clk_reset(motg);
377 if (ret)
378 return ret;
379 }
380 if (!retries)
381 return -ETIMEDOUT;
382
383 dev_info(motg->phy.dev, "phy_reset: success\n");
384 return 0;
385 }
386
387 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
388 static int msm_otg_reset(struct usb_phy *phy)
389 {
390 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
391 struct msm_otg_platform_data *pdata = motg->pdata;
392 int cnt = 0;
393 int ret;
394 u32 val = 0;
395 u32 ulpi_val = 0;
396
397 ret = msm_otg_phy_reset(motg);
398 if (ret) {
399 dev_err(phy->dev, "phy_reset failed\n");
400 return ret;
401 }
402
403 ulpi_init(motg);
404
405 writel(USBCMD_RESET, USB_USBCMD);
406 while (cnt < LINK_RESET_TIMEOUT_USEC) {
407 if (!(readl(USB_USBCMD) & USBCMD_RESET))
408 break;
409 udelay(1);
410 cnt++;
411 }
412 if (cnt >= LINK_RESET_TIMEOUT_USEC)
413 return -ETIMEDOUT;
414
415 /* select ULPI phy */
416 writel(0x80000000, USB_PORTSC);
417
418 msleep(100);
419
420 writel(0x0, USB_AHBBURST);
421 writel(0x00, USB_AHBMODE);
422
423 if (pdata->otg_control == OTG_PHY_CONTROL) {
424 val = readl(USB_OTGSC);
425 if (pdata->mode == USB_OTG) {
426 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
427 val |= OTGSC_IDIE | OTGSC_BSVIE;
428 } else if (pdata->mode == USB_PERIPHERAL) {
429 ulpi_val = ULPI_INT_SESS_VALID;
430 val |= OTGSC_BSVIE;
431 }
432 writel(val, USB_OTGSC);
433 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
434 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
435 }
436
437 return 0;
438 }
439
440 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
441 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
442
443 #ifdef CONFIG_PM_SLEEP
444 static int msm_otg_suspend(struct msm_otg *motg)
445 {
446 struct usb_phy *phy = &motg->phy;
447 struct usb_bus *bus = phy->otg->host;
448 struct msm_otg_platform_data *pdata = motg->pdata;
449 int cnt = 0;
450
451 if (atomic_read(&motg->in_lpm))
452 return 0;
453
454 disable_irq(motg->irq);
455 /*
456 * Chipidea 45-nm PHY suspend sequence:
457 *
458 * Interrupt Latch Register auto-clear feature is not present
459 * in all PHY versions. Latch register is clear on read type.
460 * Clear latch register to avoid spurious wakeup from
461 * low power mode (LPM).
462 *
463 * PHY comparators are disabled when PHY enters into low power
464 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
465 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
466 * PHY comparators. This save significant amount of power.
467 *
468 * PLL is not turned off when PHY enters into low power mode (LPM).
469 * Disable PLL for maximum power savings.
470 */
471
472 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
473 ulpi_read(phy, 0x14);
474 if (pdata->otg_control == OTG_PHY_CONTROL)
475 ulpi_write(phy, 0x01, 0x30);
476 ulpi_write(phy, 0x08, 0x09);
477 }
478
479 /*
480 * PHY may take some time or even fail to enter into low power
481 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
482 * in failure case.
483 */
484 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
485 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
486 if (readl(USB_PORTSC) & PORTSC_PHCD)
487 break;
488 udelay(1);
489 cnt++;
490 }
491
492 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
493 dev_err(phy->dev, "Unable to suspend PHY\n");
494 msm_otg_reset(phy);
495 enable_irq(motg->irq);
496 return -ETIMEDOUT;
497 }
498
499 /*
500 * PHY has capability to generate interrupt asynchronously in low
501 * power mode (LPM). This interrupt is level triggered. So USB IRQ
502 * line must be disabled till async interrupt enable bit is cleared
503 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
504 * block data communication from PHY.
505 */
506 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
507
508 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
509 motg->pdata->otg_control == OTG_PMIC_CONTROL)
510 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
511
512 clk_disable_unprepare(motg->pclk);
513 clk_disable_unprepare(motg->clk);
514 if (motg->core_clk)
515 clk_disable_unprepare(motg->core_clk);
516
517 if (!IS_ERR(motg->pclk_src))
518 clk_disable_unprepare(motg->pclk_src);
519
520 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
521 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
522 msm_hsusb_ldo_set_mode(0);
523 msm_hsusb_config_vddcx(0);
524 }
525
526 if (device_may_wakeup(phy->dev))
527 enable_irq_wake(motg->irq);
528 if (bus)
529 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
530
531 atomic_set(&motg->in_lpm, 1);
532 enable_irq(motg->irq);
533
534 dev_info(phy->dev, "USB in low power mode\n");
535
536 return 0;
537 }
538
539 static int msm_otg_resume(struct msm_otg *motg)
540 {
541 struct usb_phy *phy = &motg->phy;
542 struct usb_bus *bus = phy->otg->host;
543 int cnt = 0;
544 unsigned temp;
545
546 if (!atomic_read(&motg->in_lpm))
547 return 0;
548
549 if (!IS_ERR(motg->pclk_src))
550 clk_prepare_enable(motg->pclk_src);
551
552 clk_prepare_enable(motg->pclk);
553 clk_prepare_enable(motg->clk);
554 if (motg->core_clk)
555 clk_prepare_enable(motg->core_clk);
556
557 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
558 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
559 msm_hsusb_ldo_set_mode(1);
560 msm_hsusb_config_vddcx(1);
561 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
562 }
563
564 temp = readl(USB_USBCMD);
565 temp &= ~ASYNC_INTR_CTRL;
566 temp &= ~ULPI_STP_CTRL;
567 writel(temp, USB_USBCMD);
568
569 /*
570 * PHY comes out of low power mode (LPM) in case of wakeup
571 * from asynchronous interrupt.
572 */
573 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
574 goto skip_phy_resume;
575
576 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
577 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
578 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
579 break;
580 udelay(1);
581 cnt++;
582 }
583
584 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
585 /*
586 * This is a fatal error. Reset the link and
587 * PHY. USB state can not be restored. Re-insertion
588 * of USB cable is the only way to get USB working.
589 */
590 dev_err(phy->dev, "Unable to resume USB."
591 "Re-plugin the cable\n");
592 msm_otg_reset(phy);
593 }
594
595 skip_phy_resume:
596 if (device_may_wakeup(phy->dev))
597 disable_irq_wake(motg->irq);
598 if (bus)
599 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
600
601 atomic_set(&motg->in_lpm, 0);
602
603 if (motg->async_int) {
604 motg->async_int = 0;
605 pm_runtime_put(phy->dev);
606 enable_irq(motg->irq);
607 }
608
609 dev_info(phy->dev, "USB exited from low power mode\n");
610
611 return 0;
612 }
613 #endif
614
615 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
616 {
617 if (motg->cur_power == mA)
618 return;
619
620 /* TODO: Notify PMIC about available current */
621 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
622 motg->cur_power = mA;
623 }
624
625 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
626 {
627 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
628
629 /*
630 * Gadget driver uses set_power method to notify about the
631 * available current based on suspend/configured states.
632 *
633 * IDEV_CHG can be drawn irrespective of suspend/un-configured
634 * states when CDP/ACA is connected.
635 */
636 if (motg->chg_type == USB_SDP_CHARGER)
637 msm_otg_notify_charger(motg, mA);
638
639 return 0;
640 }
641
642 static void msm_otg_start_host(struct usb_phy *phy, int on)
643 {
644 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
645 struct msm_otg_platform_data *pdata = motg->pdata;
646 struct usb_hcd *hcd;
647
648 if (!phy->otg->host)
649 return;
650
651 hcd = bus_to_hcd(phy->otg->host);
652
653 if (on) {
654 dev_dbg(phy->dev, "host on\n");
655
656 if (pdata->vbus_power)
657 pdata->vbus_power(1);
658 /*
659 * Some boards have a switch cotrolled by gpio
660 * to enable/disable internal HUB. Enable internal
661 * HUB before kicking the host.
662 */
663 if (pdata->setup_gpio)
664 pdata->setup_gpio(OTG_STATE_A_HOST);
665 #ifdef CONFIG_USB
666 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
667 device_wakeup_enable(hcd->self.controller);
668 #endif
669 } else {
670 dev_dbg(phy->dev, "host off\n");
671
672 #ifdef CONFIG_USB
673 usb_remove_hcd(hcd);
674 #endif
675 if (pdata->setup_gpio)
676 pdata->setup_gpio(OTG_STATE_UNDEFINED);
677 if (pdata->vbus_power)
678 pdata->vbus_power(0);
679 }
680 }
681
682 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
683 {
684 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
685 struct usb_hcd *hcd;
686
687 /*
688 * Fail host registration if this board can support
689 * only peripheral configuration.
690 */
691 if (motg->pdata->mode == USB_PERIPHERAL) {
692 dev_info(otg->phy->dev, "Host mode is not supported\n");
693 return -ENODEV;
694 }
695
696 if (!host) {
697 if (otg->phy->state == OTG_STATE_A_HOST) {
698 pm_runtime_get_sync(otg->phy->dev);
699 msm_otg_start_host(otg->phy, 0);
700 otg->host = NULL;
701 otg->phy->state = OTG_STATE_UNDEFINED;
702 schedule_work(&motg->sm_work);
703 } else {
704 otg->host = NULL;
705 }
706
707 return 0;
708 }
709
710 hcd = bus_to_hcd(host);
711 hcd->power_budget = motg->pdata->power_budget;
712
713 otg->host = host;
714 dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
715
716 /*
717 * Kick the state machine work, if peripheral is not supported
718 * or peripheral is already registered with us.
719 */
720 if (motg->pdata->mode == USB_HOST || otg->gadget) {
721 pm_runtime_get_sync(otg->phy->dev);
722 schedule_work(&motg->sm_work);
723 }
724
725 return 0;
726 }
727
728 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
729 {
730 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
731 struct msm_otg_platform_data *pdata = motg->pdata;
732
733 if (!phy->otg->gadget)
734 return;
735
736 if (on) {
737 dev_dbg(phy->dev, "gadget on\n");
738 /*
739 * Some boards have a switch cotrolled by gpio
740 * to enable/disable internal HUB. Disable internal
741 * HUB before kicking the gadget.
742 */
743 if (pdata->setup_gpio)
744 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
745 usb_gadget_vbus_connect(phy->otg->gadget);
746 } else {
747 dev_dbg(phy->dev, "gadget off\n");
748 usb_gadget_vbus_disconnect(phy->otg->gadget);
749 if (pdata->setup_gpio)
750 pdata->setup_gpio(OTG_STATE_UNDEFINED);
751 }
752
753 }
754
755 static int msm_otg_set_peripheral(struct usb_otg *otg,
756 struct usb_gadget *gadget)
757 {
758 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
759
760 /*
761 * Fail peripheral registration if this board can support
762 * only host configuration.
763 */
764 if (motg->pdata->mode == USB_HOST) {
765 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
766 return -ENODEV;
767 }
768
769 if (!gadget) {
770 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
771 pm_runtime_get_sync(otg->phy->dev);
772 msm_otg_start_peripheral(otg->phy, 0);
773 otg->gadget = NULL;
774 otg->phy->state = OTG_STATE_UNDEFINED;
775 schedule_work(&motg->sm_work);
776 } else {
777 otg->gadget = NULL;
778 }
779
780 return 0;
781 }
782 otg->gadget = gadget;
783 dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
784
785 /*
786 * Kick the state machine work, if host is not supported
787 * or host is already registered with us.
788 */
789 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
790 pm_runtime_get_sync(otg->phy->dev);
791 schedule_work(&motg->sm_work);
792 }
793
794 return 0;
795 }
796
797 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
798 {
799 struct usb_phy *phy = &motg->phy;
800 u32 chg_det;
801 bool ret = false;
802
803 switch (motg->pdata->phy_type) {
804 case CI_45NM_INTEGRATED_PHY:
805 chg_det = ulpi_read(phy, 0x34);
806 ret = chg_det & (1 << 4);
807 break;
808 case SNPS_28NM_INTEGRATED_PHY:
809 chg_det = ulpi_read(phy, 0x87);
810 ret = chg_det & 1;
811 break;
812 default:
813 break;
814 }
815 return ret;
816 }
817
818 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
819 {
820 struct usb_phy *phy = &motg->phy;
821 u32 chg_det;
822
823 switch (motg->pdata->phy_type) {
824 case CI_45NM_INTEGRATED_PHY:
825 chg_det = ulpi_read(phy, 0x34);
826 /* Turn off charger block */
827 chg_det |= ~(1 << 1);
828 ulpi_write(phy, chg_det, 0x34);
829 udelay(20);
830 /* control chg block via ULPI */
831 chg_det &= ~(1 << 3);
832 ulpi_write(phy, chg_det, 0x34);
833 /* put it in host mode for enabling D- source */
834 chg_det &= ~(1 << 2);
835 ulpi_write(phy, chg_det, 0x34);
836 /* Turn on chg detect block */
837 chg_det &= ~(1 << 1);
838 ulpi_write(phy, chg_det, 0x34);
839 udelay(20);
840 /* enable chg detection */
841 chg_det &= ~(1 << 0);
842 ulpi_write(phy, chg_det, 0x34);
843 break;
844 case SNPS_28NM_INTEGRATED_PHY:
845 /*
846 * Configure DM as current source, DP as current sink
847 * and enable battery charging comparators.
848 */
849 ulpi_write(phy, 0x8, 0x85);
850 ulpi_write(phy, 0x2, 0x85);
851 ulpi_write(phy, 0x1, 0x85);
852 break;
853 default:
854 break;
855 }
856 }
857
858 static bool msm_chg_check_primary_det(struct msm_otg *motg)
859 {
860 struct usb_phy *phy = &motg->phy;
861 u32 chg_det;
862 bool ret = false;
863
864 switch (motg->pdata->phy_type) {
865 case CI_45NM_INTEGRATED_PHY:
866 chg_det = ulpi_read(phy, 0x34);
867 ret = chg_det & (1 << 4);
868 break;
869 case SNPS_28NM_INTEGRATED_PHY:
870 chg_det = ulpi_read(phy, 0x87);
871 ret = chg_det & 1;
872 break;
873 default:
874 break;
875 }
876 return ret;
877 }
878
879 static void msm_chg_enable_primary_det(struct msm_otg *motg)
880 {
881 struct usb_phy *phy = &motg->phy;
882 u32 chg_det;
883
884 switch (motg->pdata->phy_type) {
885 case CI_45NM_INTEGRATED_PHY:
886 chg_det = ulpi_read(phy, 0x34);
887 /* enable chg detection */
888 chg_det &= ~(1 << 0);
889 ulpi_write(phy, chg_det, 0x34);
890 break;
891 case SNPS_28NM_INTEGRATED_PHY:
892 /*
893 * Configure DP as current source, DM as current sink
894 * and enable battery charging comparators.
895 */
896 ulpi_write(phy, 0x2, 0x85);
897 ulpi_write(phy, 0x1, 0x85);
898 break;
899 default:
900 break;
901 }
902 }
903
904 static bool msm_chg_check_dcd(struct msm_otg *motg)
905 {
906 struct usb_phy *phy = &motg->phy;
907 u32 line_state;
908 bool ret = false;
909
910 switch (motg->pdata->phy_type) {
911 case CI_45NM_INTEGRATED_PHY:
912 line_state = ulpi_read(phy, 0x15);
913 ret = !(line_state & 1);
914 break;
915 case SNPS_28NM_INTEGRATED_PHY:
916 line_state = ulpi_read(phy, 0x87);
917 ret = line_state & 2;
918 break;
919 default:
920 break;
921 }
922 return ret;
923 }
924
925 static void msm_chg_disable_dcd(struct msm_otg *motg)
926 {
927 struct usb_phy *phy = &motg->phy;
928 u32 chg_det;
929
930 switch (motg->pdata->phy_type) {
931 case CI_45NM_INTEGRATED_PHY:
932 chg_det = ulpi_read(phy, 0x34);
933 chg_det &= ~(1 << 5);
934 ulpi_write(phy, chg_det, 0x34);
935 break;
936 case SNPS_28NM_INTEGRATED_PHY:
937 ulpi_write(phy, 0x10, 0x86);
938 break;
939 default:
940 break;
941 }
942 }
943
944 static void msm_chg_enable_dcd(struct msm_otg *motg)
945 {
946 struct usb_phy *phy = &motg->phy;
947 u32 chg_det;
948
949 switch (motg->pdata->phy_type) {
950 case CI_45NM_INTEGRATED_PHY:
951 chg_det = ulpi_read(phy, 0x34);
952 /* Turn on D+ current source */
953 chg_det |= (1 << 5);
954 ulpi_write(phy, chg_det, 0x34);
955 break;
956 case SNPS_28NM_INTEGRATED_PHY:
957 /* Data contact detection enable */
958 ulpi_write(phy, 0x10, 0x85);
959 break;
960 default:
961 break;
962 }
963 }
964
965 static void msm_chg_block_on(struct msm_otg *motg)
966 {
967 struct usb_phy *phy = &motg->phy;
968 u32 func_ctrl, chg_det;
969
970 /* put the controller in non-driving mode */
971 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
972 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
973 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
974 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
975
976 switch (motg->pdata->phy_type) {
977 case CI_45NM_INTEGRATED_PHY:
978 chg_det = ulpi_read(phy, 0x34);
979 /* control chg block via ULPI */
980 chg_det &= ~(1 << 3);
981 ulpi_write(phy, chg_det, 0x34);
982 /* Turn on chg detect block */
983 chg_det &= ~(1 << 1);
984 ulpi_write(phy, chg_det, 0x34);
985 udelay(20);
986 break;
987 case SNPS_28NM_INTEGRATED_PHY:
988 /* Clear charger detecting control bits */
989 ulpi_write(phy, 0x3F, 0x86);
990 /* Clear alt interrupt latch and enable bits */
991 ulpi_write(phy, 0x1F, 0x92);
992 ulpi_write(phy, 0x1F, 0x95);
993 udelay(100);
994 break;
995 default:
996 break;
997 }
998 }
999
1000 static void msm_chg_block_off(struct msm_otg *motg)
1001 {
1002 struct usb_phy *phy = &motg->phy;
1003 u32 func_ctrl, chg_det;
1004
1005 switch (motg->pdata->phy_type) {
1006 case CI_45NM_INTEGRATED_PHY:
1007 chg_det = ulpi_read(phy, 0x34);
1008 /* Turn off charger block */
1009 chg_det |= ~(1 << 1);
1010 ulpi_write(phy, chg_det, 0x34);
1011 break;
1012 case SNPS_28NM_INTEGRATED_PHY:
1013 /* Clear charger detecting control bits */
1014 ulpi_write(phy, 0x3F, 0x86);
1015 /* Clear alt interrupt latch and enable bits */
1016 ulpi_write(phy, 0x1F, 0x92);
1017 ulpi_write(phy, 0x1F, 0x95);
1018 break;
1019 default:
1020 break;
1021 }
1022
1023 /* put the controller in normal mode */
1024 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1025 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1026 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1027 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1028 }
1029
1030 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1031 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1032 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1033 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1034 static void msm_chg_detect_work(struct work_struct *w)
1035 {
1036 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1037 struct usb_phy *phy = &motg->phy;
1038 bool is_dcd, tmout, vout;
1039 unsigned long delay;
1040
1041 dev_dbg(phy->dev, "chg detection work\n");
1042 switch (motg->chg_state) {
1043 case USB_CHG_STATE_UNDEFINED:
1044 pm_runtime_get_sync(phy->dev);
1045 msm_chg_block_on(motg);
1046 msm_chg_enable_dcd(motg);
1047 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1048 motg->dcd_retries = 0;
1049 delay = MSM_CHG_DCD_POLL_TIME;
1050 break;
1051 case USB_CHG_STATE_WAIT_FOR_DCD:
1052 is_dcd = msm_chg_check_dcd(motg);
1053 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1054 if (is_dcd || tmout) {
1055 msm_chg_disable_dcd(motg);
1056 msm_chg_enable_primary_det(motg);
1057 delay = MSM_CHG_PRIMARY_DET_TIME;
1058 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1059 } else {
1060 delay = MSM_CHG_DCD_POLL_TIME;
1061 }
1062 break;
1063 case USB_CHG_STATE_DCD_DONE:
1064 vout = msm_chg_check_primary_det(motg);
1065 if (vout) {
1066 msm_chg_enable_secondary_det(motg);
1067 delay = MSM_CHG_SECONDARY_DET_TIME;
1068 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1069 } else {
1070 motg->chg_type = USB_SDP_CHARGER;
1071 motg->chg_state = USB_CHG_STATE_DETECTED;
1072 delay = 0;
1073 }
1074 break;
1075 case USB_CHG_STATE_PRIMARY_DONE:
1076 vout = msm_chg_check_secondary_det(motg);
1077 if (vout)
1078 motg->chg_type = USB_DCP_CHARGER;
1079 else
1080 motg->chg_type = USB_CDP_CHARGER;
1081 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1082 /* fall through */
1083 case USB_CHG_STATE_SECONDARY_DONE:
1084 motg->chg_state = USB_CHG_STATE_DETECTED;
1085 case USB_CHG_STATE_DETECTED:
1086 msm_chg_block_off(motg);
1087 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1088 schedule_work(&motg->sm_work);
1089 return;
1090 default:
1091 return;
1092 }
1093
1094 schedule_delayed_work(&motg->chg_work, delay);
1095 }
1096
1097 /*
1098 * We support OTG, Peripheral only and Host only configurations. In case
1099 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1100 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1101 * enabled when switch is controlled by user and default mode is supplied
1102 * by board file, which can be changed by userspace later.
1103 */
1104 static void msm_otg_init_sm(struct msm_otg *motg)
1105 {
1106 struct msm_otg_platform_data *pdata = motg->pdata;
1107 u32 otgsc = readl(USB_OTGSC);
1108
1109 switch (pdata->mode) {
1110 case USB_OTG:
1111 if (pdata->otg_control == OTG_PHY_CONTROL) {
1112 if (otgsc & OTGSC_ID)
1113 set_bit(ID, &motg->inputs);
1114 else
1115 clear_bit(ID, &motg->inputs);
1116
1117 if (otgsc & OTGSC_BSV)
1118 set_bit(B_SESS_VLD, &motg->inputs);
1119 else
1120 clear_bit(B_SESS_VLD, &motg->inputs);
1121 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1122 if (pdata->default_mode == USB_HOST) {
1123 clear_bit(ID, &motg->inputs);
1124 } else if (pdata->default_mode == USB_PERIPHERAL) {
1125 set_bit(ID, &motg->inputs);
1126 set_bit(B_SESS_VLD, &motg->inputs);
1127 } else {
1128 set_bit(ID, &motg->inputs);
1129 clear_bit(B_SESS_VLD, &motg->inputs);
1130 }
1131 }
1132 break;
1133 case USB_HOST:
1134 clear_bit(ID, &motg->inputs);
1135 break;
1136 case USB_PERIPHERAL:
1137 set_bit(ID, &motg->inputs);
1138 if (otgsc & OTGSC_BSV)
1139 set_bit(B_SESS_VLD, &motg->inputs);
1140 else
1141 clear_bit(B_SESS_VLD, &motg->inputs);
1142 break;
1143 default:
1144 break;
1145 }
1146 }
1147
1148 static void msm_otg_sm_work(struct work_struct *w)
1149 {
1150 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1151 struct usb_otg *otg = motg->phy.otg;
1152
1153 switch (otg->phy->state) {
1154 case OTG_STATE_UNDEFINED:
1155 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1156 msm_otg_reset(otg->phy);
1157 msm_otg_init_sm(motg);
1158 otg->phy->state = OTG_STATE_B_IDLE;
1159 /* FALL THROUGH */
1160 case OTG_STATE_B_IDLE:
1161 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1162 if (!test_bit(ID, &motg->inputs) && otg->host) {
1163 /* disable BSV bit */
1164 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1165 msm_otg_start_host(otg->phy, 1);
1166 otg->phy->state = OTG_STATE_A_HOST;
1167 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1168 switch (motg->chg_state) {
1169 case USB_CHG_STATE_UNDEFINED:
1170 msm_chg_detect_work(&motg->chg_work.work);
1171 break;
1172 case USB_CHG_STATE_DETECTED:
1173 switch (motg->chg_type) {
1174 case USB_DCP_CHARGER:
1175 msm_otg_notify_charger(motg,
1176 IDEV_CHG_MAX);
1177 break;
1178 case USB_CDP_CHARGER:
1179 msm_otg_notify_charger(motg,
1180 IDEV_CHG_MAX);
1181 msm_otg_start_peripheral(otg->phy, 1);
1182 otg->phy->state
1183 = OTG_STATE_B_PERIPHERAL;
1184 break;
1185 case USB_SDP_CHARGER:
1186 msm_otg_notify_charger(motg, IUNIT);
1187 msm_otg_start_peripheral(otg->phy, 1);
1188 otg->phy->state
1189 = OTG_STATE_B_PERIPHERAL;
1190 break;
1191 default:
1192 break;
1193 }
1194 break;
1195 default:
1196 break;
1197 }
1198 } else {
1199 /*
1200 * If charger detection work is pending, decrement
1201 * the pm usage counter to balance with the one that
1202 * is incremented in charger detection work.
1203 */
1204 if (cancel_delayed_work_sync(&motg->chg_work)) {
1205 pm_runtime_put_sync(otg->phy->dev);
1206 msm_otg_reset(otg->phy);
1207 }
1208 msm_otg_notify_charger(motg, 0);
1209 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1210 motg->chg_type = USB_INVALID_CHARGER;
1211 }
1212 pm_runtime_put_sync(otg->phy->dev);
1213 break;
1214 case OTG_STATE_B_PERIPHERAL:
1215 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1216 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1217 !test_bit(ID, &motg->inputs)) {
1218 msm_otg_notify_charger(motg, 0);
1219 msm_otg_start_peripheral(otg->phy, 0);
1220 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1221 motg->chg_type = USB_INVALID_CHARGER;
1222 otg->phy->state = OTG_STATE_B_IDLE;
1223 msm_otg_reset(otg->phy);
1224 schedule_work(w);
1225 }
1226 break;
1227 case OTG_STATE_A_HOST:
1228 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1229 if (test_bit(ID, &motg->inputs)) {
1230 msm_otg_start_host(otg->phy, 0);
1231 otg->phy->state = OTG_STATE_B_IDLE;
1232 msm_otg_reset(otg->phy);
1233 schedule_work(w);
1234 }
1235 break;
1236 default:
1237 break;
1238 }
1239 }
1240
1241 static irqreturn_t msm_otg_irq(int irq, void *data)
1242 {
1243 struct msm_otg *motg = data;
1244 struct usb_phy *phy = &motg->phy;
1245 u32 otgsc = 0;
1246
1247 if (atomic_read(&motg->in_lpm)) {
1248 disable_irq_nosync(irq);
1249 motg->async_int = 1;
1250 pm_runtime_get(phy->dev);
1251 return IRQ_HANDLED;
1252 }
1253
1254 otgsc = readl(USB_OTGSC);
1255 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1256 return IRQ_NONE;
1257
1258 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1259 if (otgsc & OTGSC_ID)
1260 set_bit(ID, &motg->inputs);
1261 else
1262 clear_bit(ID, &motg->inputs);
1263 dev_dbg(phy->dev, "ID set/clear\n");
1264 pm_runtime_get_noresume(phy->dev);
1265 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1266 if (otgsc & OTGSC_BSV)
1267 set_bit(B_SESS_VLD, &motg->inputs);
1268 else
1269 clear_bit(B_SESS_VLD, &motg->inputs);
1270 dev_dbg(phy->dev, "BSV set/clear\n");
1271 pm_runtime_get_noresume(phy->dev);
1272 }
1273
1274 writel(otgsc, USB_OTGSC);
1275 schedule_work(&motg->sm_work);
1276 return IRQ_HANDLED;
1277 }
1278
1279 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1280 {
1281 struct msm_otg *motg = s->private;
1282 struct usb_otg *otg = motg->phy.otg;
1283
1284 switch (otg->phy->state) {
1285 case OTG_STATE_A_HOST:
1286 seq_printf(s, "host\n");
1287 break;
1288 case OTG_STATE_B_PERIPHERAL:
1289 seq_printf(s, "peripheral\n");
1290 break;
1291 default:
1292 seq_printf(s, "none\n");
1293 break;
1294 }
1295
1296 return 0;
1297 }
1298
1299 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1300 {
1301 return single_open(file, msm_otg_mode_show, inode->i_private);
1302 }
1303
1304 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1305 size_t count, loff_t *ppos)
1306 {
1307 struct seq_file *s = file->private_data;
1308 struct msm_otg *motg = s->private;
1309 char buf[16];
1310 struct usb_otg *otg = motg->phy.otg;
1311 int status = count;
1312 enum usb_mode_type req_mode;
1313
1314 memset(buf, 0x00, sizeof(buf));
1315
1316 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1317 status = -EFAULT;
1318 goto out;
1319 }
1320
1321 if (!strncmp(buf, "host", 4)) {
1322 req_mode = USB_HOST;
1323 } else if (!strncmp(buf, "peripheral", 10)) {
1324 req_mode = USB_PERIPHERAL;
1325 } else if (!strncmp(buf, "none", 4)) {
1326 req_mode = USB_NONE;
1327 } else {
1328 status = -EINVAL;
1329 goto out;
1330 }
1331
1332 switch (req_mode) {
1333 case USB_NONE:
1334 switch (otg->phy->state) {
1335 case OTG_STATE_A_HOST:
1336 case OTG_STATE_B_PERIPHERAL:
1337 set_bit(ID, &motg->inputs);
1338 clear_bit(B_SESS_VLD, &motg->inputs);
1339 break;
1340 default:
1341 goto out;
1342 }
1343 break;
1344 case USB_PERIPHERAL:
1345 switch (otg->phy->state) {
1346 case OTG_STATE_B_IDLE:
1347 case OTG_STATE_A_HOST:
1348 set_bit(ID, &motg->inputs);
1349 set_bit(B_SESS_VLD, &motg->inputs);
1350 break;
1351 default:
1352 goto out;
1353 }
1354 break;
1355 case USB_HOST:
1356 switch (otg->phy->state) {
1357 case OTG_STATE_B_IDLE:
1358 case OTG_STATE_B_PERIPHERAL:
1359 clear_bit(ID, &motg->inputs);
1360 break;
1361 default:
1362 goto out;
1363 }
1364 break;
1365 default:
1366 goto out;
1367 }
1368
1369 pm_runtime_get_sync(otg->phy->dev);
1370 schedule_work(&motg->sm_work);
1371 out:
1372 return status;
1373 }
1374
1375 const struct file_operations msm_otg_mode_fops = {
1376 .open = msm_otg_mode_open,
1377 .read = seq_read,
1378 .write = msm_otg_mode_write,
1379 .llseek = seq_lseek,
1380 .release = single_release,
1381 };
1382
1383 static struct dentry *msm_otg_dbg_root;
1384 static struct dentry *msm_otg_dbg_mode;
1385
1386 static int msm_otg_debugfs_init(struct msm_otg *motg)
1387 {
1388 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1389
1390 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1391 return -ENODEV;
1392
1393 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1394 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1395 if (!msm_otg_dbg_mode) {
1396 debugfs_remove(msm_otg_dbg_root);
1397 msm_otg_dbg_root = NULL;
1398 return -ENODEV;
1399 }
1400
1401 return 0;
1402 }
1403
1404 static void msm_otg_debugfs_cleanup(void)
1405 {
1406 debugfs_remove(msm_otg_dbg_mode);
1407 debugfs_remove(msm_otg_dbg_root);
1408 }
1409
1410 static int __init msm_otg_probe(struct platform_device *pdev)
1411 {
1412 int ret = 0;
1413 struct resource *res;
1414 struct msm_otg *motg;
1415 struct usb_phy *phy;
1416
1417 dev_info(&pdev->dev, "msm_otg probe\n");
1418 if (!dev_get_platdata(&pdev->dev)) {
1419 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1420 return -ENODEV;
1421 }
1422
1423 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1424 if (!motg) {
1425 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1426 return -ENOMEM;
1427 }
1428
1429 motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
1430 if (!motg->phy.otg) {
1431 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1432 return -ENOMEM;
1433 }
1434
1435 motg->pdata = dev_get_platdata(&pdev->dev);
1436 phy = &motg->phy;
1437 phy->dev = &pdev->dev;
1438
1439 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1440 if (IS_ERR(motg->phy_reset_clk)) {
1441 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1442 ret = PTR_ERR(motg->phy_reset_clk);
1443 goto free_motg;
1444 }
1445
1446 motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1447 if (IS_ERR(motg->clk)) {
1448 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1449 ret = PTR_ERR(motg->clk);
1450 goto put_phy_reset_clk;
1451 }
1452 clk_set_rate(motg->clk, 60000000);
1453
1454 /*
1455 * If USB Core is running its protocol engine based on CORE CLK,
1456 * CORE CLK must be running at >55Mhz for correct HSUSB
1457 * operation and USB core cannot tolerate frequency changes on
1458 * CORE CLK. For such USB cores, vote for maximum clk frequency
1459 * on pclk source
1460 */
1461 if (motg->pdata->pclk_src_name) {
1462 motg->pclk_src = clk_get(&pdev->dev,
1463 motg->pdata->pclk_src_name);
1464 if (IS_ERR(motg->pclk_src))
1465 goto put_clk;
1466 clk_set_rate(motg->pclk_src, INT_MAX);
1467 clk_prepare_enable(motg->pclk_src);
1468 } else
1469 motg->pclk_src = ERR_PTR(-ENOENT);
1470
1471
1472 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1473 if (IS_ERR(motg->pclk)) {
1474 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1475 ret = PTR_ERR(motg->pclk);
1476 goto put_pclk_src;
1477 }
1478
1479 /*
1480 * USB core clock is not present on all MSM chips. This
1481 * clock is introduced to remove the dependency on AXI
1482 * bus frequency.
1483 */
1484 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1485 if (IS_ERR(motg->core_clk))
1486 motg->core_clk = NULL;
1487
1488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1489 if (!res) {
1490 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1491 ret = -ENODEV;
1492 goto put_core_clk;
1493 }
1494
1495 motg->regs = ioremap(res->start, resource_size(res));
1496 if (!motg->regs) {
1497 dev_err(&pdev->dev, "ioremap failed\n");
1498 ret = -ENOMEM;
1499 goto put_core_clk;
1500 }
1501 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1502
1503 motg->irq = platform_get_irq(pdev, 0);
1504 if (!motg->irq) {
1505 dev_err(&pdev->dev, "platform_get_irq failed\n");
1506 ret = -ENODEV;
1507 goto free_regs;
1508 }
1509
1510 clk_prepare_enable(motg->clk);
1511 clk_prepare_enable(motg->pclk);
1512
1513 ret = msm_hsusb_init_vddcx(motg, 1);
1514 if (ret) {
1515 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1516 goto free_regs;
1517 }
1518
1519 ret = msm_hsusb_ldo_init(motg, 1);
1520 if (ret) {
1521 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1522 goto vddcx_exit;
1523 }
1524 ret = msm_hsusb_ldo_set_mode(1);
1525 if (ret) {
1526 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1527 goto ldo_exit;
1528 }
1529
1530 if (motg->core_clk)
1531 clk_prepare_enable(motg->core_clk);
1532
1533 writel(0, USB_USBINTR);
1534 writel(0, USB_OTGSC);
1535
1536 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1537 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1538 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1539 "msm_otg", motg);
1540 if (ret) {
1541 dev_err(&pdev->dev, "request irq failed\n");
1542 goto disable_clks;
1543 }
1544
1545 phy->init = msm_otg_reset;
1546 phy->set_power = msm_otg_set_power;
1547
1548 phy->io_ops = &msm_otg_io_ops;
1549
1550 phy->otg->phy = &motg->phy;
1551 phy->otg->set_host = msm_otg_set_host;
1552 phy->otg->set_peripheral = msm_otg_set_peripheral;
1553
1554 ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1555 if (ret) {
1556 dev_err(&pdev->dev, "usb_add_phy failed\n");
1557 goto free_irq;
1558 }
1559
1560 platform_set_drvdata(pdev, motg);
1561 device_init_wakeup(&pdev->dev, 1);
1562
1563 if (motg->pdata->mode == USB_OTG &&
1564 motg->pdata->otg_control == OTG_USER_CONTROL) {
1565 ret = msm_otg_debugfs_init(motg);
1566 if (ret)
1567 dev_dbg(&pdev->dev, "mode debugfs file is"
1568 "not available\n");
1569 }
1570
1571 pm_runtime_set_active(&pdev->dev);
1572 pm_runtime_enable(&pdev->dev);
1573
1574 return 0;
1575 free_irq:
1576 free_irq(motg->irq, motg);
1577 disable_clks:
1578 clk_disable_unprepare(motg->pclk);
1579 clk_disable_unprepare(motg->clk);
1580 ldo_exit:
1581 msm_hsusb_ldo_init(motg, 0);
1582 vddcx_exit:
1583 msm_hsusb_init_vddcx(motg, 0);
1584 free_regs:
1585 iounmap(motg->regs);
1586 put_core_clk:
1587 if (motg->core_clk)
1588 clk_put(motg->core_clk);
1589 clk_put(motg->pclk);
1590 put_pclk_src:
1591 if (!IS_ERR(motg->pclk_src)) {
1592 clk_disable_unprepare(motg->pclk_src);
1593 clk_put(motg->pclk_src);
1594 }
1595 put_clk:
1596 clk_put(motg->clk);
1597 put_phy_reset_clk:
1598 clk_put(motg->phy_reset_clk);
1599 free_motg:
1600 kfree(motg->phy.otg);
1601 kfree(motg);
1602 return ret;
1603 }
1604
1605 static int msm_otg_remove(struct platform_device *pdev)
1606 {
1607 struct msm_otg *motg = platform_get_drvdata(pdev);
1608 struct usb_phy *phy = &motg->phy;
1609 int cnt = 0;
1610
1611 if (phy->otg->host || phy->otg->gadget)
1612 return -EBUSY;
1613
1614 msm_otg_debugfs_cleanup();
1615 cancel_delayed_work_sync(&motg->chg_work);
1616 cancel_work_sync(&motg->sm_work);
1617
1618 pm_runtime_resume(&pdev->dev);
1619
1620 device_init_wakeup(&pdev->dev, 0);
1621 pm_runtime_disable(&pdev->dev);
1622
1623 usb_remove_phy(phy);
1624 free_irq(motg->irq, motg);
1625
1626 /*
1627 * Put PHY in low power mode.
1628 */
1629 ulpi_read(phy, 0x14);
1630 ulpi_write(phy, 0x08, 0x09);
1631
1632 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1633 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1634 if (readl(USB_PORTSC) & PORTSC_PHCD)
1635 break;
1636 udelay(1);
1637 cnt++;
1638 }
1639 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1640 dev_err(phy->dev, "Unable to suspend PHY\n");
1641
1642 clk_disable_unprepare(motg->pclk);
1643 clk_disable_unprepare(motg->clk);
1644 if (motg->core_clk)
1645 clk_disable_unprepare(motg->core_clk);
1646 if (!IS_ERR(motg->pclk_src)) {
1647 clk_disable_unprepare(motg->pclk_src);
1648 clk_put(motg->pclk_src);
1649 }
1650 msm_hsusb_ldo_init(motg, 0);
1651
1652 iounmap(motg->regs);
1653 pm_runtime_set_suspended(&pdev->dev);
1654
1655 clk_put(motg->phy_reset_clk);
1656 clk_put(motg->pclk);
1657 clk_put(motg->clk);
1658 if (motg->core_clk)
1659 clk_put(motg->core_clk);
1660
1661 kfree(motg->phy.otg);
1662 kfree(motg);
1663
1664 return 0;
1665 }
1666
1667 #ifdef CONFIG_PM_RUNTIME
1668 static int msm_otg_runtime_idle(struct device *dev)
1669 {
1670 struct msm_otg *motg = dev_get_drvdata(dev);
1671 struct usb_otg *otg = motg->phy.otg;
1672
1673 dev_dbg(dev, "OTG runtime idle\n");
1674
1675 /*
1676 * It is observed some times that a spurious interrupt
1677 * comes when PHY is put into LPM immediately after PHY reset.
1678 * This 1 sec delay also prevents entering into LPM immediately
1679 * after asynchronous interrupt.
1680 */
1681 if (otg->phy->state != OTG_STATE_UNDEFINED)
1682 pm_schedule_suspend(dev, 1000);
1683
1684 return -EAGAIN;
1685 }
1686
1687 static int msm_otg_runtime_suspend(struct device *dev)
1688 {
1689 struct msm_otg *motg = dev_get_drvdata(dev);
1690
1691 dev_dbg(dev, "OTG runtime suspend\n");
1692 return msm_otg_suspend(motg);
1693 }
1694
1695 static int msm_otg_runtime_resume(struct device *dev)
1696 {
1697 struct msm_otg *motg = dev_get_drvdata(dev);
1698
1699 dev_dbg(dev, "OTG runtime resume\n");
1700 return msm_otg_resume(motg);
1701 }
1702 #endif
1703
1704 #ifdef CONFIG_PM_SLEEP
1705 static int msm_otg_pm_suspend(struct device *dev)
1706 {
1707 struct msm_otg *motg = dev_get_drvdata(dev);
1708
1709 dev_dbg(dev, "OTG PM suspend\n");
1710 return msm_otg_suspend(motg);
1711 }
1712
1713 static int msm_otg_pm_resume(struct device *dev)
1714 {
1715 struct msm_otg *motg = dev_get_drvdata(dev);
1716 int ret;
1717
1718 dev_dbg(dev, "OTG PM resume\n");
1719
1720 ret = msm_otg_resume(motg);
1721 if (ret)
1722 return ret;
1723
1724 /*
1725 * Runtime PM Documentation recommends bringing the
1726 * device to full powered state upon resume.
1727 */
1728 pm_runtime_disable(dev);
1729 pm_runtime_set_active(dev);
1730 pm_runtime_enable(dev);
1731
1732 return 0;
1733 }
1734 #endif
1735
1736 #ifdef CONFIG_PM
1737 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1738 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1739 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1740 msm_otg_runtime_idle)
1741 };
1742 #endif
1743
1744 static struct platform_driver msm_otg_driver = {
1745 .remove = msm_otg_remove,
1746 .driver = {
1747 .name = DRIVER_NAME,
1748 .owner = THIS_MODULE,
1749 #ifdef CONFIG_PM
1750 .pm = &msm_otg_dev_pm_ops,
1751 #endif
1752 },
1753 };
1754
1755 module_platform_driver_probe(msm_otg_driver, msm_otg_probe);
1756
1757 MODULE_LICENSE("GPL v2");
1758 MODULE_DESCRIPTION("MSM USB transceiver driver");
ubuntu-bionic-kernel mirror