]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/usb/phy/phy-msm-usb.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'trace-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux...
[mirror_ubuntu-bionic-kernel.git] / drivers / usb / phy / phy-msm-usb.c
1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
33
34 #include <linux/usb.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/usb/msm_hsusb.h>
40 #include <linux/usb/msm_hsusb_hw.h>
41 #include <linux/regulator/consumer.h>
42
43 #include <mach/clk.h>
44
45 #define MSM_USB_BASE (motg->regs)
46 #define DRIVER_NAME "msm_otg"
47
48 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
49
50 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
51 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
52 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
53 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
54
55 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
56 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
57 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
58 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
59
60 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
61 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
62
63 static struct regulator *hsusb_3p3;
64 static struct regulator *hsusb_1p8;
65 static struct regulator *hsusb_vddcx;
66
67 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
68 {
69 int ret = 0;
70
71 if (init) {
72 hsusb_vddcx = regulator_get(motg->phy.dev, "HSUSB_VDDCX");
73 if (IS_ERR(hsusb_vddcx)) {
74 dev_err(motg->phy.dev, "unable to get hsusb vddcx\n");
75 return PTR_ERR(hsusb_vddcx);
76 }
77
78 ret = regulator_set_voltage(hsusb_vddcx,
79 USB_PHY_VDD_DIG_VOL_MIN,
80 USB_PHY_VDD_DIG_VOL_MAX);
81 if (ret) {
82 dev_err(motg->phy.dev, "unable to set the voltage "
83 "for hsusb vddcx\n");
84 regulator_put(hsusb_vddcx);
85 return ret;
86 }
87
88 ret = regulator_enable(hsusb_vddcx);
89 if (ret) {
90 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
91 regulator_put(hsusb_vddcx);
92 }
93 } else {
94 ret = regulator_set_voltage(hsusb_vddcx, 0,
95 USB_PHY_VDD_DIG_VOL_MAX);
96 if (ret)
97 dev_err(motg->phy.dev, "unable to set the voltage "
98 "for hsusb vddcx\n");
99 ret = regulator_disable(hsusb_vddcx);
100 if (ret)
101 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
102
103 regulator_put(hsusb_vddcx);
104 }
105
106 return ret;
107 }
108
109 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
110 {
111 int rc = 0;
112
113 if (init) {
114 hsusb_3p3 = regulator_get(motg->phy.dev, "HSUSB_3p3");
115 if (IS_ERR(hsusb_3p3)) {
116 dev_err(motg->phy.dev, "unable to get hsusb 3p3\n");
117 return PTR_ERR(hsusb_3p3);
118 }
119
120 rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
121 USB_PHY_3P3_VOL_MAX);
122 if (rc) {
123 dev_err(motg->phy.dev, "unable to set voltage level "
124 "for hsusb 3p3\n");
125 goto put_3p3;
126 }
127 rc = regulator_enable(hsusb_3p3);
128 if (rc) {
129 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
130 goto put_3p3;
131 }
132 hsusb_1p8 = regulator_get(motg->phy.dev, "HSUSB_1p8");
133 if (IS_ERR(hsusb_1p8)) {
134 dev_err(motg->phy.dev, "unable to get hsusb 1p8\n");
135 rc = PTR_ERR(hsusb_1p8);
136 goto disable_3p3;
137 }
138 rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
139 USB_PHY_1P8_VOL_MAX);
140 if (rc) {
141 dev_err(motg->phy.dev, "unable to set voltage level "
142 "for hsusb 1p8\n");
143 goto put_1p8;
144 }
145 rc = regulator_enable(hsusb_1p8);
146 if (rc) {
147 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
148 goto put_1p8;
149 }
150
151 return 0;
152 }
153
154 regulator_disable(hsusb_1p8);
155 put_1p8:
156 regulator_put(hsusb_1p8);
157 disable_3p3:
158 regulator_disable(hsusb_3p3);
159 put_3p3:
160 regulator_put(hsusb_3p3);
161 return rc;
162 }
163
164 #ifdef CONFIG_PM_SLEEP
165 #define USB_PHY_SUSP_DIG_VOL 500000
166 static int msm_hsusb_config_vddcx(int high)
167 {
168 int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
169 int min_vol;
170 int ret;
171
172 if (high)
173 min_vol = USB_PHY_VDD_DIG_VOL_MIN;
174 else
175 min_vol = USB_PHY_SUSP_DIG_VOL;
176
177 ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
178 if (ret) {
179 pr_err("%s: unable to set the voltage for regulator "
180 "HSUSB_VDDCX\n", __func__);
181 return ret;
182 }
183
184 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
185
186 return ret;
187 }
188 #endif
189
190 static int msm_hsusb_ldo_set_mode(int on)
191 {
192 int ret = 0;
193
194 if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
195 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
196 return -ENODEV;
197 }
198
199 if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
200 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
201 return -ENODEV;
202 }
203
204 if (on) {
205 ret = regulator_set_optimum_mode(hsusb_1p8,
206 USB_PHY_1P8_HPM_LOAD);
207 if (ret < 0) {
208 pr_err("%s: Unable to set HPM of the regulator "
209 "HSUSB_1p8\n", __func__);
210 return ret;
211 }
212 ret = regulator_set_optimum_mode(hsusb_3p3,
213 USB_PHY_3P3_HPM_LOAD);
214 if (ret < 0) {
215 pr_err("%s: Unable to set HPM of the regulator "
216 "HSUSB_3p3\n", __func__);
217 regulator_set_optimum_mode(hsusb_1p8,
218 USB_PHY_1P8_LPM_LOAD);
219 return ret;
220 }
221 } else {
222 ret = regulator_set_optimum_mode(hsusb_1p8,
223 USB_PHY_1P8_LPM_LOAD);
224 if (ret < 0)
225 pr_err("%s: Unable to set LPM of the regulator "
226 "HSUSB_1p8\n", __func__);
227 ret = regulator_set_optimum_mode(hsusb_3p3,
228 USB_PHY_3P3_LPM_LOAD);
229 if (ret < 0)
230 pr_err("%s: Unable to set LPM of the regulator "
231 "HSUSB_3p3\n", __func__);
232 }
233
234 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
235 return ret < 0 ? ret : 0;
236 }
237
238 static int ulpi_read(struct usb_phy *phy, u32 reg)
239 {
240 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
241 int cnt = 0;
242
243 /* initiate read operation */
244 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
245 USB_ULPI_VIEWPORT);
246
247 /* wait for completion */
248 while (cnt < ULPI_IO_TIMEOUT_USEC) {
249 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
250 break;
251 udelay(1);
252 cnt++;
253 }
254
255 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
256 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
257 readl(USB_ULPI_VIEWPORT));
258 return -ETIMEDOUT;
259 }
260 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
261 }
262
263 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
264 {
265 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
266 int cnt = 0;
267
268 /* initiate write operation */
269 writel(ULPI_RUN | ULPI_WRITE |
270 ULPI_ADDR(reg) | ULPI_DATA(val),
271 USB_ULPI_VIEWPORT);
272
273 /* wait for completion */
274 while (cnt < ULPI_IO_TIMEOUT_USEC) {
275 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
276 break;
277 udelay(1);
278 cnt++;
279 }
280
281 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
282 dev_err(phy->dev, "ulpi_write: timeout\n");
283 return -ETIMEDOUT;
284 }
285 return 0;
286 }
287
288 static struct usb_phy_io_ops msm_otg_io_ops = {
289 .read = ulpi_read,
290 .write = ulpi_write,
291 };
292
293 static void ulpi_init(struct msm_otg *motg)
294 {
295 struct msm_otg_platform_data *pdata = motg->pdata;
296 int *seq = pdata->phy_init_seq;
297
298 if (!seq)
299 return;
300
301 while (seq[0] >= 0) {
302 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
303 seq[0], seq[1]);
304 ulpi_write(&motg->phy, seq[0], seq[1]);
305 seq += 2;
306 }
307 }
308
309 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
310 {
311 int ret;
312
313 if (assert) {
314 ret = clk_reset(motg->clk, CLK_RESET_ASSERT);
315 if (ret)
316 dev_err(motg->phy.dev, "usb hs_clk assert failed\n");
317 } else {
318 ret = clk_reset(motg->clk, CLK_RESET_DEASSERT);
319 if (ret)
320 dev_err(motg->phy.dev, "usb hs_clk deassert failed\n");
321 }
322 return ret;
323 }
324
325 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
326 {
327 int ret;
328
329 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_ASSERT);
330 if (ret) {
331 dev_err(motg->phy.dev, "usb phy clk assert failed\n");
332 return ret;
333 }
334 usleep_range(10000, 12000);
335 ret = clk_reset(motg->phy_reset_clk, CLK_RESET_DEASSERT);
336 if (ret)
337 dev_err(motg->phy.dev, "usb phy clk deassert failed\n");
338 return ret;
339 }
340
341 static int msm_otg_phy_reset(struct msm_otg *motg)
342 {
343 u32 val;
344 int ret;
345 int retries;
346
347 ret = msm_otg_link_clk_reset(motg, 1);
348 if (ret)
349 return ret;
350 ret = msm_otg_phy_clk_reset(motg);
351 if (ret)
352 return ret;
353 ret = msm_otg_link_clk_reset(motg, 0);
354 if (ret)
355 return ret;
356
357 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
358 writel(val | PORTSC_PTS_ULPI, USB_PORTSC);
359
360 for (retries = 3; retries > 0; retries--) {
361 ret = ulpi_write(&motg->phy, ULPI_FUNC_CTRL_SUSPENDM,
362 ULPI_CLR(ULPI_FUNC_CTRL));
363 if (!ret)
364 break;
365 ret = msm_otg_phy_clk_reset(motg);
366 if (ret)
367 return ret;
368 }
369 if (!retries)
370 return -ETIMEDOUT;
371
372 /* This reset calibrates the phy, if the above write succeeded */
373 ret = msm_otg_phy_clk_reset(motg);
374 if (ret)
375 return ret;
376
377 for (retries = 3; retries > 0; retries--) {
378 ret = ulpi_read(&motg->phy, ULPI_DEBUG);
379 if (ret != -ETIMEDOUT)
380 break;
381 ret = msm_otg_phy_clk_reset(motg);
382 if (ret)
383 return ret;
384 }
385 if (!retries)
386 return -ETIMEDOUT;
387
388 dev_info(motg->phy.dev, "phy_reset: success\n");
389 return 0;
390 }
391
392 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
393 static int msm_otg_reset(struct usb_phy *phy)
394 {
395 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
396 struct msm_otg_platform_data *pdata = motg->pdata;
397 int cnt = 0;
398 int ret;
399 u32 val = 0;
400 u32 ulpi_val = 0;
401
402 ret = msm_otg_phy_reset(motg);
403 if (ret) {
404 dev_err(phy->dev, "phy_reset failed\n");
405 return ret;
406 }
407
408 ulpi_init(motg);
409
410 writel(USBCMD_RESET, USB_USBCMD);
411 while (cnt < LINK_RESET_TIMEOUT_USEC) {
412 if (!(readl(USB_USBCMD) & USBCMD_RESET))
413 break;
414 udelay(1);
415 cnt++;
416 }
417 if (cnt >= LINK_RESET_TIMEOUT_USEC)
418 return -ETIMEDOUT;
419
420 /* select ULPI phy */
421 writel(0x80000000, USB_PORTSC);
422
423 msleep(100);
424
425 writel(0x0, USB_AHBBURST);
426 writel(0x00, USB_AHBMODE);
427
428 if (pdata->otg_control == OTG_PHY_CONTROL) {
429 val = readl(USB_OTGSC);
430 if (pdata->mode == USB_OTG) {
431 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
432 val |= OTGSC_IDIE | OTGSC_BSVIE;
433 } else if (pdata->mode == USB_PERIPHERAL) {
434 ulpi_val = ULPI_INT_SESS_VALID;
435 val |= OTGSC_BSVIE;
436 }
437 writel(val, USB_OTGSC);
438 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
439 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
440 }
441
442 return 0;
443 }
444
445 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
446 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
447
448 #ifdef CONFIG_PM_SLEEP
449 static int msm_otg_suspend(struct msm_otg *motg)
450 {
451 struct usb_phy *phy = &motg->phy;
452 struct usb_bus *bus = phy->otg->host;
453 struct msm_otg_platform_data *pdata = motg->pdata;
454 int cnt = 0;
455
456 if (atomic_read(&motg->in_lpm))
457 return 0;
458
459 disable_irq(motg->irq);
460 /*
461 * Chipidea 45-nm PHY suspend sequence:
462 *
463 * Interrupt Latch Register auto-clear feature is not present
464 * in all PHY versions. Latch register is clear on read type.
465 * Clear latch register to avoid spurious wakeup from
466 * low power mode (LPM).
467 *
468 * PHY comparators are disabled when PHY enters into low power
469 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
470 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
471 * PHY comparators. This save significant amount of power.
472 *
473 * PLL is not turned off when PHY enters into low power mode (LPM).
474 * Disable PLL for maximum power savings.
475 */
476
477 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
478 ulpi_read(phy, 0x14);
479 if (pdata->otg_control == OTG_PHY_CONTROL)
480 ulpi_write(phy, 0x01, 0x30);
481 ulpi_write(phy, 0x08, 0x09);
482 }
483
484 /*
485 * PHY may take some time or even fail to enter into low power
486 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
487 * in failure case.
488 */
489 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
490 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
491 if (readl(USB_PORTSC) & PORTSC_PHCD)
492 break;
493 udelay(1);
494 cnt++;
495 }
496
497 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
498 dev_err(phy->dev, "Unable to suspend PHY\n");
499 msm_otg_reset(phy);
500 enable_irq(motg->irq);
501 return -ETIMEDOUT;
502 }
503
504 /*
505 * PHY has capability to generate interrupt asynchronously in low
506 * power mode (LPM). This interrupt is level triggered. So USB IRQ
507 * line must be disabled till async interrupt enable bit is cleared
508 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
509 * block data communication from PHY.
510 */
511 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
512
513 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
514 motg->pdata->otg_control == OTG_PMIC_CONTROL)
515 writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
516
517 clk_disable_unprepare(motg->pclk);
518 clk_disable_unprepare(motg->clk);
519 if (motg->core_clk)
520 clk_disable_unprepare(motg->core_clk);
521
522 if (!IS_ERR(motg->pclk_src))
523 clk_disable_unprepare(motg->pclk_src);
524
525 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
526 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
527 msm_hsusb_ldo_set_mode(0);
528 msm_hsusb_config_vddcx(0);
529 }
530
531 if (device_may_wakeup(phy->dev))
532 enable_irq_wake(motg->irq);
533 if (bus)
534 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
535
536 atomic_set(&motg->in_lpm, 1);
537 enable_irq(motg->irq);
538
539 dev_info(phy->dev, "USB in low power mode\n");
540
541 return 0;
542 }
543
544 static int msm_otg_resume(struct msm_otg *motg)
545 {
546 struct usb_phy *phy = &motg->phy;
547 struct usb_bus *bus = phy->otg->host;
548 int cnt = 0;
549 unsigned temp;
550
551 if (!atomic_read(&motg->in_lpm))
552 return 0;
553
554 if (!IS_ERR(motg->pclk_src))
555 clk_prepare_enable(motg->pclk_src);
556
557 clk_prepare_enable(motg->pclk);
558 clk_prepare_enable(motg->clk);
559 if (motg->core_clk)
560 clk_prepare_enable(motg->core_clk);
561
562 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
563 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
564 msm_hsusb_ldo_set_mode(1);
565 msm_hsusb_config_vddcx(1);
566 writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
567 }
568
569 temp = readl(USB_USBCMD);
570 temp &= ~ASYNC_INTR_CTRL;
571 temp &= ~ULPI_STP_CTRL;
572 writel(temp, USB_USBCMD);
573
574 /*
575 * PHY comes out of low power mode (LPM) in case of wakeup
576 * from asynchronous interrupt.
577 */
578 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
579 goto skip_phy_resume;
580
581 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
582 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
583 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
584 break;
585 udelay(1);
586 cnt++;
587 }
588
589 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
590 /*
591 * This is a fatal error. Reset the link and
592 * PHY. USB state can not be restored. Re-insertion
593 * of USB cable is the only way to get USB working.
594 */
595 dev_err(phy->dev, "Unable to resume USB."
596 "Re-plugin the cable\n");
597 msm_otg_reset(phy);
598 }
599
600 skip_phy_resume:
601 if (device_may_wakeup(phy->dev))
602 disable_irq_wake(motg->irq);
603 if (bus)
604 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
605
606 atomic_set(&motg->in_lpm, 0);
607
608 if (motg->async_int) {
609 motg->async_int = 0;
610 pm_runtime_put(phy->dev);
611 enable_irq(motg->irq);
612 }
613
614 dev_info(phy->dev, "USB exited from low power mode\n");
615
616 return 0;
617 }
618 #endif
619
620 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
621 {
622 if (motg->cur_power == mA)
623 return;
624
625 /* TODO: Notify PMIC about available current */
626 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
627 motg->cur_power = mA;
628 }
629
630 static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
631 {
632 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
633
634 /*
635 * Gadget driver uses set_power method to notify about the
636 * available current based on suspend/configured states.
637 *
638 * IDEV_CHG can be drawn irrespective of suspend/un-configured
639 * states when CDP/ACA is connected.
640 */
641 if (motg->chg_type == USB_SDP_CHARGER)
642 msm_otg_notify_charger(motg, mA);
643
644 return 0;
645 }
646
647 static void msm_otg_start_host(struct usb_phy *phy, int on)
648 {
649 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
650 struct msm_otg_platform_data *pdata = motg->pdata;
651 struct usb_hcd *hcd;
652
653 if (!phy->otg->host)
654 return;
655
656 hcd = bus_to_hcd(phy->otg->host);
657
658 if (on) {
659 dev_dbg(phy->dev, "host on\n");
660
661 if (pdata->vbus_power)
662 pdata->vbus_power(1);
663 /*
664 * Some boards have a switch cotrolled by gpio
665 * to enable/disable internal HUB. Enable internal
666 * HUB before kicking the host.
667 */
668 if (pdata->setup_gpio)
669 pdata->setup_gpio(OTG_STATE_A_HOST);
670 #ifdef CONFIG_USB
671 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
672 device_wakeup_enable(hcd->self.controller);
673 #endif
674 } else {
675 dev_dbg(phy->dev, "host off\n");
676
677 #ifdef CONFIG_USB
678 usb_remove_hcd(hcd);
679 #endif
680 if (pdata->setup_gpio)
681 pdata->setup_gpio(OTG_STATE_UNDEFINED);
682 if (pdata->vbus_power)
683 pdata->vbus_power(0);
684 }
685 }
686
687 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
688 {
689 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
690 struct usb_hcd *hcd;
691
692 /*
693 * Fail host registration if this board can support
694 * only peripheral configuration.
695 */
696 if (motg->pdata->mode == USB_PERIPHERAL) {
697 dev_info(otg->phy->dev, "Host mode is not supported\n");
698 return -ENODEV;
699 }
700
701 if (!host) {
702 if (otg->phy->state == OTG_STATE_A_HOST) {
703 pm_runtime_get_sync(otg->phy->dev);
704 msm_otg_start_host(otg->phy, 0);
705 otg->host = NULL;
706 otg->phy->state = OTG_STATE_UNDEFINED;
707 schedule_work(&motg->sm_work);
708 } else {
709 otg->host = NULL;
710 }
711
712 return 0;
713 }
714
715 hcd = bus_to_hcd(host);
716 hcd->power_budget = motg->pdata->power_budget;
717
718 otg->host = host;
719 dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
720
721 /*
722 * Kick the state machine work, if peripheral is not supported
723 * or peripheral is already registered with us.
724 */
725 if (motg->pdata->mode == USB_HOST || otg->gadget) {
726 pm_runtime_get_sync(otg->phy->dev);
727 schedule_work(&motg->sm_work);
728 }
729
730 return 0;
731 }
732
733 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
734 {
735 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
736 struct msm_otg_platform_data *pdata = motg->pdata;
737
738 if (!phy->otg->gadget)
739 return;
740
741 if (on) {
742 dev_dbg(phy->dev, "gadget on\n");
743 /*
744 * Some boards have a switch cotrolled by gpio
745 * to enable/disable internal HUB. Disable internal
746 * HUB before kicking the gadget.
747 */
748 if (pdata->setup_gpio)
749 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
750 usb_gadget_vbus_connect(phy->otg->gadget);
751 } else {
752 dev_dbg(phy->dev, "gadget off\n");
753 usb_gadget_vbus_disconnect(phy->otg->gadget);
754 if (pdata->setup_gpio)
755 pdata->setup_gpio(OTG_STATE_UNDEFINED);
756 }
757
758 }
759
760 static int msm_otg_set_peripheral(struct usb_otg *otg,
761 struct usb_gadget *gadget)
762 {
763 struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
764
765 /*
766 * Fail peripheral registration if this board can support
767 * only host configuration.
768 */
769 if (motg->pdata->mode == USB_HOST) {
770 dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
771 return -ENODEV;
772 }
773
774 if (!gadget) {
775 if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
776 pm_runtime_get_sync(otg->phy->dev);
777 msm_otg_start_peripheral(otg->phy, 0);
778 otg->gadget = NULL;
779 otg->phy->state = OTG_STATE_UNDEFINED;
780 schedule_work(&motg->sm_work);
781 } else {
782 otg->gadget = NULL;
783 }
784
785 return 0;
786 }
787 otg->gadget = gadget;
788 dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
789
790 /*
791 * Kick the state machine work, if host is not supported
792 * or host is already registered with us.
793 */
794 if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
795 pm_runtime_get_sync(otg->phy->dev);
796 schedule_work(&motg->sm_work);
797 }
798
799 return 0;
800 }
801
802 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
803 {
804 struct usb_phy *phy = &motg->phy;
805 u32 chg_det;
806 bool ret = false;
807
808 switch (motg->pdata->phy_type) {
809 case CI_45NM_INTEGRATED_PHY:
810 chg_det = ulpi_read(phy, 0x34);
811 ret = chg_det & (1 << 4);
812 break;
813 case SNPS_28NM_INTEGRATED_PHY:
814 chg_det = ulpi_read(phy, 0x87);
815 ret = chg_det & 1;
816 break;
817 default:
818 break;
819 }
820 return ret;
821 }
822
823 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
824 {
825 struct usb_phy *phy = &motg->phy;
826 u32 chg_det;
827
828 switch (motg->pdata->phy_type) {
829 case CI_45NM_INTEGRATED_PHY:
830 chg_det = ulpi_read(phy, 0x34);
831 /* Turn off charger block */
832 chg_det |= ~(1 << 1);
833 ulpi_write(phy, chg_det, 0x34);
834 udelay(20);
835 /* control chg block via ULPI */
836 chg_det &= ~(1 << 3);
837 ulpi_write(phy, chg_det, 0x34);
838 /* put it in host mode for enabling D- source */
839 chg_det &= ~(1 << 2);
840 ulpi_write(phy, chg_det, 0x34);
841 /* Turn on chg detect block */
842 chg_det &= ~(1 << 1);
843 ulpi_write(phy, chg_det, 0x34);
844 udelay(20);
845 /* enable chg detection */
846 chg_det &= ~(1 << 0);
847 ulpi_write(phy, chg_det, 0x34);
848 break;
849 case SNPS_28NM_INTEGRATED_PHY:
850 /*
851 * Configure DM as current source, DP as current sink
852 * and enable battery charging comparators.
853 */
854 ulpi_write(phy, 0x8, 0x85);
855 ulpi_write(phy, 0x2, 0x85);
856 ulpi_write(phy, 0x1, 0x85);
857 break;
858 default:
859 break;
860 }
861 }
862
863 static bool msm_chg_check_primary_det(struct msm_otg *motg)
864 {
865 struct usb_phy *phy = &motg->phy;
866 u32 chg_det;
867 bool ret = false;
868
869 switch (motg->pdata->phy_type) {
870 case CI_45NM_INTEGRATED_PHY:
871 chg_det = ulpi_read(phy, 0x34);
872 ret = chg_det & (1 << 4);
873 break;
874 case SNPS_28NM_INTEGRATED_PHY:
875 chg_det = ulpi_read(phy, 0x87);
876 ret = chg_det & 1;
877 break;
878 default:
879 break;
880 }
881 return ret;
882 }
883
884 static void msm_chg_enable_primary_det(struct msm_otg *motg)
885 {
886 struct usb_phy *phy = &motg->phy;
887 u32 chg_det;
888
889 switch (motg->pdata->phy_type) {
890 case CI_45NM_INTEGRATED_PHY:
891 chg_det = ulpi_read(phy, 0x34);
892 /* enable chg detection */
893 chg_det &= ~(1 << 0);
894 ulpi_write(phy, chg_det, 0x34);
895 break;
896 case SNPS_28NM_INTEGRATED_PHY:
897 /*
898 * Configure DP as current source, DM as current sink
899 * and enable battery charging comparators.
900 */
901 ulpi_write(phy, 0x2, 0x85);
902 ulpi_write(phy, 0x1, 0x85);
903 break;
904 default:
905 break;
906 }
907 }
908
909 static bool msm_chg_check_dcd(struct msm_otg *motg)
910 {
911 struct usb_phy *phy = &motg->phy;
912 u32 line_state;
913 bool ret = false;
914
915 switch (motg->pdata->phy_type) {
916 case CI_45NM_INTEGRATED_PHY:
917 line_state = ulpi_read(phy, 0x15);
918 ret = !(line_state & 1);
919 break;
920 case SNPS_28NM_INTEGRATED_PHY:
921 line_state = ulpi_read(phy, 0x87);
922 ret = line_state & 2;
923 break;
924 default:
925 break;
926 }
927 return ret;
928 }
929
930 static void msm_chg_disable_dcd(struct msm_otg *motg)
931 {
932 struct usb_phy *phy = &motg->phy;
933 u32 chg_det;
934
935 switch (motg->pdata->phy_type) {
936 case CI_45NM_INTEGRATED_PHY:
937 chg_det = ulpi_read(phy, 0x34);
938 chg_det &= ~(1 << 5);
939 ulpi_write(phy, chg_det, 0x34);
940 break;
941 case SNPS_28NM_INTEGRATED_PHY:
942 ulpi_write(phy, 0x10, 0x86);
943 break;
944 default:
945 break;
946 }
947 }
948
949 static void msm_chg_enable_dcd(struct msm_otg *motg)
950 {
951 struct usb_phy *phy = &motg->phy;
952 u32 chg_det;
953
954 switch (motg->pdata->phy_type) {
955 case CI_45NM_INTEGRATED_PHY:
956 chg_det = ulpi_read(phy, 0x34);
957 /* Turn on D+ current source */
958 chg_det |= (1 << 5);
959 ulpi_write(phy, chg_det, 0x34);
960 break;
961 case SNPS_28NM_INTEGRATED_PHY:
962 /* Data contact detection enable */
963 ulpi_write(phy, 0x10, 0x85);
964 break;
965 default:
966 break;
967 }
968 }
969
970 static void msm_chg_block_on(struct msm_otg *motg)
971 {
972 struct usb_phy *phy = &motg->phy;
973 u32 func_ctrl, chg_det;
974
975 /* put the controller in non-driving mode */
976 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
977 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
978 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
979 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
980
981 switch (motg->pdata->phy_type) {
982 case CI_45NM_INTEGRATED_PHY:
983 chg_det = ulpi_read(phy, 0x34);
984 /* control chg block via ULPI */
985 chg_det &= ~(1 << 3);
986 ulpi_write(phy, chg_det, 0x34);
987 /* Turn on chg detect block */
988 chg_det &= ~(1 << 1);
989 ulpi_write(phy, chg_det, 0x34);
990 udelay(20);
991 break;
992 case SNPS_28NM_INTEGRATED_PHY:
993 /* Clear charger detecting control bits */
994 ulpi_write(phy, 0x3F, 0x86);
995 /* Clear alt interrupt latch and enable bits */
996 ulpi_write(phy, 0x1F, 0x92);
997 ulpi_write(phy, 0x1F, 0x95);
998 udelay(100);
999 break;
1000 default:
1001 break;
1002 }
1003 }
1004
1005 static void msm_chg_block_off(struct msm_otg *motg)
1006 {
1007 struct usb_phy *phy = &motg->phy;
1008 u32 func_ctrl, chg_det;
1009
1010 switch (motg->pdata->phy_type) {
1011 case CI_45NM_INTEGRATED_PHY:
1012 chg_det = ulpi_read(phy, 0x34);
1013 /* Turn off charger block */
1014 chg_det |= ~(1 << 1);
1015 ulpi_write(phy, chg_det, 0x34);
1016 break;
1017 case SNPS_28NM_INTEGRATED_PHY:
1018 /* Clear charger detecting control bits */
1019 ulpi_write(phy, 0x3F, 0x86);
1020 /* Clear alt interrupt latch and enable bits */
1021 ulpi_write(phy, 0x1F, 0x92);
1022 ulpi_write(phy, 0x1F, 0x95);
1023 break;
1024 default:
1025 break;
1026 }
1027
1028 /* put the controller in normal mode */
1029 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1030 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1031 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1032 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1033 }
1034
1035 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1036 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1037 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1038 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1039 static void msm_chg_detect_work(struct work_struct *w)
1040 {
1041 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1042 struct usb_phy *phy = &motg->phy;
1043 bool is_dcd, tmout, vout;
1044 unsigned long delay;
1045
1046 dev_dbg(phy->dev, "chg detection work\n");
1047 switch (motg->chg_state) {
1048 case USB_CHG_STATE_UNDEFINED:
1049 pm_runtime_get_sync(phy->dev);
1050 msm_chg_block_on(motg);
1051 msm_chg_enable_dcd(motg);
1052 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1053 motg->dcd_retries = 0;
1054 delay = MSM_CHG_DCD_POLL_TIME;
1055 break;
1056 case USB_CHG_STATE_WAIT_FOR_DCD:
1057 is_dcd = msm_chg_check_dcd(motg);
1058 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1059 if (is_dcd || tmout) {
1060 msm_chg_disable_dcd(motg);
1061 msm_chg_enable_primary_det(motg);
1062 delay = MSM_CHG_PRIMARY_DET_TIME;
1063 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1064 } else {
1065 delay = MSM_CHG_DCD_POLL_TIME;
1066 }
1067 break;
1068 case USB_CHG_STATE_DCD_DONE:
1069 vout = msm_chg_check_primary_det(motg);
1070 if (vout) {
1071 msm_chg_enable_secondary_det(motg);
1072 delay = MSM_CHG_SECONDARY_DET_TIME;
1073 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1074 } else {
1075 motg->chg_type = USB_SDP_CHARGER;
1076 motg->chg_state = USB_CHG_STATE_DETECTED;
1077 delay = 0;
1078 }
1079 break;
1080 case USB_CHG_STATE_PRIMARY_DONE:
1081 vout = msm_chg_check_secondary_det(motg);
1082 if (vout)
1083 motg->chg_type = USB_DCP_CHARGER;
1084 else
1085 motg->chg_type = USB_CDP_CHARGER;
1086 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1087 /* fall through */
1088 case USB_CHG_STATE_SECONDARY_DONE:
1089 motg->chg_state = USB_CHG_STATE_DETECTED;
1090 case USB_CHG_STATE_DETECTED:
1091 msm_chg_block_off(motg);
1092 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1093 schedule_work(&motg->sm_work);
1094 return;
1095 default:
1096 return;
1097 }
1098
1099 schedule_delayed_work(&motg->chg_work, delay);
1100 }
1101
1102 /*
1103 * We support OTG, Peripheral only and Host only configurations. In case
1104 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1105 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1106 * enabled when switch is controlled by user and default mode is supplied
1107 * by board file, which can be changed by userspace later.
1108 */
1109 static void msm_otg_init_sm(struct msm_otg *motg)
1110 {
1111 struct msm_otg_platform_data *pdata = motg->pdata;
1112 u32 otgsc = readl(USB_OTGSC);
1113
1114 switch (pdata->mode) {
1115 case USB_OTG:
1116 if (pdata->otg_control == OTG_PHY_CONTROL) {
1117 if (otgsc & OTGSC_ID)
1118 set_bit(ID, &motg->inputs);
1119 else
1120 clear_bit(ID, &motg->inputs);
1121
1122 if (otgsc & OTGSC_BSV)
1123 set_bit(B_SESS_VLD, &motg->inputs);
1124 else
1125 clear_bit(B_SESS_VLD, &motg->inputs);
1126 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1127 if (pdata->default_mode == USB_HOST) {
1128 clear_bit(ID, &motg->inputs);
1129 } else if (pdata->default_mode == USB_PERIPHERAL) {
1130 set_bit(ID, &motg->inputs);
1131 set_bit(B_SESS_VLD, &motg->inputs);
1132 } else {
1133 set_bit(ID, &motg->inputs);
1134 clear_bit(B_SESS_VLD, &motg->inputs);
1135 }
1136 }
1137 break;
1138 case USB_HOST:
1139 clear_bit(ID, &motg->inputs);
1140 break;
1141 case USB_PERIPHERAL:
1142 set_bit(ID, &motg->inputs);
1143 if (otgsc & OTGSC_BSV)
1144 set_bit(B_SESS_VLD, &motg->inputs);
1145 else
1146 clear_bit(B_SESS_VLD, &motg->inputs);
1147 break;
1148 default:
1149 break;
1150 }
1151 }
1152
1153 static void msm_otg_sm_work(struct work_struct *w)
1154 {
1155 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1156 struct usb_otg *otg = motg->phy.otg;
1157
1158 switch (otg->phy->state) {
1159 case OTG_STATE_UNDEFINED:
1160 dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
1161 msm_otg_reset(otg->phy);
1162 msm_otg_init_sm(motg);
1163 otg->phy->state = OTG_STATE_B_IDLE;
1164 /* FALL THROUGH */
1165 case OTG_STATE_B_IDLE:
1166 dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
1167 if (!test_bit(ID, &motg->inputs) && otg->host) {
1168 /* disable BSV bit */
1169 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1170 msm_otg_start_host(otg->phy, 1);
1171 otg->phy->state = OTG_STATE_A_HOST;
1172 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1173 switch (motg->chg_state) {
1174 case USB_CHG_STATE_UNDEFINED:
1175 msm_chg_detect_work(&motg->chg_work.work);
1176 break;
1177 case USB_CHG_STATE_DETECTED:
1178 switch (motg->chg_type) {
1179 case USB_DCP_CHARGER:
1180 msm_otg_notify_charger(motg,
1181 IDEV_CHG_MAX);
1182 break;
1183 case USB_CDP_CHARGER:
1184 msm_otg_notify_charger(motg,
1185 IDEV_CHG_MAX);
1186 msm_otg_start_peripheral(otg->phy, 1);
1187 otg->phy->state
1188 = OTG_STATE_B_PERIPHERAL;
1189 break;
1190 case USB_SDP_CHARGER:
1191 msm_otg_notify_charger(motg, IUNIT);
1192 msm_otg_start_peripheral(otg->phy, 1);
1193 otg->phy->state
1194 = OTG_STATE_B_PERIPHERAL;
1195 break;
1196 default:
1197 break;
1198 }
1199 break;
1200 default:
1201 break;
1202 }
1203 } else {
1204 /*
1205 * If charger detection work is pending, decrement
1206 * the pm usage counter to balance with the one that
1207 * is incremented in charger detection work.
1208 */
1209 if (cancel_delayed_work_sync(&motg->chg_work)) {
1210 pm_runtime_put_sync(otg->phy->dev);
1211 msm_otg_reset(otg->phy);
1212 }
1213 msm_otg_notify_charger(motg, 0);
1214 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1215 motg->chg_type = USB_INVALID_CHARGER;
1216 }
1217 pm_runtime_put_sync(otg->phy->dev);
1218 break;
1219 case OTG_STATE_B_PERIPHERAL:
1220 dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1221 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1222 !test_bit(ID, &motg->inputs)) {
1223 msm_otg_notify_charger(motg, 0);
1224 msm_otg_start_peripheral(otg->phy, 0);
1225 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1226 motg->chg_type = USB_INVALID_CHARGER;
1227 otg->phy->state = OTG_STATE_B_IDLE;
1228 msm_otg_reset(otg->phy);
1229 schedule_work(w);
1230 }
1231 break;
1232 case OTG_STATE_A_HOST:
1233 dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
1234 if (test_bit(ID, &motg->inputs)) {
1235 msm_otg_start_host(otg->phy, 0);
1236 otg->phy->state = OTG_STATE_B_IDLE;
1237 msm_otg_reset(otg->phy);
1238 schedule_work(w);
1239 }
1240 break;
1241 default:
1242 break;
1243 }
1244 }
1245
1246 static irqreturn_t msm_otg_irq(int irq, void *data)
1247 {
1248 struct msm_otg *motg = data;
1249 struct usb_phy *phy = &motg->phy;
1250 u32 otgsc = 0;
1251
1252 if (atomic_read(&motg->in_lpm)) {
1253 disable_irq_nosync(irq);
1254 motg->async_int = 1;
1255 pm_runtime_get(phy->dev);
1256 return IRQ_HANDLED;
1257 }
1258
1259 otgsc = readl(USB_OTGSC);
1260 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1261 return IRQ_NONE;
1262
1263 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1264 if (otgsc & OTGSC_ID)
1265 set_bit(ID, &motg->inputs);
1266 else
1267 clear_bit(ID, &motg->inputs);
1268 dev_dbg(phy->dev, "ID set/clear\n");
1269 pm_runtime_get_noresume(phy->dev);
1270 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1271 if (otgsc & OTGSC_BSV)
1272 set_bit(B_SESS_VLD, &motg->inputs);
1273 else
1274 clear_bit(B_SESS_VLD, &motg->inputs);
1275 dev_dbg(phy->dev, "BSV set/clear\n");
1276 pm_runtime_get_noresume(phy->dev);
1277 }
1278
1279 writel(otgsc, USB_OTGSC);
1280 schedule_work(&motg->sm_work);
1281 return IRQ_HANDLED;
1282 }
1283
1284 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1285 {
1286 struct msm_otg *motg = s->private;
1287 struct usb_otg *otg = motg->phy.otg;
1288
1289 switch (otg->phy->state) {
1290 case OTG_STATE_A_HOST:
1291 seq_printf(s, "host\n");
1292 break;
1293 case OTG_STATE_B_PERIPHERAL:
1294 seq_printf(s, "peripheral\n");
1295 break;
1296 default:
1297 seq_printf(s, "none\n");
1298 break;
1299 }
1300
1301 return 0;
1302 }
1303
1304 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1305 {
1306 return single_open(file, msm_otg_mode_show, inode->i_private);
1307 }
1308
1309 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1310 size_t count, loff_t *ppos)
1311 {
1312 struct seq_file *s = file->private_data;
1313 struct msm_otg *motg = s->private;
1314 char buf[16];
1315 struct usb_otg *otg = motg->phy.otg;
1316 int status = count;
1317 enum usb_mode_type req_mode;
1318
1319 memset(buf, 0x00, sizeof(buf));
1320
1321 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1322 status = -EFAULT;
1323 goto out;
1324 }
1325
1326 if (!strncmp(buf, "host", 4)) {
1327 req_mode = USB_HOST;
1328 } else if (!strncmp(buf, "peripheral", 10)) {
1329 req_mode = USB_PERIPHERAL;
1330 } else if (!strncmp(buf, "none", 4)) {
1331 req_mode = USB_NONE;
1332 } else {
1333 status = -EINVAL;
1334 goto out;
1335 }
1336
1337 switch (req_mode) {
1338 case USB_NONE:
1339 switch (otg->phy->state) {
1340 case OTG_STATE_A_HOST:
1341 case OTG_STATE_B_PERIPHERAL:
1342 set_bit(ID, &motg->inputs);
1343 clear_bit(B_SESS_VLD, &motg->inputs);
1344 break;
1345 default:
1346 goto out;
1347 }
1348 break;
1349 case USB_PERIPHERAL:
1350 switch (otg->phy->state) {
1351 case OTG_STATE_B_IDLE:
1352 case OTG_STATE_A_HOST:
1353 set_bit(ID, &motg->inputs);
1354 set_bit(B_SESS_VLD, &motg->inputs);
1355 break;
1356 default:
1357 goto out;
1358 }
1359 break;
1360 case USB_HOST:
1361 switch (otg->phy->state) {
1362 case OTG_STATE_B_IDLE:
1363 case OTG_STATE_B_PERIPHERAL:
1364 clear_bit(ID, &motg->inputs);
1365 break;
1366 default:
1367 goto out;
1368 }
1369 break;
1370 default:
1371 goto out;
1372 }
1373
1374 pm_runtime_get_sync(otg->phy->dev);
1375 schedule_work(&motg->sm_work);
1376 out:
1377 return status;
1378 }
1379
1380 const struct file_operations msm_otg_mode_fops = {
1381 .open = msm_otg_mode_open,
1382 .read = seq_read,
1383 .write = msm_otg_mode_write,
1384 .llseek = seq_lseek,
1385 .release = single_release,
1386 };
1387
1388 static struct dentry *msm_otg_dbg_root;
1389 static struct dentry *msm_otg_dbg_mode;
1390
1391 static int msm_otg_debugfs_init(struct msm_otg *motg)
1392 {
1393 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1394
1395 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1396 return -ENODEV;
1397
1398 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1399 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1400 if (!msm_otg_dbg_mode) {
1401 debugfs_remove(msm_otg_dbg_root);
1402 msm_otg_dbg_root = NULL;
1403 return -ENODEV;
1404 }
1405
1406 return 0;
1407 }
1408
1409 static void msm_otg_debugfs_cleanup(void)
1410 {
1411 debugfs_remove(msm_otg_dbg_mode);
1412 debugfs_remove(msm_otg_dbg_root);
1413 }
1414
1415 static int __init msm_otg_probe(struct platform_device *pdev)
1416 {
1417 int ret = 0;
1418 struct resource *res;
1419 struct msm_otg *motg;
1420 struct usb_phy *phy;
1421
1422 dev_info(&pdev->dev, "msm_otg probe\n");
1423 if (!dev_get_platdata(&pdev->dev)) {
1424 dev_err(&pdev->dev, "No platform data given. Bailing out\n");
1425 return -ENODEV;
1426 }
1427
1428 motg = kzalloc(sizeof(struct msm_otg), GFP_KERNEL);
1429 if (!motg) {
1430 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1431 return -ENOMEM;
1432 }
1433
1434 motg->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
1435 if (!motg->phy.otg) {
1436 dev_err(&pdev->dev, "unable to allocate msm_otg\n");
1437 return -ENOMEM;
1438 }
1439
1440 motg->pdata = dev_get_platdata(&pdev->dev);
1441 phy = &motg->phy;
1442 phy->dev = &pdev->dev;
1443
1444 motg->phy_reset_clk = clk_get(&pdev->dev, "usb_phy_clk");
1445 if (IS_ERR(motg->phy_reset_clk)) {
1446 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1447 ret = PTR_ERR(motg->phy_reset_clk);
1448 goto free_motg;
1449 }
1450
1451 motg->clk = clk_get(&pdev->dev, "usb_hs_clk");
1452 if (IS_ERR(motg->clk)) {
1453 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1454 ret = PTR_ERR(motg->clk);
1455 goto put_phy_reset_clk;
1456 }
1457 clk_set_rate(motg->clk, 60000000);
1458
1459 /*
1460 * If USB Core is running its protocol engine based on CORE CLK,
1461 * CORE CLK must be running at >55Mhz for correct HSUSB
1462 * operation and USB core cannot tolerate frequency changes on
1463 * CORE CLK. For such USB cores, vote for maximum clk frequency
1464 * on pclk source
1465 */
1466 if (motg->pdata->pclk_src_name) {
1467 motg->pclk_src = clk_get(&pdev->dev,
1468 motg->pdata->pclk_src_name);
1469 if (IS_ERR(motg->pclk_src))
1470 goto put_clk;
1471 clk_set_rate(motg->pclk_src, INT_MAX);
1472 clk_prepare_enable(motg->pclk_src);
1473 } else
1474 motg->pclk_src = ERR_PTR(-ENOENT);
1475
1476
1477 motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
1478 if (IS_ERR(motg->pclk)) {
1479 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1480 ret = PTR_ERR(motg->pclk);
1481 goto put_pclk_src;
1482 }
1483
1484 /*
1485 * USB core clock is not present on all MSM chips. This
1486 * clock is introduced to remove the dependency on AXI
1487 * bus frequency.
1488 */
1489 motg->core_clk = clk_get(&pdev->dev, "usb_hs_core_clk");
1490 if (IS_ERR(motg->core_clk))
1491 motg->core_clk = NULL;
1492
1493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 if (!res) {
1495 dev_err(&pdev->dev, "failed to get platform resource mem\n");
1496 ret = -ENODEV;
1497 goto put_core_clk;
1498 }
1499
1500 motg->regs = ioremap(res->start, resource_size(res));
1501 if (!motg->regs) {
1502 dev_err(&pdev->dev, "ioremap failed\n");
1503 ret = -ENOMEM;
1504 goto put_core_clk;
1505 }
1506 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1507
1508 motg->irq = platform_get_irq(pdev, 0);
1509 if (!motg->irq) {
1510 dev_err(&pdev->dev, "platform_get_irq failed\n");
1511 ret = -ENODEV;
1512 goto free_regs;
1513 }
1514
1515 clk_prepare_enable(motg->clk);
1516 clk_prepare_enable(motg->pclk);
1517
1518 ret = msm_hsusb_init_vddcx(motg, 1);
1519 if (ret) {
1520 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1521 goto free_regs;
1522 }
1523
1524 ret = msm_hsusb_ldo_init(motg, 1);
1525 if (ret) {
1526 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1527 goto vddcx_exit;
1528 }
1529 ret = msm_hsusb_ldo_set_mode(1);
1530 if (ret) {
1531 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1532 goto ldo_exit;
1533 }
1534
1535 if (motg->core_clk)
1536 clk_prepare_enable(motg->core_clk);
1537
1538 writel(0, USB_USBINTR);
1539 writel(0, USB_OTGSC);
1540
1541 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1542 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1543 ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
1544 "msm_otg", motg);
1545 if (ret) {
1546 dev_err(&pdev->dev, "request irq failed\n");
1547 goto disable_clks;
1548 }
1549
1550 phy->init = msm_otg_reset;
1551 phy->set_power = msm_otg_set_power;
1552
1553 phy->io_ops = &msm_otg_io_ops;
1554
1555 phy->otg->phy = &motg->phy;
1556 phy->otg->set_host = msm_otg_set_host;
1557 phy->otg->set_peripheral = msm_otg_set_peripheral;
1558
1559 ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2);
1560 if (ret) {
1561 dev_err(&pdev->dev, "usb_add_phy failed\n");
1562 goto free_irq;
1563 }
1564
1565 platform_set_drvdata(pdev, motg);
1566 device_init_wakeup(&pdev->dev, 1);
1567
1568 if (motg->pdata->mode == USB_OTG &&
1569 motg->pdata->otg_control == OTG_USER_CONTROL) {
1570 ret = msm_otg_debugfs_init(motg);
1571 if (ret)
1572 dev_dbg(&pdev->dev, "mode debugfs file is"
1573 "not available\n");
1574 }
1575
1576 pm_runtime_set_active(&pdev->dev);
1577 pm_runtime_enable(&pdev->dev);
1578
1579 return 0;
1580 free_irq:
1581 free_irq(motg->irq, motg);
1582 disable_clks:
1583 clk_disable_unprepare(motg->pclk);
1584 clk_disable_unprepare(motg->clk);
1585 ldo_exit:
1586 msm_hsusb_ldo_init(motg, 0);
1587 vddcx_exit:
1588 msm_hsusb_init_vddcx(motg, 0);
1589 free_regs:
1590 iounmap(motg->regs);
1591 put_core_clk:
1592 if (motg->core_clk)
1593 clk_put(motg->core_clk);
1594 clk_put(motg->pclk);
1595 put_pclk_src:
1596 if (!IS_ERR(motg->pclk_src)) {
1597 clk_disable_unprepare(motg->pclk_src);
1598 clk_put(motg->pclk_src);
1599 }
1600 put_clk:
1601 clk_put(motg->clk);
1602 put_phy_reset_clk:
1603 clk_put(motg->phy_reset_clk);
1604 free_motg:
1605 kfree(motg->phy.otg);
1606 kfree(motg);
1607 return ret;
1608 }
1609
1610 static int msm_otg_remove(struct platform_device *pdev)
1611 {
1612 struct msm_otg *motg = platform_get_drvdata(pdev);
1613 struct usb_phy *phy = &motg->phy;
1614 int cnt = 0;
1615
1616 if (phy->otg->host || phy->otg->gadget)
1617 return -EBUSY;
1618
1619 msm_otg_debugfs_cleanup();
1620 cancel_delayed_work_sync(&motg->chg_work);
1621 cancel_work_sync(&motg->sm_work);
1622
1623 pm_runtime_resume(&pdev->dev);
1624
1625 device_init_wakeup(&pdev->dev, 0);
1626 pm_runtime_disable(&pdev->dev);
1627
1628 usb_remove_phy(phy);
1629 free_irq(motg->irq, motg);
1630
1631 /*
1632 * Put PHY in low power mode.
1633 */
1634 ulpi_read(phy, 0x14);
1635 ulpi_write(phy, 0x08, 0x09);
1636
1637 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1638 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1639 if (readl(USB_PORTSC) & PORTSC_PHCD)
1640 break;
1641 udelay(1);
1642 cnt++;
1643 }
1644 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1645 dev_err(phy->dev, "Unable to suspend PHY\n");
1646
1647 clk_disable_unprepare(motg->pclk);
1648 clk_disable_unprepare(motg->clk);
1649 if (motg->core_clk)
1650 clk_disable_unprepare(motg->core_clk);
1651 if (!IS_ERR(motg->pclk_src)) {
1652 clk_disable_unprepare(motg->pclk_src);
1653 clk_put(motg->pclk_src);
1654 }
1655 msm_hsusb_ldo_init(motg, 0);
1656
1657 iounmap(motg->regs);
1658 pm_runtime_set_suspended(&pdev->dev);
1659
1660 clk_put(motg->phy_reset_clk);
1661 clk_put(motg->pclk);
1662 clk_put(motg->clk);
1663 if (motg->core_clk)
1664 clk_put(motg->core_clk);
1665
1666 kfree(motg->phy.otg);
1667 kfree(motg);
1668
1669 return 0;
1670 }
1671
1672 #ifdef CONFIG_PM_RUNTIME
1673 static int msm_otg_runtime_idle(struct device *dev)
1674 {
1675 struct msm_otg *motg = dev_get_drvdata(dev);
1676 struct usb_otg *otg = motg->phy.otg;
1677
1678 dev_dbg(dev, "OTG runtime idle\n");
1679
1680 /*
1681 * It is observed some times that a spurious interrupt
1682 * comes when PHY is put into LPM immediately after PHY reset.
1683 * This 1 sec delay also prevents entering into LPM immediately
1684 * after asynchronous interrupt.
1685 */
1686 if (otg->phy->state != OTG_STATE_UNDEFINED)
1687 pm_schedule_suspend(dev, 1000);
1688
1689 return -EAGAIN;
1690 }
1691
1692 static int msm_otg_runtime_suspend(struct device *dev)
1693 {
1694 struct msm_otg *motg = dev_get_drvdata(dev);
1695
1696 dev_dbg(dev, "OTG runtime suspend\n");
1697 return msm_otg_suspend(motg);
1698 }
1699
1700 static int msm_otg_runtime_resume(struct device *dev)
1701 {
1702 struct msm_otg *motg = dev_get_drvdata(dev);
1703
1704 dev_dbg(dev, "OTG runtime resume\n");
1705 return msm_otg_resume(motg);
1706 }
1707 #endif
1708
1709 #ifdef CONFIG_PM_SLEEP
1710 static int msm_otg_pm_suspend(struct device *dev)
1711 {
1712 struct msm_otg *motg = dev_get_drvdata(dev);
1713
1714 dev_dbg(dev, "OTG PM suspend\n");
1715 return msm_otg_suspend(motg);
1716 }
1717
1718 static int msm_otg_pm_resume(struct device *dev)
1719 {
1720 struct msm_otg *motg = dev_get_drvdata(dev);
1721 int ret;
1722
1723 dev_dbg(dev, "OTG PM resume\n");
1724
1725 ret = msm_otg_resume(motg);
1726 if (ret)
1727 return ret;
1728
1729 /*
1730 * Runtime PM Documentation recommends bringing the
1731 * device to full powered state upon resume.
1732 */
1733 pm_runtime_disable(dev);
1734 pm_runtime_set_active(dev);
1735 pm_runtime_enable(dev);
1736
1737 return 0;
1738 }
1739 #endif
1740
1741 #ifdef CONFIG_PM
1742 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
1743 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1744 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1745 msm_otg_runtime_idle)
1746 };
1747 #endif
1748
1749 static struct platform_driver msm_otg_driver = {
1750 .remove = msm_otg_remove,
1751 .driver = {
1752 .name = DRIVER_NAME,
1753 .owner = THIS_MODULE,
1754 #ifdef CONFIG_PM
1755 .pm = &msm_otg_dev_pm_ops,
1756 #endif
1757 },
1758 };
1759
1760 module_platform_driver_probe(msm_otg_driver, msm_otg_probe);
1761
1762 MODULE_LICENSE("GPL v2");
1763 MODULE_DESCRIPTION("MSM USB transceiver driver");
ubuntu-bionic-kernel mirror