1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/usb.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/usb/msm_hsusb.h>
40 #include <linux/usb/msm_hsusb_hw.h>
41 #include <linux/regulator/consumer.h>
45 #define MSM_USB_BASE (motg->regs)
46 #define DRIVER_NAME "msm_otg"
48 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
50 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
51 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
52 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
53 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
55 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
56 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
57 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
58 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
60 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
61 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
63 static struct regulator
*hsusb_3p3
;
64 static struct regulator
*hsusb_1p8
;
65 static struct regulator
*hsusb_vddcx
;
67 static int msm_hsusb_init_vddcx(struct msm_otg
*motg
, int init
)
72 hsusb_vddcx
= regulator_get(motg
->phy
.dev
, "HSUSB_VDDCX");
73 if (IS_ERR(hsusb_vddcx
)) {
74 dev_err(motg
->phy
.dev
, "unable to get hsusb vddcx\n");
75 return PTR_ERR(hsusb_vddcx
);
78 ret
= regulator_set_voltage(hsusb_vddcx
,
79 USB_PHY_VDD_DIG_VOL_MIN
,
80 USB_PHY_VDD_DIG_VOL_MAX
);
82 dev_err(motg
->phy
.dev
, "unable to set the voltage "
84 regulator_put(hsusb_vddcx
);
88 ret
= regulator_enable(hsusb_vddcx
);
90 dev_err(motg
->phy
.dev
, "unable to enable hsusb vddcx\n");
91 regulator_put(hsusb_vddcx
);
94 ret
= regulator_set_voltage(hsusb_vddcx
, 0,
95 USB_PHY_VDD_DIG_VOL_MAX
);
97 dev_err(motg
->phy
.dev
, "unable to set the voltage "
99 ret
= regulator_disable(hsusb_vddcx
);
101 dev_err(motg
->phy
.dev
, "unable to disable hsusb vddcx\n");
103 regulator_put(hsusb_vddcx
);
109 static int msm_hsusb_ldo_init(struct msm_otg
*motg
, int init
)
114 hsusb_3p3
= regulator_get(motg
->phy
.dev
, "HSUSB_3p3");
115 if (IS_ERR(hsusb_3p3
)) {
116 dev_err(motg
->phy
.dev
, "unable to get hsusb 3p3\n");
117 return PTR_ERR(hsusb_3p3
);
120 rc
= regulator_set_voltage(hsusb_3p3
, USB_PHY_3P3_VOL_MIN
,
121 USB_PHY_3P3_VOL_MAX
);
123 dev_err(motg
->phy
.dev
, "unable to set voltage level "
127 rc
= regulator_enable(hsusb_3p3
);
129 dev_err(motg
->phy
.dev
, "unable to enable the hsusb 3p3\n");
132 hsusb_1p8
= regulator_get(motg
->phy
.dev
, "HSUSB_1p8");
133 if (IS_ERR(hsusb_1p8
)) {
134 dev_err(motg
->phy
.dev
, "unable to get hsusb 1p8\n");
135 rc
= PTR_ERR(hsusb_1p8
);
138 rc
= regulator_set_voltage(hsusb_1p8
, USB_PHY_1P8_VOL_MIN
,
139 USB_PHY_1P8_VOL_MAX
);
141 dev_err(motg
->phy
.dev
, "unable to set voltage level "
145 rc
= regulator_enable(hsusb_1p8
);
147 dev_err(motg
->phy
.dev
, "unable to enable the hsusb 1p8\n");
154 regulator_disable(hsusb_1p8
);
156 regulator_put(hsusb_1p8
);
158 regulator_disable(hsusb_3p3
);
160 regulator_put(hsusb_3p3
);
164 #ifdef CONFIG_PM_SLEEP
165 #define USB_PHY_SUSP_DIG_VOL 500000
166 static int msm_hsusb_config_vddcx(int high
)
168 int max_vol
= USB_PHY_VDD_DIG_VOL_MAX
;
173 min_vol
= USB_PHY_VDD_DIG_VOL_MIN
;
175 min_vol
= USB_PHY_SUSP_DIG_VOL
;
177 ret
= regulator_set_voltage(hsusb_vddcx
, min_vol
, max_vol
);
179 pr_err("%s: unable to set the voltage for regulator "
180 "HSUSB_VDDCX\n", __func__
);
184 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__
, min_vol
, max_vol
);
190 static int msm_hsusb_ldo_set_mode(int on
)
194 if (!hsusb_1p8
|| IS_ERR(hsusb_1p8
)) {
195 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__
);
199 if (!hsusb_3p3
|| IS_ERR(hsusb_3p3
)) {
200 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__
);
205 ret
= regulator_set_optimum_mode(hsusb_1p8
,
206 USB_PHY_1P8_HPM_LOAD
);
208 pr_err("%s: Unable to set HPM of the regulator "
209 "HSUSB_1p8\n", __func__
);
212 ret
= regulator_set_optimum_mode(hsusb_3p3
,
213 USB_PHY_3P3_HPM_LOAD
);
215 pr_err("%s: Unable to set HPM of the regulator "
216 "HSUSB_3p3\n", __func__
);
217 regulator_set_optimum_mode(hsusb_1p8
,
218 USB_PHY_1P8_LPM_LOAD
);
222 ret
= regulator_set_optimum_mode(hsusb_1p8
,
223 USB_PHY_1P8_LPM_LOAD
);
225 pr_err("%s: Unable to set LPM of the regulator "
226 "HSUSB_1p8\n", __func__
);
227 ret
= regulator_set_optimum_mode(hsusb_3p3
,
228 USB_PHY_3P3_LPM_LOAD
);
230 pr_err("%s: Unable to set LPM of the regulator "
231 "HSUSB_3p3\n", __func__
);
234 pr_debug("reg (%s)\n", on
? "HPM" : "LPM");
235 return ret
< 0 ? ret
: 0;
238 static int ulpi_read(struct usb_phy
*phy
, u32 reg
)
240 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
243 /* initiate read operation */
244 writel(ULPI_RUN
| ULPI_READ
| ULPI_ADDR(reg
),
247 /* wait for completion */
248 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
249 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
255 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
256 dev_err(phy
->dev
, "ulpi_read: timeout %08x\n",
257 readl(USB_ULPI_VIEWPORT
));
260 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT
));
263 static int ulpi_write(struct usb_phy
*phy
, u32 val
, u32 reg
)
265 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
268 /* initiate write operation */
269 writel(ULPI_RUN
| ULPI_WRITE
|
270 ULPI_ADDR(reg
) | ULPI_DATA(val
),
273 /* wait for completion */
274 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
275 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
281 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
282 dev_err(phy
->dev
, "ulpi_write: timeout\n");
288 static struct usb_phy_io_ops msm_otg_io_ops
= {
293 static void ulpi_init(struct msm_otg
*motg
)
295 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
296 int *seq
= pdata
->phy_init_seq
;
301 while (seq
[0] >= 0) {
302 dev_vdbg(motg
->phy
.dev
, "ulpi: write 0x%02x to 0x%02x\n",
304 ulpi_write(&motg
->phy
, seq
[0], seq
[1]);
309 static int msm_otg_link_clk_reset(struct msm_otg
*motg
, bool assert)
314 ret
= clk_reset(motg
->clk
, CLK_RESET_ASSERT
);
316 dev_err(motg
->phy
.dev
, "usb hs_clk assert failed\n");
318 ret
= clk_reset(motg
->clk
, CLK_RESET_DEASSERT
);
320 dev_err(motg
->phy
.dev
, "usb hs_clk deassert failed\n");
325 static int msm_otg_phy_clk_reset(struct msm_otg
*motg
)
329 ret
= clk_reset(motg
->phy_reset_clk
, CLK_RESET_ASSERT
);
331 dev_err(motg
->phy
.dev
, "usb phy clk assert failed\n");
334 usleep_range(10000, 12000);
335 ret
= clk_reset(motg
->phy_reset_clk
, CLK_RESET_DEASSERT
);
337 dev_err(motg
->phy
.dev
, "usb phy clk deassert failed\n");
341 static int msm_otg_phy_reset(struct msm_otg
*motg
)
347 ret
= msm_otg_link_clk_reset(motg
, 1);
350 ret
= msm_otg_phy_clk_reset(motg
);
353 ret
= msm_otg_link_clk_reset(motg
, 0);
357 val
= readl(USB_PORTSC
) & ~PORTSC_PTS_MASK
;
358 writel(val
| PORTSC_PTS_ULPI
, USB_PORTSC
);
360 for (retries
= 3; retries
> 0; retries
--) {
361 ret
= ulpi_write(&motg
->phy
, ULPI_FUNC_CTRL_SUSPENDM
,
362 ULPI_CLR(ULPI_FUNC_CTRL
));
365 ret
= msm_otg_phy_clk_reset(motg
);
372 /* This reset calibrates the phy, if the above write succeeded */
373 ret
= msm_otg_phy_clk_reset(motg
);
377 for (retries
= 3; retries
> 0; retries
--) {
378 ret
= ulpi_read(&motg
->phy
, ULPI_DEBUG
);
379 if (ret
!= -ETIMEDOUT
)
381 ret
= msm_otg_phy_clk_reset(motg
);
388 dev_info(motg
->phy
.dev
, "phy_reset: success\n");
392 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
393 static int msm_otg_reset(struct usb_phy
*phy
)
395 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
396 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
402 ret
= msm_otg_phy_reset(motg
);
404 dev_err(phy
->dev
, "phy_reset failed\n");
410 writel(USBCMD_RESET
, USB_USBCMD
);
411 while (cnt
< LINK_RESET_TIMEOUT_USEC
) {
412 if (!(readl(USB_USBCMD
) & USBCMD_RESET
))
417 if (cnt
>= LINK_RESET_TIMEOUT_USEC
)
420 /* select ULPI phy */
421 writel(0x80000000, USB_PORTSC
);
425 writel(0x0, USB_AHBBURST
);
426 writel(0x00, USB_AHBMODE
);
428 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
429 val
= readl(USB_OTGSC
);
430 if (pdata
->mode
== USB_OTG
) {
431 ulpi_val
= ULPI_INT_IDGRD
| ULPI_INT_SESS_VALID
;
432 val
|= OTGSC_IDIE
| OTGSC_BSVIE
;
433 } else if (pdata
->mode
== USB_PERIPHERAL
) {
434 ulpi_val
= ULPI_INT_SESS_VALID
;
437 writel(val
, USB_OTGSC
);
438 ulpi_write(phy
, ulpi_val
, ULPI_USB_INT_EN_RISE
);
439 ulpi_write(phy
, ulpi_val
, ULPI_USB_INT_EN_FALL
);
445 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
446 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
448 #ifdef CONFIG_PM_SLEEP
449 static int msm_otg_suspend(struct msm_otg
*motg
)
451 struct usb_phy
*phy
= &motg
->phy
;
452 struct usb_bus
*bus
= phy
->otg
->host
;
453 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
456 if (atomic_read(&motg
->in_lpm
))
459 disable_irq(motg
->irq
);
461 * Chipidea 45-nm PHY suspend sequence:
463 * Interrupt Latch Register auto-clear feature is not present
464 * in all PHY versions. Latch register is clear on read type.
465 * Clear latch register to avoid spurious wakeup from
466 * low power mode (LPM).
468 * PHY comparators are disabled when PHY enters into low power
469 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
470 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
471 * PHY comparators. This save significant amount of power.
473 * PLL is not turned off when PHY enters into low power mode (LPM).
474 * Disable PLL for maximum power savings.
477 if (motg
->pdata
->phy_type
== CI_45NM_INTEGRATED_PHY
) {
478 ulpi_read(phy
, 0x14);
479 if (pdata
->otg_control
== OTG_PHY_CONTROL
)
480 ulpi_write(phy
, 0x01, 0x30);
481 ulpi_write(phy
, 0x08, 0x09);
485 * PHY may take some time or even fail to enter into low power
486 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
489 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
490 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
491 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
497 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
) {
498 dev_err(phy
->dev
, "Unable to suspend PHY\n");
500 enable_irq(motg
->irq
);
505 * PHY has capability to generate interrupt asynchronously in low
506 * power mode (LPM). This interrupt is level triggered. So USB IRQ
507 * line must be disabled till async interrupt enable bit is cleared
508 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
509 * block data communication from PHY.
511 writel(readl(USB_USBCMD
) | ASYNC_INTR_CTRL
| ULPI_STP_CTRL
, USB_USBCMD
);
513 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
514 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
)
515 writel(readl(USB_PHY_CTRL
) | PHY_RETEN
, USB_PHY_CTRL
);
517 clk_disable_unprepare(motg
->pclk
);
518 clk_disable_unprepare(motg
->clk
);
520 clk_disable_unprepare(motg
->core_clk
);
522 if (!IS_ERR(motg
->pclk_src
))
523 clk_disable_unprepare(motg
->pclk_src
);
525 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
526 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
527 msm_hsusb_ldo_set_mode(0);
528 msm_hsusb_config_vddcx(0);
531 if (device_may_wakeup(phy
->dev
))
532 enable_irq_wake(motg
->irq
);
534 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
536 atomic_set(&motg
->in_lpm
, 1);
537 enable_irq(motg
->irq
);
539 dev_info(phy
->dev
, "USB in low power mode\n");
544 static int msm_otg_resume(struct msm_otg
*motg
)
546 struct usb_phy
*phy
= &motg
->phy
;
547 struct usb_bus
*bus
= phy
->otg
->host
;
551 if (!atomic_read(&motg
->in_lpm
))
554 if (!IS_ERR(motg
->pclk_src
))
555 clk_prepare_enable(motg
->pclk_src
);
557 clk_prepare_enable(motg
->pclk
);
558 clk_prepare_enable(motg
->clk
);
560 clk_prepare_enable(motg
->core_clk
);
562 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
563 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
564 msm_hsusb_ldo_set_mode(1);
565 msm_hsusb_config_vddcx(1);
566 writel(readl(USB_PHY_CTRL
) & ~PHY_RETEN
, USB_PHY_CTRL
);
569 temp
= readl(USB_USBCMD
);
570 temp
&= ~ASYNC_INTR_CTRL
;
571 temp
&= ~ULPI_STP_CTRL
;
572 writel(temp
, USB_USBCMD
);
575 * PHY comes out of low power mode (LPM) in case of wakeup
576 * from asynchronous interrupt.
578 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
579 goto skip_phy_resume
;
581 writel(readl(USB_PORTSC
) & ~PORTSC_PHCD
, USB_PORTSC
);
582 while (cnt
< PHY_RESUME_TIMEOUT_USEC
) {
583 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
589 if (cnt
>= PHY_RESUME_TIMEOUT_USEC
) {
591 * This is a fatal error. Reset the link and
592 * PHY. USB state can not be restored. Re-insertion
593 * of USB cable is the only way to get USB working.
595 dev_err(phy
->dev
, "Unable to resume USB."
596 "Re-plugin the cable\n");
601 if (device_may_wakeup(phy
->dev
))
602 disable_irq_wake(motg
->irq
);
604 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
606 atomic_set(&motg
->in_lpm
, 0);
608 if (motg
->async_int
) {
610 pm_runtime_put(phy
->dev
);
611 enable_irq(motg
->irq
);
614 dev_info(phy
->dev
, "USB exited from low power mode\n");
620 static void msm_otg_notify_charger(struct msm_otg
*motg
, unsigned mA
)
622 if (motg
->cur_power
== mA
)
625 /* TODO: Notify PMIC about available current */
626 dev_info(motg
->phy
.dev
, "Avail curr from USB = %u\n", mA
);
627 motg
->cur_power
= mA
;
630 static int msm_otg_set_power(struct usb_phy
*phy
, unsigned mA
)
632 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
635 * Gadget driver uses set_power method to notify about the
636 * available current based on suspend/configured states.
638 * IDEV_CHG can be drawn irrespective of suspend/un-configured
639 * states when CDP/ACA is connected.
641 if (motg
->chg_type
== USB_SDP_CHARGER
)
642 msm_otg_notify_charger(motg
, mA
);
647 static void msm_otg_start_host(struct usb_phy
*phy
, int on
)
649 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
650 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
656 hcd
= bus_to_hcd(phy
->otg
->host
);
659 dev_dbg(phy
->dev
, "host on\n");
661 if (pdata
->vbus_power
)
662 pdata
->vbus_power(1);
664 * Some boards have a switch cotrolled by gpio
665 * to enable/disable internal HUB. Enable internal
666 * HUB before kicking the host.
668 if (pdata
->setup_gpio
)
669 pdata
->setup_gpio(OTG_STATE_A_HOST
);
671 usb_add_hcd(hcd
, hcd
->irq
, IRQF_SHARED
);
672 device_wakeup_enable(hcd
->self
.controller
);
675 dev_dbg(phy
->dev
, "host off\n");
680 if (pdata
->setup_gpio
)
681 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
682 if (pdata
->vbus_power
)
683 pdata
->vbus_power(0);
687 static int msm_otg_set_host(struct usb_otg
*otg
, struct usb_bus
*host
)
689 struct msm_otg
*motg
= container_of(otg
->phy
, struct msm_otg
, phy
);
693 * Fail host registration if this board can support
694 * only peripheral configuration.
696 if (motg
->pdata
->mode
== USB_PERIPHERAL
) {
697 dev_info(otg
->phy
->dev
, "Host mode is not supported\n");
702 if (otg
->phy
->state
== OTG_STATE_A_HOST
) {
703 pm_runtime_get_sync(otg
->phy
->dev
);
704 msm_otg_start_host(otg
->phy
, 0);
706 otg
->phy
->state
= OTG_STATE_UNDEFINED
;
707 schedule_work(&motg
->sm_work
);
715 hcd
= bus_to_hcd(host
);
716 hcd
->power_budget
= motg
->pdata
->power_budget
;
719 dev_dbg(otg
->phy
->dev
, "host driver registered w/ tranceiver\n");
722 * Kick the state machine work, if peripheral is not supported
723 * or peripheral is already registered with us.
725 if (motg
->pdata
->mode
== USB_HOST
|| otg
->gadget
) {
726 pm_runtime_get_sync(otg
->phy
->dev
);
727 schedule_work(&motg
->sm_work
);
733 static void msm_otg_start_peripheral(struct usb_phy
*phy
, int on
)
735 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
736 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
738 if (!phy
->otg
->gadget
)
742 dev_dbg(phy
->dev
, "gadget on\n");
744 * Some boards have a switch cotrolled by gpio
745 * to enable/disable internal HUB. Disable internal
746 * HUB before kicking the gadget.
748 if (pdata
->setup_gpio
)
749 pdata
->setup_gpio(OTG_STATE_B_PERIPHERAL
);
750 usb_gadget_vbus_connect(phy
->otg
->gadget
);
752 dev_dbg(phy
->dev
, "gadget off\n");
753 usb_gadget_vbus_disconnect(phy
->otg
->gadget
);
754 if (pdata
->setup_gpio
)
755 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
760 static int msm_otg_set_peripheral(struct usb_otg
*otg
,
761 struct usb_gadget
*gadget
)
763 struct msm_otg
*motg
= container_of(otg
->phy
, struct msm_otg
, phy
);
766 * Fail peripheral registration if this board can support
767 * only host configuration.
769 if (motg
->pdata
->mode
== USB_HOST
) {
770 dev_info(otg
->phy
->dev
, "Peripheral mode is not supported\n");
775 if (otg
->phy
->state
== OTG_STATE_B_PERIPHERAL
) {
776 pm_runtime_get_sync(otg
->phy
->dev
);
777 msm_otg_start_peripheral(otg
->phy
, 0);
779 otg
->phy
->state
= OTG_STATE_UNDEFINED
;
780 schedule_work(&motg
->sm_work
);
787 otg
->gadget
= gadget
;
788 dev_dbg(otg
->phy
->dev
, "peripheral driver registered w/ tranceiver\n");
791 * Kick the state machine work, if host is not supported
792 * or host is already registered with us.
794 if (motg
->pdata
->mode
== USB_PERIPHERAL
|| otg
->host
) {
795 pm_runtime_get_sync(otg
->phy
->dev
);
796 schedule_work(&motg
->sm_work
);
802 static bool msm_chg_check_secondary_det(struct msm_otg
*motg
)
804 struct usb_phy
*phy
= &motg
->phy
;
808 switch (motg
->pdata
->phy_type
) {
809 case CI_45NM_INTEGRATED_PHY
:
810 chg_det
= ulpi_read(phy
, 0x34);
811 ret
= chg_det
& (1 << 4);
813 case SNPS_28NM_INTEGRATED_PHY
:
814 chg_det
= ulpi_read(phy
, 0x87);
823 static void msm_chg_enable_secondary_det(struct msm_otg
*motg
)
825 struct usb_phy
*phy
= &motg
->phy
;
828 switch (motg
->pdata
->phy_type
) {
829 case CI_45NM_INTEGRATED_PHY
:
830 chg_det
= ulpi_read(phy
, 0x34);
831 /* Turn off charger block */
832 chg_det
|= ~(1 << 1);
833 ulpi_write(phy
, chg_det
, 0x34);
835 /* control chg block via ULPI */
836 chg_det
&= ~(1 << 3);
837 ulpi_write(phy
, chg_det
, 0x34);
838 /* put it in host mode for enabling D- source */
839 chg_det
&= ~(1 << 2);
840 ulpi_write(phy
, chg_det
, 0x34);
841 /* Turn on chg detect block */
842 chg_det
&= ~(1 << 1);
843 ulpi_write(phy
, chg_det
, 0x34);
845 /* enable chg detection */
846 chg_det
&= ~(1 << 0);
847 ulpi_write(phy
, chg_det
, 0x34);
849 case SNPS_28NM_INTEGRATED_PHY
:
851 * Configure DM as current source, DP as current sink
852 * and enable battery charging comparators.
854 ulpi_write(phy
, 0x8, 0x85);
855 ulpi_write(phy
, 0x2, 0x85);
856 ulpi_write(phy
, 0x1, 0x85);
863 static bool msm_chg_check_primary_det(struct msm_otg
*motg
)
865 struct usb_phy
*phy
= &motg
->phy
;
869 switch (motg
->pdata
->phy_type
) {
870 case CI_45NM_INTEGRATED_PHY
:
871 chg_det
= ulpi_read(phy
, 0x34);
872 ret
= chg_det
& (1 << 4);
874 case SNPS_28NM_INTEGRATED_PHY
:
875 chg_det
= ulpi_read(phy
, 0x87);
884 static void msm_chg_enable_primary_det(struct msm_otg
*motg
)
886 struct usb_phy
*phy
= &motg
->phy
;
889 switch (motg
->pdata
->phy_type
) {
890 case CI_45NM_INTEGRATED_PHY
:
891 chg_det
= ulpi_read(phy
, 0x34);
892 /* enable chg detection */
893 chg_det
&= ~(1 << 0);
894 ulpi_write(phy
, chg_det
, 0x34);
896 case SNPS_28NM_INTEGRATED_PHY
:
898 * Configure DP as current source, DM as current sink
899 * and enable battery charging comparators.
901 ulpi_write(phy
, 0x2, 0x85);
902 ulpi_write(phy
, 0x1, 0x85);
909 static bool msm_chg_check_dcd(struct msm_otg
*motg
)
911 struct usb_phy
*phy
= &motg
->phy
;
915 switch (motg
->pdata
->phy_type
) {
916 case CI_45NM_INTEGRATED_PHY
:
917 line_state
= ulpi_read(phy
, 0x15);
918 ret
= !(line_state
& 1);
920 case SNPS_28NM_INTEGRATED_PHY
:
921 line_state
= ulpi_read(phy
, 0x87);
922 ret
= line_state
& 2;
930 static void msm_chg_disable_dcd(struct msm_otg
*motg
)
932 struct usb_phy
*phy
= &motg
->phy
;
935 switch (motg
->pdata
->phy_type
) {
936 case CI_45NM_INTEGRATED_PHY
:
937 chg_det
= ulpi_read(phy
, 0x34);
938 chg_det
&= ~(1 << 5);
939 ulpi_write(phy
, chg_det
, 0x34);
941 case SNPS_28NM_INTEGRATED_PHY
:
942 ulpi_write(phy
, 0x10, 0x86);
949 static void msm_chg_enable_dcd(struct msm_otg
*motg
)
951 struct usb_phy
*phy
= &motg
->phy
;
954 switch (motg
->pdata
->phy_type
) {
955 case CI_45NM_INTEGRATED_PHY
:
956 chg_det
= ulpi_read(phy
, 0x34);
957 /* Turn on D+ current source */
959 ulpi_write(phy
, chg_det
, 0x34);
961 case SNPS_28NM_INTEGRATED_PHY
:
962 /* Data contact detection enable */
963 ulpi_write(phy
, 0x10, 0x85);
970 static void msm_chg_block_on(struct msm_otg
*motg
)
972 struct usb_phy
*phy
= &motg
->phy
;
973 u32 func_ctrl
, chg_det
;
975 /* put the controller in non-driving mode */
976 func_ctrl
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
977 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
978 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NONDRIVING
;
979 ulpi_write(phy
, func_ctrl
, ULPI_FUNC_CTRL
);
981 switch (motg
->pdata
->phy_type
) {
982 case CI_45NM_INTEGRATED_PHY
:
983 chg_det
= ulpi_read(phy
, 0x34);
984 /* control chg block via ULPI */
985 chg_det
&= ~(1 << 3);
986 ulpi_write(phy
, chg_det
, 0x34);
987 /* Turn on chg detect block */
988 chg_det
&= ~(1 << 1);
989 ulpi_write(phy
, chg_det
, 0x34);
992 case SNPS_28NM_INTEGRATED_PHY
:
993 /* Clear charger detecting control bits */
994 ulpi_write(phy
, 0x3F, 0x86);
995 /* Clear alt interrupt latch and enable bits */
996 ulpi_write(phy
, 0x1F, 0x92);
997 ulpi_write(phy
, 0x1F, 0x95);
1005 static void msm_chg_block_off(struct msm_otg
*motg
)
1007 struct usb_phy
*phy
= &motg
->phy
;
1008 u32 func_ctrl
, chg_det
;
1010 switch (motg
->pdata
->phy_type
) {
1011 case CI_45NM_INTEGRATED_PHY
:
1012 chg_det
= ulpi_read(phy
, 0x34);
1013 /* Turn off charger block */
1014 chg_det
|= ~(1 << 1);
1015 ulpi_write(phy
, chg_det
, 0x34);
1017 case SNPS_28NM_INTEGRATED_PHY
:
1018 /* Clear charger detecting control bits */
1019 ulpi_write(phy
, 0x3F, 0x86);
1020 /* Clear alt interrupt latch and enable bits */
1021 ulpi_write(phy
, 0x1F, 0x92);
1022 ulpi_write(phy
, 0x1F, 0x95);
1028 /* put the controller in normal mode */
1029 func_ctrl
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
1030 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
1031 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NORMAL
;
1032 ulpi_write(phy
, func_ctrl
, ULPI_FUNC_CTRL
);
1035 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1036 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1037 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1038 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1039 static void msm_chg_detect_work(struct work_struct
*w
)
1041 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, chg_work
.work
);
1042 struct usb_phy
*phy
= &motg
->phy
;
1043 bool is_dcd
, tmout
, vout
;
1044 unsigned long delay
;
1046 dev_dbg(phy
->dev
, "chg detection work\n");
1047 switch (motg
->chg_state
) {
1048 case USB_CHG_STATE_UNDEFINED
:
1049 pm_runtime_get_sync(phy
->dev
);
1050 msm_chg_block_on(motg
);
1051 msm_chg_enable_dcd(motg
);
1052 motg
->chg_state
= USB_CHG_STATE_WAIT_FOR_DCD
;
1053 motg
->dcd_retries
= 0;
1054 delay
= MSM_CHG_DCD_POLL_TIME
;
1056 case USB_CHG_STATE_WAIT_FOR_DCD
:
1057 is_dcd
= msm_chg_check_dcd(motg
);
1058 tmout
= ++motg
->dcd_retries
== MSM_CHG_DCD_MAX_RETRIES
;
1059 if (is_dcd
|| tmout
) {
1060 msm_chg_disable_dcd(motg
);
1061 msm_chg_enable_primary_det(motg
);
1062 delay
= MSM_CHG_PRIMARY_DET_TIME
;
1063 motg
->chg_state
= USB_CHG_STATE_DCD_DONE
;
1065 delay
= MSM_CHG_DCD_POLL_TIME
;
1068 case USB_CHG_STATE_DCD_DONE
:
1069 vout
= msm_chg_check_primary_det(motg
);
1071 msm_chg_enable_secondary_det(motg
);
1072 delay
= MSM_CHG_SECONDARY_DET_TIME
;
1073 motg
->chg_state
= USB_CHG_STATE_PRIMARY_DONE
;
1075 motg
->chg_type
= USB_SDP_CHARGER
;
1076 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1080 case USB_CHG_STATE_PRIMARY_DONE
:
1081 vout
= msm_chg_check_secondary_det(motg
);
1083 motg
->chg_type
= USB_DCP_CHARGER
;
1085 motg
->chg_type
= USB_CDP_CHARGER
;
1086 motg
->chg_state
= USB_CHG_STATE_SECONDARY_DONE
;
1088 case USB_CHG_STATE_SECONDARY_DONE
:
1089 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1090 case USB_CHG_STATE_DETECTED
:
1091 msm_chg_block_off(motg
);
1092 dev_dbg(phy
->dev
, "charger = %d\n", motg
->chg_type
);
1093 schedule_work(&motg
->sm_work
);
1099 schedule_delayed_work(&motg
->chg_work
, delay
);
1103 * We support OTG, Peripheral only and Host only configurations. In case
1104 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1105 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1106 * enabled when switch is controlled by user and default mode is supplied
1107 * by board file, which can be changed by userspace later.
1109 static void msm_otg_init_sm(struct msm_otg
*motg
)
1111 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
1112 u32 otgsc
= readl(USB_OTGSC
);
1114 switch (pdata
->mode
) {
1116 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
1117 if (otgsc
& OTGSC_ID
)
1118 set_bit(ID
, &motg
->inputs
);
1120 clear_bit(ID
, &motg
->inputs
);
1122 if (otgsc
& OTGSC_BSV
)
1123 set_bit(B_SESS_VLD
, &motg
->inputs
);
1125 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1126 } else if (pdata
->otg_control
== OTG_USER_CONTROL
) {
1127 if (pdata
->default_mode
== USB_HOST
) {
1128 clear_bit(ID
, &motg
->inputs
);
1129 } else if (pdata
->default_mode
== USB_PERIPHERAL
) {
1130 set_bit(ID
, &motg
->inputs
);
1131 set_bit(B_SESS_VLD
, &motg
->inputs
);
1133 set_bit(ID
, &motg
->inputs
);
1134 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1139 clear_bit(ID
, &motg
->inputs
);
1141 case USB_PERIPHERAL
:
1142 set_bit(ID
, &motg
->inputs
);
1143 if (otgsc
& OTGSC_BSV
)
1144 set_bit(B_SESS_VLD
, &motg
->inputs
);
1146 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1153 static void msm_otg_sm_work(struct work_struct
*w
)
1155 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, sm_work
);
1156 struct usb_otg
*otg
= motg
->phy
.otg
;
1158 switch (otg
->phy
->state
) {
1159 case OTG_STATE_UNDEFINED
:
1160 dev_dbg(otg
->phy
->dev
, "OTG_STATE_UNDEFINED state\n");
1161 msm_otg_reset(otg
->phy
);
1162 msm_otg_init_sm(motg
);
1163 otg
->phy
->state
= OTG_STATE_B_IDLE
;
1165 case OTG_STATE_B_IDLE
:
1166 dev_dbg(otg
->phy
->dev
, "OTG_STATE_B_IDLE state\n");
1167 if (!test_bit(ID
, &motg
->inputs
) && otg
->host
) {
1168 /* disable BSV bit */
1169 writel(readl(USB_OTGSC
) & ~OTGSC_BSVIE
, USB_OTGSC
);
1170 msm_otg_start_host(otg
->phy
, 1);
1171 otg
->phy
->state
= OTG_STATE_A_HOST
;
1172 } else if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1173 switch (motg
->chg_state
) {
1174 case USB_CHG_STATE_UNDEFINED
:
1175 msm_chg_detect_work(&motg
->chg_work
.work
);
1177 case USB_CHG_STATE_DETECTED
:
1178 switch (motg
->chg_type
) {
1179 case USB_DCP_CHARGER
:
1180 msm_otg_notify_charger(motg
,
1183 case USB_CDP_CHARGER
:
1184 msm_otg_notify_charger(motg
,
1186 msm_otg_start_peripheral(otg
->phy
, 1);
1188 = OTG_STATE_B_PERIPHERAL
;
1190 case USB_SDP_CHARGER
:
1191 msm_otg_notify_charger(motg
, IUNIT
);
1192 msm_otg_start_peripheral(otg
->phy
, 1);
1194 = OTG_STATE_B_PERIPHERAL
;
1205 * If charger detection work is pending, decrement
1206 * the pm usage counter to balance with the one that
1207 * is incremented in charger detection work.
1209 if (cancel_delayed_work_sync(&motg
->chg_work
)) {
1210 pm_runtime_put_sync(otg
->phy
->dev
);
1211 msm_otg_reset(otg
->phy
);
1213 msm_otg_notify_charger(motg
, 0);
1214 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1215 motg
->chg_type
= USB_INVALID_CHARGER
;
1217 pm_runtime_put_sync(otg
->phy
->dev
);
1219 case OTG_STATE_B_PERIPHERAL
:
1220 dev_dbg(otg
->phy
->dev
, "OTG_STATE_B_PERIPHERAL state\n");
1221 if (!test_bit(B_SESS_VLD
, &motg
->inputs
) ||
1222 !test_bit(ID
, &motg
->inputs
)) {
1223 msm_otg_notify_charger(motg
, 0);
1224 msm_otg_start_peripheral(otg
->phy
, 0);
1225 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1226 motg
->chg_type
= USB_INVALID_CHARGER
;
1227 otg
->phy
->state
= OTG_STATE_B_IDLE
;
1228 msm_otg_reset(otg
->phy
);
1232 case OTG_STATE_A_HOST
:
1233 dev_dbg(otg
->phy
->dev
, "OTG_STATE_A_HOST state\n");
1234 if (test_bit(ID
, &motg
->inputs
)) {
1235 msm_otg_start_host(otg
->phy
, 0);
1236 otg
->phy
->state
= OTG_STATE_B_IDLE
;
1237 msm_otg_reset(otg
->phy
);
1246 static irqreturn_t
msm_otg_irq(int irq
, void *data
)
1248 struct msm_otg
*motg
= data
;
1249 struct usb_phy
*phy
= &motg
->phy
;
1252 if (atomic_read(&motg
->in_lpm
)) {
1253 disable_irq_nosync(irq
);
1254 motg
->async_int
= 1;
1255 pm_runtime_get(phy
->dev
);
1259 otgsc
= readl(USB_OTGSC
);
1260 if (!(otgsc
& (OTGSC_IDIS
| OTGSC_BSVIS
)))
1263 if ((otgsc
& OTGSC_IDIS
) && (otgsc
& OTGSC_IDIE
)) {
1264 if (otgsc
& OTGSC_ID
)
1265 set_bit(ID
, &motg
->inputs
);
1267 clear_bit(ID
, &motg
->inputs
);
1268 dev_dbg(phy
->dev
, "ID set/clear\n");
1269 pm_runtime_get_noresume(phy
->dev
);
1270 } else if ((otgsc
& OTGSC_BSVIS
) && (otgsc
& OTGSC_BSVIE
)) {
1271 if (otgsc
& OTGSC_BSV
)
1272 set_bit(B_SESS_VLD
, &motg
->inputs
);
1274 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1275 dev_dbg(phy
->dev
, "BSV set/clear\n");
1276 pm_runtime_get_noresume(phy
->dev
);
1279 writel(otgsc
, USB_OTGSC
);
1280 schedule_work(&motg
->sm_work
);
1284 static int msm_otg_mode_show(struct seq_file
*s
, void *unused
)
1286 struct msm_otg
*motg
= s
->private;
1287 struct usb_otg
*otg
= motg
->phy
.otg
;
1289 switch (otg
->phy
->state
) {
1290 case OTG_STATE_A_HOST
:
1291 seq_printf(s
, "host\n");
1293 case OTG_STATE_B_PERIPHERAL
:
1294 seq_printf(s
, "peripheral\n");
1297 seq_printf(s
, "none\n");
1304 static int msm_otg_mode_open(struct inode
*inode
, struct file
*file
)
1306 return single_open(file
, msm_otg_mode_show
, inode
->i_private
);
1309 static ssize_t
msm_otg_mode_write(struct file
*file
, const char __user
*ubuf
,
1310 size_t count
, loff_t
*ppos
)
1312 struct seq_file
*s
= file
->private_data
;
1313 struct msm_otg
*motg
= s
->private;
1315 struct usb_otg
*otg
= motg
->phy
.otg
;
1317 enum usb_mode_type req_mode
;
1319 memset(buf
, 0x00, sizeof(buf
));
1321 if (copy_from_user(&buf
, ubuf
, min_t(size_t, sizeof(buf
) - 1, count
))) {
1326 if (!strncmp(buf
, "host", 4)) {
1327 req_mode
= USB_HOST
;
1328 } else if (!strncmp(buf
, "peripheral", 10)) {
1329 req_mode
= USB_PERIPHERAL
;
1330 } else if (!strncmp(buf
, "none", 4)) {
1331 req_mode
= USB_NONE
;
1339 switch (otg
->phy
->state
) {
1340 case OTG_STATE_A_HOST
:
1341 case OTG_STATE_B_PERIPHERAL
:
1342 set_bit(ID
, &motg
->inputs
);
1343 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1349 case USB_PERIPHERAL
:
1350 switch (otg
->phy
->state
) {
1351 case OTG_STATE_B_IDLE
:
1352 case OTG_STATE_A_HOST
:
1353 set_bit(ID
, &motg
->inputs
);
1354 set_bit(B_SESS_VLD
, &motg
->inputs
);
1361 switch (otg
->phy
->state
) {
1362 case OTG_STATE_B_IDLE
:
1363 case OTG_STATE_B_PERIPHERAL
:
1364 clear_bit(ID
, &motg
->inputs
);
1374 pm_runtime_get_sync(otg
->phy
->dev
);
1375 schedule_work(&motg
->sm_work
);
1380 const struct file_operations msm_otg_mode_fops
= {
1381 .open
= msm_otg_mode_open
,
1383 .write
= msm_otg_mode_write
,
1384 .llseek
= seq_lseek
,
1385 .release
= single_release
,
1388 static struct dentry
*msm_otg_dbg_root
;
1389 static struct dentry
*msm_otg_dbg_mode
;
1391 static int msm_otg_debugfs_init(struct msm_otg
*motg
)
1393 msm_otg_dbg_root
= debugfs_create_dir("msm_otg", NULL
);
1395 if (!msm_otg_dbg_root
|| IS_ERR(msm_otg_dbg_root
))
1398 msm_otg_dbg_mode
= debugfs_create_file("mode", S_IRUGO
| S_IWUSR
,
1399 msm_otg_dbg_root
, motg
, &msm_otg_mode_fops
);
1400 if (!msm_otg_dbg_mode
) {
1401 debugfs_remove(msm_otg_dbg_root
);
1402 msm_otg_dbg_root
= NULL
;
1409 static void msm_otg_debugfs_cleanup(void)
1411 debugfs_remove(msm_otg_dbg_mode
);
1412 debugfs_remove(msm_otg_dbg_root
);
1415 static int __init
msm_otg_probe(struct platform_device
*pdev
)
1418 struct resource
*res
;
1419 struct msm_otg
*motg
;
1420 struct usb_phy
*phy
;
1422 dev_info(&pdev
->dev
, "msm_otg probe\n");
1423 if (!dev_get_platdata(&pdev
->dev
)) {
1424 dev_err(&pdev
->dev
, "No platform data given. Bailing out\n");
1428 motg
= kzalloc(sizeof(struct msm_otg
), GFP_KERNEL
);
1430 dev_err(&pdev
->dev
, "unable to allocate msm_otg\n");
1434 motg
->phy
.otg
= kzalloc(sizeof(struct usb_otg
), GFP_KERNEL
);
1435 if (!motg
->phy
.otg
) {
1436 dev_err(&pdev
->dev
, "unable to allocate msm_otg\n");
1440 motg
->pdata
= dev_get_platdata(&pdev
->dev
);
1442 phy
->dev
= &pdev
->dev
;
1444 motg
->phy_reset_clk
= clk_get(&pdev
->dev
, "usb_phy_clk");
1445 if (IS_ERR(motg
->phy_reset_clk
)) {
1446 dev_err(&pdev
->dev
, "failed to get usb_phy_clk\n");
1447 ret
= PTR_ERR(motg
->phy_reset_clk
);
1451 motg
->clk
= clk_get(&pdev
->dev
, "usb_hs_clk");
1452 if (IS_ERR(motg
->clk
)) {
1453 dev_err(&pdev
->dev
, "failed to get usb_hs_clk\n");
1454 ret
= PTR_ERR(motg
->clk
);
1455 goto put_phy_reset_clk
;
1457 clk_set_rate(motg
->clk
, 60000000);
1460 * If USB Core is running its protocol engine based on CORE CLK,
1461 * CORE CLK must be running at >55Mhz for correct HSUSB
1462 * operation and USB core cannot tolerate frequency changes on
1463 * CORE CLK. For such USB cores, vote for maximum clk frequency
1466 if (motg
->pdata
->pclk_src_name
) {
1467 motg
->pclk_src
= clk_get(&pdev
->dev
,
1468 motg
->pdata
->pclk_src_name
);
1469 if (IS_ERR(motg
->pclk_src
))
1471 clk_set_rate(motg
->pclk_src
, INT_MAX
);
1472 clk_prepare_enable(motg
->pclk_src
);
1474 motg
->pclk_src
= ERR_PTR(-ENOENT
);
1477 motg
->pclk
= clk_get(&pdev
->dev
, "usb_hs_pclk");
1478 if (IS_ERR(motg
->pclk
)) {
1479 dev_err(&pdev
->dev
, "failed to get usb_hs_pclk\n");
1480 ret
= PTR_ERR(motg
->pclk
);
1485 * USB core clock is not present on all MSM chips. This
1486 * clock is introduced to remove the dependency on AXI
1489 motg
->core_clk
= clk_get(&pdev
->dev
, "usb_hs_core_clk");
1490 if (IS_ERR(motg
->core_clk
))
1491 motg
->core_clk
= NULL
;
1493 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1495 dev_err(&pdev
->dev
, "failed to get platform resource mem\n");
1500 motg
->regs
= ioremap(res
->start
, resource_size(res
));
1502 dev_err(&pdev
->dev
, "ioremap failed\n");
1506 dev_info(&pdev
->dev
, "OTG regs = %p\n", motg
->regs
);
1508 motg
->irq
= platform_get_irq(pdev
, 0);
1510 dev_err(&pdev
->dev
, "platform_get_irq failed\n");
1515 clk_prepare_enable(motg
->clk
);
1516 clk_prepare_enable(motg
->pclk
);
1518 ret
= msm_hsusb_init_vddcx(motg
, 1);
1520 dev_err(&pdev
->dev
, "hsusb vddcx configuration failed\n");
1524 ret
= msm_hsusb_ldo_init(motg
, 1);
1526 dev_err(&pdev
->dev
, "hsusb vreg configuration failed\n");
1529 ret
= msm_hsusb_ldo_set_mode(1);
1531 dev_err(&pdev
->dev
, "hsusb vreg enable failed\n");
1536 clk_prepare_enable(motg
->core_clk
);
1538 writel(0, USB_USBINTR
);
1539 writel(0, USB_OTGSC
);
1541 INIT_WORK(&motg
->sm_work
, msm_otg_sm_work
);
1542 INIT_DELAYED_WORK(&motg
->chg_work
, msm_chg_detect_work
);
1543 ret
= request_irq(motg
->irq
, msm_otg_irq
, IRQF_SHARED
,
1546 dev_err(&pdev
->dev
, "request irq failed\n");
1550 phy
->init
= msm_otg_reset
;
1551 phy
->set_power
= msm_otg_set_power
;
1553 phy
->io_ops
= &msm_otg_io_ops
;
1555 phy
->otg
->phy
= &motg
->phy
;
1556 phy
->otg
->set_host
= msm_otg_set_host
;
1557 phy
->otg
->set_peripheral
= msm_otg_set_peripheral
;
1559 ret
= usb_add_phy(&motg
->phy
, USB_PHY_TYPE_USB2
);
1561 dev_err(&pdev
->dev
, "usb_add_phy failed\n");
1565 platform_set_drvdata(pdev
, motg
);
1566 device_init_wakeup(&pdev
->dev
, 1);
1568 if (motg
->pdata
->mode
== USB_OTG
&&
1569 motg
->pdata
->otg_control
== OTG_USER_CONTROL
) {
1570 ret
= msm_otg_debugfs_init(motg
);
1572 dev_dbg(&pdev
->dev
, "mode debugfs file is"
1576 pm_runtime_set_active(&pdev
->dev
);
1577 pm_runtime_enable(&pdev
->dev
);
1581 free_irq(motg
->irq
, motg
);
1583 clk_disable_unprepare(motg
->pclk
);
1584 clk_disable_unprepare(motg
->clk
);
1586 msm_hsusb_ldo_init(motg
, 0);
1588 msm_hsusb_init_vddcx(motg
, 0);
1590 iounmap(motg
->regs
);
1593 clk_put(motg
->core_clk
);
1594 clk_put(motg
->pclk
);
1596 if (!IS_ERR(motg
->pclk_src
)) {
1597 clk_disable_unprepare(motg
->pclk_src
);
1598 clk_put(motg
->pclk_src
);
1603 clk_put(motg
->phy_reset_clk
);
1605 kfree(motg
->phy
.otg
);
1610 static int msm_otg_remove(struct platform_device
*pdev
)
1612 struct msm_otg
*motg
= platform_get_drvdata(pdev
);
1613 struct usb_phy
*phy
= &motg
->phy
;
1616 if (phy
->otg
->host
|| phy
->otg
->gadget
)
1619 msm_otg_debugfs_cleanup();
1620 cancel_delayed_work_sync(&motg
->chg_work
);
1621 cancel_work_sync(&motg
->sm_work
);
1623 pm_runtime_resume(&pdev
->dev
);
1625 device_init_wakeup(&pdev
->dev
, 0);
1626 pm_runtime_disable(&pdev
->dev
);
1628 usb_remove_phy(phy
);
1629 free_irq(motg
->irq
, motg
);
1632 * Put PHY in low power mode.
1634 ulpi_read(phy
, 0x14);
1635 ulpi_write(phy
, 0x08, 0x09);
1637 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
1638 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
1639 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
1644 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
)
1645 dev_err(phy
->dev
, "Unable to suspend PHY\n");
1647 clk_disable_unprepare(motg
->pclk
);
1648 clk_disable_unprepare(motg
->clk
);
1650 clk_disable_unprepare(motg
->core_clk
);
1651 if (!IS_ERR(motg
->pclk_src
)) {
1652 clk_disable_unprepare(motg
->pclk_src
);
1653 clk_put(motg
->pclk_src
);
1655 msm_hsusb_ldo_init(motg
, 0);
1657 iounmap(motg
->regs
);
1658 pm_runtime_set_suspended(&pdev
->dev
);
1660 clk_put(motg
->phy_reset_clk
);
1661 clk_put(motg
->pclk
);
1664 clk_put(motg
->core_clk
);
1666 kfree(motg
->phy
.otg
);
1672 #ifdef CONFIG_PM_RUNTIME
1673 static int msm_otg_runtime_idle(struct device
*dev
)
1675 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1676 struct usb_otg
*otg
= motg
->phy
.otg
;
1678 dev_dbg(dev
, "OTG runtime idle\n");
1681 * It is observed some times that a spurious interrupt
1682 * comes when PHY is put into LPM immediately after PHY reset.
1683 * This 1 sec delay also prevents entering into LPM immediately
1684 * after asynchronous interrupt.
1686 if (otg
->phy
->state
!= OTG_STATE_UNDEFINED
)
1687 pm_schedule_suspend(dev
, 1000);
1692 static int msm_otg_runtime_suspend(struct device
*dev
)
1694 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1696 dev_dbg(dev
, "OTG runtime suspend\n");
1697 return msm_otg_suspend(motg
);
1700 static int msm_otg_runtime_resume(struct device
*dev
)
1702 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1704 dev_dbg(dev
, "OTG runtime resume\n");
1705 return msm_otg_resume(motg
);
1709 #ifdef CONFIG_PM_SLEEP
1710 static int msm_otg_pm_suspend(struct device
*dev
)
1712 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1714 dev_dbg(dev
, "OTG PM suspend\n");
1715 return msm_otg_suspend(motg
);
1718 static int msm_otg_pm_resume(struct device
*dev
)
1720 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1723 dev_dbg(dev
, "OTG PM resume\n");
1725 ret
= msm_otg_resume(motg
);
1730 * Runtime PM Documentation recommends bringing the
1731 * device to full powered state upon resume.
1733 pm_runtime_disable(dev
);
1734 pm_runtime_set_active(dev
);
1735 pm_runtime_enable(dev
);
1742 static const struct dev_pm_ops msm_otg_dev_pm_ops
= {
1743 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend
, msm_otg_pm_resume
)
1744 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend
, msm_otg_runtime_resume
,
1745 msm_otg_runtime_idle
)
1749 static struct platform_driver msm_otg_driver
= {
1750 .remove
= msm_otg_remove
,
1752 .name
= DRIVER_NAME
,
1753 .owner
= THIS_MODULE
,
1755 .pm
= &msm_otg_dev_pm_ops
,
1760 module_platform_driver_probe(msm_otg_driver
, msm_otg_probe
);
1762 MODULE_LICENSE("GPL v2");
1763 MODULE_DESCRIPTION("MSM USB transceiver driver");