1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/extcon.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
30 #include <linux/ioport.h>
31 #include <linux/uaccess.h>
32 #include <linux/debugfs.h>
33 #include <linux/seq_file.h>
34 #include <linux/pm_runtime.h>
36 #include <linux/of_device.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/types.h>
40 #include <linux/usb/otg.h>
42 #include <linux/usb.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/of.h>
45 #include <linux/usb/ulpi.h>
46 #include <linux/usb/gadget.h>
47 #include <linux/usb/hcd.h>
48 #include <linux/usb/msm_hsusb_hw.h>
49 #include <linux/regulator/consumer.h>
54 * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host
56 * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY.
57 * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware.
58 * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs.
61 enum otg_control_type
{
71 * INVALID_PHY Unsupported PHY
72 * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
73 * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
76 enum msm_usb_phy_type
{
78 CI_45NM_INTEGRATED_PHY
,
79 SNPS_28NM_INTEGRATED_PHY
,
82 #define IDEV_CHG_MAX 1500
86 * Different states involved in USB charger detection.
88 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
89 * process is not yet started.
90 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
91 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
92 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
93 * between SDP and DCP/CDP).
94 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
95 * between DCP and CDP).
96 * USB_CHG_STATE_DETECTED USB charger type is determined.
100 USB_CHG_STATE_UNDEFINED
= 0,
101 USB_CHG_STATE_WAIT_FOR_DCD
,
102 USB_CHG_STATE_DCD_DONE
,
103 USB_CHG_STATE_PRIMARY_DONE
,
104 USB_CHG_STATE_SECONDARY_DONE
,
105 USB_CHG_STATE_DETECTED
,
111 * USB_INVALID_CHARGER Invalid USB charger.
112 * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
113 * on USB2.0 compliant host/hub.
114 * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
115 * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
116 * IDEV_CHG_MAX can be drawn irrespective of USB state.
120 USB_INVALID_CHARGER
= 0,
127 * struct msm_otg_platform_data - platform device data
128 * for msm_otg driver.
129 * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
130 * "do not overwrite default vaule at this address".
131 * @phy_init_sz: PHY configuration sequence size.
132 * @vbus_power: VBUS power on/off routine.
133 * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
134 * @mode: Supported mode (OTG/peripheral/host).
135 * @otg_control: OTG switch controlled by user/Id pin
137 struct msm_otg_platform_data
{
140 void (*vbus_power
)(bool on
);
141 unsigned power_budget
;
142 enum usb_dr_mode mode
;
143 enum otg_control_type otg_control
;
144 enum msm_usb_phy_type phy_type
;
145 void (*setup_gpio
)(enum usb_otg_state state
);
149 * struct msm_usb_cable - structure for exteternal connector cable
151 * @nb: hold event notification callback
152 * @conn: used for notification registration
154 struct msm_usb_cable
{
155 struct notifier_block nb
;
156 struct extcon_dev
*extcon
;
160 * struct msm_otg: OTG driver data. Shared by HCD and DCD.
161 * @otg: USB OTG Transceiver structure.
162 * @pdata: otg device platform data.
163 * @irq: IRQ number assigned for HSUSB controller.
164 * @clk: clock struct of usb_hs_clk.
165 * @pclk: clock struct of usb_hs_pclk.
166 * @core_clk: clock struct of usb_hs_core_clk.
167 * @regs: ioremapped register base address.
168 * @inputs: OTG state machine inputs(Id, SessValid etc).
169 * @sm_work: OTG state machine work.
170 * @in_lpm: indicates low power mode (LPM) state.
171 * @async_int: Async interrupt arrived.
172 * @cur_power: The amount of mA available from downstream port.
173 * @chg_work: Charger detection work.
174 * @chg_state: The state of charger detection process.
175 * @chg_type: The type of charger attached.
176 * @dcd_retires: The retry count used to track Data contact
178 * @manual_pullup: true if VBUS is not routed to USB controller/phy
179 * and controller driver therefore enables pull-up explicitly before
180 * starting controller using usbcmd run/stop bit.
181 * @vbus: VBUS signal state trakining, using extcon framework
182 * @id: ID signal state trakining, using extcon framework
183 * @switch_gpio: Descriptor for GPIO used to control external Dual
185 * @reboot: Used to inform the driver to route USB D+/D- line to Device
190 struct msm_otg_platform_data
*pdata
;
194 struct clk
*core_clk
;
198 unsigned long inputs
;
199 struct work_struct sm_work
;
204 struct delayed_work chg_work
;
205 enum usb_chg_state chg_state
;
206 enum usb_chg_type chg_type
;
208 struct regulator
*v3p3
;
209 struct regulator
*v1p8
;
210 struct regulator
*vddcx
;
212 struct reset_control
*phy_rst
;
213 struct reset_control
*link_rst
;
218 struct msm_usb_cable vbus
;
219 struct msm_usb_cable id
;
221 struct gpio_desc
*switch_gpio
;
222 struct notifier_block reboot
;
225 #define MSM_USB_BASE (motg->regs)
226 #define DRIVER_NAME "msm_otg"
228 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
229 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
231 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
232 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
233 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
234 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
236 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
237 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
238 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
239 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
241 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
242 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
243 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
251 static int msm_hsusb_init_vddcx(struct msm_otg
*motg
, int init
)
256 ret
= regulator_set_voltage(motg
->vddcx
,
257 motg
->vdd_levels
[VDD_LEVEL_MIN
],
258 motg
->vdd_levels
[VDD_LEVEL_MAX
]);
260 dev_err(motg
->phy
.dev
, "Cannot set vddcx voltage\n");
264 ret
= regulator_enable(motg
->vddcx
);
266 dev_err(motg
->phy
.dev
, "unable to enable hsusb vddcx\n");
268 ret
= regulator_set_voltage(motg
->vddcx
, 0,
269 motg
->vdd_levels
[VDD_LEVEL_MAX
]);
271 dev_err(motg
->phy
.dev
, "Cannot set vddcx voltage\n");
272 ret
= regulator_disable(motg
->vddcx
);
274 dev_err(motg
->phy
.dev
, "unable to disable hsusb vddcx\n");
280 static int msm_hsusb_ldo_init(struct msm_otg
*motg
, int init
)
285 rc
= regulator_set_voltage(motg
->v3p3
, USB_PHY_3P3_VOL_MIN
,
286 USB_PHY_3P3_VOL_MAX
);
288 dev_err(motg
->phy
.dev
, "Cannot set v3p3 voltage\n");
291 rc
= regulator_enable(motg
->v3p3
);
293 dev_err(motg
->phy
.dev
, "unable to enable the hsusb 3p3\n");
296 rc
= regulator_set_voltage(motg
->v1p8
, USB_PHY_1P8_VOL_MIN
,
297 USB_PHY_1P8_VOL_MAX
);
299 dev_err(motg
->phy
.dev
, "Cannot set v1p8 voltage\n");
302 rc
= regulator_enable(motg
->v1p8
);
304 dev_err(motg
->phy
.dev
, "unable to enable the hsusb 1p8\n");
311 regulator_disable(motg
->v1p8
);
313 regulator_disable(motg
->v3p3
);
318 static int msm_hsusb_ldo_set_mode(struct msm_otg
*motg
, int on
)
323 ret
= regulator_set_load(motg
->v1p8
, USB_PHY_1P8_HPM_LOAD
);
325 pr_err("Could not set HPM for v1p8\n");
328 ret
= regulator_set_load(motg
->v3p3
, USB_PHY_3P3_HPM_LOAD
);
330 pr_err("Could not set HPM for v3p3\n");
331 regulator_set_load(motg
->v1p8
, USB_PHY_1P8_LPM_LOAD
);
335 ret
= regulator_set_load(motg
->v1p8
, USB_PHY_1P8_LPM_LOAD
);
337 pr_err("Could not set LPM for v1p8\n");
338 ret
= regulator_set_load(motg
->v3p3
, USB_PHY_3P3_LPM_LOAD
);
340 pr_err("Could not set LPM for v3p3\n");
343 pr_debug("reg (%s)\n", on
? "HPM" : "LPM");
344 return ret
< 0 ? ret
: 0;
347 static int ulpi_read(struct usb_phy
*phy
, u32 reg
)
349 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
352 /* initiate read operation */
353 writel(ULPI_RUN
| ULPI_READ
| ULPI_ADDR(reg
),
356 /* wait for completion */
357 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
358 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
364 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
365 dev_err(phy
->dev
, "ulpi_read: timeout %08x\n",
366 readl(USB_ULPI_VIEWPORT
));
369 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT
));
372 static int ulpi_write(struct usb_phy
*phy
, u32 val
, u32 reg
)
374 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
377 /* initiate write operation */
378 writel(ULPI_RUN
| ULPI_WRITE
|
379 ULPI_ADDR(reg
) | ULPI_DATA(val
),
382 /* wait for completion */
383 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
384 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
390 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
391 dev_err(phy
->dev
, "ulpi_write: timeout\n");
397 static struct usb_phy_io_ops msm_otg_io_ops
= {
402 static void ulpi_init(struct msm_otg
*motg
)
404 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
405 int *seq
= pdata
->phy_init_seq
, idx
;
406 u32 addr
= ULPI_EXT_VENDOR_SPECIFIC
;
408 for (idx
= 0; idx
< pdata
->phy_init_sz
; idx
++) {
412 dev_vdbg(motg
->phy
.dev
, "ulpi: write 0x%02x to 0x%02x\n",
413 seq
[idx
], addr
+ idx
);
414 ulpi_write(&motg
->phy
, seq
[idx
], addr
+ idx
);
418 static int msm_phy_notify_disconnect(struct usb_phy
*phy
,
419 enum usb_device_speed speed
)
421 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
424 if (motg
->manual_pullup
) {
425 val
= ULPI_MISC_A_VBUSVLDEXT
| ULPI_MISC_A_VBUSVLDEXTSEL
;
426 usb_phy_io_write(phy
, val
, ULPI_CLR(ULPI_MISC_A
));
430 * Put the transceiver in non-driving mode. Otherwise host
431 * may not detect soft-disconnection.
433 val
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
434 val
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
435 val
|= ULPI_FUNC_CTRL_OPMODE_NONDRIVING
;
436 ulpi_write(phy
, val
, ULPI_FUNC_CTRL
);
441 static int msm_otg_link_clk_reset(struct msm_otg
*motg
, bool assert)
446 ret
= reset_control_assert(motg
->link_rst
);
448 ret
= reset_control_deassert(motg
->link_rst
);
451 dev_err(motg
->phy
.dev
, "usb link clk reset %s failed\n",
452 assert ? "assert" : "deassert");
457 static int msm_otg_phy_clk_reset(struct msm_otg
*motg
)
462 ret
= reset_control_reset(motg
->phy_rst
);
465 dev_err(motg
->phy
.dev
, "usb phy clk reset failed\n");
470 static int msm_link_reset(struct msm_otg
*motg
)
475 ret
= msm_otg_link_clk_reset(motg
, 1);
479 /* wait for 1ms delay as suggested in HPG. */
480 usleep_range(1000, 1200);
482 ret
= msm_otg_link_clk_reset(motg
, 0);
486 if (motg
->phy_number
)
487 writel(readl(USB_PHY_CTRL2
) | BIT(16), USB_PHY_CTRL2
);
489 /* put transceiver in serial mode as part of reset */
490 val
= readl(USB_PORTSC
) & ~PORTSC_PTS_MASK
;
491 writel(val
| PORTSC_PTS_SERIAL
, USB_PORTSC
);
496 static int msm_otg_reset(struct usb_phy
*phy
)
498 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
501 writel(USBCMD_RESET
, USB_USBCMD
);
502 while (cnt
< LINK_RESET_TIMEOUT_USEC
) {
503 if (!(readl(USB_USBCMD
) & USBCMD_RESET
))
508 if (cnt
>= LINK_RESET_TIMEOUT_USEC
)
511 /* select ULPI phy and clear other status/control bits in PORTSC */
512 writel(PORTSC_PTS_ULPI
, USB_PORTSC
);
514 writel(0x0, USB_AHBBURST
);
515 writel(0x08, USB_AHBMODE
);
517 if (motg
->phy_number
)
518 writel(readl(USB_PHY_CTRL2
) | BIT(16), USB_PHY_CTRL2
);
522 static void msm_phy_reset(struct msm_otg
*motg
)
526 if (motg
->pdata
->phy_type
!= SNPS_28NM_INTEGRATED_PHY
) {
527 msm_otg_phy_clk_reset(motg
);
532 if (motg
->phy_number
)
533 addr
= USB_PHY_CTRL2
;
535 /* Assert USB PHY_POR */
536 writel(readl(addr
) | PHY_POR_ASSERT
, addr
);
539 * wait for minimum 10 microseconds as suggested in HPG.
540 * Use a slightly larger value since the exact value didn't
541 * work 100% of the time.
545 /* Deassert USB PHY_POR */
546 writel(readl(addr
) & ~PHY_POR_ASSERT
, addr
);
549 static int msm_usb_reset(struct usb_phy
*phy
)
551 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
554 if (!IS_ERR(motg
->core_clk
))
555 clk_prepare_enable(motg
->core_clk
);
557 ret
= msm_link_reset(motg
);
559 dev_err(phy
->dev
, "phy_reset failed\n");
563 ret
= msm_otg_reset(&motg
->phy
);
565 dev_err(phy
->dev
, "link reset failed\n");
571 /* Reset USB PHY after performing USB Link RESET */
574 if (!IS_ERR(motg
->core_clk
))
575 clk_disable_unprepare(motg
->core_clk
);
580 static int msm_phy_init(struct usb_phy
*phy
)
582 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
583 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
584 u32 val
, ulpi_val
= 0;
586 /* Program USB PHY Override registers. */
590 * It is recommended in HPG to reset USB PHY after programming
591 * USB PHY Override registers.
595 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
596 val
= readl(USB_OTGSC
);
597 if (pdata
->mode
== USB_DR_MODE_OTG
) {
598 ulpi_val
= ULPI_INT_IDGRD
| ULPI_INT_SESS_VALID
;
599 val
|= OTGSC_IDIE
| OTGSC_BSVIE
;
600 } else if (pdata
->mode
== USB_DR_MODE_PERIPHERAL
) {
601 ulpi_val
= ULPI_INT_SESS_VALID
;
604 writel(val
, USB_OTGSC
);
605 ulpi_write(phy
, ulpi_val
, ULPI_USB_INT_EN_RISE
);
606 ulpi_write(phy
, ulpi_val
, ULPI_USB_INT_EN_FALL
);
609 if (motg
->manual_pullup
) {
610 val
= ULPI_MISC_A_VBUSVLDEXTSEL
| ULPI_MISC_A_VBUSVLDEXT
;
611 ulpi_write(phy
, val
, ULPI_SET(ULPI_MISC_A
));
613 val
= readl(USB_GENCONFIG_2
);
614 val
|= GENCONFIG_2_SESS_VLD_CTRL_EN
;
615 writel(val
, USB_GENCONFIG_2
);
617 val
= readl(USB_USBCMD
);
618 val
|= USBCMD_SESS_VLD_CTRL
;
619 writel(val
, USB_USBCMD
);
621 val
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
622 val
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
623 val
|= ULPI_FUNC_CTRL_OPMODE_NORMAL
;
624 ulpi_write(phy
, val
, ULPI_FUNC_CTRL
);
627 if (motg
->phy_number
)
628 writel(readl(USB_PHY_CTRL2
) | BIT(16), USB_PHY_CTRL2
);
633 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
634 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
638 static int msm_hsusb_config_vddcx(struct msm_otg
*motg
, int high
)
640 int max_vol
= motg
->vdd_levels
[VDD_LEVEL_MAX
];
645 min_vol
= motg
->vdd_levels
[VDD_LEVEL_MIN
];
647 min_vol
= motg
->vdd_levels
[VDD_LEVEL_NONE
];
649 ret
= regulator_set_voltage(motg
->vddcx
, min_vol
, max_vol
);
651 pr_err("Cannot set vddcx voltage\n");
655 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__
, min_vol
, max_vol
);
660 static int msm_otg_suspend(struct msm_otg
*motg
)
662 struct usb_phy
*phy
= &motg
->phy
;
663 struct usb_bus
*bus
= phy
->otg
->host
;
664 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
668 if (atomic_read(&motg
->in_lpm
))
671 disable_irq(motg
->irq
);
673 * Chipidea 45-nm PHY suspend sequence:
675 * Interrupt Latch Register auto-clear feature is not present
676 * in all PHY versions. Latch register is clear on read type.
677 * Clear latch register to avoid spurious wakeup from
678 * low power mode (LPM).
680 * PHY comparators are disabled when PHY enters into low power
681 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
682 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
683 * PHY comparators. This save significant amount of power.
685 * PLL is not turned off when PHY enters into low power mode (LPM).
686 * Disable PLL for maximum power savings.
689 if (motg
->pdata
->phy_type
== CI_45NM_INTEGRATED_PHY
) {
690 ulpi_read(phy
, 0x14);
691 if (pdata
->otg_control
== OTG_PHY_CONTROL
)
692 ulpi_write(phy
, 0x01, 0x30);
693 ulpi_write(phy
, 0x08, 0x09);
697 * PHY may take some time or even fail to enter into low power
698 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
701 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
702 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
703 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
709 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
) {
710 dev_err(phy
->dev
, "Unable to suspend PHY\n");
712 enable_irq(motg
->irq
);
717 * PHY has capability to generate interrupt asynchronously in low
718 * power mode (LPM). This interrupt is level triggered. So USB IRQ
719 * line must be disabled till async interrupt enable bit is cleared
720 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
721 * block data communication from PHY.
723 writel(readl(USB_USBCMD
) | ASYNC_INTR_CTRL
| ULPI_STP_CTRL
, USB_USBCMD
);
726 if (motg
->phy_number
)
727 addr
= USB_PHY_CTRL2
;
729 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
730 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
)
731 writel(readl(addr
) | PHY_RETEN
, addr
);
733 clk_disable_unprepare(motg
->pclk
);
734 clk_disable_unprepare(motg
->clk
);
735 if (!IS_ERR(motg
->core_clk
))
736 clk_disable_unprepare(motg
->core_clk
);
738 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
739 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
740 msm_hsusb_ldo_set_mode(motg
, 0);
741 msm_hsusb_config_vddcx(motg
, 0);
744 if (device_may_wakeup(phy
->dev
))
745 enable_irq_wake(motg
->irq
);
747 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
749 atomic_set(&motg
->in_lpm
, 1);
750 enable_irq(motg
->irq
);
752 dev_info(phy
->dev
, "USB in low power mode\n");
757 static int msm_otg_resume(struct msm_otg
*motg
)
759 struct usb_phy
*phy
= &motg
->phy
;
760 struct usb_bus
*bus
= phy
->otg
->host
;
765 if (!atomic_read(&motg
->in_lpm
))
768 clk_prepare_enable(motg
->pclk
);
769 clk_prepare_enable(motg
->clk
);
770 if (!IS_ERR(motg
->core_clk
))
771 clk_prepare_enable(motg
->core_clk
);
773 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
774 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
777 if (motg
->phy_number
)
778 addr
= USB_PHY_CTRL2
;
780 msm_hsusb_ldo_set_mode(motg
, 1);
781 msm_hsusb_config_vddcx(motg
, 1);
782 writel(readl(addr
) & ~PHY_RETEN
, addr
);
785 temp
= readl(USB_USBCMD
);
786 temp
&= ~ASYNC_INTR_CTRL
;
787 temp
&= ~ULPI_STP_CTRL
;
788 writel(temp
, USB_USBCMD
);
791 * PHY comes out of low power mode (LPM) in case of wakeup
792 * from asynchronous interrupt.
794 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
795 goto skip_phy_resume
;
797 writel(readl(USB_PORTSC
) & ~PORTSC_PHCD
, USB_PORTSC
);
798 while (cnt
< PHY_RESUME_TIMEOUT_USEC
) {
799 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
805 if (cnt
>= PHY_RESUME_TIMEOUT_USEC
) {
807 * This is a fatal error. Reset the link and
808 * PHY. USB state can not be restored. Re-insertion
809 * of USB cable is the only way to get USB working.
811 dev_err(phy
->dev
, "Unable to resume USB. Re-plugin the cable\n");
816 if (device_may_wakeup(phy
->dev
))
817 disable_irq_wake(motg
->irq
);
819 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
821 atomic_set(&motg
->in_lpm
, 0);
823 if (motg
->async_int
) {
825 pm_runtime_put(phy
->dev
);
826 enable_irq(motg
->irq
);
829 dev_info(phy
->dev
, "USB exited from low power mode\n");
835 static void msm_otg_notify_charger(struct msm_otg
*motg
, unsigned mA
)
837 if (motg
->cur_power
== mA
)
840 /* TODO: Notify PMIC about available current */
841 dev_info(motg
->phy
.dev
, "Avail curr from USB = %u\n", mA
);
842 motg
->cur_power
= mA
;
845 static void msm_otg_start_host(struct usb_phy
*phy
, int on
)
847 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
848 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
854 hcd
= bus_to_hcd(phy
->otg
->host
);
857 dev_dbg(phy
->dev
, "host on\n");
859 if (pdata
->vbus_power
)
860 pdata
->vbus_power(1);
862 * Some boards have a switch cotrolled by gpio
863 * to enable/disable internal HUB. Enable internal
864 * HUB before kicking the host.
866 if (pdata
->setup_gpio
)
867 pdata
->setup_gpio(OTG_STATE_A_HOST
);
869 usb_add_hcd(hcd
, hcd
->irq
, IRQF_SHARED
);
870 device_wakeup_enable(hcd
->self
.controller
);
873 dev_dbg(phy
->dev
, "host off\n");
878 if (pdata
->setup_gpio
)
879 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
880 if (pdata
->vbus_power
)
881 pdata
->vbus_power(0);
885 static int msm_otg_set_host(struct usb_otg
*otg
, struct usb_bus
*host
)
887 struct msm_otg
*motg
= container_of(otg
->usb_phy
, struct msm_otg
, phy
);
891 * Fail host registration if this board can support
892 * only peripheral configuration.
894 if (motg
->pdata
->mode
== USB_DR_MODE_PERIPHERAL
) {
895 dev_info(otg
->usb_phy
->dev
, "Host mode is not supported\n");
900 if (otg
->state
== OTG_STATE_A_HOST
) {
901 pm_runtime_get_sync(otg
->usb_phy
->dev
);
902 msm_otg_start_host(otg
->usb_phy
, 0);
904 otg
->state
= OTG_STATE_UNDEFINED
;
905 schedule_work(&motg
->sm_work
);
913 hcd
= bus_to_hcd(host
);
914 hcd
->power_budget
= motg
->pdata
->power_budget
;
917 dev_dbg(otg
->usb_phy
->dev
, "host driver registered w/ tranceiver\n");
919 pm_runtime_get_sync(otg
->usb_phy
->dev
);
920 schedule_work(&motg
->sm_work
);
925 static void msm_otg_start_peripheral(struct usb_phy
*phy
, int on
)
927 struct msm_otg
*motg
= container_of(phy
, struct msm_otg
, phy
);
928 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
930 if (!phy
->otg
->gadget
)
934 dev_dbg(phy
->dev
, "gadget on\n");
936 * Some boards have a switch cotrolled by gpio
937 * to enable/disable internal HUB. Disable internal
938 * HUB before kicking the gadget.
940 if (pdata
->setup_gpio
)
941 pdata
->setup_gpio(OTG_STATE_B_PERIPHERAL
);
942 usb_gadget_vbus_connect(phy
->otg
->gadget
);
944 dev_dbg(phy
->dev
, "gadget off\n");
945 usb_gadget_vbus_disconnect(phy
->otg
->gadget
);
946 if (pdata
->setup_gpio
)
947 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
952 static int msm_otg_set_peripheral(struct usb_otg
*otg
,
953 struct usb_gadget
*gadget
)
955 struct msm_otg
*motg
= container_of(otg
->usb_phy
, struct msm_otg
, phy
);
958 * Fail peripheral registration if this board can support
959 * only host configuration.
961 if (motg
->pdata
->mode
== USB_DR_MODE_HOST
) {
962 dev_info(otg
->usb_phy
->dev
, "Peripheral mode is not supported\n");
967 if (otg
->state
== OTG_STATE_B_PERIPHERAL
) {
968 pm_runtime_get_sync(otg
->usb_phy
->dev
);
969 msm_otg_start_peripheral(otg
->usb_phy
, 0);
971 otg
->state
= OTG_STATE_UNDEFINED
;
972 schedule_work(&motg
->sm_work
);
979 otg
->gadget
= gadget
;
980 dev_dbg(otg
->usb_phy
->dev
,
981 "peripheral driver registered w/ tranceiver\n");
983 pm_runtime_get_sync(otg
->usb_phy
->dev
);
984 schedule_work(&motg
->sm_work
);
989 static bool msm_chg_check_secondary_det(struct msm_otg
*motg
)
991 struct usb_phy
*phy
= &motg
->phy
;
995 switch (motg
->pdata
->phy_type
) {
996 case CI_45NM_INTEGRATED_PHY
:
997 chg_det
= ulpi_read(phy
, 0x34);
998 ret
= chg_det
& (1 << 4);
1000 case SNPS_28NM_INTEGRATED_PHY
:
1001 chg_det
= ulpi_read(phy
, 0x87);
1010 static void msm_chg_enable_secondary_det(struct msm_otg
*motg
)
1012 struct usb_phy
*phy
= &motg
->phy
;
1015 switch (motg
->pdata
->phy_type
) {
1016 case CI_45NM_INTEGRATED_PHY
:
1017 chg_det
= ulpi_read(phy
, 0x34);
1018 /* Turn off charger block */
1019 chg_det
|= ~(1 << 1);
1020 ulpi_write(phy
, chg_det
, 0x34);
1022 /* control chg block via ULPI */
1023 chg_det
&= ~(1 << 3);
1024 ulpi_write(phy
, chg_det
, 0x34);
1025 /* put it in host mode for enabling D- source */
1026 chg_det
&= ~(1 << 2);
1027 ulpi_write(phy
, chg_det
, 0x34);
1028 /* Turn on chg detect block */
1029 chg_det
&= ~(1 << 1);
1030 ulpi_write(phy
, chg_det
, 0x34);
1032 /* enable chg detection */
1033 chg_det
&= ~(1 << 0);
1034 ulpi_write(phy
, chg_det
, 0x34);
1036 case SNPS_28NM_INTEGRATED_PHY
:
1038 * Configure DM as current source, DP as current sink
1039 * and enable battery charging comparators.
1041 ulpi_write(phy
, 0x8, 0x85);
1042 ulpi_write(phy
, 0x2, 0x85);
1043 ulpi_write(phy
, 0x1, 0x85);
1050 static bool msm_chg_check_primary_det(struct msm_otg
*motg
)
1052 struct usb_phy
*phy
= &motg
->phy
;
1056 switch (motg
->pdata
->phy_type
) {
1057 case CI_45NM_INTEGRATED_PHY
:
1058 chg_det
= ulpi_read(phy
, 0x34);
1059 ret
= chg_det
& (1 << 4);
1061 case SNPS_28NM_INTEGRATED_PHY
:
1062 chg_det
= ulpi_read(phy
, 0x87);
1071 static void msm_chg_enable_primary_det(struct msm_otg
*motg
)
1073 struct usb_phy
*phy
= &motg
->phy
;
1076 switch (motg
->pdata
->phy_type
) {
1077 case CI_45NM_INTEGRATED_PHY
:
1078 chg_det
= ulpi_read(phy
, 0x34);
1079 /* enable chg detection */
1080 chg_det
&= ~(1 << 0);
1081 ulpi_write(phy
, chg_det
, 0x34);
1083 case SNPS_28NM_INTEGRATED_PHY
:
1085 * Configure DP as current source, DM as current sink
1086 * and enable battery charging comparators.
1088 ulpi_write(phy
, 0x2, 0x85);
1089 ulpi_write(phy
, 0x1, 0x85);
1096 static bool msm_chg_check_dcd(struct msm_otg
*motg
)
1098 struct usb_phy
*phy
= &motg
->phy
;
1102 switch (motg
->pdata
->phy_type
) {
1103 case CI_45NM_INTEGRATED_PHY
:
1104 line_state
= ulpi_read(phy
, 0x15);
1105 ret
= !(line_state
& 1);
1107 case SNPS_28NM_INTEGRATED_PHY
:
1108 line_state
= ulpi_read(phy
, 0x87);
1109 ret
= line_state
& 2;
1117 static void msm_chg_disable_dcd(struct msm_otg
*motg
)
1119 struct usb_phy
*phy
= &motg
->phy
;
1122 switch (motg
->pdata
->phy_type
) {
1123 case CI_45NM_INTEGRATED_PHY
:
1124 chg_det
= ulpi_read(phy
, 0x34);
1125 chg_det
&= ~(1 << 5);
1126 ulpi_write(phy
, chg_det
, 0x34);
1128 case SNPS_28NM_INTEGRATED_PHY
:
1129 ulpi_write(phy
, 0x10, 0x86);
1136 static void msm_chg_enable_dcd(struct msm_otg
*motg
)
1138 struct usb_phy
*phy
= &motg
->phy
;
1141 switch (motg
->pdata
->phy_type
) {
1142 case CI_45NM_INTEGRATED_PHY
:
1143 chg_det
= ulpi_read(phy
, 0x34);
1144 /* Turn on D+ current source */
1145 chg_det
|= (1 << 5);
1146 ulpi_write(phy
, chg_det
, 0x34);
1148 case SNPS_28NM_INTEGRATED_PHY
:
1149 /* Data contact detection enable */
1150 ulpi_write(phy
, 0x10, 0x85);
1157 static void msm_chg_block_on(struct msm_otg
*motg
)
1159 struct usb_phy
*phy
= &motg
->phy
;
1160 u32 func_ctrl
, chg_det
;
1162 /* put the controller in non-driving mode */
1163 func_ctrl
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
1164 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
1165 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NONDRIVING
;
1166 ulpi_write(phy
, func_ctrl
, ULPI_FUNC_CTRL
);
1168 switch (motg
->pdata
->phy_type
) {
1169 case CI_45NM_INTEGRATED_PHY
:
1170 chg_det
= ulpi_read(phy
, 0x34);
1171 /* control chg block via ULPI */
1172 chg_det
&= ~(1 << 3);
1173 ulpi_write(phy
, chg_det
, 0x34);
1174 /* Turn on chg detect block */
1175 chg_det
&= ~(1 << 1);
1176 ulpi_write(phy
, chg_det
, 0x34);
1179 case SNPS_28NM_INTEGRATED_PHY
:
1180 /* Clear charger detecting control bits */
1181 ulpi_write(phy
, 0x3F, 0x86);
1182 /* Clear alt interrupt latch and enable bits */
1183 ulpi_write(phy
, 0x1F, 0x92);
1184 ulpi_write(phy
, 0x1F, 0x95);
1192 static void msm_chg_block_off(struct msm_otg
*motg
)
1194 struct usb_phy
*phy
= &motg
->phy
;
1195 u32 func_ctrl
, chg_det
;
1197 switch (motg
->pdata
->phy_type
) {
1198 case CI_45NM_INTEGRATED_PHY
:
1199 chg_det
= ulpi_read(phy
, 0x34);
1200 /* Turn off charger block */
1201 chg_det
|= ~(1 << 1);
1202 ulpi_write(phy
, chg_det
, 0x34);
1204 case SNPS_28NM_INTEGRATED_PHY
:
1205 /* Clear charger detecting control bits */
1206 ulpi_write(phy
, 0x3F, 0x86);
1207 /* Clear alt interrupt latch and enable bits */
1208 ulpi_write(phy
, 0x1F, 0x92);
1209 ulpi_write(phy
, 0x1F, 0x95);
1215 /* put the controller in normal mode */
1216 func_ctrl
= ulpi_read(phy
, ULPI_FUNC_CTRL
);
1217 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
1218 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NORMAL
;
1219 ulpi_write(phy
, func_ctrl
, ULPI_FUNC_CTRL
);
1222 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1223 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1224 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1225 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1226 static void msm_chg_detect_work(struct work_struct
*w
)
1228 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, chg_work
.work
);
1229 struct usb_phy
*phy
= &motg
->phy
;
1230 bool is_dcd
, tmout
, vout
;
1231 unsigned long delay
;
1233 dev_dbg(phy
->dev
, "chg detection work\n");
1234 switch (motg
->chg_state
) {
1235 case USB_CHG_STATE_UNDEFINED
:
1236 pm_runtime_get_sync(phy
->dev
);
1237 msm_chg_block_on(motg
);
1238 msm_chg_enable_dcd(motg
);
1239 motg
->chg_state
= USB_CHG_STATE_WAIT_FOR_DCD
;
1240 motg
->dcd_retries
= 0;
1241 delay
= MSM_CHG_DCD_POLL_TIME
;
1243 case USB_CHG_STATE_WAIT_FOR_DCD
:
1244 is_dcd
= msm_chg_check_dcd(motg
);
1245 tmout
= ++motg
->dcd_retries
== MSM_CHG_DCD_MAX_RETRIES
;
1246 if (is_dcd
|| tmout
) {
1247 msm_chg_disable_dcd(motg
);
1248 msm_chg_enable_primary_det(motg
);
1249 delay
= MSM_CHG_PRIMARY_DET_TIME
;
1250 motg
->chg_state
= USB_CHG_STATE_DCD_DONE
;
1252 delay
= MSM_CHG_DCD_POLL_TIME
;
1255 case USB_CHG_STATE_DCD_DONE
:
1256 vout
= msm_chg_check_primary_det(motg
);
1258 msm_chg_enable_secondary_det(motg
);
1259 delay
= MSM_CHG_SECONDARY_DET_TIME
;
1260 motg
->chg_state
= USB_CHG_STATE_PRIMARY_DONE
;
1262 motg
->chg_type
= USB_SDP_CHARGER
;
1263 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1267 case USB_CHG_STATE_PRIMARY_DONE
:
1268 vout
= msm_chg_check_secondary_det(motg
);
1270 motg
->chg_type
= USB_DCP_CHARGER
;
1272 motg
->chg_type
= USB_CDP_CHARGER
;
1273 motg
->chg_state
= USB_CHG_STATE_SECONDARY_DONE
;
1275 case USB_CHG_STATE_SECONDARY_DONE
:
1276 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1277 case USB_CHG_STATE_DETECTED
:
1278 msm_chg_block_off(motg
);
1279 dev_dbg(phy
->dev
, "charger = %d\n", motg
->chg_type
);
1280 schedule_work(&motg
->sm_work
);
1286 schedule_delayed_work(&motg
->chg_work
, delay
);
1290 * We support OTG, Peripheral only and Host only configurations. In case
1291 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1292 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1293 * enabled when switch is controlled by user and default mode is supplied
1294 * by board file, which can be changed by userspace later.
1296 static void msm_otg_init_sm(struct msm_otg
*motg
)
1298 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
1299 u32 otgsc
= readl(USB_OTGSC
);
1301 switch (pdata
->mode
) {
1302 case USB_DR_MODE_OTG
:
1303 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
1304 if (otgsc
& OTGSC_ID
)
1305 set_bit(ID
, &motg
->inputs
);
1307 clear_bit(ID
, &motg
->inputs
);
1309 if (otgsc
& OTGSC_BSV
)
1310 set_bit(B_SESS_VLD
, &motg
->inputs
);
1312 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1313 } else if (pdata
->otg_control
== OTG_USER_CONTROL
) {
1314 set_bit(ID
, &motg
->inputs
);
1315 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1318 case USB_DR_MODE_HOST
:
1319 clear_bit(ID
, &motg
->inputs
);
1321 case USB_DR_MODE_PERIPHERAL
:
1322 set_bit(ID
, &motg
->inputs
);
1323 if (otgsc
& OTGSC_BSV
)
1324 set_bit(B_SESS_VLD
, &motg
->inputs
);
1326 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1333 static void msm_otg_sm_work(struct work_struct
*w
)
1335 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, sm_work
);
1336 struct usb_otg
*otg
= motg
->phy
.otg
;
1338 switch (otg
->state
) {
1339 case OTG_STATE_UNDEFINED
:
1340 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_UNDEFINED state\n");
1341 msm_otg_reset(otg
->usb_phy
);
1342 msm_otg_init_sm(motg
);
1343 otg
->state
= OTG_STATE_B_IDLE
;
1345 case OTG_STATE_B_IDLE
:
1346 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_B_IDLE state\n");
1347 if (!test_bit(ID
, &motg
->inputs
) && otg
->host
) {
1348 /* disable BSV bit */
1349 writel(readl(USB_OTGSC
) & ~OTGSC_BSVIE
, USB_OTGSC
);
1350 msm_otg_start_host(otg
->usb_phy
, 1);
1351 otg
->state
= OTG_STATE_A_HOST
;
1352 } else if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1353 switch (motg
->chg_state
) {
1354 case USB_CHG_STATE_UNDEFINED
:
1355 msm_chg_detect_work(&motg
->chg_work
.work
);
1357 case USB_CHG_STATE_DETECTED
:
1358 switch (motg
->chg_type
) {
1359 case USB_DCP_CHARGER
:
1360 msm_otg_notify_charger(motg
,
1363 case USB_CDP_CHARGER
:
1364 msm_otg_notify_charger(motg
,
1366 msm_otg_start_peripheral(otg
->usb_phy
,
1369 = OTG_STATE_B_PERIPHERAL
;
1371 case USB_SDP_CHARGER
:
1372 msm_otg_notify_charger(motg
, IUNIT
);
1373 msm_otg_start_peripheral(otg
->usb_phy
,
1376 = OTG_STATE_B_PERIPHERAL
;
1387 * If charger detection work is pending, decrement
1388 * the pm usage counter to balance with the one that
1389 * is incremented in charger detection work.
1391 if (cancel_delayed_work_sync(&motg
->chg_work
)) {
1392 pm_runtime_put_sync(otg
->usb_phy
->dev
);
1393 msm_otg_reset(otg
->usb_phy
);
1395 msm_otg_notify_charger(motg
, 0);
1396 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1397 motg
->chg_type
= USB_INVALID_CHARGER
;
1400 if (otg
->state
== OTG_STATE_B_IDLE
)
1401 pm_runtime_put_sync(otg
->usb_phy
->dev
);
1403 case OTG_STATE_B_PERIPHERAL
:
1404 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_B_PERIPHERAL state\n");
1405 if (!test_bit(B_SESS_VLD
, &motg
->inputs
) ||
1406 !test_bit(ID
, &motg
->inputs
)) {
1407 msm_otg_notify_charger(motg
, 0);
1408 msm_otg_start_peripheral(otg
->usb_phy
, 0);
1409 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1410 motg
->chg_type
= USB_INVALID_CHARGER
;
1411 otg
->state
= OTG_STATE_B_IDLE
;
1412 msm_otg_reset(otg
->usb_phy
);
1416 case OTG_STATE_A_HOST
:
1417 dev_dbg(otg
->usb_phy
->dev
, "OTG_STATE_A_HOST state\n");
1418 if (test_bit(ID
, &motg
->inputs
)) {
1419 msm_otg_start_host(otg
->usb_phy
, 0);
1420 otg
->state
= OTG_STATE_B_IDLE
;
1421 msm_otg_reset(otg
->usb_phy
);
1430 static irqreturn_t
msm_otg_irq(int irq
, void *data
)
1432 struct msm_otg
*motg
= data
;
1433 struct usb_phy
*phy
= &motg
->phy
;
1436 if (atomic_read(&motg
->in_lpm
)) {
1437 disable_irq_nosync(irq
);
1438 motg
->async_int
= 1;
1439 pm_runtime_get(phy
->dev
);
1443 otgsc
= readl(USB_OTGSC
);
1444 if (!(otgsc
& (OTGSC_IDIS
| OTGSC_BSVIS
)))
1447 if ((otgsc
& OTGSC_IDIS
) && (otgsc
& OTGSC_IDIE
)) {
1448 if (otgsc
& OTGSC_ID
)
1449 set_bit(ID
, &motg
->inputs
);
1451 clear_bit(ID
, &motg
->inputs
);
1452 dev_dbg(phy
->dev
, "ID set/clear\n");
1453 pm_runtime_get_noresume(phy
->dev
);
1454 } else if ((otgsc
& OTGSC_BSVIS
) && (otgsc
& OTGSC_BSVIE
)) {
1455 if (otgsc
& OTGSC_BSV
)
1456 set_bit(B_SESS_VLD
, &motg
->inputs
);
1458 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1459 dev_dbg(phy
->dev
, "BSV set/clear\n");
1460 pm_runtime_get_noresume(phy
->dev
);
1463 writel(otgsc
, USB_OTGSC
);
1464 schedule_work(&motg
->sm_work
);
1468 static int msm_otg_mode_show(struct seq_file
*s
, void *unused
)
1470 struct msm_otg
*motg
= s
->private;
1471 struct usb_otg
*otg
= motg
->phy
.otg
;
1473 switch (otg
->state
) {
1474 case OTG_STATE_A_HOST
:
1475 seq_puts(s
, "host\n");
1477 case OTG_STATE_B_PERIPHERAL
:
1478 seq_puts(s
, "peripheral\n");
1481 seq_puts(s
, "none\n");
1488 static int msm_otg_mode_open(struct inode
*inode
, struct file
*file
)
1490 return single_open(file
, msm_otg_mode_show
, inode
->i_private
);
1493 static ssize_t
msm_otg_mode_write(struct file
*file
, const char __user
*ubuf
,
1494 size_t count
, loff_t
*ppos
)
1496 struct seq_file
*s
= file
->private_data
;
1497 struct msm_otg
*motg
= s
->private;
1499 struct usb_otg
*otg
= motg
->phy
.otg
;
1501 enum usb_dr_mode req_mode
;
1503 memset(buf
, 0x00, sizeof(buf
));
1505 if (copy_from_user(&buf
, ubuf
, min_t(size_t, sizeof(buf
) - 1, count
))) {
1510 if (!strncmp(buf
, "host", 4)) {
1511 req_mode
= USB_DR_MODE_HOST
;
1512 } else if (!strncmp(buf
, "peripheral", 10)) {
1513 req_mode
= USB_DR_MODE_PERIPHERAL
;
1514 } else if (!strncmp(buf
, "none", 4)) {
1515 req_mode
= USB_DR_MODE_UNKNOWN
;
1522 case USB_DR_MODE_UNKNOWN
:
1523 switch (otg
->state
) {
1524 case OTG_STATE_A_HOST
:
1525 case OTG_STATE_B_PERIPHERAL
:
1526 set_bit(ID
, &motg
->inputs
);
1527 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1533 case USB_DR_MODE_PERIPHERAL
:
1534 switch (otg
->state
) {
1535 case OTG_STATE_B_IDLE
:
1536 case OTG_STATE_A_HOST
:
1537 set_bit(ID
, &motg
->inputs
);
1538 set_bit(B_SESS_VLD
, &motg
->inputs
);
1544 case USB_DR_MODE_HOST
:
1545 switch (otg
->state
) {
1546 case OTG_STATE_B_IDLE
:
1547 case OTG_STATE_B_PERIPHERAL
:
1548 clear_bit(ID
, &motg
->inputs
);
1558 pm_runtime_get_sync(otg
->usb_phy
->dev
);
1559 schedule_work(&motg
->sm_work
);
1564 static const struct file_operations msm_otg_mode_fops
= {
1565 .open
= msm_otg_mode_open
,
1567 .write
= msm_otg_mode_write
,
1568 .llseek
= seq_lseek
,
1569 .release
= single_release
,
1572 static struct dentry
*msm_otg_dbg_root
;
1573 static struct dentry
*msm_otg_dbg_mode
;
1575 static int msm_otg_debugfs_init(struct msm_otg
*motg
)
1577 msm_otg_dbg_root
= debugfs_create_dir("msm_otg", NULL
);
1579 if (!msm_otg_dbg_root
|| IS_ERR(msm_otg_dbg_root
))
1582 msm_otg_dbg_mode
= debugfs_create_file("mode", S_IRUGO
| S_IWUSR
,
1583 msm_otg_dbg_root
, motg
, &msm_otg_mode_fops
);
1584 if (!msm_otg_dbg_mode
) {
1585 debugfs_remove(msm_otg_dbg_root
);
1586 msm_otg_dbg_root
= NULL
;
1593 static void msm_otg_debugfs_cleanup(void)
1595 debugfs_remove(msm_otg_dbg_mode
);
1596 debugfs_remove(msm_otg_dbg_root
);
1599 static const struct of_device_id msm_otg_dt_match
[] = {
1601 .compatible
= "qcom,usb-otg-ci",
1602 .data
= (void *) CI_45NM_INTEGRATED_PHY
1605 .compatible
= "qcom,usb-otg-snps",
1606 .data
= (void *) SNPS_28NM_INTEGRATED_PHY
1610 MODULE_DEVICE_TABLE(of
, msm_otg_dt_match
);
1612 static int msm_otg_vbus_notifier(struct notifier_block
*nb
, unsigned long event
,
1615 struct msm_usb_cable
*vbus
= container_of(nb
, struct msm_usb_cable
, nb
);
1616 struct msm_otg
*motg
= container_of(vbus
, struct msm_otg
, vbus
);
1619 set_bit(B_SESS_VLD
, &motg
->inputs
);
1621 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1623 if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1624 /* Switch D+/D- lines to Device connector */
1625 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1627 /* Switch D+/D- lines to Hub */
1628 gpiod_set_value_cansleep(motg
->switch_gpio
, 1);
1631 schedule_work(&motg
->sm_work
);
1636 static int msm_otg_id_notifier(struct notifier_block
*nb
, unsigned long event
,
1639 struct msm_usb_cable
*id
= container_of(nb
, struct msm_usb_cable
, nb
);
1640 struct msm_otg
*motg
= container_of(id
, struct msm_otg
, id
);
1643 clear_bit(ID
, &motg
->inputs
);
1645 set_bit(ID
, &motg
->inputs
);
1647 schedule_work(&motg
->sm_work
);
1652 static int msm_otg_read_dt(struct platform_device
*pdev
, struct msm_otg
*motg
)
1654 struct msm_otg_platform_data
*pdata
;
1655 struct extcon_dev
*ext_id
, *ext_vbus
;
1656 struct device_node
*node
= pdev
->dev
.of_node
;
1657 struct property
*prop
;
1658 int len
, ret
, words
;
1661 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1665 motg
->pdata
= pdata
;
1667 pdata
->phy_type
= (enum msm_usb_phy_type
)of_device_get_match_data(&pdev
->dev
);
1668 if (!pdata
->phy_type
)
1671 motg
->link_rst
= devm_reset_control_get(&pdev
->dev
, "link");
1672 if (IS_ERR(motg
->link_rst
))
1673 return PTR_ERR(motg
->link_rst
);
1675 motg
->phy_rst
= devm_reset_control_get(&pdev
->dev
, "phy");
1676 if (IS_ERR(motg
->phy_rst
))
1677 motg
->phy_rst
= NULL
;
1679 pdata
->mode
= usb_get_dr_mode(&pdev
->dev
);
1680 if (pdata
->mode
== USB_DR_MODE_UNKNOWN
)
1681 pdata
->mode
= USB_DR_MODE_OTG
;
1683 pdata
->otg_control
= OTG_PHY_CONTROL
;
1684 if (!of_property_read_u32(node
, "qcom,otg-control", &val
))
1685 if (val
== OTG_PMIC_CONTROL
)
1686 pdata
->otg_control
= val
;
1688 if (!of_property_read_u32(node
, "qcom,phy-num", &val
) && val
< 2)
1689 motg
->phy_number
= val
;
1691 motg
->vdd_levels
[VDD_LEVEL_NONE
] = USB_PHY_SUSP_DIG_VOL
;
1692 motg
->vdd_levels
[VDD_LEVEL_MIN
] = USB_PHY_VDD_DIG_VOL_MIN
;
1693 motg
->vdd_levels
[VDD_LEVEL_MAX
] = USB_PHY_VDD_DIG_VOL_MAX
;
1695 if (of_get_property(node
, "qcom,vdd-levels", &len
) &&
1696 len
== sizeof(tmp
)) {
1697 of_property_read_u32_array(node
, "qcom,vdd-levels",
1698 tmp
, len
/ sizeof(*tmp
));
1699 motg
->vdd_levels
[VDD_LEVEL_NONE
] = tmp
[VDD_LEVEL_NONE
];
1700 motg
->vdd_levels
[VDD_LEVEL_MIN
] = tmp
[VDD_LEVEL_MIN
];
1701 motg
->vdd_levels
[VDD_LEVEL_MAX
] = tmp
[VDD_LEVEL_MAX
];
1704 motg
->manual_pullup
= of_property_read_bool(node
, "qcom,manual-pullup");
1706 motg
->switch_gpio
= devm_gpiod_get_optional(&pdev
->dev
, "switch",
1708 if (IS_ERR(motg
->switch_gpio
))
1709 return PTR_ERR(motg
->switch_gpio
);
1711 ext_id
= ERR_PTR(-ENODEV
);
1712 ext_vbus
= ERR_PTR(-ENODEV
);
1713 if (of_property_read_bool(node
, "extcon")) {
1715 /* Each one of them is not mandatory */
1716 ext_vbus
= extcon_get_edev_by_phandle(&pdev
->dev
, 0);
1717 if (IS_ERR(ext_vbus
) && PTR_ERR(ext_vbus
) != -ENODEV
)
1718 return PTR_ERR(ext_vbus
);
1720 ext_id
= extcon_get_edev_by_phandle(&pdev
->dev
, 1);
1721 if (IS_ERR(ext_id
) && PTR_ERR(ext_id
) != -ENODEV
)
1722 return PTR_ERR(ext_id
);
1725 if (!IS_ERR(ext_vbus
)) {
1726 motg
->vbus
.extcon
= ext_vbus
;
1727 motg
->vbus
.nb
.notifier_call
= msm_otg_vbus_notifier
;
1728 ret
= devm_extcon_register_notifier(&pdev
->dev
, ext_vbus
,
1729 EXTCON_USB
, &motg
->vbus
.nb
);
1731 dev_err(&pdev
->dev
, "register VBUS notifier failed\n");
1735 ret
= extcon_get_state(ext_vbus
, EXTCON_USB
);
1737 set_bit(B_SESS_VLD
, &motg
->inputs
);
1739 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1742 if (!IS_ERR(ext_id
)) {
1743 motg
->id
.extcon
= ext_id
;
1744 motg
->id
.nb
.notifier_call
= msm_otg_id_notifier
;
1745 ret
= devm_extcon_register_notifier(&pdev
->dev
, ext_id
,
1746 EXTCON_USB_HOST
, &motg
->id
.nb
);
1748 dev_err(&pdev
->dev
, "register ID notifier failed\n");
1752 ret
= extcon_get_state(ext_id
, EXTCON_USB_HOST
);
1754 clear_bit(ID
, &motg
->inputs
);
1756 set_bit(ID
, &motg
->inputs
);
1759 prop
= of_find_property(node
, "qcom,phy-init-sequence", &len
);
1763 words
= len
/ sizeof(u32
);
1765 if (words
>= ULPI_EXT_VENDOR_SPECIFIC
) {
1766 dev_warn(&pdev
->dev
, "Too big PHY init sequence %d\n", words
);
1770 pdata
->phy_init_seq
= devm_kzalloc(&pdev
->dev
, len
, GFP_KERNEL
);
1771 if (!pdata
->phy_init_seq
)
1774 ret
= of_property_read_u32_array(node
, "qcom,phy-init-sequence",
1775 pdata
->phy_init_seq
, words
);
1777 pdata
->phy_init_sz
= words
;
1782 static int msm_otg_reboot_notify(struct notifier_block
*this,
1783 unsigned long code
, void *unused
)
1785 struct msm_otg
*motg
= container_of(this, struct msm_otg
, reboot
);
1788 * Ensure that D+/D- lines are routed to uB connector, so
1789 * we could load bootloader/kernel at next reboot
1791 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1795 static int msm_otg_probe(struct platform_device
*pdev
)
1797 struct regulator_bulk_data regs
[3];
1799 struct device_node
*np
= pdev
->dev
.of_node
;
1800 struct msm_otg_platform_data
*pdata
;
1801 struct resource
*res
;
1802 struct msm_otg
*motg
;
1803 struct usb_phy
*phy
;
1804 void __iomem
*phy_select
;
1806 motg
= devm_kzalloc(&pdev
->dev
, sizeof(struct msm_otg
), GFP_KERNEL
);
1810 motg
->phy
.otg
= devm_kzalloc(&pdev
->dev
, sizeof(struct usb_otg
),
1816 phy
->dev
= &pdev
->dev
;
1818 motg
->clk
= devm_clk_get(&pdev
->dev
, np
? "core" : "usb_hs_clk");
1819 if (IS_ERR(motg
->clk
)) {
1820 dev_err(&pdev
->dev
, "failed to get usb_hs_clk\n");
1821 return PTR_ERR(motg
->clk
);
1825 * If USB Core is running its protocol engine based on CORE CLK,
1826 * CORE CLK must be running at >55Mhz for correct HSUSB
1827 * operation and USB core cannot tolerate frequency changes on
1830 motg
->pclk
= devm_clk_get(&pdev
->dev
, np
? "iface" : "usb_hs_pclk");
1831 if (IS_ERR(motg
->pclk
)) {
1832 dev_err(&pdev
->dev
, "failed to get usb_hs_pclk\n");
1833 return PTR_ERR(motg
->pclk
);
1837 * USB core clock is not present on all MSM chips. This
1838 * clock is introduced to remove the dependency on AXI
1841 motg
->core_clk
= devm_clk_get(&pdev
->dev
,
1842 np
? "alt_core" : "usb_hs_core_clk");
1844 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1847 motg
->regs
= devm_ioremap(&pdev
->dev
, res
->start
, resource_size(res
));
1851 pdata
= dev_get_platdata(&pdev
->dev
);
1855 ret
= msm_otg_read_dt(pdev
, motg
);
1861 * NOTE: The PHYs can be multiplexed between the chipidea controller
1862 * and the dwc3 controller, using a single bit. It is important that
1863 * the dwc3 driver does not set this bit in an incompatible way.
1865 if (motg
->phy_number
) {
1866 phy_select
= devm_ioremap_nocache(&pdev
->dev
, USB2_PHY_SEL
, 4);
1870 /* Enable second PHY with the OTG port */
1871 writel(0x1, phy_select
);
1874 dev_info(&pdev
->dev
, "OTG regs = %p\n", motg
->regs
);
1876 motg
->irq
= platform_get_irq(pdev
, 0);
1877 if (motg
->irq
< 0) {
1878 dev_err(&pdev
->dev
, "platform_get_irq failed\n");
1883 regs
[0].supply
= "vddcx";
1884 regs
[1].supply
= "v3p3";
1885 regs
[2].supply
= "v1p8";
1887 ret
= devm_regulator_bulk_get(motg
->phy
.dev
, ARRAY_SIZE(regs
), regs
);
1891 motg
->vddcx
= regs
[0].consumer
;
1892 motg
->v3p3
= regs
[1].consumer
;
1893 motg
->v1p8
= regs
[2].consumer
;
1895 clk_set_rate(motg
->clk
, 60000000);
1897 clk_prepare_enable(motg
->clk
);
1898 clk_prepare_enable(motg
->pclk
);
1900 if (!IS_ERR(motg
->core_clk
))
1901 clk_prepare_enable(motg
->core_clk
);
1903 ret
= msm_hsusb_init_vddcx(motg
, 1);
1905 dev_err(&pdev
->dev
, "hsusb vddcx configuration failed\n");
1909 ret
= msm_hsusb_ldo_init(motg
, 1);
1911 dev_err(&pdev
->dev
, "hsusb vreg configuration failed\n");
1914 ret
= msm_hsusb_ldo_set_mode(motg
, 1);
1916 dev_err(&pdev
->dev
, "hsusb vreg enable failed\n");
1920 writel(0, USB_USBINTR
);
1921 writel(0, USB_OTGSC
);
1923 INIT_WORK(&motg
->sm_work
, msm_otg_sm_work
);
1924 INIT_DELAYED_WORK(&motg
->chg_work
, msm_chg_detect_work
);
1925 ret
= devm_request_irq(&pdev
->dev
, motg
->irq
, msm_otg_irq
, IRQF_SHARED
,
1928 dev_err(&pdev
->dev
, "request irq failed\n");
1932 phy
->init
= msm_phy_init
;
1933 phy
->notify_disconnect
= msm_phy_notify_disconnect
;
1934 phy
->type
= USB_PHY_TYPE_USB2
;
1936 phy
->io_ops
= &msm_otg_io_ops
;
1938 phy
->otg
->usb_phy
= &motg
->phy
;
1939 phy
->otg
->set_host
= msm_otg_set_host
;
1940 phy
->otg
->set_peripheral
= msm_otg_set_peripheral
;
1944 ret
= usb_add_phy_dev(&motg
->phy
);
1946 dev_err(&pdev
->dev
, "usb_add_phy failed\n");
1950 platform_set_drvdata(pdev
, motg
);
1951 device_init_wakeup(&pdev
->dev
, 1);
1953 if (motg
->pdata
->mode
== USB_DR_MODE_OTG
&&
1954 motg
->pdata
->otg_control
== OTG_USER_CONTROL
) {
1955 ret
= msm_otg_debugfs_init(motg
);
1957 dev_dbg(&pdev
->dev
, "Can not create mode change file\n");
1960 if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1961 /* Switch D+/D- lines to Device connector */
1962 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
1964 /* Switch D+/D- lines to Hub */
1965 gpiod_set_value_cansleep(motg
->switch_gpio
, 1);
1968 motg
->reboot
.notifier_call
= msm_otg_reboot_notify
;
1969 register_reboot_notifier(&motg
->reboot
);
1971 pm_runtime_set_active(&pdev
->dev
);
1972 pm_runtime_enable(&pdev
->dev
);
1977 msm_hsusb_ldo_init(motg
, 0);
1979 msm_hsusb_init_vddcx(motg
, 0);
1981 clk_disable_unprepare(motg
->pclk
);
1982 clk_disable_unprepare(motg
->clk
);
1983 if (!IS_ERR(motg
->core_clk
))
1984 clk_disable_unprepare(motg
->core_clk
);
1989 static int msm_otg_remove(struct platform_device
*pdev
)
1991 struct msm_otg
*motg
= platform_get_drvdata(pdev
);
1992 struct usb_phy
*phy
= &motg
->phy
;
1995 if (phy
->otg
->host
|| phy
->otg
->gadget
)
1998 unregister_reboot_notifier(&motg
->reboot
);
2001 * Ensure that D+/D- lines are routed to uB connector, so
2002 * we could load bootloader/kernel at next reboot
2004 gpiod_set_value_cansleep(motg
->switch_gpio
, 0);
2006 msm_otg_debugfs_cleanup();
2007 cancel_delayed_work_sync(&motg
->chg_work
);
2008 cancel_work_sync(&motg
->sm_work
);
2010 pm_runtime_resume(&pdev
->dev
);
2012 device_init_wakeup(&pdev
->dev
, 0);
2013 pm_runtime_disable(&pdev
->dev
);
2015 usb_remove_phy(phy
);
2016 disable_irq(motg
->irq
);
2019 * Put PHY in low power mode.
2021 ulpi_read(phy
, 0x14);
2022 ulpi_write(phy
, 0x08, 0x09);
2024 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
2025 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
2026 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
2031 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
)
2032 dev_err(phy
->dev
, "Unable to suspend PHY\n");
2034 clk_disable_unprepare(motg
->pclk
);
2035 clk_disable_unprepare(motg
->clk
);
2036 if (!IS_ERR(motg
->core_clk
))
2037 clk_disable_unprepare(motg
->core_clk
);
2038 msm_hsusb_ldo_init(motg
, 0);
2040 pm_runtime_set_suspended(&pdev
->dev
);
2046 static int msm_otg_runtime_idle(struct device
*dev
)
2048 struct msm_otg
*motg
= dev_get_drvdata(dev
);
2049 struct usb_otg
*otg
= motg
->phy
.otg
;
2051 dev_dbg(dev
, "OTG runtime idle\n");
2054 * It is observed some times that a spurious interrupt
2055 * comes when PHY is put into LPM immediately after PHY reset.
2056 * This 1 sec delay also prevents entering into LPM immediately
2057 * after asynchronous interrupt.
2059 if (otg
->state
!= OTG_STATE_UNDEFINED
)
2060 pm_schedule_suspend(dev
, 1000);
2065 static int msm_otg_runtime_suspend(struct device
*dev
)
2067 struct msm_otg
*motg
= dev_get_drvdata(dev
);
2069 dev_dbg(dev
, "OTG runtime suspend\n");
2070 return msm_otg_suspend(motg
);
2073 static int msm_otg_runtime_resume(struct device
*dev
)
2075 struct msm_otg
*motg
= dev_get_drvdata(dev
);
2077 dev_dbg(dev
, "OTG runtime resume\n");
2078 return msm_otg_resume(motg
);
2082 #ifdef CONFIG_PM_SLEEP
2083 static int msm_otg_pm_suspend(struct device
*dev
)
2085 struct msm_otg
*motg
= dev_get_drvdata(dev
);
2087 dev_dbg(dev
, "OTG PM suspend\n");
2088 return msm_otg_suspend(motg
);
2091 static int msm_otg_pm_resume(struct device
*dev
)
2093 struct msm_otg
*motg
= dev_get_drvdata(dev
);
2096 dev_dbg(dev
, "OTG PM resume\n");
2098 ret
= msm_otg_resume(motg
);
2103 * Runtime PM Documentation recommends bringing the
2104 * device to full powered state upon resume.
2106 pm_runtime_disable(dev
);
2107 pm_runtime_set_active(dev
);
2108 pm_runtime_enable(dev
);
2114 static const struct dev_pm_ops msm_otg_dev_pm_ops
= {
2115 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend
, msm_otg_pm_resume
)
2116 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend
, msm_otg_runtime_resume
,
2117 msm_otg_runtime_idle
)
2120 static struct platform_driver msm_otg_driver
= {
2121 .probe
= msm_otg_probe
,
2122 .remove
= msm_otg_remove
,
2124 .name
= DRIVER_NAME
,
2125 .pm
= &msm_otg_dev_pm_ops
,
2126 .of_match_table
= msm_otg_dt_match
,
2130 module_platform_driver(msm_otg_driver
);
2132 MODULE_LICENSE("GPL v2");
2133 MODULE_DESCRIPTION("MSM USB transceiver driver");