1 // SPDX-License-Identifier: GPL-2.0
3 * typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
5 * Copyright (C) 2017 Intel Corporation
6 * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/usb/tcpm.h>
12 #include <linux/interrupt.h>
13 #include <linux/platform_device.h>
14 #include <linux/mfd/intel_soc_pmic.h>
16 /* Register offsets */
17 #define WCOVE_CHGRIRQ0 0x4e09
19 #define USBC_CONTROL1 0x7001
20 #define USBC_CONTROL2 0x7002
21 #define USBC_CONTROL3 0x7003
22 #define USBC_CC1_CTRL 0x7004
23 #define USBC_CC2_CTRL 0x7005
24 #define USBC_STATUS1 0x7007
25 #define USBC_STATUS2 0x7008
26 #define USBC_STATUS3 0x7009
27 #define USBC_CC1 0x700a
28 #define USBC_CC2 0x700b
29 #define USBC_CC1_STATUS 0x700c
30 #define USBC_CC2_STATUS 0x700d
31 #define USBC_IRQ1 0x7015
32 #define USBC_IRQ2 0x7016
33 #define USBC_IRQMASK1 0x7017
34 #define USBC_IRQMASK2 0x7018
35 #define USBC_PDCFG2 0x701a
36 #define USBC_PDCFG3 0x701b
37 #define USBC_PDSTATUS 0x701c
38 #define USBC_RXSTATUS 0x701d
39 #define USBC_RXINFO 0x701e
40 #define USBC_TXCMD 0x701f
41 #define USBC_TXINFO 0x7020
42 #define USBC_RX_DATA 0x7028
43 #define USBC_TX_DATA 0x7047
47 #define USBC_CONTROL1_MODE_MASK 0x3
48 #define USBC_CONTROL1_MODE_SNK 0
49 #define USBC_CONTROL1_MODE_SNKACC 1
50 #define USBC_CONTROL1_MODE_SRC 2
51 #define USBC_CONTROL1_MODE_SRCACC 3
52 #define USBC_CONTROL1_MODE_DRP 4
53 #define USBC_CONTROL1_MODE_DRPACC 5
54 #define USBC_CONTROL1_MODE_TEST 7
55 #define USBC_CONTROL1_CURSRC_MASK 0xc
56 #define USBC_CONTROL1_CURSRC_UA_0 (0 << 3)
57 #define USBC_CONTROL1_CURSRC_UA_80 (1 << 3)
58 #define USBC_CONTROL1_CURSRC_UA_180 (2 << 3)
59 #define USBC_CONTROL1_CURSRC_UA_330 (3 << 3)
60 #define USBC_CONTROL1_DRPTOGGLE_RANDOM 0xe0
62 #define USBC_CONTROL2_UNATT_SNK BIT(0)
63 #define USBC_CONTROL2_UNATT_SRC BIT(1)
64 #define USBC_CONTROL2_DIS_ST BIT(2)
66 #define USBC_CONTROL3_DET_DIS BIT(0)
67 #define USBC_CONTROL3_PD_DIS BIT(1)
68 #define USBC_CONTROL3_RESETPHY BIT(2)
70 #define USBC_CC_CTRL_PU_EN BIT(0)
71 #define USBC_CC_CTRL_VCONN_EN BIT(1)
72 #define USBC_CC_CTRL_TX_EN BIT(2)
73 #define USBC_CC_CTRL_PD_EN BIT(3)
74 #define USBC_CC_CTRL_CDET_EN BIT(4)
75 #define USBC_CC_CTRL_RDET_EN BIT(5)
76 #define USBC_CC_CTRL_ADC_EN BIT(6)
77 #define USBC_CC_CTRL_VBUSOK BIT(7)
79 #define USBC_STATUS1_DET_ONGOING BIT(6)
80 #define USBC_STATUS1_RSLT(r) ((r) & 0xf)
81 #define USBC_RSLT_NOTHING 0
82 #define USBC_RSLT_SRC_DEFAULT 1
83 #define USBC_RSLT_SRC_1_5A 2
84 #define USBC_RSLT_SRC_3_0A 3
85 #define USBC_RSLT_SNK 4
86 #define USBC_RSLT_DEBUG_ACC 5
87 #define USBC_RSLT_AUDIO_ACC 6
88 #define USBC_RSLT_UNDEF 15
89 #define USBC_STATUS1_ORIENT(r) (((r) >> 4) & 0x3)
90 #define USBC_ORIENT_NORMAL 1
91 #define USBC_ORIENT_REVERSE 2
93 #define USBC_STATUS2_VBUS_REQ BIT(5)
95 #define UCSC_CC_STATUS_SNK_RP BIT(0)
96 #define UCSC_CC_STATUS_PWRDEFSNK BIT(1)
97 #define UCSC_CC_STATUS_PWR_1P5A_SNK BIT(2)
98 #define UCSC_CC_STATUS_PWR_3A_SNK BIT(3)
99 #define UCSC_CC_STATUS_SRC_RP BIT(4)
100 #define UCSC_CC_STATUS_RX(r) (((r) >> 5) & 0x3)
101 #define USBC_CC_STATUS_RD 1
102 #define USBC_CC_STATUS_RA 2
104 #define USBC_IRQ1_ADCDONE1 BIT(2)
105 #define USBC_IRQ1_OVERTEMP BIT(1)
106 #define USBC_IRQ1_SHORT BIT(0)
108 #define USBC_IRQ2_CC_CHANGE BIT(7)
109 #define USBC_IRQ2_RX_PD BIT(6)
110 #define USBC_IRQ2_RX_HR BIT(5)
111 #define USBC_IRQ2_RX_CR BIT(4)
112 #define USBC_IRQ2_TX_SUCCESS BIT(3)
113 #define USBC_IRQ2_TX_FAIL BIT(2)
115 #define USBC_IRQMASK1_ALL (USBC_IRQ1_ADCDONE1 | USBC_IRQ1_OVERTEMP | \
118 #define USBC_IRQMASK2_ALL (USBC_IRQ2_CC_CHANGE | USBC_IRQ2_RX_PD | \
119 USBC_IRQ2_RX_HR | USBC_IRQ2_RX_CR | \
120 USBC_IRQ2_TX_SUCCESS | USBC_IRQ2_TX_FAIL)
122 #define USBC_PDCFG2_SOP BIT(0)
123 #define USBC_PDCFG2_SOP_P BIT(1)
124 #define USBC_PDCFG2_SOP_PP BIT(2)
125 #define USBC_PDCFG2_SOP_P_DEBUG BIT(3)
126 #define USBC_PDCFG2_SOP_PP_DEBUG BIT(4)
128 #define USBC_PDCFG3_DATAROLE_SHIFT 1
129 #define USBC_PDCFG3_SOP_SHIFT 2
131 #define USBC_RXSTATUS_RXCLEAR BIT(0)
132 #define USBC_RXSTATUS_RXDATA BIT(7)
134 #define USBC_RXINFO_RXBYTES(i) (((i) >> 3) & 0x1f)
136 #define USBC_TXCMD_BUF_RDY BIT(0)
137 #define USBC_TXCMD_START BIT(1)
138 #define USBC_TXCMD_NOP (0 << 5)
139 #define USBC_TXCMD_MSG (1 << 5)
140 #define USBC_TXCMD_CR (2 << 5)
141 #define USBC_TXCMD_HR (3 << 5)
142 #define USBC_TXCMD_BIST (4 << 5)
144 #define USBC_TXINFO_RETRIES(d) (d << 3)
147 struct mutex lock
; /* device lock */
149 struct regmap
*regmap
;
154 struct tcpc_dev tcpc
;
155 struct tcpm_port
*tcpm
;
158 #define tcpc_to_wcove(_tcpc_) container_of(_tcpc_, struct wcove_typec, tcpc)
160 enum wcove_typec_func
{
161 WCOVE_FUNC_DRIVE_VBUS
= 1,
162 WCOVE_FUNC_ORIENTATION
,
164 WCOVE_FUNC_DRIVE_VCONN
,
167 enum wcove_typec_orientation
{
168 WCOVE_ORIENTATION_NORMAL
,
169 WCOVE_ORIENTATION_REVERSE
,
172 enum wcove_typec_role
{
177 #define WCOVE_DSM_UUID "482383f0-2876-4e49-8685-db66211af037"
179 static int wcove_typec_func(struct wcove_typec
*wcove
,
180 enum wcove_typec_func func
, int param
)
182 union acpi_object
*obj
;
183 union acpi_object tmp
;
184 union acpi_object argv4
= ACPI_INIT_DSM_ARGV4(1, &tmp
);
186 tmp
.type
= ACPI_TYPE_INTEGER
;
187 tmp
.integer
.value
= param
;
189 obj
= acpi_evaluate_dsm(ACPI_HANDLE(wcove
->dev
), &wcove
->guid
, 1, func
,
192 dev_err(wcove
->dev
, "%s: failed to evaluate _DSM\n", __func__
);
200 static int wcove_init(struct tcpc_dev
*tcpc
)
202 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
205 /* Unmask everything */
206 ret
= regmap_write(wcove
->regmap
, USBC_IRQMASK1
, 0);
210 return regmap_write(wcove
->regmap
, USBC_IRQMASK2
, 0);
213 static int wcove_get_vbus(struct tcpc_dev
*tcpc
)
215 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
216 unsigned int cc1ctrl
;
219 ret
= regmap_read(wcove
->regmap
, USBC_CC1_CTRL
, &cc1ctrl
);
223 wcove
->vbus
= !!(cc1ctrl
& USBC_CC_CTRL_VBUSOK
);
228 static int wcove_set_vbus(struct tcpc_dev
*tcpc
, bool on
, bool sink
)
230 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
232 return wcove_typec_func(wcove
, WCOVE_FUNC_DRIVE_VBUS
, on
);
235 static int wcove_set_vconn(struct tcpc_dev
*tcpc
, bool on
)
237 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
239 return wcove_typec_func(wcove
, WCOVE_FUNC_DRIVE_VCONN
, on
);
242 static enum typec_cc_status
wcove_to_typec_cc(unsigned int cc
)
244 if (cc
& UCSC_CC_STATUS_SNK_RP
) {
245 if (cc
& UCSC_CC_STATUS_PWRDEFSNK
)
246 return TYPEC_CC_RP_DEF
;
247 else if (cc
& UCSC_CC_STATUS_PWR_1P5A_SNK
)
248 return TYPEC_CC_RP_1_5
;
249 else if (cc
& UCSC_CC_STATUS_PWR_3A_SNK
)
250 return TYPEC_CC_RP_3_0
;
252 switch (UCSC_CC_STATUS_RX(cc
)) {
253 case USBC_CC_STATUS_RD
:
255 case USBC_CC_STATUS_RA
:
261 return TYPEC_CC_OPEN
;
264 static int wcove_get_cc(struct tcpc_dev
*tcpc
, enum typec_cc_status
*cc1
,
265 enum typec_cc_status
*cc2
)
267 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
268 unsigned int cc1_status
;
269 unsigned int cc2_status
;
272 ret
= regmap_read(wcove
->regmap
, USBC_CC1_STATUS
, &cc1_status
);
276 ret
= regmap_read(wcove
->regmap
, USBC_CC2_STATUS
, &cc2_status
);
280 *cc1
= wcove_to_typec_cc(cc1_status
);
281 *cc2
= wcove_to_typec_cc(cc2_status
);
286 static int wcove_set_cc(struct tcpc_dev
*tcpc
, enum typec_cc_status cc
)
288 /* XXX: Relying on the HW FSM to configure things correctly for now */
292 static int wcove_set_polarity(struct tcpc_dev
*tcpc
, enum typec_cc_polarity pol
)
294 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
296 return wcove_typec_func(wcove
, WCOVE_FUNC_ORIENTATION
, pol
);
299 static int wcove_set_current_limit(struct tcpc_dev
*tcpc
, u32 max_ma
, u32 mv
)
304 static int wcove_set_roles(struct tcpc_dev
*tcpc
, bool attached
,
305 enum typec_role role
, enum typec_data_role data
)
307 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
311 ret
= wcove_typec_func(wcove
, WCOVE_FUNC_ROLE
, data
== TYPEC_HOST
?
312 WCOVE_ROLE_HOST
: WCOVE_ROLE_DEVICE
);
317 val
|= data
<< USBC_PDCFG3_DATAROLE_SHIFT
;
318 val
|= PD_REV20
<< USBC_PDCFG3_SOP_SHIFT
;
320 return regmap_write(wcove
->regmap
, USBC_PDCFG3
, val
);
323 static int wcove_set_pd_rx(struct tcpc_dev
*tcpc
, bool on
)
325 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
327 return regmap_write(wcove
->regmap
, USBC_PDCFG2
,
328 on
? USBC_PDCFG2_SOP
: 0);
331 static int wcove_pd_transmit(struct tcpc_dev
*tcpc
,
332 enum tcpm_transmit_type type
,
333 const struct pd_message
*msg
)
335 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
336 unsigned int info
= 0;
340 ret
= regmap_read(wcove
->regmap
, USBC_TXCMD
, &cmd
);
344 if (!(cmd
& USBC_TXCMD_BUF_RDY
)) {
345 dev_warn(wcove
->dev
, "%s: Last transmission still ongoing!",
351 const u8
*data
= (void *)msg
;
354 for (i
= 0; i
< pd_header_cnt(msg
->header
) * 4 + 2; i
++) {
355 ret
= regmap_write(wcove
->regmap
, USBC_TX_DATA
+ i
,
364 case TCPC_TX_SOP_PRIME
:
365 case TCPC_TX_SOP_PRIME_PRIME
:
366 case TCPC_TX_SOP_DEBUG_PRIME
:
367 case TCPC_TX_SOP_DEBUG_PRIME_PRIME
:
369 cmd
= USBC_TXCMD_MSG
;
371 case TCPC_TX_HARD_RESET
:
374 case TCPC_TX_CABLE_RESET
:
377 case TCPC_TX_BIST_MODE_2
:
378 cmd
= USBC_TXCMD_BIST
;
384 /* NOTE Setting maximum number of retries (7) */
385 ret
= regmap_write(wcove
->regmap
, USBC_TXINFO
,
386 info
| USBC_TXINFO_RETRIES(7));
390 return regmap_write(wcove
->regmap
, USBC_TXCMD
, cmd
| USBC_TXCMD_START
);
393 static int wcove_start_drp_toggling(struct tcpc_dev
*tcpc
,
394 enum typec_cc_status cc
)
396 struct wcove_typec
*wcove
= tcpc_to_wcove(tcpc
);
397 unsigned int usbc_ctrl
;
399 usbc_ctrl
= USBC_CONTROL1_MODE_DRP
| USBC_CONTROL1_DRPTOGGLE_RANDOM
;
402 case TYPEC_CC_RP_1_5
:
403 usbc_ctrl
|= USBC_CONTROL1_CURSRC_UA_180
;
405 case TYPEC_CC_RP_3_0
:
406 usbc_ctrl
|= USBC_CONTROL1_CURSRC_UA_330
;
409 usbc_ctrl
|= USBC_CONTROL1_CURSRC_UA_80
;
413 return regmap_write(wcove
->regmap
, USBC_CONTROL1
, usbc_ctrl
);
416 static int wcove_read_rx_buffer(struct wcove_typec
*wcove
, void *msg
)
422 ret
= regmap_read(wcove
->regmap
, USBC_RXINFO
, &info
);
426 /* FIXME: Check that USBC_RXINFO_RXBYTES(info) matches the header */
428 for (i
= 0; i
< USBC_RXINFO_RXBYTES(info
); i
++) {
429 ret
= regmap_read(wcove
->regmap
, USBC_RX_DATA
+ i
, msg
+ i
);
434 return regmap_write(wcove
->regmap
, USBC_RXSTATUS
,
435 USBC_RXSTATUS_RXCLEAR
);
438 static irqreturn_t
wcove_typec_irq(int irq
, void *data
)
440 struct wcove_typec
*wcove
= data
;
441 unsigned int usbc_irq1
= 0;
442 unsigned int usbc_irq2
= 0;
443 unsigned int cc1ctrl
;
446 mutex_lock(&wcove
->lock
);
449 ret
= regmap_read(wcove
->regmap
, USBC_IRQ1
, &usbc_irq1
);
453 ret
= regmap_read(wcove
->regmap
, USBC_IRQ2
, &usbc_irq2
);
457 ret
= regmap_read(wcove
->regmap
, USBC_CC1_CTRL
, &cc1ctrl
);
465 if (usbc_irq1
& USBC_IRQ1_OVERTEMP
) {
466 dev_err(wcove
->dev
, "VCONN Switch Over Temperature!\n");
467 wcove_typec_func(wcove
, WCOVE_FUNC_DRIVE_VCONN
, false);
468 /* REVISIT: Report an error? */
471 if (usbc_irq1
& USBC_IRQ1_SHORT
) {
472 dev_err(wcove
->dev
, "VCONN Switch Short Circuit!\n");
473 wcove_typec_func(wcove
, WCOVE_FUNC_DRIVE_VCONN
, false);
474 /* REVISIT: Report an error? */
477 if (wcove
->vbus
!= !!(cc1ctrl
& USBC_CC_CTRL_VBUSOK
))
478 tcpm_vbus_change(wcove
->tcpm
);
480 /* REVISIT: See if tcpm code can be made to consider Type-C HW FSMs */
481 if (usbc_irq2
& USBC_IRQ2_CC_CHANGE
)
482 tcpm_cc_change(wcove
->tcpm
);
484 if (usbc_irq2
& USBC_IRQ2_RX_PD
) {
488 * FIXME: Need to check if TX is ongoing and report
489 * TX_DIREGARDED if needed?
492 ret
= regmap_read(wcove
->regmap
, USBC_RXSTATUS
, &status
);
496 /* Flush all buffers */
497 while (status
& USBC_RXSTATUS_RXDATA
) {
498 struct pd_message msg
;
500 ret
= wcove_read_rx_buffer(wcove
, &msg
);
502 dev_err(wcove
->dev
, "%s: RX read failed\n",
507 tcpm_pd_receive(wcove
->tcpm
, &msg
);
509 ret
= regmap_read(wcove
->regmap
, USBC_RXSTATUS
,
516 if (usbc_irq2
& USBC_IRQ2_RX_HR
)
517 tcpm_pd_hard_reset(wcove
->tcpm
);
519 /* REVISIT: if (usbc_irq2 & USBC_IRQ2_RX_CR) */
521 if (usbc_irq2
& USBC_IRQ2_TX_SUCCESS
)
522 tcpm_pd_transmit_complete(wcove
->tcpm
, TCPC_TX_SUCCESS
);
524 if (usbc_irq2
& USBC_IRQ2_TX_FAIL
)
525 tcpm_pd_transmit_complete(wcove
->tcpm
, TCPC_TX_FAILED
);
530 ret
= regmap_write(wcove
->regmap
, USBC_IRQ1
, usbc_irq1
);
532 dev_WARN(wcove
->dev
, "%s failed to clear IRQ1\n",
537 ret
= regmap_write(wcove
->regmap
, USBC_IRQ2
, usbc_irq2
);
539 dev_WARN(wcove
->dev
, "%s failed to clear IRQ2\n",
543 /* REVISIT: Clear WhiskeyCove CHGR Type-C interrupt */
544 regmap_write(wcove
->regmap
, WCOVE_CHGRIRQ0
, BIT(5));
546 mutex_unlock(&wcove
->lock
);
551 * The following power levels should be safe to use with Joule board.
553 static const u32 src_pdo
[] = {
554 PDO_FIXED(5000, 1500, PDO_FIXED_DUAL_ROLE
| PDO_FIXED_DATA_SWAP
|
558 static const u32 snk_pdo
[] = {
559 PDO_FIXED(12000, 3000, PDO_FIXED_DUAL_ROLE
| PDO_FIXED_DATA_SWAP
|
561 PDO_BATT(4750, 12000, 15000),
562 PDO_VAR(4750, 12000, 3000),
565 static struct tcpc_config wcove_typec_config
= {
567 .nr_src_pdo
= ARRAY_SIZE(src_pdo
),
569 .nr_snk_pdo
= ARRAY_SIZE(snk_pdo
),
574 .operating_snk_mw
= 15000,
576 .type
= TYPEC_PORT_DRP
,
577 .default_role
= TYPEC_SINK
,
580 static int wcove_typec_probe(struct platform_device
*pdev
)
582 struct intel_soc_pmic
*pmic
= dev_get_drvdata(pdev
->dev
.parent
);
583 struct wcove_typec
*wcove
;
587 wcove
= devm_kzalloc(&pdev
->dev
, sizeof(*wcove
), GFP_KERNEL
);
591 mutex_init(&wcove
->lock
);
592 wcove
->dev
= &pdev
->dev
;
593 wcove
->regmap
= pmic
->regmap
;
595 irq
= regmap_irq_get_virq(pmic
->irq_chip_data_chgr
,
596 platform_get_irq(pdev
, 0));
600 ret
= guid_parse(WCOVE_DSM_UUID
, &wcove
->guid
);
604 if (!acpi_check_dsm(ACPI_HANDLE(&pdev
->dev
), &wcove
->guid
, 0, 0x1f)) {
605 dev_err(&pdev
->dev
, "Missing _DSM functions\n");
609 wcove
->tcpc
.init
= wcove_init
;
610 wcove
->tcpc
.get_vbus
= wcove_get_vbus
;
611 wcove
->tcpc
.set_vbus
= wcove_set_vbus
;
612 wcove
->tcpc
.set_cc
= wcove_set_cc
;
613 wcove
->tcpc
.get_cc
= wcove_get_cc
;
614 wcove
->tcpc
.set_polarity
= wcove_set_polarity
;
615 wcove
->tcpc
.set_vconn
= wcove_set_vconn
;
616 wcove
->tcpc
.set_current_limit
= wcove_set_current_limit
;
617 wcove
->tcpc
.start_drp_toggling
= wcove_start_drp_toggling
;
619 wcove
->tcpc
.set_pd_rx
= wcove_set_pd_rx
;
620 wcove
->tcpc
.set_roles
= wcove_set_roles
;
621 wcove
->tcpc
.pd_transmit
= wcove_pd_transmit
;
623 wcove
->tcpc
.config
= &wcove_typec_config
;
625 wcove
->tcpm
= tcpm_register_port(wcove
->dev
, &wcove
->tcpc
);
626 if (IS_ERR(wcove
->tcpm
))
627 return PTR_ERR(wcove
->tcpm
);
629 ret
= devm_request_threaded_irq(&pdev
->dev
, irq
, NULL
,
630 wcove_typec_irq
, IRQF_ONESHOT
,
631 "wcove_typec", wcove
);
633 tcpm_unregister_port(wcove
->tcpm
);
637 platform_set_drvdata(pdev
, wcove
);
641 static int wcove_typec_remove(struct platform_device
*pdev
)
643 struct wcove_typec
*wcove
= platform_get_drvdata(pdev
);
646 /* Mask everything */
647 regmap_read(wcove
->regmap
, USBC_IRQMASK1
, &val
);
648 regmap_write(wcove
->regmap
, USBC_IRQMASK1
, val
| USBC_IRQMASK1_ALL
);
649 regmap_read(wcove
->regmap
, USBC_IRQMASK2
, &val
);
650 regmap_write(wcove
->regmap
, USBC_IRQMASK2
, val
| USBC_IRQMASK2_ALL
);
652 tcpm_unregister_port(wcove
->tcpm
);
657 static struct platform_driver wcove_typec_driver
= {
659 .name
= "bxt_wcove_usbc",
661 .probe
= wcove_typec_probe
,
662 .remove
= wcove_typec_remove
,
665 module_platform_driver(wcove_typec_driver
);
667 MODULE_AUTHOR("Intel Corporation");
668 MODULE_LICENSE("GPL v2");
669 MODULE_DESCRIPTION("WhiskeyCove PMIC USB Type-C PHY driver");
670 MODULE_ALIAS("platform:bxt_wcove_usbc");