2 * VFIO PCI config space virtualization
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
31 #include "vfio_pci_private.h"
33 #define PCI_CFG_SPACE_SIZE 256
35 /* Useful "pseudo" capabilities */
36 #define PCI_CAP_ID_BASIC 0
37 #define PCI_CAP_ID_INVALID 0xFF
39 #define is_bar(offset) \
40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
44 * Lengths of PCI Config Capabilities
45 * 0: Removed from the user visible capability list
48 static u8 pci_cap_length
[] = {
49 [PCI_CAP_ID_BASIC
] = PCI_STD_HEADER_SIZEOF
, /* pci config header */
50 [PCI_CAP_ID_PM
] = PCI_PM_SIZEOF
,
51 [PCI_CAP_ID_AGP
] = PCI_AGP_SIZEOF
,
52 [PCI_CAP_ID_VPD
] = PCI_CAP_VPD_SIZEOF
,
53 [PCI_CAP_ID_SLOTID
] = 0, /* bridge - don't care */
54 [PCI_CAP_ID_MSI
] = 0xFF, /* 10, 14, 20, or 24 */
55 [PCI_CAP_ID_CHSWP
] = 0, /* cpci - not yet */
56 [PCI_CAP_ID_PCIX
] = 0xFF, /* 8 or 24 */
57 [PCI_CAP_ID_HT
] = 0xFF, /* hypertransport */
58 [PCI_CAP_ID_VNDR
] = 0xFF, /* variable */
59 [PCI_CAP_ID_DBG
] = 0, /* debug - don't care */
60 [PCI_CAP_ID_CCRC
] = 0, /* cpci - not yet */
61 [PCI_CAP_ID_SHPC
] = 0, /* hotswap - not yet */
62 [PCI_CAP_ID_SSVID
] = 0, /* bridge - don't care */
63 [PCI_CAP_ID_AGP3
] = 0, /* AGP8x - not yet */
64 [PCI_CAP_ID_SECDEV
] = 0, /* secure device not yet */
65 [PCI_CAP_ID_EXP
] = 0xFF, /* 20 or 44 */
66 [PCI_CAP_ID_MSIX
] = PCI_CAP_MSIX_SIZEOF
,
67 [PCI_CAP_ID_SATA
] = 0xFF,
68 [PCI_CAP_ID_AF
] = PCI_CAP_AF_SIZEOF
,
72 * Lengths of PCIe/PCI-X Extended Config Capabilities
73 * 0: Removed or masked from the user visible capabilty list
76 static u16 pci_ext_cap_length
[] = {
77 [PCI_EXT_CAP_ID_ERR
] = PCI_ERR_ROOT_COMMAND
,
78 [PCI_EXT_CAP_ID_VC
] = 0xFF,
79 [PCI_EXT_CAP_ID_DSN
] = PCI_EXT_CAP_DSN_SIZEOF
,
80 [PCI_EXT_CAP_ID_PWR
] = PCI_EXT_CAP_PWR_SIZEOF
,
81 [PCI_EXT_CAP_ID_RCLD
] = 0, /* root only - don't care */
82 [PCI_EXT_CAP_ID_RCILC
] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCEC
] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_MFVC
] = 0xFF,
85 [PCI_EXT_CAP_ID_VC9
] = 0xFF, /* same as CAP_ID_VC */
86 [PCI_EXT_CAP_ID_RCRB
] = 0, /* root only - don't care */
87 [PCI_EXT_CAP_ID_VNDR
] = 0xFF,
88 [PCI_EXT_CAP_ID_CAC
] = 0, /* obsolete */
89 [PCI_EXT_CAP_ID_ACS
] = 0xFF,
90 [PCI_EXT_CAP_ID_ARI
] = PCI_EXT_CAP_ARI_SIZEOF
,
91 [PCI_EXT_CAP_ID_ATS
] = PCI_EXT_CAP_ATS_SIZEOF
,
92 [PCI_EXT_CAP_ID_SRIOV
] = PCI_EXT_CAP_SRIOV_SIZEOF
,
93 [PCI_EXT_CAP_ID_MRIOV
] = 0, /* not yet */
94 [PCI_EXT_CAP_ID_MCAST
] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF
,
95 [PCI_EXT_CAP_ID_PRI
] = PCI_EXT_CAP_PRI_SIZEOF
,
96 [PCI_EXT_CAP_ID_AMD_XXX
] = 0, /* not yet */
97 [PCI_EXT_CAP_ID_REBAR
] = 0xFF,
98 [PCI_EXT_CAP_ID_DPA
] = 0xFF,
99 [PCI_EXT_CAP_ID_TPH
] = 0xFF,
100 [PCI_EXT_CAP_ID_LTR
] = PCI_EXT_CAP_LTR_SIZEOF
,
101 [PCI_EXT_CAP_ID_SECPCI
] = 0, /* not yet */
102 [PCI_EXT_CAP_ID_PMUX
] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PASID
] = 0, /* not yet */
107 * Read/Write Permission Bits - one bit for each bit in capability
108 * Any field can be read if it exists, but what is read depends on
109 * whether the field is 'virtualized', or just pass thru to the
110 * hardware. Any virtualized field is also virtualized for writes.
111 * Writes are only permitted if they have a 1 bit here.
114 u8
*virt
; /* read/write virtual data, not hw */
115 u8
*write
; /* writeable bits */
116 int (*readfn
)(struct vfio_pci_device
*vdev
, int pos
, int count
,
117 struct perm_bits
*perm
, int offset
, __le32
*val
);
118 int (*writefn
)(struct vfio_pci_device
*vdev
, int pos
, int count
,
119 struct perm_bits
*perm
, int offset
, __le32 val
);
123 #define ALL_VIRT 0xFFFFFFFFU
125 #define ALL_WRITE 0xFFFFFFFFU
127 static int vfio_user_config_read(struct pci_dev
*pdev
, int offset
,
128 __le32
*val
, int count
)
137 ret
= pci_user_read_config_byte(pdev
, offset
, &tmp
);
144 ret
= pci_user_read_config_word(pdev
, offset
, &tmp
);
149 ret
= pci_user_read_config_dword(pdev
, offset
, &tmp_val
);
153 *val
= cpu_to_le32(tmp_val
);
155 return pcibios_err_to_errno(ret
);
158 static int vfio_user_config_write(struct pci_dev
*pdev
, int offset
,
159 __le32 val
, int count
)
162 u32 tmp_val
= le32_to_cpu(val
);
166 ret
= pci_user_write_config_byte(pdev
, offset
, tmp_val
);
169 ret
= pci_user_write_config_word(pdev
, offset
, tmp_val
);
172 ret
= pci_user_write_config_dword(pdev
, offset
, tmp_val
);
176 return pcibios_err_to_errno(ret
);
179 static int vfio_default_config_read(struct vfio_pci_device
*vdev
, int pos
,
180 int count
, struct perm_bits
*perm
,
181 int offset
, __le32
*val
)
185 memcpy(val
, vdev
->vconfig
+ pos
, count
);
187 memcpy(&virt
, perm
->virt
+ offset
, count
);
189 /* Any non-virtualized bits? */
190 if (cpu_to_le32(~0U >> (32 - (count
* 8))) != virt
) {
191 struct pci_dev
*pdev
= vdev
->pdev
;
195 ret
= vfio_user_config_read(pdev
, pos
, &phys_val
, count
);
199 *val
= (phys_val
& ~virt
) | (*val
& virt
);
205 static int vfio_default_config_write(struct vfio_pci_device
*vdev
, int pos
,
206 int count
, struct perm_bits
*perm
,
207 int offset
, __le32 val
)
209 __le32 virt
= 0, write
= 0;
211 memcpy(&write
, perm
->write
+ offset
, count
);
214 return count
; /* drop, no writable bits */
216 memcpy(&virt
, perm
->virt
+ offset
, count
);
218 /* Virtualized and writable bits go to vconfig */
222 memcpy(&virt_val
, vdev
->vconfig
+ pos
, count
);
224 virt_val
&= ~(write
& virt
);
225 virt_val
|= (val
& (write
& virt
));
227 memcpy(vdev
->vconfig
+ pos
, &virt_val
, count
);
230 /* Non-virtualzed and writable bits go to hardware */
232 struct pci_dev
*pdev
= vdev
->pdev
;
236 ret
= vfio_user_config_read(pdev
, pos
, &phys_val
, count
);
240 phys_val
&= ~(write
& ~virt
);
241 phys_val
|= (val
& (write
& ~virt
));
243 ret
= vfio_user_config_write(pdev
, pos
, phys_val
, count
);
251 /* Allow direct read from hardware, except for capability next pointer */
252 static int vfio_direct_config_read(struct vfio_pci_device
*vdev
, int pos
,
253 int count
, struct perm_bits
*perm
,
254 int offset
, __le32
*val
)
258 ret
= vfio_user_config_read(vdev
->pdev
, pos
, val
, count
);
260 return pcibios_err_to_errno(ret
);
262 if (pos
>= PCI_CFG_SPACE_SIZE
) { /* Extended cap header mangling */
264 memcpy(val
, vdev
->vconfig
+ pos
, count
);
265 } else if (pos
>= PCI_STD_HEADER_SIZEOF
) { /* Std cap mangling */
266 if (offset
== PCI_CAP_LIST_ID
&& count
> 1)
267 memcpy(val
, vdev
->vconfig
+ pos
,
268 min(PCI_CAP_FLAGS
, count
));
269 else if (offset
== PCI_CAP_LIST_NEXT
)
270 memcpy(val
, vdev
->vconfig
+ pos
, 1);
276 static int vfio_direct_config_write(struct vfio_pci_device
*vdev
, int pos
,
277 int count
, struct perm_bits
*perm
,
278 int offset
, __le32 val
)
282 ret
= vfio_user_config_write(vdev
->pdev
, pos
, val
, count
);
289 /* Default all regions to read-only, no-virtualization */
290 static struct perm_bits cap_perms
[PCI_CAP_ID_MAX
+ 1] = {
291 [0 ... PCI_CAP_ID_MAX
] = { .readfn
= vfio_direct_config_read
}
293 static struct perm_bits ecap_perms
[PCI_EXT_CAP_ID_MAX
+ 1] = {
294 [0 ... PCI_EXT_CAP_ID_MAX
] = { .readfn
= vfio_direct_config_read
}
297 static void free_perm_bits(struct perm_bits
*perm
)
305 static int alloc_perm_bits(struct perm_bits
*perm
, int size
)
308 * Round up all permission bits to the next dword, this lets us
309 * ignore whether a read/write exceeds the defined capability
310 * structure. We can do this because:
311 * - Standard config space is already dword aligned
312 * - Capabilities are all dword alinged (bits 0:1 of next reserved)
313 * - Express capabilities defined as dword aligned
315 size
= round_up(size
, 4);
319 * - All Readable, None Writeable, None Virtualized
321 perm
->virt
= kzalloc(size
, GFP_KERNEL
);
322 perm
->write
= kzalloc(size
, GFP_KERNEL
);
323 if (!perm
->virt
|| !perm
->write
) {
324 free_perm_bits(perm
);
328 perm
->readfn
= vfio_default_config_read
;
329 perm
->writefn
= vfio_default_config_write
;
335 * Helper functions for filling in permission tables
337 static inline void p_setb(struct perm_bits
*p
, int off
, u8 virt
, u8 write
)
340 p
->write
[off
] = write
;
343 /* Handle endian-ness - pci and tables are little-endian */
344 static inline void p_setw(struct perm_bits
*p
, int off
, u16 virt
, u16 write
)
346 *(__le16
*)(&p
->virt
[off
]) = cpu_to_le16(virt
);
347 *(__le16
*)(&p
->write
[off
]) = cpu_to_le16(write
);
350 /* Handle endian-ness - pci and tables are little-endian */
351 static inline void p_setd(struct perm_bits
*p
, int off
, u32 virt
, u32 write
)
353 *(__le32
*)(&p
->virt
[off
]) = cpu_to_le32(virt
);
354 *(__le32
*)(&p
->write
[off
]) = cpu_to_le32(write
);
358 * Restore the *real* BARs after we detect a FLR or backdoor reset.
359 * (backdoor = some device specific technique that we didn't catch)
361 static void vfio_bar_restore(struct vfio_pci_device
*vdev
)
363 struct pci_dev
*pdev
= vdev
->pdev
;
364 u32
*rbar
= vdev
->rbar
;
370 pr_info("%s: %s reset recovery - restoring bars\n",
371 __func__
, dev_name(&pdev
->dev
));
373 for (i
= PCI_BASE_ADDRESS_0
; i
<= PCI_BASE_ADDRESS_5
; i
+= 4, rbar
++)
374 pci_user_write_config_dword(pdev
, i
, *rbar
);
376 pci_user_write_config_dword(pdev
, PCI_ROM_ADDRESS
, *rbar
);
379 static __le32
vfio_generate_bar_flags(struct pci_dev
*pdev
, int bar
)
381 unsigned long flags
= pci_resource_flags(pdev
, bar
);
384 if (flags
& IORESOURCE_IO
)
385 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO
);
387 val
= PCI_BASE_ADDRESS_SPACE_MEMORY
;
389 if (flags
& IORESOURCE_PREFETCH
)
390 val
|= PCI_BASE_ADDRESS_MEM_PREFETCH
;
392 if (flags
& IORESOURCE_MEM_64
)
393 val
|= PCI_BASE_ADDRESS_MEM_TYPE_64
;
395 return cpu_to_le32(val
);
399 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
400 * to reflect the hardware capabilities. This implements BAR sizing.
402 static void vfio_bar_fixup(struct vfio_pci_device
*vdev
)
404 struct pci_dev
*pdev
= vdev
->pdev
;
409 bar
= (__le32
*)&vdev
->vconfig
[PCI_BASE_ADDRESS_0
];
411 for (i
= PCI_STD_RESOURCES
; i
<= PCI_STD_RESOURCE_END
; i
++, bar
++) {
412 if (!pci_resource_start(pdev
, i
)) {
413 *bar
= 0; /* Unmapped by host = unimplemented to user */
417 mask
= ~(pci_resource_len(pdev
, i
) - 1);
419 *bar
&= cpu_to_le32((u32
)mask
);
420 *bar
|= vfio_generate_bar_flags(pdev
, i
);
422 if (*bar
& cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
424 *bar
&= cpu_to_le32((u32
)(mask
>> 32));
429 bar
= (__le32
*)&vdev
->vconfig
[PCI_ROM_ADDRESS
];
432 * NB. we expose the actual BAR size here, regardless of whether
433 * we can read it. When we report the REGION_INFO for the ROM
434 * we report what PCI tells us is the actual ROM size.
436 if (pci_resource_start(pdev
, PCI_ROM_RESOURCE
)) {
437 mask
= ~(pci_resource_len(pdev
, PCI_ROM_RESOURCE
) - 1);
438 mask
|= PCI_ROM_ADDRESS_ENABLE
;
439 *bar
&= cpu_to_le32((u32
)mask
);
443 vdev
->bardirty
= false;
446 static int vfio_basic_config_read(struct vfio_pci_device
*vdev
, int pos
,
447 int count
, struct perm_bits
*perm
,
448 int offset
, __le32
*val
)
450 if (is_bar(offset
)) /* pos == offset for basic config */
451 vfio_bar_fixup(vdev
);
453 count
= vfio_default_config_read(vdev
, pos
, count
, perm
, offset
, val
);
455 /* Mask in virtual memory enable for SR-IOV devices */
456 if (offset
== PCI_COMMAND
&& vdev
->pdev
->is_virtfn
) {
457 u16 cmd
= le16_to_cpu(*(__le16
*)&vdev
->vconfig
[PCI_COMMAND
]);
458 u32 tmp_val
= le32_to_cpu(*val
);
460 tmp_val
|= cmd
& PCI_COMMAND_MEMORY
;
461 *val
= cpu_to_le32(tmp_val
);
467 static int vfio_basic_config_write(struct vfio_pci_device
*vdev
, int pos
,
468 int count
, struct perm_bits
*perm
,
469 int offset
, __le32 val
)
471 struct pci_dev
*pdev
= vdev
->pdev
;
476 virt_cmd
= (__le16
*)&vdev
->vconfig
[PCI_COMMAND
];
478 if (offset
== PCI_COMMAND
) {
479 bool phys_mem
, virt_mem
, new_mem
, phys_io
, virt_io
, new_io
;
482 ret
= pci_user_read_config_word(pdev
, PCI_COMMAND
, &phys_cmd
);
486 new_cmd
= le32_to_cpu(val
);
488 phys_mem
= !!(phys_cmd
& PCI_COMMAND_MEMORY
);
489 virt_mem
= !!(le16_to_cpu(*virt_cmd
) & PCI_COMMAND_MEMORY
);
490 new_mem
= !!(new_cmd
& PCI_COMMAND_MEMORY
);
492 phys_io
= !!(phys_cmd
& PCI_COMMAND_IO
);
493 virt_io
= !!(le16_to_cpu(*virt_cmd
) & PCI_COMMAND_IO
);
494 new_io
= !!(new_cmd
& PCI_COMMAND_IO
);
497 * If the user is writing mem/io enable (new_mem/io) and we
498 * think it's already enabled (virt_mem/io), but the hardware
499 * shows it disabled (phys_mem/io, then the device has
500 * undergone some kind of backdoor reset and needs to be
501 * restored before we allow it to enable the bars.
502 * SR-IOV devices will trigger this, but we catch them later
504 if ((new_mem
&& virt_mem
&& !phys_mem
) ||
505 (new_io
&& virt_io
&& !phys_io
))
506 vfio_bar_restore(vdev
);
509 count
= vfio_default_config_write(vdev
, pos
, count
, perm
, offset
, val
);
514 * Save current memory/io enable bits in vconfig to allow for
515 * the test above next time.
517 if (offset
== PCI_COMMAND
) {
518 u16 mask
= PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
;
520 *virt_cmd
&= cpu_to_le16(~mask
);
521 *virt_cmd
|= cpu_to_le16(new_cmd
& mask
);
524 /* Emulate INTx disable */
525 if (offset
>= PCI_COMMAND
&& offset
<= PCI_COMMAND
+ 1) {
526 bool virt_intx_disable
;
528 virt_intx_disable
= !!(le16_to_cpu(*virt_cmd
) &
529 PCI_COMMAND_INTX_DISABLE
);
531 if (virt_intx_disable
&& !vdev
->virq_disabled
) {
532 vdev
->virq_disabled
= true;
533 vfio_pci_intx_mask(vdev
);
534 } else if (!virt_intx_disable
&& vdev
->virq_disabled
) {
535 vdev
->virq_disabled
= false;
536 vfio_pci_intx_unmask(vdev
);
541 vdev
->bardirty
= true;
546 /* Permissions for the Basic PCI Header */
547 static int __init
init_pci_cap_basic_perm(struct perm_bits
*perm
)
549 if (alloc_perm_bits(perm
, PCI_STD_HEADER_SIZEOF
))
552 perm
->readfn
= vfio_basic_config_read
;
553 perm
->writefn
= vfio_basic_config_write
;
555 /* Virtualized for SR-IOV functions, which just have FFFF */
556 p_setw(perm
, PCI_VENDOR_ID
, (u16
)ALL_VIRT
, NO_WRITE
);
557 p_setw(perm
, PCI_DEVICE_ID
, (u16
)ALL_VIRT
, NO_WRITE
);
560 * Virtualize INTx disable, we use it internally for interrupt
561 * control and can emulate it for non-PCI 2.3 devices.
563 p_setw(perm
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
, (u16
)ALL_WRITE
);
565 /* Virtualize capability list, we might want to skip/disable */
566 p_setw(perm
, PCI_STATUS
, PCI_STATUS_CAP_LIST
, NO_WRITE
);
568 /* No harm to write */
569 p_setb(perm
, PCI_CACHE_LINE_SIZE
, NO_VIRT
, (u8
)ALL_WRITE
);
570 p_setb(perm
, PCI_LATENCY_TIMER
, NO_VIRT
, (u8
)ALL_WRITE
);
571 p_setb(perm
, PCI_BIST
, NO_VIRT
, (u8
)ALL_WRITE
);
573 /* Virtualize all bars, can't touch the real ones */
574 p_setd(perm
, PCI_BASE_ADDRESS_0
, ALL_VIRT
, ALL_WRITE
);
575 p_setd(perm
, PCI_BASE_ADDRESS_1
, ALL_VIRT
, ALL_WRITE
);
576 p_setd(perm
, PCI_BASE_ADDRESS_2
, ALL_VIRT
, ALL_WRITE
);
577 p_setd(perm
, PCI_BASE_ADDRESS_3
, ALL_VIRT
, ALL_WRITE
);
578 p_setd(perm
, PCI_BASE_ADDRESS_4
, ALL_VIRT
, ALL_WRITE
);
579 p_setd(perm
, PCI_BASE_ADDRESS_5
, ALL_VIRT
, ALL_WRITE
);
580 p_setd(perm
, PCI_ROM_ADDRESS
, ALL_VIRT
, ALL_WRITE
);
582 /* Allow us to adjust capability chain */
583 p_setb(perm
, PCI_CAPABILITY_LIST
, (u8
)ALL_VIRT
, NO_WRITE
);
585 /* Sometimes used by sw, just virtualize */
586 p_setb(perm
, PCI_INTERRUPT_LINE
, (u8
)ALL_VIRT
, (u8
)ALL_WRITE
);
590 /* Permissions for the Power Management capability */
591 static int __init
init_pci_cap_pm_perm(struct perm_bits
*perm
)
593 if (alloc_perm_bits(perm
, pci_cap_length
[PCI_CAP_ID_PM
]))
597 * We always virtualize the next field so we can remove
598 * capabilities from the chain if we want to.
600 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
603 * Power management is defined *per function*,
604 * so we let the user write this
606 p_setd(perm
, PCI_PM_CTRL
, NO_VIRT
, ALL_WRITE
);
610 /* Permissions for PCI-X capability */
611 static int __init
init_pci_cap_pcix_perm(struct perm_bits
*perm
)
613 /* Alloc 24, but only 8 are used in v0 */
614 if (alloc_perm_bits(perm
, PCI_CAP_PCIX_SIZEOF_V2
))
617 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
619 p_setw(perm
, PCI_X_CMD
, NO_VIRT
, (u16
)ALL_WRITE
);
620 p_setd(perm
, PCI_X_ECC_CSR
, NO_VIRT
, ALL_WRITE
);
624 /* Permissions for PCI Express capability */
625 static int __init
init_pci_cap_exp_perm(struct perm_bits
*perm
)
627 /* Alloc larger of two possible sizes */
628 if (alloc_perm_bits(perm
, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2
))
631 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
634 * Allow writes to device control fields (includes FLR!)
635 * but not to devctl_phantom which could confuse IOMMU
636 * or to the ARI bit in devctl2 which is set at probe time
638 p_setw(perm
, PCI_EXP_DEVCTL
, NO_VIRT
, ~PCI_EXP_DEVCTL_PHANTOM
);
639 p_setw(perm
, PCI_EXP_DEVCTL2
, NO_VIRT
, ~PCI_EXP_DEVCTL2_ARI
);
643 /* Permissions for Advanced Function capability */
644 static int __init
init_pci_cap_af_perm(struct perm_bits
*perm
)
646 if (alloc_perm_bits(perm
, pci_cap_length
[PCI_CAP_ID_AF
]))
649 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
650 p_setb(perm
, PCI_AF_CTRL
, NO_VIRT
, PCI_AF_CTRL_FLR
);
654 /* Permissions for Advanced Error Reporting extended capability */
655 static int __init
init_pci_ext_cap_err_perm(struct perm_bits
*perm
)
659 if (alloc_perm_bits(perm
, pci_ext_cap_length
[PCI_EXT_CAP_ID_ERR
]))
663 * Virtualize the first dword of all express capabilities
664 * because it includes the next pointer. This lets us later
665 * remove capabilities from the chain if we need to.
667 p_setd(perm
, 0, ALL_VIRT
, NO_WRITE
);
669 /* Writable bits mask */
670 mask
= PCI_ERR_UNC_TRAIN
| /* Training */
671 PCI_ERR_UNC_DLP
| /* Data Link Protocol */
672 PCI_ERR_UNC_SURPDN
| /* Surprise Down */
673 PCI_ERR_UNC_POISON_TLP
| /* Poisoned TLP */
674 PCI_ERR_UNC_FCP
| /* Flow Control Protocol */
675 PCI_ERR_UNC_COMP_TIME
| /* Completion Timeout */
676 PCI_ERR_UNC_COMP_ABORT
| /* Completer Abort */
677 PCI_ERR_UNC_UNX_COMP
| /* Unexpected Completion */
678 PCI_ERR_UNC_RX_OVER
| /* Receiver Overflow */
679 PCI_ERR_UNC_MALF_TLP
| /* Malformed TLP */
680 PCI_ERR_UNC_ECRC
| /* ECRC Error Status */
681 PCI_ERR_UNC_UNSUP
| /* Unsupported Request */
682 PCI_ERR_UNC_ACSV
| /* ACS Violation */
683 PCI_ERR_UNC_INTN
| /* internal error */
684 PCI_ERR_UNC_MCBTLP
| /* MC blocked TLP */
685 PCI_ERR_UNC_ATOMEG
| /* Atomic egress blocked */
686 PCI_ERR_UNC_TLPPRE
; /* TLP prefix blocked */
687 p_setd(perm
, PCI_ERR_UNCOR_STATUS
, NO_VIRT
, mask
);
688 p_setd(perm
, PCI_ERR_UNCOR_MASK
, NO_VIRT
, mask
);
689 p_setd(perm
, PCI_ERR_UNCOR_SEVER
, NO_VIRT
, mask
);
691 mask
= PCI_ERR_COR_RCVR
| /* Receiver Error Status */
692 PCI_ERR_COR_BAD_TLP
| /* Bad TLP Status */
693 PCI_ERR_COR_BAD_DLLP
| /* Bad DLLP Status */
694 PCI_ERR_COR_REP_ROLL
| /* REPLAY_NUM Rollover */
695 PCI_ERR_COR_REP_TIMER
| /* Replay Timer Timeout */
696 PCI_ERR_COR_ADV_NFAT
| /* Advisory Non-Fatal */
697 PCI_ERR_COR_INTERNAL
| /* Corrected Internal */
698 PCI_ERR_COR_LOG_OVER
; /* Header Log Overflow */
699 p_setd(perm
, PCI_ERR_COR_STATUS
, NO_VIRT
, mask
);
700 p_setd(perm
, PCI_ERR_COR_MASK
, NO_VIRT
, mask
);
702 mask
= PCI_ERR_CAP_ECRC_GENE
| /* ECRC Generation Enable */
703 PCI_ERR_CAP_ECRC_CHKE
; /* ECRC Check Enable */
704 p_setd(perm
, PCI_ERR_CAP
, NO_VIRT
, mask
);
708 /* Permissions for Power Budgeting extended capability */
709 static int __init
init_pci_ext_cap_pwr_perm(struct perm_bits
*perm
)
711 if (alloc_perm_bits(perm
, pci_ext_cap_length
[PCI_EXT_CAP_ID_PWR
]))
714 p_setd(perm
, 0, ALL_VIRT
, NO_WRITE
);
716 /* Writing the data selector is OK, the info is still read-only */
717 p_setb(perm
, PCI_PWR_DATA
, NO_VIRT
, (u8
)ALL_WRITE
);
722 * Initialize the shared permission tables
724 void vfio_pci_uninit_perm_bits(void)
726 free_perm_bits(&cap_perms
[PCI_CAP_ID_BASIC
]);
728 free_perm_bits(&cap_perms
[PCI_CAP_ID_PM
]);
729 free_perm_bits(&cap_perms
[PCI_CAP_ID_PCIX
]);
730 free_perm_bits(&cap_perms
[PCI_CAP_ID_EXP
]);
731 free_perm_bits(&cap_perms
[PCI_CAP_ID_AF
]);
733 free_perm_bits(&ecap_perms
[PCI_EXT_CAP_ID_ERR
]);
734 free_perm_bits(&ecap_perms
[PCI_EXT_CAP_ID_PWR
]);
737 int __init
vfio_pci_init_perm_bits(void)
741 /* Basic config space */
742 ret
= init_pci_cap_basic_perm(&cap_perms
[PCI_CAP_ID_BASIC
]);
745 ret
|= init_pci_cap_pm_perm(&cap_perms
[PCI_CAP_ID_PM
]);
746 cap_perms
[PCI_CAP_ID_VPD
].writefn
= vfio_direct_config_write
;
747 ret
|= init_pci_cap_pcix_perm(&cap_perms
[PCI_CAP_ID_PCIX
]);
748 cap_perms
[PCI_CAP_ID_VNDR
].writefn
= vfio_direct_config_write
;
749 ret
|= init_pci_cap_exp_perm(&cap_perms
[PCI_CAP_ID_EXP
]);
750 ret
|= init_pci_cap_af_perm(&cap_perms
[PCI_CAP_ID_AF
]);
752 /* Extended capabilities */
753 ret
|= init_pci_ext_cap_err_perm(&ecap_perms
[PCI_EXT_CAP_ID_ERR
]);
754 ret
|= init_pci_ext_cap_pwr_perm(&ecap_perms
[PCI_EXT_CAP_ID_PWR
]);
755 ecap_perms
[PCI_EXT_CAP_ID_VNDR
].writefn
= vfio_direct_config_write
;
758 vfio_pci_uninit_perm_bits();
763 static int vfio_find_cap_start(struct vfio_pci_device
*vdev
, int pos
)
766 int base
= (pos
>= PCI_CFG_SPACE_SIZE
) ? PCI_CFG_SPACE_SIZE
:
767 PCI_STD_HEADER_SIZEOF
;
771 cap
= vdev
->pci_config_map
[pos
];
773 if (cap
== PCI_CAP_ID_BASIC
)
776 /* XXX Can we have to abutting capabilities of the same type? */
777 while (pos
- 1 >= base
&& vdev
->pci_config_map
[pos
- 1] == cap
)
783 static int vfio_msi_config_read(struct vfio_pci_device
*vdev
, int pos
,
784 int count
, struct perm_bits
*perm
,
785 int offset
, __le32
*val
)
787 /* Update max available queue size from msi_qmax */
788 if (offset
<= PCI_MSI_FLAGS
&& offset
+ count
>= PCI_MSI_FLAGS
) {
792 start
= vfio_find_cap_start(vdev
, pos
);
794 flags
= (__le16
*)&vdev
->vconfig
[start
];
796 *flags
&= cpu_to_le16(~PCI_MSI_FLAGS_QMASK
);
797 *flags
|= cpu_to_le16(vdev
->msi_qmax
<< 1);
800 return vfio_default_config_read(vdev
, pos
, count
, perm
, offset
, val
);
803 static int vfio_msi_config_write(struct vfio_pci_device
*vdev
, int pos
,
804 int count
, struct perm_bits
*perm
,
805 int offset
, __le32 val
)
807 count
= vfio_default_config_write(vdev
, pos
, count
, perm
, offset
, val
);
811 /* Fixup and write configured queue size and enable to hardware */
812 if (offset
<= PCI_MSI_FLAGS
&& offset
+ count
>= PCI_MSI_FLAGS
) {
817 start
= vfio_find_cap_start(vdev
, pos
);
819 pflags
= (__le16
*)&vdev
->vconfig
[start
+ PCI_MSI_FLAGS
];
821 flags
= le16_to_cpu(*pflags
);
823 /* MSI is enabled via ioctl */
825 flags
&= ~PCI_MSI_FLAGS_ENABLE
;
827 /* Check queue size */
828 if ((flags
& PCI_MSI_FLAGS_QSIZE
) >> 4 > vdev
->msi_qmax
) {
829 flags
&= ~PCI_MSI_FLAGS_QSIZE
;
830 flags
|= vdev
->msi_qmax
<< 4;
833 /* Write back to virt and to hardware */
834 *pflags
= cpu_to_le16(flags
);
835 ret
= pci_user_write_config_word(vdev
->pdev
,
836 start
+ PCI_MSI_FLAGS
,
839 return pcibios_err_to_errno(ret
);
846 * MSI determination is per-device, so this routine gets used beyond
847 * initialization time. Don't add __init
849 static int init_pci_cap_msi_perm(struct perm_bits
*perm
, int len
, u16 flags
)
851 if (alloc_perm_bits(perm
, len
))
854 perm
->readfn
= vfio_msi_config_read
;
855 perm
->writefn
= vfio_msi_config_write
;
857 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
860 * The upper byte of the control register is reserved,
861 * just setup the lower byte.
863 p_setb(perm
, PCI_MSI_FLAGS
, (u8
)ALL_VIRT
, (u8
)ALL_WRITE
);
864 p_setd(perm
, PCI_MSI_ADDRESS_LO
, ALL_VIRT
, ALL_WRITE
);
865 if (flags
& PCI_MSI_FLAGS_64BIT
) {
866 p_setd(perm
, PCI_MSI_ADDRESS_HI
, ALL_VIRT
, ALL_WRITE
);
867 p_setw(perm
, PCI_MSI_DATA_64
, (u16
)ALL_VIRT
, (u16
)ALL_WRITE
);
868 if (flags
& PCI_MSI_FLAGS_MASKBIT
) {
869 p_setd(perm
, PCI_MSI_MASK_64
, NO_VIRT
, ALL_WRITE
);
870 p_setd(perm
, PCI_MSI_PENDING_64
, NO_VIRT
, ALL_WRITE
);
873 p_setw(perm
, PCI_MSI_DATA_32
, (u16
)ALL_VIRT
, (u16
)ALL_WRITE
);
874 if (flags
& PCI_MSI_FLAGS_MASKBIT
) {
875 p_setd(perm
, PCI_MSI_MASK_32
, NO_VIRT
, ALL_WRITE
);
876 p_setd(perm
, PCI_MSI_PENDING_32
, NO_VIRT
, ALL_WRITE
);
882 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
883 static int vfio_msi_cap_len(struct vfio_pci_device
*vdev
, u8 pos
)
885 struct pci_dev
*pdev
= vdev
->pdev
;
889 ret
= pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &flags
);
891 return pcibios_err_to_errno(ret
);
893 len
= 10; /* Minimum size */
894 if (flags
& PCI_MSI_FLAGS_64BIT
)
896 if (flags
& PCI_MSI_FLAGS_MASKBIT
)
902 vdev
->msi_perm
= kmalloc(sizeof(struct perm_bits
), GFP_KERNEL
);
906 ret
= init_pci_cap_msi_perm(vdev
->msi_perm
, len
, flags
);
913 /* Determine extended capability length for VC (2 & 9) and MFVC */
914 static int vfio_vc_cap_len(struct vfio_pci_device
*vdev
, u16 pos
)
916 struct pci_dev
*pdev
= vdev
->pdev
;
918 int ret
, evcc
, phases
, vc_arb
;
919 int len
= PCI_CAP_VC_BASE_SIZEOF
;
921 ret
= pci_read_config_dword(pdev
, pos
+ PCI_VC_PORT_REG1
, &tmp
);
923 return pcibios_err_to_errno(ret
);
925 evcc
= tmp
& PCI_VC_REG1_EVCC
; /* extended vc count */
926 ret
= pci_read_config_dword(pdev
, pos
+ PCI_VC_PORT_REG2
, &tmp
);
928 return pcibios_err_to_errno(ret
);
930 if (tmp
& PCI_VC_REG2_128_PHASE
)
932 else if (tmp
& PCI_VC_REG2_64_PHASE
)
934 else if (tmp
& PCI_VC_REG2_32_PHASE
)
942 * Port arbitration tables are root & switch only;
943 * function arbitration tables are function 0 only.
944 * In either case, we'll never let user write them so
945 * we don't care how big they are
947 len
+= (1 + evcc
) * PCI_CAP_VC_PER_VC_SIZEOF
;
949 len
= round_up(len
, 16);
955 static int vfio_cap_len(struct vfio_pci_device
*vdev
, u8 cap
, u8 pos
)
957 struct pci_dev
*pdev
= vdev
->pdev
;
964 return vfio_msi_cap_len(vdev
, pos
);
965 case PCI_CAP_ID_PCIX
:
966 ret
= pci_read_config_word(pdev
, pos
+ PCI_X_CMD
, &word
);
968 return pcibios_err_to_errno(ret
);
970 if (PCI_X_CMD_VERSION(word
)) {
971 vdev
->extended_caps
= true;
972 return PCI_CAP_PCIX_SIZEOF_V2
;
974 return PCI_CAP_PCIX_SIZEOF_V0
;
975 case PCI_CAP_ID_VNDR
:
976 /* length follows next field */
977 ret
= pci_read_config_byte(pdev
, pos
+ PCI_CAP_FLAGS
, &byte
);
979 return pcibios_err_to_errno(ret
);
983 /* length based on version */
984 ret
= pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, &word
);
986 return pcibios_err_to_errno(ret
);
988 if ((word
& PCI_EXP_FLAGS_VERS
) == 1)
989 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1
;
991 vdev
->extended_caps
= true;
992 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2
;
995 ret
= pci_read_config_byte(pdev
, pos
+ 3, &byte
);
997 return pcibios_err_to_errno(ret
);
999 return (byte
& HT_3BIT_CAP_MASK
) ?
1000 HT_CAP_SIZEOF_SHORT
: HT_CAP_SIZEOF_LONG
;
1001 case PCI_CAP_ID_SATA
:
1002 ret
= pci_read_config_byte(pdev
, pos
+ PCI_SATA_REGS
, &byte
);
1004 return pcibios_err_to_errno(ret
);
1006 byte
&= PCI_SATA_REGS_MASK
;
1007 if (byte
== PCI_SATA_REGS_INLINE
)
1008 return PCI_SATA_SIZEOF_LONG
;
1010 return PCI_SATA_SIZEOF_SHORT
;
1012 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1013 dev_name(&pdev
->dev
), __func__
, cap
, pos
);
1019 static int vfio_ext_cap_len(struct vfio_pci_device
*vdev
, u16 ecap
, u16 epos
)
1021 struct pci_dev
*pdev
= vdev
->pdev
;
1027 case PCI_EXT_CAP_ID_VNDR
:
1028 ret
= pci_read_config_dword(pdev
, epos
+ PCI_VSEC_HDR
, &dword
);
1030 return pcibios_err_to_errno(ret
);
1032 return dword
>> PCI_VSEC_HDR_LEN_SHIFT
;
1033 case PCI_EXT_CAP_ID_VC
:
1034 case PCI_EXT_CAP_ID_VC9
:
1035 case PCI_EXT_CAP_ID_MFVC
:
1036 return vfio_vc_cap_len(vdev
, epos
);
1037 case PCI_EXT_CAP_ID_ACS
:
1038 ret
= pci_read_config_byte(pdev
, epos
+ PCI_ACS_CAP
, &byte
);
1040 return pcibios_err_to_errno(ret
);
1042 if (byte
& PCI_ACS_EC
) {
1045 ret
= pci_read_config_byte(pdev
,
1046 epos
+ PCI_ACS_EGRESS_BITS
,
1049 return pcibios_err_to_errno(ret
);
1051 bits
= byte
? round_up(byte
, 32) : 256;
1052 return 8 + (bits
/ 8);
1056 case PCI_EXT_CAP_ID_REBAR
:
1057 ret
= pci_read_config_byte(pdev
, epos
+ PCI_REBAR_CTRL
, &byte
);
1059 return pcibios_err_to_errno(ret
);
1061 byte
&= PCI_REBAR_CTRL_NBAR_MASK
;
1062 byte
>>= PCI_REBAR_CTRL_NBAR_SHIFT
;
1064 return 4 + (byte
* 8);
1065 case PCI_EXT_CAP_ID_DPA
:
1066 ret
= pci_read_config_byte(pdev
, epos
+ PCI_DPA_CAP
, &byte
);
1068 return pcibios_err_to_errno(ret
);
1070 byte
&= PCI_DPA_CAP_SUBSTATE_MASK
;
1071 byte
= round_up(byte
+ 1, 4);
1072 return PCI_DPA_BASE_SIZEOF
+ byte
;
1073 case PCI_EXT_CAP_ID_TPH
:
1074 ret
= pci_read_config_dword(pdev
, epos
+ PCI_TPH_CAP
, &dword
);
1076 return pcibios_err_to_errno(ret
);
1078 if ((dword
& PCI_TPH_CAP_LOC_MASK
) == PCI_TPH_LOC_CAP
) {
1081 sts
= byte
& PCI_TPH_CAP_ST_MASK
;
1082 sts
>>= PCI_TPH_CAP_ST_SHIFT
;
1083 return PCI_TPH_BASE_SIZEOF
+ round_up(sts
* 2, 4);
1085 return PCI_TPH_BASE_SIZEOF
;
1087 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1088 dev_name(&pdev
->dev
), __func__
, ecap
, epos
);
1094 static int vfio_fill_vconfig_bytes(struct vfio_pci_device
*vdev
,
1095 int offset
, int size
)
1097 struct pci_dev
*pdev
= vdev
->pdev
;
1101 * We try to read physical config space in the largest chunks
1102 * we can, assuming that all of the fields support dword access.
1103 * pci_save_state() makes this same assumption and seems to do ok.
1108 if (size
>= 4 && !(offset
% 4)) {
1109 __le32
*dwordp
= (__le32
*)&vdev
->vconfig
[offset
];
1112 ret
= pci_read_config_dword(pdev
, offset
, &dword
);
1115 *dwordp
= cpu_to_le32(dword
);
1117 } else if (size
>= 2 && !(offset
% 2)) {
1118 __le16
*wordp
= (__le16
*)&vdev
->vconfig
[offset
];
1121 ret
= pci_read_config_word(pdev
, offset
, &word
);
1124 *wordp
= cpu_to_le16(word
);
1127 u8
*byte
= &vdev
->vconfig
[offset
];
1128 ret
= pci_read_config_byte(pdev
, offset
, byte
);
1141 static int vfio_cap_init(struct vfio_pci_device
*vdev
)
1143 struct pci_dev
*pdev
= vdev
->pdev
;
1144 u8
*map
= vdev
->pci_config_map
;
1147 int loops
, ret
, caps
= 0;
1149 /* Any capabilities? */
1150 ret
= pci_read_config_word(pdev
, PCI_STATUS
, &status
);
1154 if (!(status
& PCI_STATUS_CAP_LIST
))
1155 return 0; /* Done */
1157 ret
= pci_read_config_byte(pdev
, PCI_CAPABILITY_LIST
, &pos
);
1161 /* Mark the previous position in case we want to skip a capability */
1162 prev
= &vdev
->vconfig
[PCI_CAPABILITY_LIST
];
1164 /* We can bound our loop, capabilities are dword aligned */
1165 loops
= (PCI_CFG_SPACE_SIZE
- PCI_STD_HEADER_SIZEOF
) / PCI_CAP_SIZEOF
;
1166 while (pos
&& loops
--) {
1170 ret
= pci_read_config_byte(pdev
, pos
, &cap
);
1174 ret
= pci_read_config_byte(pdev
,
1175 pos
+ PCI_CAP_LIST_NEXT
, &next
);
1179 if (cap
<= PCI_CAP_ID_MAX
) {
1180 len
= pci_cap_length
[cap
];
1181 if (len
== 0xFF) { /* Variable length */
1182 len
= vfio_cap_len(vdev
, cap
, pos
);
1189 pr_info("%s: %s hiding cap 0x%x\n",
1190 __func__
, dev_name(&pdev
->dev
), cap
);
1196 /* Sanity check, do we overlap other capabilities? */
1197 for (i
= 0; i
< len
; i
+= 4) {
1198 if (likely(map
[(pos
+ i
) / 4] == PCI_CAP_ID_INVALID
))
1201 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1202 __func__
, dev_name(&pdev
->dev
),
1203 pos
+ i
, map
[pos
+ i
], cap
);
1206 memset(map
+ (pos
/ 4), cap
, len
/ 4);
1207 ret
= vfio_fill_vconfig_bytes(vdev
, pos
, len
);
1211 prev
= &vdev
->vconfig
[pos
+ PCI_CAP_LIST_NEXT
];
1216 /* If we didn't fill any capabilities, clear the status flag */
1218 __le16
*vstatus
= (__le16
*)&vdev
->vconfig
[PCI_STATUS
];
1219 *vstatus
&= ~cpu_to_le16(PCI_STATUS_CAP_LIST
);
1225 static int vfio_ecap_init(struct vfio_pci_device
*vdev
)
1227 struct pci_dev
*pdev
= vdev
->pdev
;
1228 u8
*map
= vdev
->pci_config_map
;
1230 __le32
*prev
= NULL
;
1231 int loops
, ret
, ecaps
= 0;
1233 if (!vdev
->extended_caps
)
1236 epos
= PCI_CFG_SPACE_SIZE
;
1238 loops
= (pdev
->cfg_size
- PCI_CFG_SPACE_SIZE
) / PCI_CAP_SIZEOF
;
1240 while (loops
-- && epos
>= PCI_CFG_SPACE_SIZE
) {
1244 bool hidden
= false;
1246 ret
= pci_read_config_dword(pdev
, epos
, &header
);
1250 ecap
= PCI_EXT_CAP_ID(header
);
1252 if (ecap
<= PCI_EXT_CAP_ID_MAX
) {
1253 len
= pci_ext_cap_length
[ecap
];
1255 len
= vfio_ext_cap_len(vdev
, ecap
, epos
);
1262 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1263 __func__
, dev_name(&pdev
->dev
), ecap
, epos
);
1265 /* If not the first in the chain, we can skip over it */
1267 u32 val
= epos
= PCI_EXT_CAP_NEXT(header
);
1268 *prev
&= cpu_to_le32(~(0xffcU
<< 20));
1269 *prev
|= cpu_to_le32(val
<< 20);
1274 * Otherwise, fill in a placeholder, the direct
1275 * readfn will virtualize this automatically
1277 len
= PCI_CAP_SIZEOF
;
1281 for (i
= 0; i
< len
; i
+= 4) {
1282 if (likely(map
[(epos
+ i
) / 4] == PCI_CAP_ID_INVALID
))
1285 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1286 __func__
, dev_name(&pdev
->dev
),
1287 epos
+ i
, map
[epos
+ i
], ecap
);
1291 * Even though ecap is 2 bytes, we're currently a long way
1292 * from exceeding 1 byte capabilities. If we ever make it
1293 * up to 0xFF we'll need to up this to a two-byte, byte map.
1295 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX
>= PCI_CAP_ID_INVALID
);
1297 memset(map
+ (epos
/ 4), ecap
, len
/ 4);
1298 ret
= vfio_fill_vconfig_bytes(vdev
, epos
, len
);
1303 * If we're just using this capability to anchor the list,
1304 * hide the real ID. Only count real ecaps. XXX PCI spec
1305 * indicates to use cap id = 0, version = 0, next = 0 if
1306 * ecaps are absent, hope users check all the way to next.
1309 *(__le32
*)&vdev
->vconfig
[epos
] &=
1310 cpu_to_le32((0xffcU
<< 20));
1314 prev
= (__le32
*)&vdev
->vconfig
[epos
];
1315 epos
= PCI_EXT_CAP_NEXT(header
);
1319 *(u32
*)&vdev
->vconfig
[PCI_CFG_SPACE_SIZE
] = 0;
1325 * For each device we allocate a pci_config_map that indicates the
1326 * capability occupying each dword and thus the struct perm_bits we
1327 * use for read and write. We also allocate a virtualized config
1328 * space which tracks reads and writes to bits that we emulate for
1329 * the user. Initial values filled from device.
1331 * Using shared stuct perm_bits between all vfio-pci devices saves
1332 * us from allocating cfg_size buffers for virt and write for every
1333 * device. We could remove vconfig and allocate individual buffers
1334 * for each area requring emulated bits, but the array of pointers
1335 * would be comparable in size (at least for standard config space).
1337 int vfio_config_init(struct vfio_pci_device
*vdev
)
1339 struct pci_dev
*pdev
= vdev
->pdev
;
1344 * Config space, caps and ecaps are all dword aligned, so we can
1345 * use one byte per dword to record the type.
1347 map
= kmalloc(pdev
->cfg_size
/ 4, GFP_KERNEL
);
1351 vconfig
= kmalloc(pdev
->cfg_size
, GFP_KERNEL
);
1357 vdev
->pci_config_map
= map
;
1358 vdev
->vconfig
= vconfig
;
1360 memset(map
, PCI_CAP_ID_BASIC
, PCI_STD_HEADER_SIZEOF
/ 4);
1361 memset(map
+ (PCI_STD_HEADER_SIZEOF
/ 4), PCI_CAP_ID_INVALID
,
1362 (pdev
->cfg_size
- PCI_STD_HEADER_SIZEOF
) / 4);
1364 ret
= vfio_fill_vconfig_bytes(vdev
, 0, PCI_STD_HEADER_SIZEOF
);
1368 vdev
->bardirty
= true;
1371 * XXX can we just pci_load_saved_state/pci_restore_state?
1372 * may need to rebuild vconfig after that
1375 /* For restore after reset */
1376 vdev
->rbar
[0] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_0
]);
1377 vdev
->rbar
[1] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_1
]);
1378 vdev
->rbar
[2] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_2
]);
1379 vdev
->rbar
[3] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_3
]);
1380 vdev
->rbar
[4] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_4
]);
1381 vdev
->rbar
[5] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_5
]);
1382 vdev
->rbar
[6] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_ROM_ADDRESS
]);
1384 if (pdev
->is_virtfn
) {
1385 *(__le16
*)&vconfig
[PCI_VENDOR_ID
] = cpu_to_le16(pdev
->vendor
);
1386 *(__le16
*)&vconfig
[PCI_DEVICE_ID
] = cpu_to_le16(pdev
->device
);
1389 ret
= vfio_cap_init(vdev
);
1393 ret
= vfio_ecap_init(vdev
);
1401 vdev
->pci_config_map
= NULL
;
1403 vdev
->vconfig
= NULL
;
1404 return pcibios_err_to_errno(ret
);
1407 void vfio_config_free(struct vfio_pci_device
*vdev
)
1409 kfree(vdev
->vconfig
);
1410 vdev
->vconfig
= NULL
;
1411 kfree(vdev
->pci_config_map
);
1412 vdev
->pci_config_map
= NULL
;
1413 kfree(vdev
->msi_perm
);
1414 vdev
->msi_perm
= NULL
;
1417 static ssize_t
vfio_config_do_rw(struct vfio_pci_device
*vdev
, char __user
*buf
,
1418 size_t count
, loff_t
*ppos
, bool iswrite
)
1420 struct pci_dev
*pdev
= vdev
->pdev
;
1421 struct perm_bits
*perm
;
1423 int cap_start
= 0, offset
;
1425 ssize_t ret
= count
;
1427 if (*ppos
< 0 || *ppos
+ count
> pdev
->cfg_size
)
1431 * gcc can't seem to figure out we're a static function, only called
1432 * with count of 1/2/4 and hits copy_from_user_overflow without this.
1434 if (count
> sizeof(val
))
1437 cap_id
= vdev
->pci_config_map
[*ppos
/ 4];
1439 if (cap_id
== PCI_CAP_ID_INVALID
) {
1441 return ret
; /* drop */
1444 * Per PCI spec 3.0, section 6.1, reads from reserved and
1445 * unimplemented registers return 0
1447 if (copy_to_user(buf
, &val
, count
))
1454 * All capabilities are minimum 4 bytes and aligned on dword
1455 * boundaries. Since we don't support unaligned accesses, we're
1456 * only ever accessing a single capability.
1458 if (*ppos
>= PCI_CFG_SPACE_SIZE
) {
1459 WARN_ON(cap_id
> PCI_EXT_CAP_ID_MAX
);
1461 perm
= &ecap_perms
[cap_id
];
1462 cap_start
= vfio_find_cap_start(vdev
, *ppos
);
1465 WARN_ON(cap_id
> PCI_CAP_ID_MAX
);
1467 perm
= &cap_perms
[cap_id
];
1469 if (cap_id
== PCI_CAP_ID_MSI
)
1470 perm
= vdev
->msi_perm
;
1472 if (cap_id
> PCI_CAP_ID_BASIC
)
1473 cap_start
= vfio_find_cap_start(vdev
, *ppos
);
1476 WARN_ON(!cap_start
&& cap_id
!= PCI_CAP_ID_BASIC
);
1477 WARN_ON(cap_start
> *ppos
);
1479 offset
= *ppos
- cap_start
;
1485 if (copy_from_user(&val
, buf
, count
))
1488 ret
= perm
->writefn(vdev
, *ppos
, count
, perm
, offset
, val
);
1491 ret
= perm
->readfn(vdev
, *ppos
, count
,
1492 perm
, offset
, &val
);
1497 if (copy_to_user(buf
, &val
, count
))
1504 ssize_t
vfio_pci_config_readwrite(struct vfio_pci_device
*vdev
,
1505 char __user
*buf
, size_t count
,
1506 loff_t
*ppos
, bool iswrite
)
1512 pos
&= VFIO_PCI_OFFSET_MASK
;
1515 * We want to both keep the access size the caller users as well as
1516 * support reading large chunks of config space in a single call.
1517 * PCI doesn't support unaligned accesses, so we can safely break
1521 if (count
>= 4 && !(pos
% 4))
1522 ret
= vfio_config_do_rw(vdev
, buf
, 4, &pos
, iswrite
);
1523 else if (count
>= 2 && !(pos
% 2))
1524 ret
= vfio_config_do_rw(vdev
, buf
, 2, &pos
, iswrite
);
1526 ret
= vfio_config_do_rw(vdev
, buf
, 1, &pos
, iswrite
);