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[mirror_ubuntu-bionic-kernel.git] / drivers / video / aty / atyfb_base.c
1 /*
2 * ATI Frame Buffer Device Driver Core
3 *
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 *
9 * This driver supports the following ATI graphics chips:
10 * - ATI Mach64
11 *
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
15 *
16 * This driver is partly based on the PowerMac console driver:
17 *
18 * Copyright (C) 1996 Paul Mackerras
19 *
20 * and on the PowerMac ATI/mach64 display driver:
21 *
22 * Copyright (C) 1997 Michael AK Tesch
23 *
24 * with work by Jon Howell
25 * Harry AC Eaton
26 * Anthony Tong <atong@uiuc.edu>
27 *
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30 *
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
33 * more details.
34 *
35 * Many thanks to Nitya from ATI devrel for support and patience !
36 */
37
38 /******************************************************************************
39
40 TODO:
41
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
46
47 (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
57 #include <linux/mm.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/console.h>
62 #include <linux/fb.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/spinlock.h>
67 #include <linux/wait.h>
68 #include <linux/backlight.h>
69
70 #include <asm/io.h>
71 #include <asm/uaccess.h>
72
73 #include <video/mach64.h>
74 #include "atyfb.h"
75 #include "ati_ids.h"
76
77 #ifdef __powerpc__
78 #include <asm/machdep.h>
79 #include <asm/prom.h>
80 #include "../macmodes.h"
81 #endif
82 #ifdef __sparc__
83 #include <asm/pbm.h>
84 #include <asm/fbio.h>
85 #endif
86
87 #ifdef CONFIG_ADB_PMU
88 #include <linux/adb.h>
89 #include <linux/pmu.h>
90 #endif
91 #ifdef CONFIG_BOOTX_TEXT
92 #include <asm/btext.h>
93 #endif
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 #include <asm/backlight.h>
96 #endif
97 #ifdef CONFIG_MTRR
98 #include <asm/mtrr.h>
99 #endif
100
101 /*
102 * Debug flags.
103 */
104 #undef DEBUG
105 /*#define DEBUG*/
106
107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
108 /* - must be large enough to catch all GUI-Regs */
109 /* - must be aligned to a PAGE boundary */
110 #define GUI_RESERVE (1 * PAGE_SIZE)
111
112 /* FIXME: remove the FAIL definition */
113 #define FAIL(msg) do { \
114 if (!(var->activate & FB_ACTIVATE_TEST)) \
115 printk(KERN_CRIT "atyfb: " msg "\n"); \
116 return -EINVAL; \
117 } while (0)
118 #define FAIL_MAX(msg, x, _max_) do { \
119 if (x > _max_) { \
120 if (!(var->activate & FB_ACTIVATE_TEST)) \
121 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
122 return -EINVAL; \
123 } \
124 } while (0)
125 #ifdef DEBUG
126 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
127 #else
128 #define DPRINTK(fmt, args...)
129 #endif
130
131 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
132 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
133
134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
135 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
136 static const u32 lt_lcd_regs[] = {
137 CONFIG_PANEL_LG,
138 LCD_GEN_CNTL_LG,
139 DSTN_CONTROL_LG,
140 HFB_PITCH_ADDR_LG,
141 HORZ_STRETCHING_LG,
142 VERT_STRETCHING_LG,
143 0, /* EXT_VERT_STRETCH */
144 LT_GIO_LG,
145 POWER_MANAGEMENT_LG
146 };
147
148 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
149 {
150 if (M64_HAS(LT_LCD_REGS)) {
151 aty_st_le32(lt_lcd_regs[index], val, par);
152 } else {
153 unsigned long temp;
154
155 /* write addr byte */
156 temp = aty_ld_le32(LCD_INDEX, par);
157 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
158 /* write the register value */
159 aty_st_le32(LCD_DATA, val, par);
160 }
161 }
162
163 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
164 {
165 if (M64_HAS(LT_LCD_REGS)) {
166 return aty_ld_le32(lt_lcd_regs[index], par);
167 } else {
168 unsigned long temp;
169
170 /* write addr byte */
171 temp = aty_ld_le32(LCD_INDEX, par);
172 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
173 /* read the register value */
174 return aty_ld_le32(LCD_DATA, par);
175 }
176 }
177 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
178
179 #ifdef CONFIG_FB_ATY_GENERIC_LCD
180 /*
181 * ATIReduceRatio --
182 *
183 * Reduce a fraction by factoring out the largest common divider of the
184 * fraction's numerator and denominator.
185 */
186 static void ATIReduceRatio(int *Numerator, int *Denominator)
187 {
188 int Multiplier, Divider, Remainder;
189
190 Multiplier = *Numerator;
191 Divider = *Denominator;
192
193 while ((Remainder = Multiplier % Divider))
194 {
195 Multiplier = Divider;
196 Divider = Remainder;
197 }
198
199 *Numerator /= Divider;
200 *Denominator /= Divider;
201 }
202 #endif
203 /*
204 * The Hardware parameters for each card
205 */
206
207 struct pci_mmap_map {
208 unsigned long voff;
209 unsigned long poff;
210 unsigned long size;
211 unsigned long prot_flag;
212 unsigned long prot_mask;
213 };
214
215 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
216 .id = "ATY Mach64",
217 .type = FB_TYPE_PACKED_PIXELS,
218 .visual = FB_VISUAL_PSEUDOCOLOR,
219 .xpanstep = 8,
220 .ypanstep = 1,
221 };
222
223 /*
224 * Frame buffer device API
225 */
226
227 static int atyfb_open(struct fb_info *info, int user);
228 static int atyfb_release(struct fb_info *info, int user);
229 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
230 static int atyfb_set_par(struct fb_info *info);
231 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
232 u_int transp, struct fb_info *info);
233 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
234 static int atyfb_blank(int blank, struct fb_info *info);
235 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
236 #ifdef __sparc__
237 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
238 #endif
239 static int atyfb_sync(struct fb_info *info);
240
241 /*
242 * Internal routines
243 */
244
245 static int aty_init(struct fb_info *info);
246 static void aty_resume_chip(struct fb_info *info);
247 #ifdef CONFIG_ATARI
248 static int store_video_par(char *videopar, unsigned char m64_num);
249 #endif
250
251 static struct crtc saved_crtc;
252 static union aty_pll saved_pll;
253 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
254
255 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
256 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
257 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
258 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
259 #ifdef CONFIG_PPC
260 static int read_aty_sense(const struct atyfb_par *par);
261 #endif
262
263
264 /*
265 * Interface used by the world
266 */
267
268 static struct fb_var_screeninfo default_var = {
269 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
270 640, 480, 640, 480, 0, 0, 8, 0,
271 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
272 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
273 0, FB_VMODE_NONINTERLACED
274 };
275
276 static struct fb_videomode defmode = {
277 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
278 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
279 0, FB_VMODE_NONINTERLACED
280 };
281
282 static struct fb_ops atyfb_ops = {
283 .owner = THIS_MODULE,
284 .fb_open = atyfb_open,
285 .fb_release = atyfb_release,
286 .fb_check_var = atyfb_check_var,
287 .fb_set_par = atyfb_set_par,
288 .fb_setcolreg = atyfb_setcolreg,
289 .fb_pan_display = atyfb_pan_display,
290 .fb_blank = atyfb_blank,
291 .fb_ioctl = atyfb_ioctl,
292 .fb_fillrect = atyfb_fillrect,
293 .fb_copyarea = atyfb_copyarea,
294 .fb_imageblit = atyfb_imageblit,
295 #ifdef __sparc__
296 .fb_mmap = atyfb_mmap,
297 #endif
298 .fb_sync = atyfb_sync,
299 };
300
301 static int noaccel;
302 #ifdef CONFIG_MTRR
303 static int nomtrr;
304 #endif
305 static int vram;
306 static int pll;
307 static int mclk;
308 static int xclk;
309 static int comp_sync __devinitdata = -1;
310 static char *mode;
311
312 #ifdef CONFIG_PMAC_BACKLIGHT
313 static int backlight __devinitdata = 1;
314 #else
315 static int backlight __devinitdata = 0;
316 #endif
317
318 #ifdef CONFIG_PPC
319 static int default_vmode __devinitdata = VMODE_CHOOSE;
320 static int default_cmode __devinitdata = CMODE_CHOOSE;
321
322 module_param_named(vmode, default_vmode, int, 0);
323 MODULE_PARM_DESC(vmode, "int: video mode for mac");
324 module_param_named(cmode, default_cmode, int, 0);
325 MODULE_PARM_DESC(cmode, "int: color mode for mac");
326 #endif
327
328 #ifdef CONFIG_ATARI
329 static unsigned int mach64_count __devinitdata = 0;
330 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
331 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
332 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
333 #endif
334
335 /* top -> down is an evolution of mach64 chipset, any corrections? */
336 #define ATI_CHIP_88800GX (M64F_GX)
337 #define ATI_CHIP_88800CX (M64F_GX)
338
339 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
340 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
341
342 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
344
345 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
346 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
347 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
348
349 /* FIXME what is this chip? */
350 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
351
352 /* make sets shorter */
353 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
354
355 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
356 /*#define ATI_CHIP_264GTDVD ?*/
357 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
358
359 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
360 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
361 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
362
363 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
364 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
365
366 static struct {
367 u16 pci_id;
368 const char *name;
369 int pll, mclk, xclk, ecp_max;
370 u32 features;
371 } aty_chips[] __devinitdata = {
372 #ifdef CONFIG_FB_ATY_GX
373 /* Mach64 GX */
374 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
375 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
376 #endif /* CONFIG_FB_ATY_GX */
377
378 #ifdef CONFIG_FB_ATY_CT
379 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
380 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
381
382 /* FIXME what is this chip? */
383 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
384
385 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
386 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
387
388 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
389 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
390
391 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
392
393 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
394
395 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
396 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
397 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
398 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399
400 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
401 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
402 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
403 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405
406 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
407 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
408 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
409 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
410 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411
412 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
413 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
414 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
415 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
416 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
417 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
418
419 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
420 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
421 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
422 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423 #endif /* CONFIG_FB_ATY_CT */
424 };
425
426 /* can not fail */
427 static int __devinit correct_chipset(struct atyfb_par *par)
428 {
429 u8 rev;
430 u16 type;
431 u32 chip_id;
432 const char *name;
433 int i;
434
435 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
436 if (par->pci_id == aty_chips[i].pci_id)
437 break;
438
439 name = aty_chips[i].name;
440 par->pll_limits.pll_max = aty_chips[i].pll;
441 par->pll_limits.mclk = aty_chips[i].mclk;
442 par->pll_limits.xclk = aty_chips[i].xclk;
443 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
444 par->features = aty_chips[i].features;
445
446 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
447 type = chip_id & CFG_CHIP_TYPE;
448 rev = (chip_id & CFG_CHIP_REV) >> 24;
449
450 switch(par->pci_id) {
451 #ifdef CONFIG_FB_ATY_GX
452 case PCI_CHIP_MACH64GX:
453 if(type != 0x00d7)
454 return -ENODEV;
455 break;
456 case PCI_CHIP_MACH64CX:
457 if(type != 0x0057)
458 return -ENODEV;
459 break;
460 #endif
461 #ifdef CONFIG_FB_ATY_CT
462 case PCI_CHIP_MACH64VT:
463 switch (rev & 0x07) {
464 case 0x00:
465 switch (rev & 0xc0) {
466 case 0x00:
467 name = "ATI264VT (A3) (Mach64 VT)";
468 par->pll_limits.pll_max = 170;
469 par->pll_limits.mclk = 67;
470 par->pll_limits.xclk = 67;
471 par->pll_limits.ecp_max = 80;
472 par->features = ATI_CHIP_264VT;
473 break;
474 case 0x40:
475 name = "ATI264VT2 (A4) (Mach64 VT)";
476 par->pll_limits.pll_max = 200;
477 par->pll_limits.mclk = 67;
478 par->pll_limits.xclk = 67;
479 par->pll_limits.ecp_max = 80;
480 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
481 break;
482 }
483 break;
484 case 0x01:
485 name = "ATI264VT3 (B1) (Mach64 VT)";
486 par->pll_limits.pll_max = 200;
487 par->pll_limits.mclk = 67;
488 par->pll_limits.xclk = 67;
489 par->pll_limits.ecp_max = 80;
490 par->features = ATI_CHIP_264VTB;
491 break;
492 case 0x02:
493 name = "ATI264VT3 (B2) (Mach64 VT)";
494 par->pll_limits.pll_max = 200;
495 par->pll_limits.mclk = 67;
496 par->pll_limits.xclk = 67;
497 par->pll_limits.ecp_max = 80;
498 par->features = ATI_CHIP_264VT3;
499 break;
500 }
501 break;
502 case PCI_CHIP_MACH64GT:
503 switch (rev & 0x07) {
504 case 0x01:
505 name = "3D RAGE II (Mach64 GT)";
506 par->pll_limits.pll_max = 170;
507 par->pll_limits.mclk = 67;
508 par->pll_limits.xclk = 67;
509 par->pll_limits.ecp_max = 80;
510 par->features = ATI_CHIP_264GTB;
511 break;
512 case 0x02:
513 name = "3D RAGE II+ (Mach64 GT)";
514 par->pll_limits.pll_max = 200;
515 par->pll_limits.mclk = 67;
516 par->pll_limits.xclk = 67;
517 par->pll_limits.ecp_max = 100;
518 par->features = ATI_CHIP_264GTB;
519 break;
520 }
521 break;
522 #endif
523 }
524
525 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
526 return 0;
527 }
528
529 static char ram_dram[] __devinitdata = "DRAM";
530 static char ram_resv[] __devinitdata = "RESV";
531 #ifdef CONFIG_FB_ATY_GX
532 static char ram_vram[] __devinitdata = "VRAM";
533 #endif /* CONFIG_FB_ATY_GX */
534 #ifdef CONFIG_FB_ATY_CT
535 static char ram_edo[] __devinitdata = "EDO";
536 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
537 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
538 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
539 static char ram_off[] __devinitdata = "OFF";
540 #endif /* CONFIG_FB_ATY_CT */
541
542
543 static u32 pseudo_palette[17];
544
545 #ifdef CONFIG_FB_ATY_GX
546 static char *aty_gx_ram[8] __devinitdata = {
547 ram_dram, ram_vram, ram_vram, ram_dram,
548 ram_dram, ram_vram, ram_vram, ram_resv
549 };
550 #endif /* CONFIG_FB_ATY_GX */
551
552 #ifdef CONFIG_FB_ATY_CT
553 static char *aty_ct_ram[8] __devinitdata = {
554 ram_off, ram_dram, ram_edo, ram_edo,
555 ram_sdram, ram_sgram, ram_sdram32, ram_resv
556 };
557 #endif /* CONFIG_FB_ATY_CT */
558
559 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
560 {
561 u32 pixclock = var->pixclock;
562 #ifdef CONFIG_FB_ATY_GENERIC_LCD
563 u32 lcd_on_off;
564 par->pll.ct.xres = 0;
565 if (par->lcd_table != 0) {
566 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
567 if(lcd_on_off & LCD_ON) {
568 par->pll.ct.xres = var->xres;
569 pixclock = par->lcd_pixclock;
570 }
571 }
572 #endif
573 return pixclock;
574 }
575
576 #if defined(CONFIG_PPC)
577
578 /*
579 * Apple monitor sense
580 */
581
582 static int __devinit read_aty_sense(const struct atyfb_par *par)
583 {
584 int sense, i;
585
586 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
587 __delay(200);
588 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
589 __delay(2000);
590 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
591 sense = ((i & 0x3000) >> 3) | (i & 0x100);
592
593 /* drive each sense line low in turn and collect the other 2 */
594 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
595 __delay(2000);
596 i = aty_ld_le32(GP_IO, par);
597 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
598 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
599 __delay(200);
600
601 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
602 __delay(2000);
603 i = aty_ld_le32(GP_IO, par);
604 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
605 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
606 __delay(200);
607
608 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
609 __delay(2000);
610 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
611 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
612 return sense;
613 }
614
615 #endif /* defined(CONFIG_PPC) */
616
617 /* ------------------------------------------------------------------------- */
618
619 /*
620 * CRTC programming
621 */
622
623 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
624 {
625 #ifdef CONFIG_FB_ATY_GENERIC_LCD
626 if (par->lcd_table != 0) {
627 if(!M64_HAS(LT_LCD_REGS)) {
628 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
629 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
630 }
631 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
632 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
633
634
635 /* switch to non shadow registers */
636 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
637 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
638
639 /* save stretching */
640 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
641 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
642 if (!M64_HAS(LT_LCD_REGS))
643 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
644 }
645 #endif
646 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
647 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
648 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
649 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
650 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
651 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
652 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
653
654 #ifdef CONFIG_FB_ATY_GENERIC_LCD
655 if (par->lcd_table != 0) {
656 /* switch to shadow registers */
657 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
658 SHADOW_EN | SHADOW_RW_EN, par);
659
660 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
661 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
662 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
663 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
664
665 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
666 }
667 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
668 }
669
670 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
671 {
672 #ifdef CONFIG_FB_ATY_GENERIC_LCD
673 if (par->lcd_table != 0) {
674 /* stop CRTC */
675 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
676
677 /* update non-shadow registers first */
678 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
679 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
680 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
681
682 /* temporarily disable stretching */
683 aty_st_lcd(HORZ_STRETCHING,
684 crtc->horz_stretching &
685 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
686 aty_st_lcd(VERT_STRETCHING,
687 crtc->vert_stretching &
688 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
689 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
690 }
691 #endif
692 /* turn off CRT */
693 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
694
695 DPRINTK("setting up CRTC\n");
696 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
697 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
698 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
699 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
700
701 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
702 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
703 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
704 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
705 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
706 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
707 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
708
709 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
710 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
711 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
712 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
713 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
714 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
715
716 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
717 #if 0
718 FIXME
719 if (par->accel_flags & FB_ACCELF_TEXT)
720 aty_init_engine(par, info);
721 #endif
722 #ifdef CONFIG_FB_ATY_GENERIC_LCD
723 /* after setting the CRTC registers we should set the LCD registers. */
724 if (par->lcd_table != 0) {
725 /* switch to shadow registers */
726 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
727 (SHADOW_EN | SHADOW_RW_EN), par);
728
729 DPRINTK("set shadow CRT to %ix%i %c%c\n",
730 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
731 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
732
733 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
734 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
735 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
736 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
737
738 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
739 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
740 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
741 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
742
743 /* restore CRTC selection & shadow state and enable stretching */
744 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
745 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
746 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
747 if(!M64_HAS(LT_LCD_REGS))
748 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
749
750 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
751 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
752 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
753 if(!M64_HAS(LT_LCD_REGS)) {
754 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
755 aty_ld_le32(LCD_INDEX, par);
756 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
757 }
758 }
759 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
760 }
761
762 static int aty_var_to_crtc(const struct fb_info *info,
763 const struct fb_var_screeninfo *var, struct crtc *crtc)
764 {
765 struct atyfb_par *par = (struct atyfb_par *) info->par;
766 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
767 u32 sync, vmode, vdisplay;
768 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
769 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
770 u32 pix_width, dp_pix_width, dp_chain_mask;
771
772 /* input */
773 xres = var->xres;
774 yres = var->yres;
775 vxres = var->xres_virtual;
776 vyres = var->yres_virtual;
777 xoffset = var->xoffset;
778 yoffset = var->yoffset;
779 bpp = var->bits_per_pixel;
780 if (bpp == 16)
781 bpp = (var->green.length == 5) ? 15 : 16;
782 sync = var->sync;
783 vmode = var->vmode;
784
785 /* convert (and round up) and validate */
786 if (vxres < xres + xoffset)
787 vxres = xres + xoffset;
788 h_disp = xres;
789
790 if (vyres < yres + yoffset)
791 vyres = yres + yoffset;
792 v_disp = yres;
793
794 if (bpp <= 8) {
795 bpp = 8;
796 pix_width = CRTC_PIX_WIDTH_8BPP;
797 dp_pix_width =
798 HOST_8BPP | SRC_8BPP | DST_8BPP |
799 BYTE_ORDER_LSB_TO_MSB;
800 dp_chain_mask = DP_CHAIN_8BPP;
801 } else if (bpp <= 15) {
802 bpp = 16;
803 pix_width = CRTC_PIX_WIDTH_15BPP;
804 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
805 BYTE_ORDER_LSB_TO_MSB;
806 dp_chain_mask = DP_CHAIN_15BPP;
807 } else if (bpp <= 16) {
808 bpp = 16;
809 pix_width = CRTC_PIX_WIDTH_16BPP;
810 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
811 BYTE_ORDER_LSB_TO_MSB;
812 dp_chain_mask = DP_CHAIN_16BPP;
813 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
814 bpp = 24;
815 pix_width = CRTC_PIX_WIDTH_24BPP;
816 dp_pix_width =
817 HOST_8BPP | SRC_8BPP | DST_8BPP |
818 BYTE_ORDER_LSB_TO_MSB;
819 dp_chain_mask = DP_CHAIN_24BPP;
820 } else if (bpp <= 32) {
821 bpp = 32;
822 pix_width = CRTC_PIX_WIDTH_32BPP;
823 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
824 BYTE_ORDER_LSB_TO_MSB;
825 dp_chain_mask = DP_CHAIN_32BPP;
826 } else
827 FAIL("invalid bpp");
828
829 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
830 FAIL("not enough video RAM");
831
832 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
833 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
834
835 if((xres > 1600) || (yres > 1200)) {
836 FAIL("MACH64 chips are designed for max 1600x1200\n"
837 "select anoter resolution.");
838 }
839 h_sync_strt = h_disp + var->right_margin;
840 h_sync_end = h_sync_strt + var->hsync_len;
841 h_sync_dly = var->right_margin & 7;
842 h_total = h_sync_end + h_sync_dly + var->left_margin;
843
844 v_sync_strt = v_disp + var->lower_margin;
845 v_sync_end = v_sync_strt + var->vsync_len;
846 v_total = v_sync_end + var->upper_margin;
847
848 #ifdef CONFIG_FB_ATY_GENERIC_LCD
849 if (par->lcd_table != 0) {
850 if(!M64_HAS(LT_LCD_REGS)) {
851 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
852 crtc->lcd_index = lcd_index &
853 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
854 aty_st_le32(LCD_INDEX, lcd_index, par);
855 }
856
857 if (!M64_HAS(MOBIL_BUS))
858 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
859
860 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
861 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
862
863 crtc->lcd_gen_cntl &=
864 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
865 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
866 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
867 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
868
869 if((crtc->lcd_gen_cntl & LCD_ON) &&
870 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
871 /* We cannot display the mode on the LCD. If the CRT is enabled
872 we can turn off the LCD.
873 If the CRT is off, it isn't a good idea to switch it on; we don't
874 know if one is connected. So it's better to fail then.
875 */
876 if (crtc->lcd_gen_cntl & CRT_ON) {
877 if (!(var->activate & FB_ACTIVATE_TEST))
878 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
879 crtc->lcd_gen_cntl &= ~LCD_ON;
880 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
881 } else {
882 if (!(var->activate & FB_ACTIVATE_TEST))
883 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
884 return -EINVAL;
885 }
886 }
887 }
888
889 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
890 int VScan = 1;
891 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
892 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
893 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
894
895 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
896
897 /* This is horror! When we simulate, say 640x480 on an 800x600
898 LCD monitor, the CRTC should be programmed 800x600 values for
899 the non visible part, but 640x480 for the visible part.
900 This code has been tested on a laptop with it's 1400x1050 LCD
901 monitor and a conventional monitor both switched on.
902 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
903 works with little glitches also with DOUBLESCAN modes
904 */
905 if (yres < par->lcd_height) {
906 VScan = par->lcd_height / yres;
907 if(VScan > 1) {
908 VScan = 2;
909 vmode |= FB_VMODE_DOUBLE;
910 }
911 }
912
913 h_sync_strt = h_disp + par->lcd_right_margin;
914 h_sync_end = h_sync_strt + par->lcd_hsync_len;
915 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
916 h_total = h_disp + par->lcd_hblank_len;
917
918 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
919 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
920 v_total = v_disp + par->lcd_vblank_len / VScan;
921 }
922 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
923
924 h_disp = (h_disp >> 3) - 1;
925 h_sync_strt = (h_sync_strt >> 3) - 1;
926 h_sync_end = (h_sync_end >> 3) - 1;
927 h_total = (h_total >> 3) - 1;
928 h_sync_wid = h_sync_end - h_sync_strt;
929
930 FAIL_MAX("h_disp too large", h_disp, 0xff);
931 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
932 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
933 if(h_sync_wid > 0x1f)
934 h_sync_wid = 0x1f;
935 FAIL_MAX("h_total too large", h_total, 0x1ff);
936
937 if (vmode & FB_VMODE_DOUBLE) {
938 v_disp <<= 1;
939 v_sync_strt <<= 1;
940 v_sync_end <<= 1;
941 v_total <<= 1;
942 }
943
944 vdisplay = yres;
945 #ifdef CONFIG_FB_ATY_GENERIC_LCD
946 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
947 vdisplay = par->lcd_height;
948 #endif
949
950 v_disp--;
951 v_sync_strt--;
952 v_sync_end--;
953 v_total--;
954 v_sync_wid = v_sync_end - v_sync_strt;
955
956 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
957 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
958 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
959 if(v_sync_wid > 0x1f)
960 v_sync_wid = 0x1f;
961 FAIL_MAX("v_total too large", v_total, 0x7ff);
962
963 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
964
965 /* output */
966 crtc->vxres = vxres;
967 crtc->vyres = vyres;
968 crtc->xoffset = xoffset;
969 crtc->yoffset = yoffset;
970 crtc->bpp = bpp;
971 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
972 crtc->vline_crnt_vline = 0;
973
974 crtc->h_tot_disp = h_total | (h_disp<<16);
975 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
976 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
977 crtc->v_tot_disp = v_total | (v_disp<<16);
978 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
979
980 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
981 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
982 crtc->gen_cntl |= CRTC_VGA_LINEAR;
983
984 /* Enable doublescan mode if requested */
985 if (vmode & FB_VMODE_DOUBLE)
986 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
987 /* Enable interlaced mode if requested */
988 if (vmode & FB_VMODE_INTERLACED)
989 crtc->gen_cntl |= CRTC_INTERLACE_EN;
990 #ifdef CONFIG_FB_ATY_GENERIC_LCD
991 if (par->lcd_table != 0) {
992 vdisplay = yres;
993 if(vmode & FB_VMODE_DOUBLE)
994 vdisplay <<= 1;
995 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
996 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
997 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
998 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
999 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1000
1001 /* MOBILITY M1 tested, FIXME: LT */
1002 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1003 if (!M64_HAS(LT_LCD_REGS))
1004 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1005 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1006
1007 crtc->horz_stretching &=
1008 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1009 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1010 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1011 do {
1012 /*
1013 * The horizontal blender misbehaves when HDisplay is less than a
1014 * a certain threshold (440 for a 1024-wide panel). It doesn't
1015 * stretch such modes enough. Use pixel replication instead of
1016 * blending to stretch modes that can be made to exactly fit the
1017 * panel width. The undocumented "NoLCDBlend" option allows the
1018 * pixel-replicated mode to be slightly wider or narrower than the
1019 * panel width. It also causes a mode that is exactly half as wide
1020 * as the panel to be pixel-replicated, rather than blended.
1021 */
1022 int HDisplay = xres & ~7;
1023 int nStretch = par->lcd_width / HDisplay;
1024 int Remainder = par->lcd_width % HDisplay;
1025
1026 if ((!Remainder && ((nStretch > 2))) ||
1027 (((HDisplay * 16) / par->lcd_width) < 7)) {
1028 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1029 int horz_stretch_loop = -1, BestRemainder;
1030 int Numerator = HDisplay, Denominator = par->lcd_width;
1031 int Index = 5;
1032 ATIReduceRatio(&Numerator, &Denominator);
1033
1034 BestRemainder = (Numerator * 16) / Denominator;
1035 while (--Index >= 0) {
1036 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1037 Denominator;
1038 if (Remainder < BestRemainder) {
1039 horz_stretch_loop = Index;
1040 if (!(BestRemainder = Remainder))
1041 break;
1042 }
1043 }
1044
1045 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1046 int horz_stretch_ratio = 0, Accumulator = 0;
1047 int reuse_previous = 1;
1048
1049 Index = StretchLoops[horz_stretch_loop];
1050
1051 while (--Index >= 0) {
1052 if (Accumulator > 0)
1053 horz_stretch_ratio |= reuse_previous;
1054 else
1055 Accumulator += Denominator;
1056 Accumulator -= Numerator;
1057 reuse_previous <<= 1;
1058 }
1059
1060 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1061 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1062 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1063 break; /* Out of the do { ... } while (0) */
1064 }
1065 }
1066
1067 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1068 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1069 } while (0);
1070 }
1071
1072 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1073 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1074 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1075
1076 if (!M64_HAS(LT_LCD_REGS) &&
1077 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1078 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1079 } else {
1080 /*
1081 * Don't use vertical blending if the mode is too wide or not
1082 * vertically stretched.
1083 */
1084 crtc->vert_stretching = 0;
1085 }
1086 /* copy to shadow crtc */
1087 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1088 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1089 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1090 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1091 }
1092 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1093
1094 if (M64_HAS(MAGIC_FIFO)) {
1095 /* FIXME: display FIFO low watermark values */
1096 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1097 }
1098 crtc->dp_pix_width = dp_pix_width;
1099 crtc->dp_chain_mask = dp_chain_mask;
1100
1101 return 0;
1102 }
1103
1104 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1105 {
1106 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1107 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1108 h_sync_pol;
1109 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1110 u32 pix_width;
1111 u32 double_scan, interlace;
1112
1113 /* input */
1114 h_total = crtc->h_tot_disp & 0x1ff;
1115 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1116 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1117 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1118 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1119 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1120 v_total = crtc->v_tot_disp & 0x7ff;
1121 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1122 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1123 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1124 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1125 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1126 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1127 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1128 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1129
1130 /* convert */
1131 xres = (h_disp + 1) * 8;
1132 yres = v_disp + 1;
1133 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1134 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1135 hslen = h_sync_wid * 8;
1136 upper = v_total - v_sync_strt - v_sync_wid;
1137 lower = v_sync_strt - v_disp;
1138 vslen = v_sync_wid;
1139 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1140 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1141 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1142
1143 switch (pix_width) {
1144 #if 0
1145 case CRTC_PIX_WIDTH_4BPP:
1146 bpp = 4;
1147 var->red.offset = 0;
1148 var->red.length = 8;
1149 var->green.offset = 0;
1150 var->green.length = 8;
1151 var->blue.offset = 0;
1152 var->blue.length = 8;
1153 var->transp.offset = 0;
1154 var->transp.length = 0;
1155 break;
1156 #endif
1157 case CRTC_PIX_WIDTH_8BPP:
1158 bpp = 8;
1159 var->red.offset = 0;
1160 var->red.length = 8;
1161 var->green.offset = 0;
1162 var->green.length = 8;
1163 var->blue.offset = 0;
1164 var->blue.length = 8;
1165 var->transp.offset = 0;
1166 var->transp.length = 0;
1167 break;
1168 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1169 bpp = 16;
1170 var->red.offset = 10;
1171 var->red.length = 5;
1172 var->green.offset = 5;
1173 var->green.length = 5;
1174 var->blue.offset = 0;
1175 var->blue.length = 5;
1176 var->transp.offset = 0;
1177 var->transp.length = 0;
1178 break;
1179 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1180 bpp = 16;
1181 var->red.offset = 11;
1182 var->red.length = 5;
1183 var->green.offset = 5;
1184 var->green.length = 6;
1185 var->blue.offset = 0;
1186 var->blue.length = 5;
1187 var->transp.offset = 0;
1188 var->transp.length = 0;
1189 break;
1190 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1191 bpp = 24;
1192 var->red.offset = 16;
1193 var->red.length = 8;
1194 var->green.offset = 8;
1195 var->green.length = 8;
1196 var->blue.offset = 0;
1197 var->blue.length = 8;
1198 var->transp.offset = 0;
1199 var->transp.length = 0;
1200 break;
1201 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1202 bpp = 32;
1203 var->red.offset = 16;
1204 var->red.length = 8;
1205 var->green.offset = 8;
1206 var->green.length = 8;
1207 var->blue.offset = 0;
1208 var->blue.length = 8;
1209 var->transp.offset = 24;
1210 var->transp.length = 8;
1211 break;
1212 default:
1213 PRINTKE("Invalid pixel width\n");
1214 return -EINVAL;
1215 }
1216
1217 /* output */
1218 var->xres = xres;
1219 var->yres = yres;
1220 var->xres_virtual = crtc->vxres;
1221 var->yres_virtual = crtc->vyres;
1222 var->bits_per_pixel = bpp;
1223 var->left_margin = left;
1224 var->right_margin = right;
1225 var->upper_margin = upper;
1226 var->lower_margin = lower;
1227 var->hsync_len = hslen;
1228 var->vsync_len = vslen;
1229 var->sync = sync;
1230 var->vmode = FB_VMODE_NONINTERLACED;
1231 /* In double scan mode, the vertical parameters are doubled, so we need to
1232 half them to get the right values.
1233 In interlaced mode the values are already correct, so no correction is
1234 necessary.
1235 */
1236 if (interlace)
1237 var->vmode = FB_VMODE_INTERLACED;
1238
1239 if (double_scan) {
1240 var->vmode = FB_VMODE_DOUBLE;
1241 var->yres>>=1;
1242 var->upper_margin>>=1;
1243 var->lower_margin>>=1;
1244 var->vsync_len>>=1;
1245 }
1246
1247 return 0;
1248 }
1249
1250 /* ------------------------------------------------------------------------- */
1251
1252 static int atyfb_set_par(struct fb_info *info)
1253 {
1254 struct atyfb_par *par = (struct atyfb_par *) info->par;
1255 struct fb_var_screeninfo *var = &info->var;
1256 u32 tmp, pixclock;
1257 int err;
1258 #ifdef DEBUG
1259 struct fb_var_screeninfo debug;
1260 u32 pixclock_in_ps;
1261 #endif
1262 if (par->asleep)
1263 return 0;
1264
1265 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1266 return err;
1267
1268 pixclock = atyfb_get_pixclock(var, par);
1269
1270 if (pixclock == 0) {
1271 PRINTKE("Invalid pixclock\n");
1272 return -EINVAL;
1273 } else {
1274 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1275 return err;
1276 }
1277
1278 par->accel_flags = var->accel_flags; /* hack */
1279
1280 if (var->accel_flags) {
1281 info->fbops->fb_sync = atyfb_sync;
1282 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1283 } else {
1284 info->fbops->fb_sync = NULL;
1285 info->flags |= FBINFO_HWACCEL_DISABLED;
1286 }
1287
1288 if (par->blitter_may_be_busy)
1289 wait_for_idle(par);
1290
1291 aty_set_crtc(par, &par->crtc);
1292 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1293 par->pll_ops->set_pll(info, &par->pll);
1294
1295 #ifdef DEBUG
1296 if(par->pll_ops && par->pll_ops->pll_to_var)
1297 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1298 else
1299 pixclock_in_ps = 0;
1300
1301 if(0 == pixclock_in_ps) {
1302 PRINTKE("ALERT ops->pll_to_var get 0\n");
1303 pixclock_in_ps = pixclock;
1304 }
1305
1306 memset(&debug, 0, sizeof(debug));
1307 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1308 u32 hSync, vRefresh;
1309 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1310 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1311
1312 h_disp = debug.xres;
1313 h_sync_strt = h_disp + debug.right_margin;
1314 h_sync_end = h_sync_strt + debug.hsync_len;
1315 h_total = h_sync_end + debug.left_margin;
1316 v_disp = debug.yres;
1317 v_sync_strt = v_disp + debug.lower_margin;
1318 v_sync_end = v_sync_strt + debug.vsync_len;
1319 v_total = v_sync_end + debug.upper_margin;
1320
1321 hSync = 1000000000 / (pixclock_in_ps * h_total);
1322 vRefresh = (hSync * 1000) / v_total;
1323 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1324 vRefresh *= 2;
1325 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1326 vRefresh /= 2;
1327
1328 DPRINTK("atyfb_set_par\n");
1329 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1330 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1331 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1332 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1333 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1334 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1335 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1336 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1337 h_disp, h_sync_strt, h_sync_end, h_total,
1338 v_disp, v_sync_strt, v_sync_end, v_total);
1339 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1340 pixclock_in_ps,
1341 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1342 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1343 }
1344 #endif /* DEBUG */
1345
1346 if (!M64_HAS(INTEGRATED)) {
1347 /* Don't forget MEM_CNTL */
1348 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1349 switch (var->bits_per_pixel) {
1350 case 8:
1351 tmp |= 0x02000000;
1352 break;
1353 case 16:
1354 tmp |= 0x03000000;
1355 break;
1356 case 32:
1357 tmp |= 0x06000000;
1358 break;
1359 }
1360 aty_st_le32(MEM_CNTL, tmp, par);
1361 } else {
1362 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1363 if (!M64_HAS(MAGIC_POSTDIV))
1364 tmp |= par->mem_refresh_rate << 20;
1365 switch (var->bits_per_pixel) {
1366 case 8:
1367 case 24:
1368 tmp |= 0x00000000;
1369 break;
1370 case 16:
1371 tmp |= 0x04000000;
1372 break;
1373 case 32:
1374 tmp |= 0x08000000;
1375 break;
1376 }
1377 if (M64_HAS(CT_BUS)) {
1378 aty_st_le32(DAC_CNTL, 0x87010184, par);
1379 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1380 } else if (M64_HAS(VT_BUS)) {
1381 aty_st_le32(DAC_CNTL, 0x87010184, par);
1382 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1383 } else if (M64_HAS(MOBIL_BUS)) {
1384 aty_st_le32(DAC_CNTL, 0x80010102, par);
1385 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1386 } else {
1387 /* GT */
1388 aty_st_le32(DAC_CNTL, 0x86010102, par);
1389 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1390 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1391 }
1392 aty_st_le32(MEM_CNTL, tmp, par);
1393 }
1394 aty_st_8(DAC_MASK, 0xff, par);
1395
1396 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1397 info->fix.visual = var->bits_per_pixel <= 8 ?
1398 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1399
1400 /* Initialize the graphics engine */
1401 if (par->accel_flags & FB_ACCELF_TEXT)
1402 aty_init_engine(par, info);
1403
1404 #ifdef CONFIG_BOOTX_TEXT
1405 btext_update_display(info->fix.smem_start,
1406 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1407 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1408 var->bits_per_pixel,
1409 par->crtc.vxres * var->bits_per_pixel / 8);
1410 #endif /* CONFIG_BOOTX_TEXT */
1411 #if 0
1412 /* switch to accelerator mode */
1413 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1414 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1415 #endif
1416 #ifdef DEBUG
1417 {
1418 /* dump non shadow CRTC, pll, LCD registers */
1419 int i; u32 base;
1420
1421 /* CRTC registers */
1422 base = 0x2000;
1423 printk("debug atyfb: Mach64 non-shadow register values:");
1424 for (i = 0; i < 256; i = i+4) {
1425 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1426 printk(" %08X", aty_ld_le32(i, par));
1427 }
1428 printk("\n\n");
1429
1430 #ifdef CONFIG_FB_ATY_CT
1431 /* PLL registers */
1432 base = 0x00;
1433 printk("debug atyfb: Mach64 PLL register values:");
1434 for (i = 0; i < 64; i++) {
1435 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1436 if(i%4 == 0) printk(" ");
1437 printk("%02X", aty_ld_pll_ct(i, par));
1438 }
1439 printk("\n\n");
1440 #endif /* CONFIG_FB_ATY_CT */
1441
1442 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1443 if (par->lcd_table != 0) {
1444 /* LCD registers */
1445 base = 0x00;
1446 printk("debug atyfb: LCD register values:");
1447 if(M64_HAS(LT_LCD_REGS)) {
1448 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1449 if(i == EXT_VERT_STRETCH)
1450 continue;
1451 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1452 printk(" %08X", aty_ld_lcd(i, par));
1453 }
1454
1455 } else {
1456 for (i = 0; i < 64; i++) {
1457 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1458 printk(" %08X", aty_ld_lcd(i, par));
1459 }
1460 }
1461 printk("\n\n");
1462 }
1463 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1464 }
1465 #endif /* DEBUG */
1466 return 0;
1467 }
1468
1469 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1470 {
1471 struct atyfb_par *par = (struct atyfb_par *) info->par;
1472 int err;
1473 struct crtc crtc;
1474 union aty_pll pll;
1475 u32 pixclock;
1476
1477 memcpy(&pll, &(par->pll), sizeof(pll));
1478
1479 if((err = aty_var_to_crtc(info, var, &crtc)))
1480 return err;
1481
1482 pixclock = atyfb_get_pixclock(var, par);
1483
1484 if (pixclock == 0) {
1485 if (!(var->activate & FB_ACTIVATE_TEST))
1486 PRINTKE("Invalid pixclock\n");
1487 return -EINVAL;
1488 } else {
1489 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1490 return err;
1491 }
1492
1493 if (var->accel_flags & FB_ACCELF_TEXT)
1494 info->var.accel_flags = FB_ACCELF_TEXT;
1495 else
1496 info->var.accel_flags = 0;
1497
1498 aty_crtc_to_var(&crtc, var);
1499 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1500 return 0;
1501 }
1502
1503 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1504 {
1505 u32 xoffset = info->var.xoffset;
1506 u32 yoffset = info->var.yoffset;
1507 u32 vxres = par->crtc.vxres;
1508 u32 bpp = info->var.bits_per_pixel;
1509
1510 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1511 }
1512
1513
1514 /*
1515 * Open/Release the frame buffer device
1516 */
1517
1518 static int atyfb_open(struct fb_info *info, int user)
1519 {
1520 struct atyfb_par *par = (struct atyfb_par *) info->par;
1521
1522 if (user) {
1523 par->open++;
1524 #ifdef __sparc__
1525 par->mmaped = 0;
1526 #endif
1527 }
1528 return (0);
1529 }
1530
1531 static irqreturn_t aty_irq(int irq, void *dev_id)
1532 {
1533 struct atyfb_par *par = dev_id;
1534 int handled = 0;
1535 u32 int_cntl;
1536
1537 spin_lock(&par->int_lock);
1538
1539 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1540
1541 if (int_cntl & CRTC_VBLANK_INT) {
1542 /* clear interrupt */
1543 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1544 par->vblank.count++;
1545 if (par->vblank.pan_display) {
1546 par->vblank.pan_display = 0;
1547 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1548 }
1549 wake_up_interruptible(&par->vblank.wait);
1550 handled = 1;
1551 }
1552
1553 spin_unlock(&par->int_lock);
1554
1555 return IRQ_RETVAL(handled);
1556 }
1557
1558 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1559 {
1560 u32 int_cntl;
1561
1562 if (!test_and_set_bit(0, &par->irq_flags)) {
1563 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1564 clear_bit(0, &par->irq_flags);
1565 return -EINVAL;
1566 }
1567 spin_lock_irq(&par->int_lock);
1568 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1569 /* clear interrupt */
1570 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1571 /* enable interrupt */
1572 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1573 spin_unlock_irq(&par->int_lock);
1574 } else if (reenable) {
1575 spin_lock_irq(&par->int_lock);
1576 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1577 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1578 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1579 /* re-enable interrupt */
1580 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1581 }
1582 spin_unlock_irq(&par->int_lock);
1583 }
1584
1585 return 0;
1586 }
1587
1588 static int aty_disable_irq(struct atyfb_par *par)
1589 {
1590 u32 int_cntl;
1591
1592 if (test_and_clear_bit(0, &par->irq_flags)) {
1593 if (par->vblank.pan_display) {
1594 par->vblank.pan_display = 0;
1595 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1596 }
1597 spin_lock_irq(&par->int_lock);
1598 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1599 /* disable interrupt */
1600 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1601 spin_unlock_irq(&par->int_lock);
1602 free_irq(par->irq, par);
1603 }
1604
1605 return 0;
1606 }
1607
1608 static int atyfb_release(struct fb_info *info, int user)
1609 {
1610 struct atyfb_par *par = (struct atyfb_par *) info->par;
1611 if (user) {
1612 par->open--;
1613 mdelay(1);
1614 wait_for_idle(par);
1615 if (!par->open) {
1616 #ifdef __sparc__
1617 int was_mmaped = par->mmaped;
1618
1619 par->mmaped = 0;
1620
1621 if (was_mmaped) {
1622 struct fb_var_screeninfo var;
1623
1624 /* Now reset the default display config, we have no
1625 * idea what the program(s) which mmap'd the chip did
1626 * to the configuration, nor whether it restored it
1627 * correctly.
1628 */
1629 var = default_var;
1630 if (noaccel)
1631 var.accel_flags &= ~FB_ACCELF_TEXT;
1632 else
1633 var.accel_flags |= FB_ACCELF_TEXT;
1634 if (var.yres == var.yres_virtual) {
1635 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1636 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1637 if (var.yres_virtual < var.yres)
1638 var.yres_virtual = var.yres;
1639 }
1640 }
1641 #endif
1642 aty_disable_irq(par);
1643 }
1644 }
1645 return (0);
1646 }
1647
1648 /*
1649 * Pan or Wrap the Display
1650 *
1651 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1652 */
1653
1654 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1655 {
1656 struct atyfb_par *par = (struct atyfb_par *) info->par;
1657 u32 xres, yres, xoffset, yoffset;
1658
1659 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1660 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1661 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1662 yres >>= 1;
1663 xoffset = (var->xoffset + 7) & ~7;
1664 yoffset = var->yoffset;
1665 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1666 return -EINVAL;
1667 info->var.xoffset = xoffset;
1668 info->var.yoffset = yoffset;
1669 if (par->asleep)
1670 return 0;
1671
1672 set_off_pitch(par, info);
1673 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1674 par->vblank.pan_display = 1;
1675 } else {
1676 par->vblank.pan_display = 0;
1677 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1678 }
1679
1680 return 0;
1681 }
1682
1683 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1684 {
1685 struct aty_interrupt *vbl;
1686 unsigned int count;
1687 int ret;
1688
1689 switch (crtc) {
1690 case 0:
1691 vbl = &par->vblank;
1692 break;
1693 default:
1694 return -ENODEV;
1695 }
1696
1697 ret = aty_enable_irq(par, 0);
1698 if (ret)
1699 return ret;
1700
1701 count = vbl->count;
1702 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1703 if (ret < 0) {
1704 return ret;
1705 }
1706 if (ret == 0) {
1707 aty_enable_irq(par, 1);
1708 return -ETIMEDOUT;
1709 }
1710
1711 return 0;
1712 }
1713
1714
1715 #ifdef DEBUG
1716 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1717 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1718
1719 struct atyclk {
1720 u32 ref_clk_per;
1721 u8 pll_ref_div;
1722 u8 mclk_fb_div;
1723 u8 mclk_post_div; /* 1,2,3,4,8 */
1724 u8 mclk_fb_mult; /* 2 or 4 */
1725 u8 xclk_post_div; /* 1,2,3,4,8 */
1726 u8 vclk_fb_div;
1727 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1728 u32 dsp_xclks_per_row; /* 0-16383 */
1729 u32 dsp_loop_latency; /* 0-15 */
1730 u32 dsp_precision; /* 0-7 */
1731 u32 dsp_on; /* 0-2047 */
1732 u32 dsp_off; /* 0-2047 */
1733 };
1734
1735 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1736 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1737 #endif
1738
1739 #ifndef FBIO_WAITFORVSYNC
1740 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1741 #endif
1742
1743 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1744 {
1745 struct atyfb_par *par = (struct atyfb_par *) info->par;
1746 #ifdef __sparc__
1747 struct fbtype fbtyp;
1748 #endif
1749
1750 switch (cmd) {
1751 #ifdef __sparc__
1752 case FBIOGTYPE:
1753 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1754 fbtyp.fb_width = par->crtc.vxres;
1755 fbtyp.fb_height = par->crtc.vyres;
1756 fbtyp.fb_depth = info->var.bits_per_pixel;
1757 fbtyp.fb_cmsize = info->cmap.len;
1758 fbtyp.fb_size = info->fix.smem_len;
1759 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1760 return -EFAULT;
1761 break;
1762 #endif /* __sparc__ */
1763
1764 case FBIO_WAITFORVSYNC:
1765 {
1766 u32 crtc;
1767
1768 if (get_user(crtc, (__u32 __user *) arg))
1769 return -EFAULT;
1770
1771 return aty_waitforvblank(par, crtc);
1772 }
1773 break;
1774
1775 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1776 case ATYIO_CLKR:
1777 if (M64_HAS(INTEGRATED)) {
1778 struct atyclk clk;
1779 union aty_pll *pll = &(par->pll);
1780 u32 dsp_config = pll->ct.dsp_config;
1781 u32 dsp_on_off = pll->ct.dsp_on_off;
1782 clk.ref_clk_per = par->ref_clk_per;
1783 clk.pll_ref_div = pll->ct.pll_ref_div;
1784 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1785 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1786 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1787 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1788 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1789 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1790 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1791 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1792 clk.dsp_precision = (dsp_config >> 20) & 7;
1793 clk.dsp_off = dsp_on_off & 0x7ff;
1794 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1795 if (copy_to_user((struct atyclk __user *) arg, &clk,
1796 sizeof(clk)))
1797 return -EFAULT;
1798 } else
1799 return -EINVAL;
1800 break;
1801 case ATYIO_CLKW:
1802 if (M64_HAS(INTEGRATED)) {
1803 struct atyclk clk;
1804 union aty_pll *pll = &(par->pll);
1805 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1806 return -EFAULT;
1807 par->ref_clk_per = clk.ref_clk_per;
1808 pll->ct.pll_ref_div = clk.pll_ref_div;
1809 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1810 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1811 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1812 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1813 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1814 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1815 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1816 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1817 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1818 /*aty_calc_pll_ct(info, &pll->ct);*/
1819 aty_set_pll_ct(info, pll);
1820 } else
1821 return -EINVAL;
1822 break;
1823 case ATYIO_FEATR:
1824 if (get_user(par->features, (u32 __user *) arg))
1825 return -EFAULT;
1826 break;
1827 case ATYIO_FEATW:
1828 if (put_user(par->features, (u32 __user *) arg))
1829 return -EFAULT;
1830 break;
1831 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1832 default:
1833 return -EINVAL;
1834 }
1835 return 0;
1836 }
1837
1838 static int atyfb_sync(struct fb_info *info)
1839 {
1840 struct atyfb_par *par = (struct atyfb_par *) info->par;
1841
1842 if (par->blitter_may_be_busy)
1843 wait_for_idle(par);
1844 return 0;
1845 }
1846
1847 #ifdef __sparc__
1848 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1849 {
1850 struct atyfb_par *par = (struct atyfb_par *) info->par;
1851 unsigned int size, page, map_size = 0;
1852 unsigned long map_offset = 0;
1853 unsigned long off;
1854 int i;
1855
1856 if (!par->mmap_map)
1857 return -ENXIO;
1858
1859 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1860 return -EINVAL;
1861
1862 off = vma->vm_pgoff << PAGE_SHIFT;
1863 size = vma->vm_end - vma->vm_start;
1864
1865 /* To stop the swapper from even considering these pages. */
1866 vma->vm_flags |= (VM_IO | VM_RESERVED);
1867
1868 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1869 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1870 off += 0x8000000000000000UL;
1871
1872 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1873
1874 /* Each page, see which map applies */
1875 for (page = 0; page < size;) {
1876 map_size = 0;
1877 for (i = 0; par->mmap_map[i].size; i++) {
1878 unsigned long start = par->mmap_map[i].voff;
1879 unsigned long end = start + par->mmap_map[i].size;
1880 unsigned long offset = off + page;
1881
1882 if (start > offset)
1883 continue;
1884 if (offset >= end)
1885 continue;
1886
1887 map_size = par->mmap_map[i].size - (offset - start);
1888 map_offset =
1889 par->mmap_map[i].poff + (offset - start);
1890 break;
1891 }
1892 if (!map_size) {
1893 page += PAGE_SIZE;
1894 continue;
1895 }
1896 if (page + map_size > size)
1897 map_size = size - page;
1898
1899 pgprot_val(vma->vm_page_prot) &=
1900 ~(par->mmap_map[i].prot_mask);
1901 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1902
1903 if (remap_pfn_range(vma, vma->vm_start + page,
1904 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1905 return -EAGAIN;
1906
1907 page += map_size;
1908 }
1909
1910 if (!map_size)
1911 return -EINVAL;
1912
1913 if (!par->mmaped)
1914 par->mmaped = 1;
1915 return 0;
1916 }
1917
1918 static struct {
1919 u32 yoffset;
1920 u8 r[2][256];
1921 u8 g[2][256];
1922 u8 b[2][256];
1923 } atyfb_save;
1924
1925 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1926 {
1927 int i, tmp;
1928
1929 for (i = 0; i < 256; i++) {
1930 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1931 if (M64_HAS(EXTRA_BRIGHT))
1932 tmp |= 0x2;
1933 aty_st_8(DAC_CNTL, tmp, par);
1934 aty_st_8(DAC_MASK, 0xff, par);
1935
1936 aty_st_8(DAC_R_INDEX, i, par);
1937 atyfb_save.r[enter][i] = aty_ld_8(DAC_DATA, par);
1938 atyfb_save.g[enter][i] = aty_ld_8(DAC_DATA, par);
1939 atyfb_save.b[enter][i] = aty_ld_8(DAC_DATA, par);
1940 aty_st_8(DAC_W_INDEX, i, par);
1941 aty_st_8(DAC_DATA, atyfb_save.r[1 - enter][i], par);
1942 aty_st_8(DAC_DATA, atyfb_save.g[1 - enter][i], par);
1943 aty_st_8(DAC_DATA, atyfb_save.b[1 - enter][i], par);
1944 }
1945 }
1946
1947 static void atyfb_palette(int enter)
1948 {
1949 struct atyfb_par *par;
1950 struct fb_info *info;
1951 int i;
1952
1953 for (i = 0; i < FB_MAX; i++) {
1954 info = registered_fb[i];
1955 if (info && info->fbops == &atyfb_ops) {
1956 par = (struct atyfb_par *) info->par;
1957
1958 atyfb_save_palette(par, enter);
1959 if (enter) {
1960 atyfb_save.yoffset = info->var.yoffset;
1961 info->var.yoffset = 0;
1962 set_off_pitch(par, info);
1963 } else {
1964 info->var.yoffset = atyfb_save.yoffset;
1965 set_off_pitch(par, info);
1966 }
1967 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1968 break;
1969 }
1970 }
1971 }
1972 #endif /* __sparc__ */
1973
1974
1975
1976 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1977
1978 #ifdef CONFIG_PPC_PMAC
1979 /* Power management routines. Those are used for PowerBook sleep.
1980 */
1981 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1982 {
1983 u32 pm;
1984 int timeout;
1985
1986 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1987 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1988 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1990
1991 timeout = 2000;
1992 if (sleep) {
1993 /* Sleep */
1994 pm &= ~PWR_MGT_ON;
1995 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1996 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1997 udelay(10);
1998 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1999 pm |= SUSPEND_NOW;
2000 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2001 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2002 udelay(10);
2003 pm |= PWR_MGT_ON;
2004 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2005 do {
2006 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2007 mdelay(1);
2008 if ((--timeout) == 0)
2009 break;
2010 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2011 } else {
2012 /* Wakeup */
2013 pm &= ~PWR_MGT_ON;
2014 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2015 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2016 udelay(10);
2017 pm &= ~SUSPEND_NOW;
2018 pm |= (PWR_BLON | AUTO_PWR_UP);
2019 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2020 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2021 udelay(10);
2022 pm |= PWR_MGT_ON;
2023 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2024 do {
2025 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2026 mdelay(1);
2027 if ((--timeout) == 0)
2028 break;
2029 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2030 }
2031 mdelay(500);
2032
2033 return timeout ? 0 : -EIO;
2034 }
2035 #endif
2036
2037 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2038 {
2039 struct fb_info *info = pci_get_drvdata(pdev);
2040 struct atyfb_par *par = (struct atyfb_par *) info->par;
2041
2042 if (state.event == pdev->dev.power.power_state.event)
2043 return 0;
2044
2045 acquire_console_sem();
2046
2047 fb_set_suspend(info, 1);
2048
2049 /* Idle & reset engine */
2050 wait_for_idle(par);
2051 aty_reset_engine(par);
2052
2053 /* Blank display and LCD */
2054 atyfb_blank(FB_BLANK_POWERDOWN, info);
2055
2056 par->asleep = 1;
2057 par->lock_blank = 1;
2058
2059 #ifdef CONFIG_PPC_PMAC
2060 /* Set chip to "suspend" mode */
2061 if (aty_power_mgmt(1, par)) {
2062 par->asleep = 0;
2063 par->lock_blank = 0;
2064 atyfb_blank(FB_BLANK_UNBLANK, info);
2065 fb_set_suspend(info, 0);
2066 release_console_sem();
2067 return -EIO;
2068 }
2069 #else
2070 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2071 #endif
2072
2073 release_console_sem();
2074
2075 pdev->dev.power.power_state = state;
2076
2077 return 0;
2078 }
2079
2080 static int atyfb_pci_resume(struct pci_dev *pdev)
2081 {
2082 struct fb_info *info = pci_get_drvdata(pdev);
2083 struct atyfb_par *par = (struct atyfb_par *) info->par;
2084
2085 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2086 return 0;
2087
2088 acquire_console_sem();
2089
2090 #ifdef CONFIG_PPC_PMAC
2091 if (pdev->dev.power.power_state.event == 2)
2092 aty_power_mgmt(0, par);
2093 #else
2094 pci_set_power_state(pdev, PCI_D0);
2095 #endif
2096
2097 aty_resume_chip(info);
2098
2099 par->asleep = 0;
2100
2101 /* Restore display */
2102 atyfb_set_par(info);
2103
2104 /* Refresh */
2105 fb_set_suspend(info, 0);
2106
2107 /* Unblank */
2108 par->lock_blank = 0;
2109 atyfb_blank(FB_BLANK_UNBLANK, info);
2110
2111 release_console_sem();
2112
2113 pdev->dev.power.power_state = PMSG_ON;
2114
2115 return 0;
2116 }
2117
2118 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2119
2120 /* Backlight */
2121 #ifdef CONFIG_FB_ATY_BACKLIGHT
2122 #define MAX_LEVEL 0xFF
2123
2124 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2125 {
2126 struct fb_info *info = pci_get_drvdata(par->pdev);
2127 int atylevel;
2128
2129 /* Get and convert the value */
2130 /* No locking of bl_curve since we read a single value */
2131 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2132
2133 if (atylevel < 0)
2134 atylevel = 0;
2135 else if (atylevel > MAX_LEVEL)
2136 atylevel = MAX_LEVEL;
2137
2138 return atylevel;
2139 }
2140
2141 static int aty_bl_update_status(struct backlight_device *bd)
2142 {
2143 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2144 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2145 int level;
2146
2147 if (bd->props.power != FB_BLANK_UNBLANK ||
2148 bd->props.fb_blank != FB_BLANK_UNBLANK)
2149 level = 0;
2150 else
2151 level = bd->props.brightness;
2152
2153 reg |= (BLMOD_EN | BIASMOD_EN);
2154 if (level > 0) {
2155 reg &= ~BIAS_MOD_LEVEL_MASK;
2156 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2157 } else {
2158 reg &= ~BIAS_MOD_LEVEL_MASK;
2159 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2160 }
2161 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2162
2163 return 0;
2164 }
2165
2166 static int aty_bl_get_brightness(struct backlight_device *bd)
2167 {
2168 return bd->props.brightness;
2169 }
2170
2171 static struct backlight_ops aty_bl_data = {
2172 .get_brightness = aty_bl_get_brightness,
2173 .update_status = aty_bl_update_status,
2174 };
2175
2176 static void aty_bl_init(struct atyfb_par *par)
2177 {
2178 struct fb_info *info = pci_get_drvdata(par->pdev);
2179 struct backlight_device *bd;
2180 char name[12];
2181
2182 #ifdef CONFIG_PMAC_BACKLIGHT
2183 if (!pmac_has_backlight_type("ati"))
2184 return;
2185 #endif
2186
2187 snprintf(name, sizeof(name), "atybl%d", info->node);
2188
2189 bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2190 if (IS_ERR(bd)) {
2191 info->bl_dev = NULL;
2192 printk(KERN_WARNING "aty: Backlight registration failed\n");
2193 goto error;
2194 }
2195
2196 info->bl_dev = bd;
2197 fb_bl_default_curve(info, 0,
2198 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2199 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2200
2201 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2202 bd->props.brightness = bd->props.max_brightness;
2203 bd->props.power = FB_BLANK_UNBLANK;
2204 backlight_update_status(bd);
2205
2206 printk("aty: Backlight initialized (%s)\n", name);
2207
2208 return;
2209
2210 error:
2211 return;
2212 }
2213
2214 static void aty_bl_exit(struct backlight_device *bd)
2215 {
2216 backlight_device_unregister(bd);
2217 printk("aty: Backlight unloaded\n");
2218 }
2219
2220 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2221
2222 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2223 {
2224 const int ragepro_tbl[] = {
2225 44, 50, 55, 66, 75, 80, 100
2226 };
2227 const int ragexl_tbl[] = {
2228 50, 66, 75, 83, 90, 95, 100, 105,
2229 110, 115, 120, 125, 133, 143, 166
2230 };
2231 const int *refresh_tbl;
2232 int i, size;
2233
2234 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2235 refresh_tbl = ragexl_tbl;
2236 size = ARRAY_SIZE(ragexl_tbl);
2237 } else {
2238 refresh_tbl = ragepro_tbl;
2239 size = ARRAY_SIZE(ragepro_tbl);
2240 }
2241
2242 for (i=0; i < size; i++) {
2243 if (xclk < refresh_tbl[i])
2244 break;
2245 }
2246 par->mem_refresh_rate = i;
2247 }
2248
2249 /*
2250 * Initialisation
2251 */
2252
2253 static struct fb_info *fb_list = NULL;
2254
2255 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2256 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2257 struct fb_var_screeninfo *var)
2258 {
2259 int ret = -EINVAL;
2260
2261 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2262 *var = default_var;
2263 var->xres = var->xres_virtual = par->lcd_hdisp;
2264 var->right_margin = par->lcd_right_margin;
2265 var->left_margin = par->lcd_hblank_len -
2266 (par->lcd_right_margin + par->lcd_hsync_dly +
2267 par->lcd_hsync_len);
2268 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2269 var->yres = var->yres_virtual = par->lcd_vdisp;
2270 var->lower_margin = par->lcd_lower_margin;
2271 var->upper_margin = par->lcd_vblank_len -
2272 (par->lcd_lower_margin + par->lcd_vsync_len);
2273 var->vsync_len = par->lcd_vsync_len;
2274 var->pixclock = par->lcd_pixclock;
2275 ret = 0;
2276 }
2277
2278 return ret;
2279 }
2280 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2281
2282 static int __devinit aty_init(struct fb_info *info)
2283 {
2284 struct atyfb_par *par = (struct atyfb_par *) info->par;
2285 const char *ramname = NULL, *xtal;
2286 int gtb_memsize, has_var = 0;
2287 struct fb_var_screeninfo var;
2288
2289 init_waitqueue_head(&par->vblank.wait);
2290 spin_lock_init(&par->int_lock);
2291
2292 #ifdef CONFIG_PPC_PMAC
2293 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2294 * and set the frequency manually. */
2295 if (machine_is_compatible("PowerBook2,1")) {
2296 par->pll_limits.mclk = 70;
2297 par->pll_limits.xclk = 53;
2298 }
2299 #endif
2300
2301 #ifdef CONFIG_FB_ATY_GX
2302 if (!M64_HAS(INTEGRATED)) {
2303 u32 stat0;
2304 u8 dac_type, dac_subtype, clk_type;
2305 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2306 par->bus_type = (stat0 >> 0) & 0x07;
2307 par->ram_type = (stat0 >> 3) & 0x07;
2308 ramname = aty_gx_ram[par->ram_type];
2309 /* FIXME: clockchip/RAMDAC probing? */
2310 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2311 #ifdef CONFIG_ATARI
2312 clk_type = CLK_ATI18818_1;
2313 dac_type = (stat0 >> 9) & 0x07;
2314 if (dac_type == 0x07)
2315 dac_subtype = DAC_ATT20C408;
2316 else
2317 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2318 #else
2319 dac_type = DAC_IBMRGB514;
2320 dac_subtype = DAC_IBMRGB514;
2321 clk_type = CLK_IBMRGB514;
2322 #endif
2323 switch (dac_subtype) {
2324 case DAC_IBMRGB514:
2325 par->dac_ops = &aty_dac_ibm514;
2326 break;
2327 #ifdef CONFIG_ATARI
2328 case DAC_ATI68860_B:
2329 case DAC_ATI68860_C:
2330 par->dac_ops = &aty_dac_ati68860b;
2331 break;
2332 case DAC_ATT20C408:
2333 case DAC_ATT21C498:
2334 par->dac_ops = &aty_dac_att21c498;
2335 break;
2336 #endif
2337 default:
2338 PRINTKI("aty_init: DAC type not implemented yet!\n");
2339 par->dac_ops = &aty_dac_unsupported;
2340 break;
2341 }
2342 switch (clk_type) {
2343 #ifdef CONFIG_ATARI
2344 case CLK_ATI18818_1:
2345 par->pll_ops = &aty_pll_ati18818_1;
2346 break;
2347 #else
2348 case CLK_IBMRGB514:
2349 par->pll_ops = &aty_pll_ibm514;
2350 break;
2351 #endif
2352 #if 0 /* dead code */
2353 case CLK_STG1703:
2354 par->pll_ops = &aty_pll_stg1703;
2355 break;
2356 case CLK_CH8398:
2357 par->pll_ops = &aty_pll_ch8398;
2358 break;
2359 case CLK_ATT20C408:
2360 par->pll_ops = &aty_pll_att20c408;
2361 break;
2362 #endif
2363 default:
2364 PRINTKI("aty_init: CLK type not implemented yet!");
2365 par->pll_ops = &aty_pll_unsupported;
2366 break;
2367 }
2368 }
2369 #endif /* CONFIG_FB_ATY_GX */
2370 #ifdef CONFIG_FB_ATY_CT
2371 if (M64_HAS(INTEGRATED)) {
2372 par->dac_ops = &aty_dac_ct;
2373 par->pll_ops = &aty_pll_ct;
2374 par->bus_type = PCI;
2375 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2376 ramname = aty_ct_ram[par->ram_type];
2377 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2378 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2379 par->pll_limits.mclk = 63;
2380 /* Mobility + 32bit memory interface need halved XCLK. */
2381 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2382 par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2383 }
2384 #endif
2385
2386 /* Allow command line to override clocks. */
2387 if (pll)
2388 par->pll_limits.pll_max = pll;
2389 if (mclk)
2390 par->pll_limits.mclk = mclk;
2391 if (xclk)
2392 par->pll_limits.xclk = xclk;
2393
2394 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2395 par->pll_per = 1000000/par->pll_limits.pll_max;
2396 par->mclk_per = 1000000/par->pll_limits.mclk;
2397 par->xclk_per = 1000000/par->pll_limits.xclk;
2398
2399 par->ref_clk_per = 1000000000000ULL / 14318180;
2400 xtal = "14.31818";
2401
2402 #ifdef CONFIG_FB_ATY_CT
2403 if (M64_HAS(GTB_DSP)) {
2404 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2405
2406 if (pll_ref_div) {
2407 int diff1, diff2;
2408 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2409 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2410 if (diff1 < 0)
2411 diff1 = -diff1;
2412 if (diff2 < 0)
2413 diff2 = -diff2;
2414 if (diff2 < diff1) {
2415 par->ref_clk_per = 1000000000000ULL / 29498928;
2416 xtal = "29.498928";
2417 }
2418 }
2419 }
2420 #endif /* CONFIG_FB_ATY_CT */
2421
2422 /* save previous video mode */
2423 aty_get_crtc(par, &saved_crtc);
2424 if(par->pll_ops->get_pll)
2425 par->pll_ops->get_pll(info, &saved_pll);
2426
2427 par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2428 gtb_memsize = M64_HAS(GTB_DSP);
2429 if (gtb_memsize)
2430 switch (par->mem_cntl & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2431 case MEM_SIZE_512K:
2432 info->fix.smem_len = 0x80000;
2433 break;
2434 case MEM_SIZE_1M:
2435 info->fix.smem_len = 0x100000;
2436 break;
2437 case MEM_SIZE_2M_GTB:
2438 info->fix.smem_len = 0x200000;
2439 break;
2440 case MEM_SIZE_4M_GTB:
2441 info->fix.smem_len = 0x400000;
2442 break;
2443 case MEM_SIZE_6M_GTB:
2444 info->fix.smem_len = 0x600000;
2445 break;
2446 case MEM_SIZE_8M_GTB:
2447 info->fix.smem_len = 0x800000;
2448 break;
2449 default:
2450 info->fix.smem_len = 0x80000;
2451 } else
2452 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2453 case MEM_SIZE_512K:
2454 info->fix.smem_len = 0x80000;
2455 break;
2456 case MEM_SIZE_1M:
2457 info->fix.smem_len = 0x100000;
2458 break;
2459 case MEM_SIZE_2M:
2460 info->fix.smem_len = 0x200000;
2461 break;
2462 case MEM_SIZE_4M:
2463 info->fix.smem_len = 0x400000;
2464 break;
2465 case MEM_SIZE_6M:
2466 info->fix.smem_len = 0x600000;
2467 break;
2468 case MEM_SIZE_8M:
2469 info->fix.smem_len = 0x800000;
2470 break;
2471 default:
2472 info->fix.smem_len = 0x80000;
2473 }
2474
2475 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2476 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2477 info->fix.smem_len += 0x400000;
2478 }
2479
2480 if (vram) {
2481 info->fix.smem_len = vram * 1024;
2482 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2483 if (info->fix.smem_len <= 0x80000)
2484 par->mem_cntl |= MEM_SIZE_512K;
2485 else if (info->fix.smem_len <= 0x100000)
2486 par->mem_cntl |= MEM_SIZE_1M;
2487 else if (info->fix.smem_len <= 0x200000)
2488 par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2489 else if (info->fix.smem_len <= 0x400000)
2490 par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2491 else if (info->fix.smem_len <= 0x600000)
2492 par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2493 else
2494 par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2495 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2496 }
2497
2498 /*
2499 * Reg Block 0 (CT-compatible block) is at mmio_start
2500 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2501 */
2502 if (M64_HAS(GX)) {
2503 info->fix.mmio_len = 0x400;
2504 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2505 } else if (M64_HAS(CT)) {
2506 info->fix.mmio_len = 0x400;
2507 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2508 } else if (M64_HAS(VT)) {
2509 info->fix.mmio_start -= 0x400;
2510 info->fix.mmio_len = 0x800;
2511 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2512 } else {/* GT */
2513 info->fix.mmio_start -= 0x400;
2514 info->fix.mmio_len = 0x800;
2515 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2516 }
2517
2518 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2519 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2520 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2521 par->pll_limits.mclk, par->pll_limits.xclk);
2522
2523 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2524 if (M64_HAS(INTEGRATED)) {
2525 int i;
2526 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2527 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2528 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2529 "debug atyfb: PLL",
2530 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2531 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2532 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2533 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2534 for (i = 0; i < 40; i++)
2535 printk(" %02x", aty_ld_pll_ct(i, par));
2536 printk("\n");
2537 }
2538 #endif
2539 if(par->pll_ops->init_pll)
2540 par->pll_ops->init_pll(info, &par->pll);
2541 if (par->pll_ops->resume_pll)
2542 par->pll_ops->resume_pll(info, &par->pll);
2543
2544 /*
2545 * Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2546 * unless the auxiliary register aperture is used.
2547 */
2548
2549 if (!par->aux_start &&
2550 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2551 info->fix.smem_len -= GUI_RESERVE;
2552
2553 /*
2554 * Disable register access through the linear aperture
2555 * if the auxiliary aperture is used so we can access
2556 * the full 8 MB of video RAM on 8 MB boards.
2557 */
2558 if (par->aux_start)
2559 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2560
2561 #ifdef CONFIG_MTRR
2562 par->mtrr_aper = -1;
2563 par->mtrr_reg = -1;
2564 if (!nomtrr) {
2565 /* Cover the whole resource. */
2566 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2567 if (par->mtrr_aper >= 0 && !par->aux_start) {
2568 /* Make a hole for mmio. */
2569 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2570 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2571 if (par->mtrr_reg < 0) {
2572 mtrr_del(par->mtrr_aper, 0, 0);
2573 par->mtrr_aper = -1;
2574 }
2575 }
2576 }
2577 #endif
2578
2579 info->fbops = &atyfb_ops;
2580 info->pseudo_palette = pseudo_palette;
2581 info->flags = FBINFO_DEFAULT |
2582 FBINFO_HWACCEL_IMAGEBLIT |
2583 FBINFO_HWACCEL_FILLRECT |
2584 FBINFO_HWACCEL_COPYAREA |
2585 FBINFO_HWACCEL_YPAN;
2586
2587 #ifdef CONFIG_PMAC_BACKLIGHT
2588 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2589 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2590 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2591 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2592 } else
2593 #endif
2594 if (M64_HAS(MOBIL_BUS) && backlight) {
2595 #ifdef CONFIG_FB_ATY_BACKLIGHT
2596 aty_bl_init (par);
2597 #endif
2598 }
2599
2600 memset(&var, 0, sizeof(var));
2601 #ifdef CONFIG_PPC
2602 if (machine_is(powermac)) {
2603 /*
2604 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2605 * applies to all Mac video cards
2606 */
2607 if (mode) {
2608 if (mac_find_mode(&var, info, mode, 8))
2609 has_var = 1;
2610 } else {
2611 if (default_vmode == VMODE_CHOOSE) {
2612 int sense;
2613 if (M64_HAS(G3_PB_1024x768))
2614 /* G3 PowerBook with 1024x768 LCD */
2615 default_vmode = VMODE_1024_768_60;
2616 else if (machine_is_compatible("iMac"))
2617 default_vmode = VMODE_1024_768_75;
2618 else if (machine_is_compatible
2619 ("PowerBook2,1"))
2620 /* iBook with 800x600 LCD */
2621 default_vmode = VMODE_800_600_60;
2622 else
2623 default_vmode = VMODE_640_480_67;
2624 sense = read_aty_sense(par);
2625 PRINTKI("monitor sense=%x, mode %d\n",
2626 sense, mac_map_monitor_sense(sense));
2627 }
2628 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2629 default_vmode = VMODE_640_480_60;
2630 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2631 default_cmode = CMODE_8;
2632 if (!mac_vmode_to_var(default_vmode, default_cmode,
2633 &var))
2634 has_var = 1;
2635 }
2636 }
2637
2638 #endif /* !CONFIG_PPC */
2639
2640 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2641 if (!atyfb_get_timings_from_lcd(par, &var))
2642 has_var = 1;
2643 #endif
2644
2645 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2646 has_var = 1;
2647
2648 if (!has_var)
2649 var = default_var;
2650
2651 if (noaccel)
2652 var.accel_flags &= ~FB_ACCELF_TEXT;
2653 else
2654 var.accel_flags |= FB_ACCELF_TEXT;
2655
2656 if (comp_sync != -1) {
2657 if (!comp_sync)
2658 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2659 else
2660 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2661 }
2662
2663 if (var.yres == var.yres_virtual) {
2664 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2665 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2666 if (var.yres_virtual < var.yres)
2667 var.yres_virtual = var.yres;
2668 }
2669
2670 if (atyfb_check_var(&var, info)) {
2671 PRINTKE("can't set default video mode\n");
2672 goto aty_init_exit;
2673 }
2674
2675 #ifdef __sparc__
2676 atyfb_save_palette(par, 0);
2677 #endif
2678
2679 #ifdef CONFIG_FB_ATY_CT
2680 if (!noaccel && M64_HAS(INTEGRATED))
2681 aty_init_cursor(info);
2682 #endif /* CONFIG_FB_ATY_CT */
2683 info->var = var;
2684
2685 fb_alloc_cmap(&info->cmap, 256, 0);
2686
2687 if (register_framebuffer(info) < 0)
2688 goto aty_init_exit;
2689
2690 fb_list = info;
2691
2692 PRINTKI("fb%d: %s frame buffer device on %s\n",
2693 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2694 return 0;
2695
2696 aty_init_exit:
2697 /* restore video mode */
2698 aty_set_crtc(par, &saved_crtc);
2699 par->pll_ops->set_pll(info, &saved_pll);
2700
2701 #ifdef CONFIG_MTRR
2702 if (par->mtrr_reg >= 0) {
2703 mtrr_del(par->mtrr_reg, 0, 0);
2704 par->mtrr_reg = -1;
2705 }
2706 if (par->mtrr_aper >= 0) {
2707 mtrr_del(par->mtrr_aper, 0, 0);
2708 par->mtrr_aper = -1;
2709 }
2710 #endif
2711 return -1;
2712 }
2713
2714 static void aty_resume_chip(struct fb_info *info)
2715 {
2716 struct atyfb_par *par = info->par;
2717
2718 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2719
2720 if (par->pll_ops->resume_pll)
2721 par->pll_ops->resume_pll(info, &par->pll);
2722
2723 if (par->aux_start)
2724 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2725 }
2726
2727 #ifdef CONFIG_ATARI
2728 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2729 {
2730 char *p;
2731 unsigned long vmembase, size, guiregbase;
2732
2733 PRINTKI("store_video_par() '%s' \n", video_str);
2734
2735 if (!(p = strsep(&video_str, ";")) || !*p)
2736 goto mach64_invalid;
2737 vmembase = simple_strtoul(p, NULL, 0);
2738 if (!(p = strsep(&video_str, ";")) || !*p)
2739 goto mach64_invalid;
2740 size = simple_strtoul(p, NULL, 0);
2741 if (!(p = strsep(&video_str, ";")) || !*p)
2742 goto mach64_invalid;
2743 guiregbase = simple_strtoul(p, NULL, 0);
2744
2745 phys_vmembase[m64_num] = vmembase;
2746 phys_size[m64_num] = size;
2747 phys_guiregbase[m64_num] = guiregbase;
2748 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2749 guiregbase);
2750 return 0;
2751
2752 mach64_invalid:
2753 phys_vmembase[m64_num] = 0;
2754 return -1;
2755 }
2756 #endif /* CONFIG_ATARI */
2757
2758 /*
2759 * Blank the display.
2760 */
2761
2762 static int atyfb_blank(int blank, struct fb_info *info)
2763 {
2764 struct atyfb_par *par = (struct atyfb_par *) info->par;
2765 u32 gen_cntl;
2766
2767 if (par->lock_blank || par->asleep)
2768 return 0;
2769
2770 #ifdef CONFIG_FB_ATY_BACKLIGHT
2771 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2772 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2773 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2774 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2775 pm &= ~PWR_BLON;
2776 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2777 }
2778 #endif
2779
2780 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2781 gen_cntl &= ~0x400004c;
2782 switch (blank) {
2783 case FB_BLANK_UNBLANK:
2784 break;
2785 case FB_BLANK_NORMAL:
2786 gen_cntl |= 0x4000040;
2787 break;
2788 case FB_BLANK_VSYNC_SUSPEND:
2789 gen_cntl |= 0x4000048;
2790 break;
2791 case FB_BLANK_HSYNC_SUSPEND:
2792 gen_cntl |= 0x4000044;
2793 break;
2794 case FB_BLANK_POWERDOWN:
2795 gen_cntl |= 0x400004c;
2796 break;
2797 }
2798 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2799
2800 #ifdef CONFIG_FB_ATY_BACKLIGHT
2801 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2802 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2803 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2804 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2805 pm |= PWR_BLON;
2806 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2807 }
2808 #endif
2809
2810 return 0;
2811 }
2812
2813 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2814 const struct atyfb_par *par)
2815 {
2816 aty_st_8(DAC_W_INDEX, regno, par);
2817 aty_st_8(DAC_DATA, red, par);
2818 aty_st_8(DAC_DATA, green, par);
2819 aty_st_8(DAC_DATA, blue, par);
2820 }
2821
2822 /*
2823 * Set a single color register. The values supplied are already
2824 * rounded down to the hardware's capabilities (according to the
2825 * entries in the var structure). Return != 0 for invalid regno.
2826 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2827 */
2828
2829 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2830 u_int transp, struct fb_info *info)
2831 {
2832 struct atyfb_par *par = (struct atyfb_par *) info->par;
2833 int i, depth;
2834 u32 *pal = info->pseudo_palette;
2835
2836 depth = info->var.bits_per_pixel;
2837 if (depth == 16)
2838 depth = (info->var.green.length == 5) ? 15 : 16;
2839
2840 if (par->asleep)
2841 return 0;
2842
2843 if (regno > 255 ||
2844 (depth == 16 && regno > 63) ||
2845 (depth == 15 && regno > 31))
2846 return 1;
2847
2848 red >>= 8;
2849 green >>= 8;
2850 blue >>= 8;
2851
2852 par->palette[regno].red = red;
2853 par->palette[regno].green = green;
2854 par->palette[regno].blue = blue;
2855
2856 if (regno < 16) {
2857 switch (depth) {
2858 case 15:
2859 pal[regno] = (regno << 10) | (regno << 5) | regno;
2860 break;
2861 case 16:
2862 pal[regno] = (regno << 11) | (regno << 5) | regno;
2863 break;
2864 case 24:
2865 pal[regno] = (regno << 16) | (regno << 8) | regno;
2866 break;
2867 case 32:
2868 i = (regno << 8) | regno;
2869 pal[regno] = (i << 16) | i;
2870 break;
2871 }
2872 }
2873
2874 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2875 if (M64_HAS(EXTRA_BRIGHT))
2876 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2877 aty_st_8(DAC_CNTL, i, par);
2878 aty_st_8(DAC_MASK, 0xff, par);
2879
2880 if (M64_HAS(INTEGRATED)) {
2881 if (depth == 16) {
2882 if (regno < 32)
2883 aty_st_pal(regno << 3, red,
2884 par->palette[regno<<1].green,
2885 blue, par);
2886 red = par->palette[regno>>1].red;
2887 blue = par->palette[regno>>1].blue;
2888 regno <<= 2;
2889 } else if (depth == 15) {
2890 regno <<= 3;
2891 for(i = 0; i < 8; i++) {
2892 aty_st_pal(regno + i, red, green, blue, par);
2893 }
2894 }
2895 }
2896 aty_st_pal(regno, red, green, blue, par);
2897
2898 return 0;
2899 }
2900
2901 #ifdef CONFIG_PCI
2902
2903 #ifdef __sparc__
2904
2905 extern void (*prom_palette) (int);
2906
2907 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2908 struct fb_info *info, unsigned long addr)
2909 {
2910 struct atyfb_par *par = info->par;
2911 struct device_node *dp;
2912 char prop[128];
2913 int node, len, i, j, ret;
2914 u32 mem, chip_id;
2915
2916 /* Do not attach when we have a serial console. */
2917 if (!con_is_present())
2918 return -ENXIO;
2919
2920 /*
2921 * Map memory-mapped registers.
2922 */
2923 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2924 info->fix.mmio_start = addr + 0x7ffc00UL;
2925
2926 /*
2927 * Map in big-endian aperture.
2928 */
2929 info->screen_base = (char *) (addr + 0x800000UL);
2930 info->fix.smem_start = addr + 0x800000UL;
2931
2932 /*
2933 * Figure mmap addresses from PCI config space.
2934 * Split Framebuffer in big- and little-endian halfs.
2935 */
2936 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2937 /* nothing */ ;
2938 j = i + 4;
2939
2940 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2941 if (!par->mmap_map) {
2942 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2943 return -ENOMEM;
2944 }
2945 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2946
2947 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2948 struct resource *rp = &pdev->resource[i];
2949 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2950 unsigned long base;
2951 u32 size, pbase;
2952
2953 base = rp->start;
2954
2955 io = (rp->flags & IORESOURCE_IO);
2956
2957 size = rp->end - base + 1;
2958
2959 pci_read_config_dword(pdev, breg, &pbase);
2960
2961 if (io)
2962 size &= ~1;
2963
2964 /*
2965 * Map the framebuffer a second time, this time without
2966 * the braindead _PAGE_IE setting. This is used by the
2967 * fixed Xserver, but we need to maintain the old mapping
2968 * to stay compatible with older ones...
2969 */
2970 if (base == addr) {
2971 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2972 par->mmap_map[j].poff = base & PAGE_MASK;
2973 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2974 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2975 par->mmap_map[j].prot_flag = _PAGE_E;
2976 j++;
2977 }
2978
2979 /*
2980 * Here comes the old framebuffer mapping with _PAGE_IE
2981 * set for the big endian half of the framebuffer...
2982 */
2983 if (base == addr) {
2984 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2985 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2986 par->mmap_map[j].size = 0x800000;
2987 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2988 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2989 size -= 0x800000;
2990 j++;
2991 }
2992
2993 par->mmap_map[j].voff = pbase & PAGE_MASK;
2994 par->mmap_map[j].poff = base & PAGE_MASK;
2995 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2996 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2997 par->mmap_map[j].prot_flag = _PAGE_E;
2998 j++;
2999 }
3000
3001 if((ret = correct_chipset(par)))
3002 return ret;
3003
3004 if (IS_XL(pdev->device)) {
3005 /*
3006 * Fix PROMs idea of MEM_CNTL settings...
3007 */
3008 mem = aty_ld_le32(MEM_CNTL, par);
3009 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3010 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3011 switch (mem & 0x0f) {
3012 case 3:
3013 mem = (mem & ~(0x0f)) | 2;
3014 break;
3015 case 7:
3016 mem = (mem & ~(0x0f)) | 3;
3017 break;
3018 case 9:
3019 mem = (mem & ~(0x0f)) | 4;
3020 break;
3021 case 11:
3022 mem = (mem & ~(0x0f)) | 5;
3023 break;
3024 default:
3025 break;
3026 }
3027 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3028 mem &= ~(0x00700000);
3029 }
3030 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3031 aty_st_le32(MEM_CNTL, mem, par);
3032 }
3033
3034 /*
3035 * If this is the console device, we will set default video
3036 * settings to what the PROM left us with.
3037 */
3038 node = prom_getchild(prom_root_node);
3039 node = prom_searchsiblings(node, "aliases");
3040 if (node) {
3041 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3042 if (len > 0) {
3043 prop[len] = '\0';
3044 node = prom_finddevice(prop);
3045 } else
3046 node = 0;
3047 }
3048
3049 dp = pci_device_to_OF_node(pdev);
3050 if (node == dp->node) {
3051 struct fb_var_screeninfo *var = &default_var;
3052 unsigned int N, P, Q, M, T, R;
3053 u32 v_total, h_total;
3054 struct crtc crtc;
3055 u8 pll_regs[16];
3056 u8 clock_cntl;
3057
3058 crtc.vxres = prom_getintdefault(node, "width", 1024);
3059 crtc.vyres = prom_getintdefault(node, "height", 768);
3060 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3061 var->xoffset = var->yoffset = 0;
3062 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3063 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3064 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3065 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3066 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3067 aty_crtc_to_var(&crtc, var);
3068
3069 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3070 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3071
3072 /*
3073 * Read the PLL to figure actual Refresh Rate.
3074 */
3075 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3076 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3077 for (i = 0; i < 16; i++)
3078 pll_regs[i] = aty_ld_pll_ct(i, par);
3079
3080 /*
3081 * PLL Reference Divider M:
3082 */
3083 M = pll_regs[2];
3084
3085 /*
3086 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3087 */
3088 N = pll_regs[7 + (clock_cntl & 3)];
3089
3090 /*
3091 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3092 */
3093 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3094
3095 /*
3096 * PLL Divider Q:
3097 */
3098 Q = N / P;
3099
3100 /*
3101 * Target Frequency:
3102 *
3103 * T * M
3104 * Q = -------
3105 * 2 * R
3106 *
3107 * where R is XTALIN (= 14318 or 29498 kHz).
3108 */
3109 if (IS_XL(pdev->device))
3110 R = 29498;
3111 else
3112 R = 14318;
3113
3114 T = 2 * Q * R / M;
3115
3116 default_var.pixclock = 1000000000 / T;
3117 }
3118
3119 return 0;
3120 }
3121
3122 #else /* __sparc__ */
3123
3124 #ifdef __i386__
3125 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3126 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3127 {
3128 u32 driv_inf_tab, sig;
3129 u16 lcd_ofs;
3130
3131 /* To support an LCD panel, we should know it's dimensions and
3132 * it's desired pixel clock.
3133 * There are two ways to do it:
3134 * - Check the startup video mode and calculate the panel
3135 * size from it. This is unreliable.
3136 * - Read it from the driver information table in the video BIOS.
3137 */
3138 /* Address of driver information table is at offset 0x78. */
3139 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3140
3141 /* Check for the driver information table signature. */
3142 sig = (*(u32 *)driv_inf_tab);
3143 if ((sig == 0x54504c24) || /* Rage LT pro */
3144 (sig == 0x544d5224) || /* Rage mobility */
3145 (sig == 0x54435824) || /* Rage XC */
3146 (sig == 0x544c5824)) { /* Rage XL */
3147 PRINTKI("BIOS contains driver information table.\n");
3148 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3149 par->lcd_table = 0;
3150 if (lcd_ofs != 0) {
3151 par->lcd_table = bios_base + lcd_ofs;
3152 }
3153 }
3154
3155 if (par->lcd_table != 0) {
3156 char model[24];
3157 char strbuf[16];
3158 char refresh_rates_buf[100];
3159 int id, tech, f, i, m, default_refresh_rate;
3160 char *txtcolour;
3161 char *txtmonitor;
3162 char *txtdual;
3163 char *txtformat;
3164 u16 width, height, panel_type, refresh_rates;
3165 u16 *lcdmodeptr;
3166 u32 format;
3167 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3168 /* The most important information is the panel size at
3169 * offset 25 and 27, but there's some other nice information
3170 * which we print to the screen.
3171 */
3172 id = *(u8 *)par->lcd_table;
3173 strncpy(model,(char *)par->lcd_table+1,24);
3174 model[23]=0;
3175
3176 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3177 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3178 panel_type = *(u16 *)(par->lcd_table+29);
3179 if (panel_type & 1)
3180 txtcolour = "colour";
3181 else
3182 txtcolour = "monochrome";
3183 if (panel_type & 2)
3184 txtdual = "dual (split) ";
3185 else
3186 txtdual = "";
3187 tech = (panel_type>>2) & 63;
3188 switch (tech) {
3189 case 0:
3190 txtmonitor = "passive matrix";
3191 break;
3192 case 1:
3193 txtmonitor = "active matrix";
3194 break;
3195 case 2:
3196 txtmonitor = "active addressed STN";
3197 break;
3198 case 3:
3199 txtmonitor = "EL";
3200 break;
3201 case 4:
3202 txtmonitor = "plasma";
3203 break;
3204 default:
3205 txtmonitor = "unknown";
3206 }
3207 format = *(u32 *)(par->lcd_table+57);
3208 if (tech == 0 || tech == 2) {
3209 switch (format & 7) {
3210 case 0:
3211 txtformat = "12 bit interface";
3212 break;
3213 case 1:
3214 txtformat = "16 bit interface";
3215 break;
3216 case 2:
3217 txtformat = "24 bit interface";
3218 break;
3219 default:
3220 txtformat = "unkown format";
3221 }
3222 } else {
3223 switch (format & 7) {
3224 case 0:
3225 txtformat = "8 colours";
3226 break;
3227 case 1:
3228 txtformat = "512 colours";
3229 break;
3230 case 2:
3231 txtformat = "4096 colours";
3232 break;
3233 case 4:
3234 txtformat = "262144 colours (LT mode)";
3235 break;
3236 case 5:
3237 txtformat = "16777216 colours";
3238 break;
3239 case 6:
3240 txtformat = "262144 colours (FDPI-2 mode)";
3241 break;
3242 default:
3243 txtformat = "unkown format";
3244 }
3245 }
3246 PRINTKI("%s%s %s monitor detected: %s\n",
3247 txtdual ,txtcolour, txtmonitor, model);
3248 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3249 id, width, height, txtformat);
3250 refresh_rates_buf[0] = 0;
3251 refresh_rates = *(u16 *)(par->lcd_table+62);
3252 m = 1;
3253 f = 0;
3254 for (i=0;i<16;i++) {
3255 if (refresh_rates & m) {
3256 if (f == 0) {
3257 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3258 f++;
3259 } else {
3260 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3261 }
3262 strcat(refresh_rates_buf,strbuf);
3263 }
3264 m = m << 1;
3265 }
3266 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3267 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3268 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3269 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3270 /* We now need to determine the crtc parameters for the
3271 * LCD monitor. This is tricky, because they are not stored
3272 * individually in the BIOS. Instead, the BIOS contains a
3273 * table of display modes that work for this monitor.
3274 *
3275 * The idea is that we search for a mode of the same dimensions
3276 * as the dimensions of the LCD monitor. Say our LCD monitor
3277 * is 800x600 pixels, we search for a 800x600 monitor.
3278 * The CRTC parameters we find here are the ones that we need
3279 * to use to simulate other resolutions on the LCD screen.
3280 */
3281 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3282 while (*lcdmodeptr != 0) {
3283 u32 modeptr;
3284 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3285 modeptr = bios_base + *lcdmodeptr;
3286
3287 mwidth = *((u16 *)(modeptr+0));
3288 mheight = *((u16 *)(modeptr+2));
3289
3290 if (mwidth == width && mheight == height) {
3291 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3292 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3293 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3294 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3295 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3296 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3297
3298 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3299 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3300 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3301 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3302
3303 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3304 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3305 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3306 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3307
3308 par->lcd_vtotal++;
3309 par->lcd_vdisp++;
3310 lcd_vsync_start++;
3311
3312 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3313 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3314 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3315 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3316 break;
3317 }
3318
3319 lcdmodeptr++;
3320 }
3321 if (*lcdmodeptr == 0) {
3322 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3323 /* To do: Switch to CRT if possible. */
3324 } else {
3325 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3326 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3327 par->lcd_hdisp,
3328 par->lcd_hdisp + par->lcd_right_margin,
3329 par->lcd_hdisp + par->lcd_right_margin
3330 + par->lcd_hsync_dly + par->lcd_hsync_len,
3331 par->lcd_htotal,
3332 par->lcd_vdisp,
3333 par->lcd_vdisp + par->lcd_lower_margin,
3334 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3335 par->lcd_vtotal);
3336 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3337 par->lcd_pixclock,
3338 par->lcd_hblank_len - (par->lcd_right_margin +
3339 par->lcd_hsync_dly + par->lcd_hsync_len),
3340 par->lcd_hdisp,
3341 par->lcd_right_margin,
3342 par->lcd_hsync_len,
3343 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3344 par->lcd_vdisp,
3345 par->lcd_lower_margin,
3346 par->lcd_vsync_len);
3347 }
3348 }
3349 }
3350 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3351
3352 static int __devinit init_from_bios(struct atyfb_par *par)
3353 {
3354 u32 bios_base, rom_addr;
3355 int ret;
3356
3357 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3358 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3359
3360 /* The BIOS starts with 0xaa55. */
3361 if (*((u16 *)bios_base) == 0xaa55) {
3362
3363 u8 *bios_ptr;
3364 u16 rom_table_offset, freq_table_offset;
3365 PLL_BLOCK_MACH64 pll_block;
3366
3367 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3368
3369 /* check for frequncy table */
3370 bios_ptr = (u8*)bios_base;
3371 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3372 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3373 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3374
3375 PRINTKI("BIOS frequency table:\n");
3376 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3377 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3378 pll_block.ref_freq, pll_block.ref_divider);
3379 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3380 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3381 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3382
3383 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3384 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3385 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3386 par->pll_limits.ref_div = pll_block.ref_divider;
3387 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3388 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3389 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3390 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3391 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3392 aty_init_lcd(par, bios_base);
3393 #endif
3394 ret = 0;
3395 } else {
3396 PRINTKE("no BIOS frequency table found, use parameters\n");
3397 ret = -ENXIO;
3398 }
3399 iounmap((void* __iomem )bios_base);
3400
3401 return ret;
3402 }
3403 #endif /* __i386__ */
3404
3405 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3406 {
3407 struct atyfb_par *par = info->par;
3408 u16 tmp;
3409 unsigned long raddr;
3410 struct resource *rrp;
3411 int ret = 0;
3412
3413 raddr = addr + 0x7ff000UL;
3414 rrp = &pdev->resource[2];
3415 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3416 par->aux_start = rrp->start;
3417 par->aux_size = rrp->end - rrp->start + 1;
3418 raddr = rrp->start;
3419 PRINTKI("using auxiliary register aperture\n");
3420 }
3421
3422 info->fix.mmio_start = raddr;
3423 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3424 if (par->ati_regbase == 0)
3425 return -ENOMEM;
3426
3427 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3428 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3429
3430 /*
3431 * Enable memory-space accesses using config-space
3432 * command register.
3433 */
3434 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3435 if (!(tmp & PCI_COMMAND_MEMORY)) {
3436 tmp |= PCI_COMMAND_MEMORY;
3437 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3438 }
3439 #ifdef __BIG_ENDIAN
3440 /* Use the big-endian aperture */
3441 addr += 0x800000;
3442 #endif
3443
3444 /* Map in frame buffer */
3445 info->fix.smem_start = addr;
3446 info->screen_base = ioremap(addr, 0x800000);
3447 if (info->screen_base == NULL) {
3448 ret = -ENOMEM;
3449 goto atyfb_setup_generic_fail;
3450 }
3451
3452 if((ret = correct_chipset(par)))
3453 goto atyfb_setup_generic_fail;
3454 #ifdef __i386__
3455 if((ret = init_from_bios(par)))
3456 goto atyfb_setup_generic_fail;
3457 #endif
3458 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3459 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3460 else
3461 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3462
3463 /* according to ATI, we should use clock 3 for acelerated mode */
3464 par->clk_wr_offset = 3;
3465
3466 return 0;
3467
3468 atyfb_setup_generic_fail:
3469 iounmap(par->ati_regbase);
3470 par->ati_regbase = NULL;
3471 if (info->screen_base) {
3472 iounmap(info->screen_base);
3473 info->screen_base = NULL;
3474 }
3475 return ret;
3476 }
3477
3478 #endif /* !__sparc__ */
3479
3480 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3481 {
3482 unsigned long addr, res_start, res_size;
3483 struct fb_info *info;
3484 struct resource *rp;
3485 struct atyfb_par *par;
3486 int i, rc = -ENOMEM;
3487
3488 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3489 if (pdev->device == aty_chips[i].pci_id)
3490 break;
3491
3492 if (i < 0)
3493 return -ENODEV;
3494
3495 /* Enable device in PCI config */
3496 if (pci_enable_device(pdev)) {
3497 PRINTKE("Cannot enable PCI device\n");
3498 return -ENXIO;
3499 }
3500
3501 /* Find which resource to use */
3502 rp = &pdev->resource[0];
3503 if (rp->flags & IORESOURCE_IO)
3504 rp = &pdev->resource[1];
3505 addr = rp->start;
3506 if (!addr)
3507 return -ENXIO;
3508
3509 /* Reserve space */
3510 res_start = rp->start;
3511 res_size = rp->end - rp->start + 1;
3512 if (!request_mem_region (res_start, res_size, "atyfb"))
3513 return -EBUSY;
3514
3515 /* Allocate framebuffer */
3516 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3517 if (!info) {
3518 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3519 return -ENOMEM;
3520 }
3521 par = info->par;
3522 info->fix = atyfb_fix;
3523 info->device = &pdev->dev;
3524 par->pci_id = aty_chips[i].pci_id;
3525 par->res_start = res_start;
3526 par->res_size = res_size;
3527 par->irq = pdev->irq;
3528 par->pdev = pdev;
3529
3530 /* Setup "info" structure */
3531 #ifdef __sparc__
3532 rc = atyfb_setup_sparc(pdev, info, addr);
3533 #else
3534 rc = atyfb_setup_generic(pdev, info, addr);
3535 #endif
3536 if (rc)
3537 goto err_release_mem;
3538
3539 pci_set_drvdata(pdev, info);
3540
3541 /* Init chip & register framebuffer */
3542 if (aty_init(info))
3543 goto err_release_io;
3544
3545 #ifdef __sparc__
3546 if (!prom_palette)
3547 prom_palette = atyfb_palette;
3548
3549 /*
3550 * Add /dev/fb mmap values.
3551 */
3552 par->mmap_map[0].voff = 0x8000000000000000UL;
3553 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3554 par->mmap_map[0].size = info->fix.smem_len;
3555 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3556 par->mmap_map[0].prot_flag = _PAGE_E;
3557 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3558 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3559 par->mmap_map[1].size = PAGE_SIZE;
3560 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3561 par->mmap_map[1].prot_flag = _PAGE_E;
3562 #endif /* __sparc__ */
3563
3564 return 0;
3565
3566 err_release_io:
3567 #ifdef __sparc__
3568 kfree(par->mmap_map);
3569 #else
3570 if (par->ati_regbase)
3571 iounmap(par->ati_regbase);
3572 if (info->screen_base)
3573 iounmap(info->screen_base);
3574 #endif
3575 err_release_mem:
3576 if (par->aux_start)
3577 release_mem_region(par->aux_start, par->aux_size);
3578
3579 release_mem_region(par->res_start, par->res_size);
3580 framebuffer_release(info);
3581
3582 return rc;
3583 }
3584
3585 #endif /* CONFIG_PCI */
3586
3587 #ifdef CONFIG_ATARI
3588
3589 static int __init atyfb_atari_probe(void)
3590 {
3591 struct atyfb_par *par;
3592 struct fb_info *info;
3593 int m64_num;
3594 u32 clock_r;
3595 int num_found = 0;
3596
3597 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3598 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3599 !phys_guiregbase[m64_num]) {
3600 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3601 continue;
3602 }
3603
3604 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3605 if (!info) {
3606 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3607 return -ENOMEM;
3608 }
3609 par = info->par;
3610
3611 info->fix = atyfb_fix;
3612
3613 par->irq = (unsigned int) -1; /* something invalid */
3614
3615 /*
3616 * Map the video memory (physical address given) to somewhere in the
3617 * kernel address space.
3618 */
3619 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3620 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3621 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3622 0xFC00ul;
3623 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3624
3625 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3626 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3627
3628 switch (clock_r & 0x003F) {
3629 case 0x12:
3630 par->clk_wr_offset = 3; /* */
3631 break;
3632 case 0x34:
3633 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3634 break;
3635 case 0x16:
3636 par->clk_wr_offset = 1; /* */
3637 break;
3638 case 0x38:
3639 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3640 break;
3641 }
3642
3643 /* Fake pci_id for correct_chipset() */
3644 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3645 case 0x00d7:
3646 par->pci_id = PCI_CHIP_MACH64GX;
3647 break;
3648 case 0x0057:
3649 par->pci_id = PCI_CHIP_MACH64CX;
3650 break;
3651 default:
3652 break;
3653 }
3654
3655 if (correct_chipset(par) || aty_init(info)) {
3656 iounmap(info->screen_base);
3657 iounmap(par->ati_regbase);
3658 framebuffer_release(info);
3659 } else {
3660 num_found++;
3661 }
3662 }
3663
3664 return num_found ? 0 : -ENXIO;
3665 }
3666
3667 #endif /* CONFIG_ATARI */
3668
3669 #ifdef CONFIG_PCI
3670
3671 static void __devexit atyfb_remove(struct fb_info *info)
3672 {
3673 struct atyfb_par *par = (struct atyfb_par *) info->par;
3674
3675 /* restore video mode */
3676 aty_set_crtc(par, &saved_crtc);
3677 par->pll_ops->set_pll(info, &saved_pll);
3678
3679 unregister_framebuffer(info);
3680
3681 #ifdef CONFIG_FB_ATY_BACKLIGHT
3682 if (M64_HAS(MOBIL_BUS))
3683 aty_bl_exit(info->bl_dev);
3684 #endif
3685
3686 #ifdef CONFIG_MTRR
3687 if (par->mtrr_reg >= 0) {
3688 mtrr_del(par->mtrr_reg, 0, 0);
3689 par->mtrr_reg = -1;
3690 }
3691 if (par->mtrr_aper >= 0) {
3692 mtrr_del(par->mtrr_aper, 0, 0);
3693 par->mtrr_aper = -1;
3694 }
3695 #endif
3696 #ifndef __sparc__
3697 if (par->ati_regbase)
3698 iounmap(par->ati_regbase);
3699 if (info->screen_base)
3700 iounmap(info->screen_base);
3701 #ifdef __BIG_ENDIAN
3702 if (info->sprite.addr)
3703 iounmap(info->sprite.addr);
3704 #endif
3705 #endif
3706 #ifdef __sparc__
3707 kfree(par->mmap_map);
3708 #endif
3709 if (par->aux_start)
3710 release_mem_region(par->aux_start, par->aux_size);
3711
3712 if (par->res_start)
3713 release_mem_region(par->res_start, par->res_size);
3714
3715 framebuffer_release(info);
3716 }
3717
3718
3719 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3720 {
3721 struct fb_info *info = pci_get_drvdata(pdev);
3722
3723 atyfb_remove(info);
3724 }
3725
3726 /*
3727 * This driver uses its own matching table. That will be more difficult
3728 * to fix, so for now, we just match against any ATI ID and let the
3729 * probe() function find out what's up. That also mean we don't have
3730 * a module ID table though.
3731 */
3732 static struct pci_device_id atyfb_pci_tbl[] = {
3733 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3734 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3735 { 0, }
3736 };
3737
3738 static struct pci_driver atyfb_driver = {
3739 .name = "atyfb",
3740 .id_table = atyfb_pci_tbl,
3741 .probe = atyfb_pci_probe,
3742 .remove = __devexit_p(atyfb_pci_remove),
3743 #ifdef CONFIG_PM
3744 .suspend = atyfb_pci_suspend,
3745 .resume = atyfb_pci_resume,
3746 #endif /* CONFIG_PM */
3747 };
3748
3749 #endif /* CONFIG_PCI */
3750
3751 #ifndef MODULE
3752 static int __init atyfb_setup(char *options)
3753 {
3754 char *this_opt;
3755
3756 if (!options || !*options)
3757 return 0;
3758
3759 while ((this_opt = strsep(&options, ",")) != NULL) {
3760 if (!strncmp(this_opt, "noaccel", 7)) {
3761 noaccel = 1;
3762 #ifdef CONFIG_MTRR
3763 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3764 nomtrr = 1;
3765 #endif
3766 } else if (!strncmp(this_opt, "vram:", 5))
3767 vram = simple_strtoul(this_opt + 5, NULL, 0);
3768 else if (!strncmp(this_opt, "pll:", 4))
3769 pll = simple_strtoul(this_opt + 4, NULL, 0);
3770 else if (!strncmp(this_opt, "mclk:", 5))
3771 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3772 else if (!strncmp(this_opt, "xclk:", 5))
3773 xclk = simple_strtoul(this_opt+5, NULL, 0);
3774 else if (!strncmp(this_opt, "comp_sync:", 10))
3775 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3776 else if (!strncmp(this_opt, "backlight:", 10))
3777 backlight = simple_strtoul(this_opt+10, NULL, 0);
3778 #ifdef CONFIG_PPC
3779 else if (!strncmp(this_opt, "vmode:", 6)) {
3780 unsigned int vmode =
3781 simple_strtoul(this_opt + 6, NULL, 0);
3782 if (vmode > 0 && vmode <= VMODE_MAX)
3783 default_vmode = vmode;
3784 } else if (!strncmp(this_opt, "cmode:", 6)) {
3785 unsigned int cmode =
3786 simple_strtoul(this_opt + 6, NULL, 0);
3787 switch (cmode) {
3788 case 0:
3789 case 8:
3790 default_cmode = CMODE_8;
3791 break;
3792 case 15:
3793 case 16:
3794 default_cmode = CMODE_16;
3795 break;
3796 case 24:
3797 case 32:
3798 default_cmode = CMODE_32;
3799 break;
3800 }
3801 }
3802 #endif
3803 #ifdef CONFIG_ATARI
3804 /*
3805 * Why do we need this silly Mach64 argument?
3806 * We are already here because of mach64= so its redundant.
3807 */
3808 else if (MACH_IS_ATARI
3809 && (!strncmp(this_opt, "Mach64:", 7))) {
3810 static unsigned char m64_num;
3811 static char mach64_str[80];
3812 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3813 if (!store_video_par(mach64_str, m64_num)) {
3814 m64_num++;
3815 mach64_count = m64_num;
3816 }
3817 }
3818 #endif
3819 else
3820 mode = this_opt;
3821 }
3822 return 0;
3823 }
3824 #endif /* MODULE */
3825
3826 static int __init atyfb_init(void)
3827 {
3828 int err1 = 1, err2 = 1;
3829 #ifndef MODULE
3830 char *option = NULL;
3831
3832 if (fb_get_options("atyfb", &option))
3833 return -ENODEV;
3834 atyfb_setup(option);
3835 #endif
3836
3837 #ifdef CONFIG_PCI
3838 err1 = pci_register_driver(&atyfb_driver);
3839 #endif
3840 #ifdef CONFIG_ATARI
3841 err2 = atyfb_atari_probe();
3842 #endif
3843
3844 return (err1 && err2) ? -ENODEV : 0;
3845 }
3846
3847 static void __exit atyfb_exit(void)
3848 {
3849 #ifdef CONFIG_PCI
3850 pci_unregister_driver(&atyfb_driver);
3851 #endif
3852 }
3853
3854 module_init(atyfb_init);
3855 module_exit(atyfb_exit);
3856
3857 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3858 MODULE_LICENSE("GPL");
3859 module_param(noaccel, bool, 0);
3860 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3861 module_param(vram, int, 0);
3862 MODULE_PARM_DESC(vram, "int: override size of video ram");
3863 module_param(pll, int, 0);
3864 MODULE_PARM_DESC(pll, "int: override video clock");
3865 module_param(mclk, int, 0);
3866 MODULE_PARM_DESC(mclk, "int: override memory clock");
3867 module_param(xclk, int, 0);
3868 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3869 module_param(comp_sync, int, 0);
3870 MODULE_PARM_DESC(comp_sync,
3871 "Set composite sync signal to low (0) or high (1)");
3872 module_param(mode, charp, 0);
3873 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3874 #ifdef CONFIG_MTRR
3875 module_param(nomtrr, bool, 0);
3876 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3877 #endif
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