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Linux-2.6.12-rc2
[mirror_ubuntu-artful-kernel.git] / drivers / video / cyber2000fb.c
1 /*
2 * linux/drivers/video/cyber2000fb.c
3 *
4 * Copyright (C) 1998-2002 Russell King
5 *
6 * MIPS and 50xx clock support
7 * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
8 *
9 * 32 bit support, text color and panning fixes for modes != 8 bit
10 * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
17 *
18 * Based on cyberfb.c.
19 *
20 * Note that we now use the new fbcon fix, var and cmap scheme. We do
21 * still have to check which console is the currently displayed one
22 * however, especially for the colourmap stuff.
23 *
24 * We also use the new hotplug PCI subsystem. I'm not sure if there
25 * are any such cards, but I'm erring on the side of caution. We don't
26 * want to go pop just because someone does have one.
27 *
28 * Note that this doesn't work fully in the case of multiple CyberPro
29 * cards with grabbers. We currently can only attach to the first
30 * CyberPro card found.
31 *
32 * When we're in truecolour mode, we power down the LUT RAM as a power
33 * saving feature. Also, when we enter any of the powersaving modes
34 * (except soft blanking) we power down the RAMDACs. This saves about
35 * 1W, which is roughly 8% of the power consumption of a NetWinder
36 * (which, incidentally, is about the same saving as a 2.5in hard disk
37 * entering standby mode.)
38 */
39 #include <linux/config.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/errno.h>
43 #include <linux/string.h>
44 #include <linux/mm.h>
45 #include <linux/tty.h>
46 #include <linux/slab.h>
47 #include <linux/delay.h>
48 #include <linux/fb.h>
49 #include <linux/pci.h>
50 #include <linux/init.h>
51
52 #include <asm/io.h>
53 #include <asm/irq.h>
54 #include <asm/pgtable.h>
55 #include <asm/system.h>
56 #include <asm/uaccess.h>
57
58 #ifdef __arm__
59 #include <asm/mach-types.h>
60 #endif
61
62 #include "cyber2000fb.h"
63
64 struct cfb_info {
65 struct fb_info fb;
66 struct display_switch *dispsw;
67 struct display *display;
68 struct pci_dev *dev;
69 unsigned char __iomem *region;
70 unsigned char __iomem *regs;
71 u_int id;
72 int func_use_count;
73 u_long ref_ps;
74
75 /*
76 * Clock divisors
77 */
78 u_int divisors[4];
79
80 struct {
81 u8 red, green, blue;
82 } palette[NR_PALETTE];
83
84 u_char mem_ctl1;
85 u_char mem_ctl2;
86 u_char mclk_mult;
87 u_char mclk_div;
88 /*
89 * RAMDAC control register is both of these or'ed together
90 */
91 u_char ramdac_ctrl;
92 u_char ramdac_powerdown;
93 };
94
95 static char *default_font = "Acorn8x8";
96 module_param(default_font, charp, 0);
97 MODULE_PARM_DESC(default_font, "Default font name");
98
99 /*
100 * Our access methods.
101 */
102 #define cyber2000fb_writel(val,reg,cfb) writel(val, (cfb)->regs + (reg))
103 #define cyber2000fb_writew(val,reg,cfb) writew(val, (cfb)->regs + (reg))
104 #define cyber2000fb_writeb(val,reg,cfb) writeb(val, (cfb)->regs + (reg))
105
106 #define cyber2000fb_readb(reg,cfb) readb((cfb)->regs + (reg))
107
108 static inline void
109 cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
110 {
111 cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
112 }
113
114 static inline void
115 cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
116 {
117 cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
118 }
119
120 static inline unsigned int
121 cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
122 {
123 cyber2000fb_writeb(reg, 0x3ce, cfb);
124 return cyber2000fb_readb(0x3cf, cfb);
125 }
126
127 static inline void
128 cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
129 {
130 cyber2000fb_readb(0x3da, cfb);
131 cyber2000fb_writeb(reg, 0x3c0, cfb);
132 cyber2000fb_readb(0x3c1, cfb);
133 cyber2000fb_writeb(val, 0x3c0, cfb);
134 }
135
136 static inline void
137 cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
138 {
139 cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
140 }
141
142 /* -------------------- Hardware specific routines ------------------------- */
143
144 /*
145 * Hardware Cyber2000 Acceleration
146 */
147 static void
148 cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
149 {
150 struct cfb_info *cfb = (struct cfb_info *)info;
151 unsigned long dst, col;
152
153 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
154 cfb_fillrect(info, rect);
155 return;
156 }
157
158 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
159 cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
160 cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
161
162 col = rect->color;
163 if (cfb->fb.var.bits_per_pixel > 8)
164 col = ((u32 *)cfb->fb.pseudo_palette)[col];
165 cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
166
167 dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
168 if (cfb->fb.var.bits_per_pixel == 24) {
169 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
170 dst *= 3;
171 }
172
173 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
174 cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
175 cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
176 cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
177 }
178
179 static void
180 cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
181 {
182 struct cfb_info *cfb = (struct cfb_info *)info;
183 unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
184 unsigned long src, dst;
185
186 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
187 cfb_copyarea(info, region);
188 return;
189 }
190
191 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
192 cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
193 cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
194
195 src = region->sx + region->sy * cfb->fb.var.xres_virtual;
196 dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
197
198 if (region->sx < region->dx) {
199 src += region->width - 1;
200 dst += region->width - 1;
201 cmd |= CO_CMD_L_INC_LEFT;
202 }
203
204 if (region->sy < region->dy) {
205 src += (region->height - 1) * cfb->fb.var.xres_virtual;
206 dst += (region->height - 1) * cfb->fb.var.xres_virtual;
207 cmd |= CO_CMD_L_INC_UP;
208 }
209
210 if (cfb->fb.var.bits_per_pixel == 24) {
211 cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
212 src *= 3;
213 dst *= 3;
214 }
215 cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
216 cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
217 cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
218 cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
219 cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
220 CO_REG_CMD_H, cfb);
221 }
222
223 static void
224 cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image)
225 {
226 // struct cfb_info *cfb = (struct cfb_info *)info;
227
228 // if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
229 cfb_imageblit(info, image);
230 return;
231 // }
232 }
233
234 static int cyber2000fb_sync(struct fb_info *info)
235 {
236 struct cfb_info *cfb = (struct cfb_info *)info;
237 int count = 100000;
238
239 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
240 return 0;
241
242 while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
243 if (!count--) {
244 debug_printf("accel_wait timed out\n");
245 cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
246 break;
247 }
248 udelay(1);
249 }
250 return 0;
251 }
252
253 /*
254 * ===========================================================================
255 */
256
257 static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
258 {
259 u_int mask = (1 << bf->length) - 1;
260
261 return (val >> (16 - bf->length) & mask) << bf->offset;
262 }
263
264 /*
265 * Set a single color register. Return != 0 for invalid regno.
266 */
267 static int
268 cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
269 u_int transp, struct fb_info *info)
270 {
271 struct cfb_info *cfb = (struct cfb_info *)info;
272 struct fb_var_screeninfo *var = &cfb->fb.var;
273 u32 pseudo_val;
274 int ret = 1;
275
276 switch (cfb->fb.fix.visual) {
277 default:
278 return 1;
279
280 /*
281 * Pseudocolour:
282 * 8 8
283 * pixel --/--+--/--> red lut --> red dac
284 * | 8
285 * +--/--> green lut --> green dac
286 * | 8
287 * +--/--> blue lut --> blue dac
288 */
289 case FB_VISUAL_PSEUDOCOLOR:
290 if (regno >= NR_PALETTE)
291 return 1;
292
293 red >>= 8;
294 green >>= 8;
295 blue >>= 8;
296
297 cfb->palette[regno].red = red;
298 cfb->palette[regno].green = green;
299 cfb->palette[regno].blue = blue;
300
301 cyber2000fb_writeb(regno, 0x3c8, cfb);
302 cyber2000fb_writeb(red, 0x3c9, cfb);
303 cyber2000fb_writeb(green, 0x3c9, cfb);
304 cyber2000fb_writeb(blue, 0x3c9, cfb);
305 return 0;
306
307 /*
308 * Direct colour:
309 * n rl
310 * pixel --/--+--/--> red lut --> red dac
311 * | gl
312 * +--/--> green lut --> green dac
313 * | bl
314 * +--/--> blue lut --> blue dac
315 * n = bpp, rl = red length, gl = green length, bl = blue length
316 */
317 case FB_VISUAL_DIRECTCOLOR:
318 red >>= 8;
319 green >>= 8;
320 blue >>= 8;
321
322 if (var->green.length == 6 && regno < 64) {
323 cfb->palette[regno << 2].green = green;
324
325 /*
326 * The 6 bits of the green component are applied
327 * to the high 6 bits of the LUT.
328 */
329 cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
330 cyber2000fb_writeb(cfb->palette[regno >> 1].red, 0x3c9, cfb);
331 cyber2000fb_writeb(green, 0x3c9, cfb);
332 cyber2000fb_writeb(cfb->palette[regno >> 1].blue, 0x3c9, cfb);
333
334 green = cfb->palette[regno << 3].green;
335
336 ret = 0;
337 }
338
339 if (var->green.length >= 5 && regno < 32) {
340 cfb->palette[regno << 3].red = red;
341 cfb->palette[regno << 3].green = green;
342 cfb->palette[regno << 3].blue = blue;
343
344 /*
345 * The 5 bits of each colour component are
346 * applied to the high 5 bits of the LUT.
347 */
348 cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
349 cyber2000fb_writeb(red, 0x3c9, cfb);
350 cyber2000fb_writeb(green, 0x3c9, cfb);
351 cyber2000fb_writeb(blue, 0x3c9, cfb);
352 ret = 0;
353 }
354
355 if (var->green.length == 4 && regno < 16) {
356 cfb->palette[regno << 4].red = red;
357 cfb->palette[regno << 4].green = green;
358 cfb->palette[regno << 4].blue = blue;
359
360 /*
361 * The 5 bits of each colour component are
362 * applied to the high 5 bits of the LUT.
363 */
364 cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
365 cyber2000fb_writeb(red, 0x3c9, cfb);
366 cyber2000fb_writeb(green, 0x3c9, cfb);
367 cyber2000fb_writeb(blue, 0x3c9, cfb);
368 ret = 0;
369 }
370
371 /*
372 * Since this is only used for the first 16 colours, we
373 * don't have to care about overflowing for regno >= 32
374 */
375 pseudo_val = regno << var->red.offset |
376 regno << var->green.offset |
377 regno << var->blue.offset;
378 break;
379
380 /*
381 * True colour:
382 * n rl
383 * pixel --/--+--/--> red dac
384 * | gl
385 * +--/--> green dac
386 * | bl
387 * +--/--> blue dac
388 * n = bpp, rl = red length, gl = green length, bl = blue length
389 */
390 case FB_VISUAL_TRUECOLOR:
391 pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
392 pseudo_val |= convert_bitfield(red, &var->red);
393 pseudo_val |= convert_bitfield(green, &var->green);
394 pseudo_val |= convert_bitfield(blue, &var->blue);
395 break;
396 }
397
398 /*
399 * Now set our pseudo palette for the CFB16/24/32 drivers.
400 */
401 if (regno < 16)
402 ((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
403
404 return ret;
405 }
406
407 struct par_info {
408 /*
409 * Hardware
410 */
411 u_char clock_mult;
412 u_char clock_div;
413 u_char extseqmisc;
414 u_char co_pixfmt;
415 u_char crtc_ofl;
416 u_char crtc[19];
417 u_int width;
418 u_int pitch;
419 u_int fetch;
420
421 /*
422 * Other
423 */
424 u_char ramdac;
425 };
426
427 static const u_char crtc_idx[] = {
428 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
429 0x08, 0x09,
430 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
431 };
432
433 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
434 {
435 unsigned int i;
436 unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
437
438 cyber2000fb_writeb(0x56, 0x3ce, cfb);
439 i = cyber2000fb_readb(0x3cf, cfb);
440 cyber2000fb_writeb(i | 4, 0x3cf, cfb);
441 cyber2000fb_writeb(val, 0x3c6, cfb);
442 cyber2000fb_writeb(i, 0x3cf, cfb);
443 }
444
445 static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
446 {
447 u_int i;
448
449 /*
450 * Blank palette
451 */
452 for (i = 0; i < NR_PALETTE; i++) {
453 cyber2000fb_writeb(i, 0x3c8, cfb);
454 cyber2000fb_writeb(0, 0x3c9, cfb);
455 cyber2000fb_writeb(0, 0x3c9, cfb);
456 cyber2000fb_writeb(0, 0x3c9, cfb);
457 }
458
459 cyber2000fb_writeb(0xef, 0x3c2, cfb);
460 cyber2000_crtcw(0x11, 0x0b, cfb);
461 cyber2000_attrw(0x11, 0x00, cfb);
462
463 cyber2000_seqw(0x00, 0x01, cfb);
464 cyber2000_seqw(0x01, 0x01, cfb);
465 cyber2000_seqw(0x02, 0x0f, cfb);
466 cyber2000_seqw(0x03, 0x00, cfb);
467 cyber2000_seqw(0x04, 0x0e, cfb);
468 cyber2000_seqw(0x00, 0x03, cfb);
469
470 for (i = 0; i < sizeof(crtc_idx); i++)
471 cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
472
473 for (i = 0x0a; i < 0x10; i++)
474 cyber2000_crtcw(i, 0, cfb);
475
476 cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
477 cyber2000_grphw(0x00, 0x00, cfb);
478 cyber2000_grphw(0x01, 0x00, cfb);
479 cyber2000_grphw(0x02, 0x00, cfb);
480 cyber2000_grphw(0x03, 0x00, cfb);
481 cyber2000_grphw(0x04, 0x00, cfb);
482 cyber2000_grphw(0x05, 0x60, cfb);
483 cyber2000_grphw(0x06, 0x05, cfb);
484 cyber2000_grphw(0x07, 0x0f, cfb);
485 cyber2000_grphw(0x08, 0xff, cfb);
486
487 /* Attribute controller registers */
488 for (i = 0; i < 16; i++)
489 cyber2000_attrw(i, i, cfb);
490
491 cyber2000_attrw(0x10, 0x01, cfb);
492 cyber2000_attrw(0x11, 0x00, cfb);
493 cyber2000_attrw(0x12, 0x0f, cfb);
494 cyber2000_attrw(0x13, 0x00, cfb);
495 cyber2000_attrw(0x14, 0x00, cfb);
496
497 /* PLL registers */
498 cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
499 cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb);
500 cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
501 cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb);
502 cyber2000_grphw(0x90, 0x01, cfb);
503 cyber2000_grphw(0xb9, 0x80, cfb);
504 cyber2000_grphw(0xb9, 0x00, cfb);
505
506 cfb->ramdac_ctrl = hw->ramdac;
507 cyber2000fb_write_ramdac_ctrl(cfb);
508
509 cyber2000fb_writeb(0x20, 0x3c0, cfb);
510 cyber2000fb_writeb(0xff, 0x3c6, cfb);
511
512 cyber2000_grphw(0x14, hw->fetch, cfb);
513 cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
514 ((hw->pitch >> 4) & 0x30), cfb);
515 cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
516
517 /*
518 * Set up accelerator registers
519 */
520 cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb);
521 cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb);
522 cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
523 }
524
525 static inline int
526 cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
527 {
528 u_int base = var->yoffset * var->xres_virtual + var->xoffset;
529
530 base *= var->bits_per_pixel;
531
532 /*
533 * Convert to bytes and shift two extra bits because DAC
534 * can only start on 4 byte aligned data.
535 */
536 base >>= 5;
537
538 if (base >= 1 << 20)
539 return -EINVAL;
540
541 cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
542 cyber2000_crtcw(0x0c, base >> 8, cfb);
543 cyber2000_crtcw(0x0d, base, cfb);
544
545 return 0;
546 }
547
548 static int
549 cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
550 struct fb_var_screeninfo *var)
551 {
552 u_int Htotal, Hblankend, Hsyncend;
553 u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
554 #define BIT(v,b1,m,b2) (((v >> b1) & m) << b2)
555
556 hw->crtc[13] = hw->pitch;
557 hw->crtc[17] = 0xe3;
558 hw->crtc[14] = 0;
559 hw->crtc[8] = 0;
560
561 Htotal = var->xres + var->right_margin +
562 var->hsync_len + var->left_margin;
563
564 if (Htotal > 2080)
565 return -EINVAL;
566
567 hw->crtc[0] = (Htotal >> 3) - 5;
568 hw->crtc[1] = (var->xres >> 3) - 1;
569 hw->crtc[2] = var->xres >> 3;
570 hw->crtc[4] = (var->xres + var->right_margin) >> 3;
571
572 Hblankend = (Htotal - 4*8) >> 3;
573
574 hw->crtc[3] = BIT(Hblankend, 0, 0x1f, 0) |
575 BIT(1, 0, 0x01, 7);
576
577 Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3;
578
579 hw->crtc[5] = BIT(Hsyncend, 0, 0x1f, 0) |
580 BIT(Hblankend, 5, 0x01, 7);
581
582 Vdispend = var->yres - 1;
583 Vsyncstart = var->yres + var->lower_margin;
584 Vsyncend = var->yres + var->lower_margin + var->vsync_len;
585 Vtotal = var->yres + var->lower_margin + var->vsync_len +
586 var->upper_margin - 2;
587
588 if (Vtotal > 2047)
589 return -EINVAL;
590
591 Vblankstart = var->yres + 6;
592 Vblankend = Vtotal - 10;
593
594 hw->crtc[6] = Vtotal;
595 hw->crtc[7] = BIT(Vtotal, 8, 0x01, 0) |
596 BIT(Vdispend, 8, 0x01, 1) |
597 BIT(Vsyncstart, 8, 0x01, 2) |
598 BIT(Vblankstart,8, 0x01, 3) |
599 BIT(1, 0, 0x01, 4) |
600 BIT(Vtotal, 9, 0x01, 5) |
601 BIT(Vdispend, 9, 0x01, 6) |
602 BIT(Vsyncstart, 9, 0x01, 7);
603 hw->crtc[9] = BIT(0, 0, 0x1f, 0) |
604 BIT(Vblankstart,9, 0x01, 5) |
605 BIT(1, 0, 0x01, 6);
606 hw->crtc[10] = Vsyncstart;
607 hw->crtc[11] = BIT(Vsyncend, 0, 0x0f, 0) |
608 BIT(1, 0, 0x01, 7);
609 hw->crtc[12] = Vdispend;
610 hw->crtc[15] = Vblankstart;
611 hw->crtc[16] = Vblankend;
612 hw->crtc[18] = 0xff;
613
614 /*
615 * overflow - graphics reg 0x11
616 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
617 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
618 */
619 hw->crtc_ofl =
620 BIT(Vtotal, 10, 0x01, 0) |
621 BIT(Vdispend, 10, 0x01, 1) |
622 BIT(Vsyncstart, 10, 0x01, 2) |
623 BIT(Vblankstart,10, 0x01, 3) |
624 EXT_CRT_VRTOFL_LINECOMP10;
625
626 /* woody: set the interlaced bit... */
627 /* FIXME: what about doublescan? */
628 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
629 hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
630
631 return 0;
632 }
633
634 /*
635 * The following was discovered by a good monitor, bit twiddling, theorising
636 * and but mostly luck. Strangely, it looks like everyone elses' PLL!
637 *
638 * Clock registers:
639 * fclock = fpll / div2
640 * fpll = fref * mult / div1
641 * where:
642 * fref = 14.318MHz (69842ps)
643 * mult = reg0xb0.7:0
644 * div1 = (reg0xb1.5:0 + 1)
645 * div2 = 2^(reg0xb1.7:6)
646 * fpll should be between 115 and 260 MHz
647 * (8696ps and 3846ps)
648 */
649 static int
650 cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
651 struct fb_var_screeninfo *var)
652 {
653 u_long pll_ps = var->pixclock;
654 const u_long ref_ps = cfb->ref_ps;
655 u_int div2, t_div1, best_div1, best_mult;
656 int best_diff;
657 int vco;
658
659 /*
660 * Step 1:
661 * find div2 such that 115MHz < fpll < 260MHz
662 * and 0 <= div2 < 4
663 */
664 for (div2 = 0; div2 < 4; div2++) {
665 u_long new_pll;
666
667 new_pll = pll_ps / cfb->divisors[div2];
668 if (8696 > new_pll && new_pll > 3846) {
669 pll_ps = new_pll;
670 break;
671 }
672 }
673
674 if (div2 == 4)
675 return -EINVAL;
676
677 /*
678 * Step 2:
679 * Given pll_ps and ref_ps, find:
680 * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
681 * where { 1 < best_div1 < 32, 1 < best_mult < 256 }
682 * pll_ps_calc = best_div1 / (ref_ps * best_mult)
683 */
684 best_diff = 0x7fffffff;
685 best_mult = 32;
686 best_div1 = 255;
687 for (t_div1 = 32; t_div1 > 1; t_div1 -= 1) {
688 u_int rr, t_mult, t_pll_ps;
689 int diff;
690
691 /*
692 * Find the multiplier for this divisor
693 */
694 rr = ref_ps * t_div1;
695 t_mult = (rr + pll_ps / 2) / pll_ps;
696
697 /*
698 * Is the multiplier within the correct range?
699 */
700 if (t_mult > 256 || t_mult < 2)
701 continue;
702
703 /*
704 * Calculate the actual clock period from this multiplier
705 * and divisor, and estimate the error.
706 */
707 t_pll_ps = (rr + t_mult / 2) / t_mult;
708 diff = pll_ps - t_pll_ps;
709 if (diff < 0)
710 diff = -diff;
711
712 if (diff < best_diff) {
713 best_diff = diff;
714 best_mult = t_mult;
715 best_div1 = t_div1;
716 }
717
718 /*
719 * If we hit an exact value, there is no point in continuing.
720 */
721 if (diff == 0)
722 break;
723 }
724
725 /*
726 * Step 3:
727 * combine values
728 */
729 hw->clock_mult = best_mult - 1;
730 hw->clock_div = div2 << 6 | (best_div1 - 1);
731
732 vco = ref_ps * best_div1 / best_mult;
733 if ((ref_ps == 40690) && (vco < 5556))
734 /* Set VFSEL when VCO > 180MHz (5.556 ps). */
735 hw->clock_div |= EXT_DCLK_DIV_VFSEL;
736
737 return 0;
738 }
739
740 /*
741 * Set the User Defined Part of the Display
742 */
743 static int
744 cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
745 {
746 struct cfb_info *cfb = (struct cfb_info *)info;
747 struct par_info hw;
748 unsigned int mem;
749 int err;
750
751 var->transp.msb_right = 0;
752 var->red.msb_right = 0;
753 var->green.msb_right = 0;
754 var->blue.msb_right = 0;
755
756 switch (var->bits_per_pixel) {
757 case 8: /* PSEUDOCOLOUR, 256 */
758 var->transp.offset = 0;
759 var->transp.length = 0;
760 var->red.offset = 0;
761 var->red.length = 8;
762 var->green.offset = 0;
763 var->green.length = 8;
764 var->blue.offset = 0;
765 var->blue.length = 8;
766 break;
767
768 case 16:/* DIRECTCOLOUR, 64k or 32k */
769 switch (var->green.length) {
770 case 6: /* RGB565, 64k */
771 var->transp.offset = 0;
772 var->transp.length = 0;
773 var->red.offset = 11;
774 var->red.length = 5;
775 var->green.offset = 5;
776 var->green.length = 6;
777 var->blue.offset = 0;
778 var->blue.length = 5;
779 break;
780
781 default:
782 case 5: /* RGB555, 32k */
783 var->transp.offset = 0;
784 var->transp.length = 0;
785 var->red.offset = 10;
786 var->red.length = 5;
787 var->green.offset = 5;
788 var->green.length = 5;
789 var->blue.offset = 0;
790 var->blue.length = 5;
791 break;
792
793 case 4: /* RGB444, 4k + transparency? */
794 var->transp.offset = 12;
795 var->transp.length = 4;
796 var->red.offset = 8;
797 var->red.length = 4;
798 var->green.offset = 4;
799 var->green.length = 4;
800 var->blue.offset = 0;
801 var->blue.length = 4;
802 break;
803 }
804 break;
805
806 case 24:/* TRUECOLOUR, 16m */
807 var->transp.offset = 0;
808 var->transp.length = 0;
809 var->red.offset = 16;
810 var->red.length = 8;
811 var->green.offset = 8;
812 var->green.length = 8;
813 var->blue.offset = 0;
814 var->blue.length = 8;
815 break;
816
817 case 32:/* TRUECOLOUR, 16m */
818 var->transp.offset = 24;
819 var->transp.length = 8;
820 var->red.offset = 16;
821 var->red.length = 8;
822 var->green.offset = 8;
823 var->green.length = 8;
824 var->blue.offset = 0;
825 var->blue.length = 8;
826 break;
827
828 default:
829 return -EINVAL;
830 }
831
832 mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
833 if (mem > cfb->fb.fix.smem_len)
834 var->yres_virtual = cfb->fb.fix.smem_len * 8 /
835 (var->bits_per_pixel * var->xres_virtual);
836
837 if (var->yres > var->yres_virtual)
838 var->yres = var->yres_virtual;
839 if (var->xres > var->xres_virtual)
840 var->xres = var->xres_virtual;
841
842 err = cyber2000fb_decode_clock(&hw, cfb, var);
843 if (err)
844 return err;
845
846 err = cyber2000fb_decode_crtc(&hw, cfb, var);
847 if (err)
848 return err;
849
850 return 0;
851 }
852
853 static int cyber2000fb_set_par(struct fb_info *info)
854 {
855 struct cfb_info *cfb = (struct cfb_info *)info;
856 struct fb_var_screeninfo *var = &cfb->fb.var;
857 struct par_info hw;
858 unsigned int mem;
859
860 hw.width = var->xres_virtual;
861 hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
862
863 switch (var->bits_per_pixel) {
864 case 8:
865 hw.co_pixfmt = CO_PIXFMT_8BPP;
866 hw.pitch = hw.width >> 3;
867 hw.extseqmisc = EXT_SEQ_MISC_8;
868 break;
869
870 case 16:
871 hw.co_pixfmt = CO_PIXFMT_16BPP;
872 hw.pitch = hw.width >> 2;
873
874 switch (var->green.length) {
875 case 6: /* RGB565, 64k */
876 hw.extseqmisc = EXT_SEQ_MISC_16_RGB565;
877 break;
878 case 5: /* RGB555, 32k */
879 hw.extseqmisc = EXT_SEQ_MISC_16_RGB555;
880 break;
881 case 4: /* RGB444, 4k + transparency? */
882 hw.extseqmisc = EXT_SEQ_MISC_16_RGB444;
883 break;
884 default:
885 BUG();
886 }
887 case 24:/* TRUECOLOUR, 16m */
888 hw.co_pixfmt = CO_PIXFMT_24BPP;
889 hw.width *= 3;
890 hw.pitch = hw.width >> 3;
891 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
892 hw.extseqmisc = EXT_SEQ_MISC_24_RGB888;
893 break;
894
895 case 32:/* TRUECOLOUR, 16m */
896 hw.co_pixfmt = CO_PIXFMT_32BPP;
897 hw.pitch = hw.width >> 1;
898 hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
899 hw.extseqmisc = EXT_SEQ_MISC_32;
900 break;
901
902 default:
903 BUG();
904 }
905
906 /*
907 * Sigh, this is absolutely disgusting, but caused by
908 * the way the fbcon developers want to separate out
909 * the "checking" and the "setting" of the video mode.
910 *
911 * If the mode is not suitable for the hardware here,
912 * we can't prevent it being set by returning an error.
913 *
914 * In theory, since NetWinders contain just one VGA card,
915 * we should never end up hitting this problem.
916 */
917 BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
918 BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
919
920 hw.width -= 1;
921 hw.fetch = hw.pitch;
922 if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
923 hw.fetch <<= 1;
924 hw.fetch += 1;
925
926 cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
927
928 /*
929 * Same here - if the size of the video mode exceeds the
930 * available RAM, we can't prevent this mode being set.
931 *
932 * In theory, since NetWinders contain just one VGA card,
933 * we should never end up hitting this problem.
934 */
935 mem = cfb->fb.fix.line_length * var->yres_virtual;
936 BUG_ON(mem > cfb->fb.fix.smem_len);
937
938 /*
939 * 8bpp displays are always pseudo colour. 16bpp and above
940 * are direct colour or true colour, depending on whether
941 * the RAMDAC palettes are bypassed. (Direct colour has
942 * palettes, true colour does not.)
943 */
944 if (var->bits_per_pixel == 8)
945 cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
946 else if (hw.ramdac & RAMDAC_BYPASS)
947 cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
948 else
949 cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
950
951 cyber2000fb_set_timing(cfb, &hw);
952 cyber2000fb_update_start(cfb, var);
953
954 return 0;
955 }
956
957
958 /*
959 * Pan or Wrap the Display
960 */
961 static int
962 cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
963 {
964 struct cfb_info *cfb = (struct cfb_info *)info;
965
966 if (cyber2000fb_update_start(cfb, var))
967 return -EINVAL;
968
969 cfb->fb.var.xoffset = var->xoffset;
970 cfb->fb.var.yoffset = var->yoffset;
971
972 if (var->vmode & FB_VMODE_YWRAP) {
973 cfb->fb.var.vmode |= FB_VMODE_YWRAP;
974 } else {
975 cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
976 }
977
978 return 0;
979 }
980
981 /*
982 * (Un)Blank the display.
983 *
984 * Blank the screen if blank_mode != 0, else unblank. If
985 * blank == NULL then the caller blanks by setting the CLUT
986 * (Color Look Up Table) to all black. Return 0 if blanking
987 * succeeded, != 0 if un-/blanking failed due to e.g. a
988 * video mode which doesn't support it. Implements VESA
989 * suspend and powerdown modes on hardware that supports
990 * disabling hsync/vsync:
991 * blank_mode == 2: suspend vsync
992 * blank_mode == 3: suspend hsync
993 * blank_mode == 4: powerdown
994 *
995 * wms...Enable VESA DMPS compatible powerdown mode
996 * run "setterm -powersave powerdown" to take advantage
997 */
998 static int cyber2000fb_blank(int blank, struct fb_info *info)
999 {
1000 struct cfb_info *cfb = (struct cfb_info *)info;
1001 unsigned int sync = 0;
1002 int i;
1003
1004 switch (blank) {
1005 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
1006 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
1007 break;
1008 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
1009 sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
1010 break;
1011 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
1012 sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
1013 break;
1014 case FB_BLANK_NORMAL: /* soft blank */
1015 default: /* unblank */
1016 break;
1017 }
1018
1019 cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
1020
1021 if (blank <= 1) {
1022 /* turn on ramdacs */
1023 cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
1024 cyber2000fb_write_ramdac_ctrl(cfb);
1025 }
1026
1027 /*
1028 * Soft blank/unblank the display.
1029 */
1030 if (blank) { /* soft blank */
1031 for (i = 0; i < NR_PALETTE; i++) {
1032 cyber2000fb_writeb(i, 0x3c8, cfb);
1033 cyber2000fb_writeb(0, 0x3c9, cfb);
1034 cyber2000fb_writeb(0, 0x3c9, cfb);
1035 cyber2000fb_writeb(0, 0x3c9, cfb);
1036 }
1037 } else { /* unblank */
1038 for (i = 0; i < NR_PALETTE; i++) {
1039 cyber2000fb_writeb(i, 0x3c8, cfb);
1040 cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
1041 cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
1042 cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
1043 }
1044 }
1045
1046 if (blank >= 2) {
1047 /* turn off ramdacs */
1048 cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS | RAMDAC_RAMPWRDN;
1049 cyber2000fb_write_ramdac_ctrl(cfb);
1050 }
1051
1052 return 0;
1053 }
1054
1055 static struct fb_ops cyber2000fb_ops = {
1056 .owner = THIS_MODULE,
1057 .fb_check_var = cyber2000fb_check_var,
1058 .fb_set_par = cyber2000fb_set_par,
1059 .fb_setcolreg = cyber2000fb_setcolreg,
1060 .fb_blank = cyber2000fb_blank,
1061 .fb_pan_display = cyber2000fb_pan_display,
1062 .fb_fillrect = cyber2000fb_fillrect,
1063 .fb_copyarea = cyber2000fb_copyarea,
1064 .fb_imageblit = cyber2000fb_imageblit,
1065 .fb_cursor = soft_cursor,
1066 .fb_sync = cyber2000fb_sync,
1067 };
1068
1069 /*
1070 * This is the only "static" reference to the internal data structures
1071 * of this driver. It is here solely at the moment to support the other
1072 * CyberPro modules external to this driver.
1073 */
1074 static struct cfb_info *int_cfb_info;
1075
1076 /*
1077 * Enable access to the extended registers
1078 */
1079 void cyber2000fb_enable_extregs(struct cfb_info *cfb)
1080 {
1081 cfb->func_use_count += 1;
1082
1083 if (cfb->func_use_count == 1) {
1084 int old;
1085
1086 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1087 old |= EXT_FUNC_CTL_EXTREGENBL;
1088 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1089 }
1090 }
1091
1092 /*
1093 * Disable access to the extended registers
1094 */
1095 void cyber2000fb_disable_extregs(struct cfb_info *cfb)
1096 {
1097 if (cfb->func_use_count == 1) {
1098 int old;
1099
1100 old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
1101 old &= ~EXT_FUNC_CTL_EXTREGENBL;
1102 cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
1103 }
1104
1105 if (cfb->func_use_count == 0)
1106 printk(KERN_ERR "disable_extregs: count = 0\n");
1107 else
1108 cfb->func_use_count -= 1;
1109 }
1110
1111 void cyber2000fb_get_fb_var(struct cfb_info *cfb, struct fb_var_screeninfo *var)
1112 {
1113 memcpy(var, &cfb->fb.var, sizeof(struct fb_var_screeninfo));
1114 }
1115
1116 /*
1117 * Attach a capture/tv driver to the core CyberX0X0 driver.
1118 */
1119 int cyber2000fb_attach(struct cyberpro_info *info, int idx)
1120 {
1121 if (int_cfb_info != NULL) {
1122 info->dev = int_cfb_info->dev;
1123 info->regs = int_cfb_info->regs;
1124 info->fb = int_cfb_info->fb.screen_base;
1125 info->fb_size = int_cfb_info->fb.fix.smem_len;
1126 info->enable_extregs = cyber2000fb_enable_extregs;
1127 info->disable_extregs = cyber2000fb_disable_extregs;
1128 info->info = int_cfb_info;
1129
1130 strlcpy(info->dev_name, int_cfb_info->fb.fix.id, sizeof(info->dev_name));
1131 }
1132
1133 return int_cfb_info != NULL;
1134 }
1135
1136 /*
1137 * Detach a capture/tv driver from the core CyberX0X0 driver.
1138 */
1139 void cyber2000fb_detach(int idx)
1140 {
1141 }
1142
1143 EXPORT_SYMBOL(cyber2000fb_attach);
1144 EXPORT_SYMBOL(cyber2000fb_detach);
1145 EXPORT_SYMBOL(cyber2000fb_enable_extregs);
1146 EXPORT_SYMBOL(cyber2000fb_disable_extregs);
1147 EXPORT_SYMBOL(cyber2000fb_get_fb_var);
1148
1149 /*
1150 * These parameters give
1151 * 640x480, hsync 31.5kHz, vsync 60Hz
1152 */
1153 static struct fb_videomode __devinitdata cyber2000fb_default_mode = {
1154 .refresh = 60,
1155 .xres = 640,
1156 .yres = 480,
1157 .pixclock = 39722,
1158 .left_margin = 56,
1159 .right_margin = 16,
1160 .upper_margin = 34,
1161 .lower_margin = 9,
1162 .hsync_len = 88,
1163 .vsync_len = 2,
1164 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1165 .vmode = FB_VMODE_NONINTERLACED
1166 };
1167
1168 static char igs_regs[] = {
1169 EXT_CRT_IRQ, 0,
1170 EXT_CRT_TEST, 0,
1171 EXT_SYNC_CTL, 0,
1172 EXT_SEG_WRITE_PTR, 0,
1173 EXT_SEG_READ_PTR, 0,
1174 EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE |
1175 EXT_BIU_MISC_COP_ENABLE |
1176 EXT_BIU_MISC_COP_BFC,
1177 EXT_FUNC_CTL, 0,
1178 CURS_H_START, 0,
1179 CURS_H_START + 1, 0,
1180 CURS_H_PRESET, 0,
1181 CURS_V_START, 0,
1182 CURS_V_START + 1, 0,
1183 CURS_V_PRESET, 0,
1184 CURS_CTL, 0,
1185 EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT,
1186 EXT_OVERSCAN_RED, 0,
1187 EXT_OVERSCAN_GREEN, 0,
1188 EXT_OVERSCAN_BLUE, 0,
1189
1190 /* some of these are questionable when we have a BIOS */
1191 EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK |
1192 EXT_MEM_CTL0_RAS_1 |
1193 EXT_MEM_CTL0_MULTCAS,
1194 EXT_HIDDEN_CTL1, 0x30,
1195 EXT_FIFO_CTL, 0x0b,
1196 EXT_FIFO_CTL + 1, 0x17,
1197 0x76, 0x00,
1198 EXT_HIDDEN_CTL4, 0xc8
1199 };
1200
1201 /*
1202 * Initialise the CyberPro hardware. On the CyberPro5XXXX,
1203 * ensure that we're using the correct PLL (5XXX's may be
1204 * programmed to use an additional set of PLLs.)
1205 */
1206 static void cyberpro_init_hw(struct cfb_info *cfb)
1207 {
1208 int i;
1209
1210 for (i = 0; i < sizeof(igs_regs); i += 2)
1211 cyber2000_grphw(igs_regs[i], igs_regs[i+1], cfb);
1212
1213 if (cfb->id == ID_CYBERPRO_5000) {
1214 unsigned char val;
1215 cyber2000fb_writeb(0xba, 0x3ce, cfb);
1216 val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
1217 cyber2000fb_writeb(val, 0x3cf, cfb);
1218 }
1219 }
1220
1221 static struct cfb_info * __devinit
1222 cyberpro_alloc_fb_info(unsigned int id, char *name)
1223 {
1224 struct cfb_info *cfb;
1225
1226 cfb = kmalloc(sizeof(struct cfb_info) +
1227 sizeof(u32) * 16, GFP_KERNEL);
1228
1229 if (!cfb)
1230 return NULL;
1231
1232 memset(cfb, 0, sizeof(struct cfb_info));
1233
1234 cfb->id = id;
1235
1236 if (id == ID_CYBERPRO_5000)
1237 cfb->ref_ps = 40690; // 24.576 MHz
1238 else
1239 cfb->ref_ps = 69842; // 14.31818 MHz (69841?)
1240
1241 cfb->divisors[0] = 1;
1242 cfb->divisors[1] = 2;
1243 cfb->divisors[2] = 4;
1244
1245 if (id == ID_CYBERPRO_2000)
1246 cfb->divisors[3] = 8;
1247 else
1248 cfb->divisors[3] = 6;
1249
1250 strcpy(cfb->fb.fix.id, name);
1251
1252 cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1253 cfb->fb.fix.type_aux = 0;
1254 cfb->fb.fix.xpanstep = 0;
1255 cfb->fb.fix.ypanstep = 1;
1256 cfb->fb.fix.ywrapstep = 0;
1257
1258 switch (id) {
1259 case ID_IGA_1682:
1260 cfb->fb.fix.accel = 0;
1261 break;
1262
1263 case ID_CYBERPRO_2000:
1264 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
1265 break;
1266
1267 case ID_CYBERPRO_2010:
1268 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
1269 break;
1270
1271 case ID_CYBERPRO_5000:
1272 cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
1273 break;
1274 }
1275
1276 cfb->fb.var.nonstd = 0;
1277 cfb->fb.var.activate = FB_ACTIVATE_NOW;
1278 cfb->fb.var.height = -1;
1279 cfb->fb.var.width = -1;
1280 cfb->fb.var.accel_flags = FB_ACCELF_TEXT;
1281
1282 cfb->fb.fbops = &cyber2000fb_ops;
1283 cfb->fb.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1284 cfb->fb.pseudo_palette = (void *)(cfb + 1);
1285
1286 fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
1287
1288 return cfb;
1289 }
1290
1291 static void
1292 cyberpro_free_fb_info(struct cfb_info *cfb)
1293 {
1294 if (cfb) {
1295 /*
1296 * Free the colourmap
1297 */
1298 fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
1299
1300 kfree(cfb);
1301 }
1302 }
1303
1304 /*
1305 * Parse Cyber2000fb options. Usage:
1306 * video=cyber2000:font:fontname
1307 */
1308 #ifndef MODULE
1309 static int
1310 cyber2000fb_setup(char *options)
1311 {
1312 char *opt;
1313
1314 if (!options || !*options)
1315 return 0;
1316
1317 while ((opt = strsep(&options, ",")) != NULL) {
1318 if (!*opt)
1319 continue;
1320
1321 if (strncmp(opt, "font:", 5) == 0) {
1322 static char default_font_storage[40];
1323
1324 strlcpy(default_font_storage, opt + 5, sizeof(default_font_storage));
1325 default_font = default_font_storage;
1326 continue;
1327 }
1328
1329 printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
1330 }
1331 return 0;
1332 }
1333 #endif /* MODULE */
1334
1335 /*
1336 * The CyberPro chips can be placed on many different bus types.
1337 * This probe function is common to all bus types. The bus-specific
1338 * probe function is expected to have:
1339 * - enabled access to the linear memory region
1340 * - memory mapped access to the registers
1341 * - initialised mem_ctl1 and mem_ctl2 appropriately.
1342 */
1343 static int __devinit cyberpro_common_probe(struct cfb_info *cfb)
1344 {
1345 u_long smem_size;
1346 u_int h_sync, v_sync;
1347 int err;
1348
1349 cyberpro_init_hw(cfb);
1350
1351 /*
1352 * Get the video RAM size and width from the VGA register.
1353 * This should have been already initialised by the BIOS,
1354 * but if it's garbage, claim default 1MB VRAM (woody)
1355 */
1356 cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
1357 cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
1358
1359 /*
1360 * Determine the size of the memory.
1361 */
1362 switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
1363 case MEM_CTL2_SIZE_4MB: smem_size = 0x00400000; break;
1364 case MEM_CTL2_SIZE_2MB: smem_size = 0x00200000; break;
1365 case MEM_CTL2_SIZE_1MB: smem_size = 0x00100000; break;
1366 default: smem_size = 0x00100000; break;
1367 }
1368
1369 cfb->fb.fix.smem_len = smem_size;
1370 cfb->fb.fix.mmio_len = MMIO_SIZE;
1371 cfb->fb.screen_base = cfb->region;
1372
1373 err = -EINVAL;
1374 if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
1375 &cyber2000fb_default_mode, 8)) {
1376 printk("%s: no valid mode found\n", cfb->fb.fix.id);
1377 goto failed;
1378 }
1379
1380 cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
1381 (cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
1382
1383 if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
1384 cfb->fb.var.yres_virtual = cfb->fb.var.yres;
1385
1386 // fb_set_var(&cfb->fb.var, -1, &cfb->fb);
1387
1388 /*
1389 * Calculate the hsync and vsync frequencies. Note that
1390 * we split the 1e12 constant up so that we can preserve
1391 * the precision and fit the results into 32-bit registers.
1392 * (1953125000 * 512 = 1e12)
1393 */
1394 h_sync = 1953125000 / cfb->fb.var.pixclock;
1395 h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
1396 cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
1397 v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
1398 cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
1399
1400 printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
1401 cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
1402 cfb->fb.var.xres, cfb->fb.var.yres,
1403 h_sync / 1000, h_sync % 1000, v_sync);
1404
1405 if (cfb->dev)
1406 cfb->fb.device = &cfb->dev->dev;
1407 err = register_framebuffer(&cfb->fb);
1408
1409 failed:
1410 return err;
1411 }
1412
1413 static void cyberpro_common_resume(struct cfb_info *cfb)
1414 {
1415 cyberpro_init_hw(cfb);
1416
1417 /*
1418 * Reprogram the MEM_CTL1 and MEM_CTL2 registers
1419 */
1420 cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
1421 cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
1422
1423 /*
1424 * Restore the old video mode and the palette.
1425 * We also need to tell fbcon to redraw the console.
1426 */
1427 cyber2000fb_set_par(&cfb->fb);
1428 }
1429
1430 #ifdef CONFIG_ARCH_SHARK
1431
1432 #include <asm/arch/hardware.h>
1433
1434 static int __devinit
1435 cyberpro_vl_probe(void)
1436 {
1437 struct cfb_info *cfb;
1438 int err = -ENOMEM;
1439
1440 if (!request_mem_region(FB_START,FB_SIZE,"CyberPro2010")) return err;
1441
1442 cfb = cyberpro_alloc_fb_info(ID_CYBERPRO_2010, "CyberPro2010");
1443 if (!cfb)
1444 goto failed_release;
1445
1446 cfb->dev = NULL;
1447 cfb->region = ioremap(FB_START,FB_SIZE);
1448 if (!cfb->region)
1449 goto failed_ioremap;
1450
1451 cfb->regs = cfb->region + MMIO_OFFSET;
1452 cfb->fb.fix.mmio_start = FB_START + MMIO_OFFSET;
1453 cfb->fb.fix.smem_start = FB_START;
1454
1455 /*
1456 * Bring up the hardware. This is expected to enable access
1457 * to the linear memory region, and allow access to the memory
1458 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
1459 * initialised.
1460 */
1461 cyber2000fb_writeb(0x18, 0x46e8, cfb);
1462 cyber2000fb_writeb(0x01, 0x102, cfb);
1463 cyber2000fb_writeb(0x08, 0x46e8, cfb);
1464 cyber2000fb_writeb(EXT_BIU_MISC, 0x3ce, cfb);
1465 cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf, cfb);
1466
1467 cfb->mclk_mult = 0xdb;
1468 cfb->mclk_div = 0x54;
1469
1470 err = cyberpro_common_probe(cfb);
1471 if (err)
1472 goto failed;
1473
1474 if (int_cfb_info == NULL)
1475 int_cfb_info = cfb;
1476
1477 return 0;
1478
1479 failed:
1480 iounmap(cfb->region);
1481 failed_ioremap:
1482 cyberpro_free_fb_info(cfb);
1483 failed_release:
1484 release_mem_region(FB_START,FB_SIZE);
1485
1486 return err;
1487 }
1488 #endif /* CONFIG_ARCH_SHARK */
1489
1490 /*
1491 * PCI specific support.
1492 */
1493 #ifdef CONFIG_PCI
1494 /*
1495 * We need to wake up the CyberPro, and make sure its in linear memory
1496 * mode. Unfortunately, this is specific to the platform and card that
1497 * we are running on.
1498 *
1499 * On x86 and ARM, should we be initialising the CyberPro first via the
1500 * IO registers, and then the MMIO registers to catch all cases? Can we
1501 * end up in the situation where the chip is in MMIO mode, but not awake
1502 * on an x86 system?
1503 */
1504 static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
1505 {
1506 unsigned char val;
1507
1508 #if defined(__sparc_v9__)
1509 #error "You lose, consult DaveM."
1510 #elif defined(__sparc__)
1511 /*
1512 * SPARC does not have an "outb" instruction, so we generate
1513 * I/O cycles storing into a reserved memory space at
1514 * physical address 0x3000000
1515 */
1516 unsigned char *iop;
1517
1518 iop = ioremap(0x3000000, 0x5000);
1519 if (iop == NULL) {
1520 prom_printf("iga5000: cannot map I/O\n");
1521 return -ENOMEM;
1522 }
1523
1524 writeb(0x18, iop + 0x46e8);
1525 writeb(0x01, iop + 0x102);
1526 writeb(0x08, iop + 0x46e8);
1527 writeb(EXT_BIU_MISC, iop + 0x3ce);
1528 writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
1529
1530 iounmap((void *)iop);
1531 #else
1532 /*
1533 * Most other machine types are "normal", so
1534 * we use the standard IO-based wakeup.
1535 */
1536 outb(0x18, 0x46e8);
1537 outb(0x01, 0x102);
1538 outb(0x08, 0x46e8);
1539 outb(EXT_BIU_MISC, 0x3ce);
1540 outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
1541 #endif
1542
1543 /*
1544 * Allow the CyberPro to accept PCI burst accesses
1545 */
1546 val = cyber2000_grphr(EXT_BUS_CTL, cfb);
1547 if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
1548 printk(KERN_INFO "%s: enabling PCI bursts\n", cfb->fb.fix.id);
1549
1550 val |= EXT_BUS_CTL_PCIBURST_WRITE;
1551
1552 if (cfb->id == ID_CYBERPRO_5000)
1553 val |= EXT_BUS_CTL_PCIBURST_READ;
1554
1555 cyber2000_grphw(EXT_BUS_CTL, val, cfb);
1556 }
1557
1558 return 0;
1559 }
1560
1561 static int __devinit
1562 cyberpro_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1563 {
1564 struct cfb_info *cfb;
1565 char name[16];
1566 int err;
1567
1568 sprintf(name, "CyberPro%4X", id->device);
1569
1570 err = pci_enable_device(dev);
1571 if (err)
1572 return err;
1573
1574 err = pci_request_regions(dev, name);
1575 if (err)
1576 return err;
1577
1578 err = -ENOMEM;
1579 cfb = cyberpro_alloc_fb_info(id->driver_data, name);
1580 if (!cfb)
1581 goto failed_release;
1582
1583 cfb->dev = dev;
1584 cfb->region = ioremap(pci_resource_start(dev, 0),
1585 pci_resource_len(dev, 0));
1586 if (!cfb->region)
1587 goto failed_ioremap;
1588
1589 cfb->regs = cfb->region + MMIO_OFFSET;
1590 cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
1591 cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
1592
1593 /*
1594 * Bring up the hardware. This is expected to enable access
1595 * to the linear memory region, and allow access to the memory
1596 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
1597 * initialised.
1598 */
1599 err = cyberpro_pci_enable_mmio(cfb);
1600 if (err)
1601 goto failed;
1602
1603 /*
1604 * Use MCLK from BIOS. FIXME: what about hotplug?
1605 */
1606 cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
1607 cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb);
1608
1609 #ifdef __arm__
1610 /*
1611 * MCLK on the NetWinder and the Shark is fixed at 75MHz
1612 */
1613 if (machine_is_netwinder()) {
1614 cfb->mclk_mult = 0xdb;
1615 cfb->mclk_div = 0x54;
1616 }
1617 #endif
1618
1619 err = cyberpro_common_probe(cfb);
1620 if (err)
1621 goto failed;
1622
1623 /*
1624 * Our driver data
1625 */
1626 pci_set_drvdata(dev, cfb);
1627 if (int_cfb_info == NULL)
1628 int_cfb_info = cfb;
1629
1630 return 0;
1631
1632 failed:
1633 iounmap(cfb->region);
1634 failed_ioremap:
1635 cyberpro_free_fb_info(cfb);
1636 failed_release:
1637 pci_release_regions(dev);
1638
1639 return err;
1640 }
1641
1642 static void __devexit cyberpro_pci_remove(struct pci_dev *dev)
1643 {
1644 struct cfb_info *cfb = pci_get_drvdata(dev);
1645
1646 if (cfb) {
1647 /*
1648 * If unregister_framebuffer fails, then
1649 * we will be leaving hooks that could cause
1650 * oopsen laying around.
1651 */
1652 if (unregister_framebuffer(&cfb->fb))
1653 printk(KERN_WARNING "%s: danger Will Robinson, "
1654 "danger danger! Oopsen imminent!\n",
1655 cfb->fb.fix.id);
1656 iounmap(cfb->region);
1657 cyberpro_free_fb_info(cfb);
1658
1659 /*
1660 * Ensure that the driver data is no longer
1661 * valid.
1662 */
1663 pci_set_drvdata(dev, NULL);
1664 if (cfb == int_cfb_info)
1665 int_cfb_info = NULL;
1666
1667 pci_release_regions(dev);
1668 }
1669 }
1670
1671 static int cyberpro_pci_suspend(struct pci_dev *dev, pm_message_t state)
1672 {
1673 return 0;
1674 }
1675
1676 /*
1677 * Re-initialise the CyberPro hardware
1678 */
1679 static int cyberpro_pci_resume(struct pci_dev *dev)
1680 {
1681 struct cfb_info *cfb = pci_get_drvdata(dev);
1682
1683 if (cfb) {
1684 cyberpro_pci_enable_mmio(cfb);
1685 cyberpro_common_resume(cfb);
1686 }
1687
1688 return 0;
1689 }
1690
1691 static struct pci_device_id cyberpro_pci_table[] = {
1692 // Not yet
1693 // { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
1694 // PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
1695 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
1696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
1697 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
1698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
1699 { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
1700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
1701 { 0, }
1702 };
1703
1704 MODULE_DEVICE_TABLE(pci,cyberpro_pci_table);
1705
1706 static struct pci_driver cyberpro_driver = {
1707 .name = "CyberPro",
1708 .probe = cyberpro_pci_probe,
1709 .remove = __devexit_p(cyberpro_pci_remove),
1710 .suspend = cyberpro_pci_suspend,
1711 .resume = cyberpro_pci_resume,
1712 .id_table = cyberpro_pci_table
1713 };
1714 #endif
1715
1716 /*
1717 * I don't think we can use the "module_init" stuff here because
1718 * the fbcon stuff may not be initialised yet. Hence the #ifdef
1719 * around module_init.
1720 *
1721 * Tony: "module_init" is now required
1722 */
1723 static int __init cyber2000fb_init(void)
1724 {
1725 int ret = -1, err;
1726
1727 #ifndef MODULE
1728 char *option = NULL;
1729
1730 if (fb_get_options("cyber2000fb", &option))
1731 return -ENODEV;
1732 cyber2000fb_setup(option);
1733 #endif
1734
1735 #ifdef CONFIG_ARCH_SHARK
1736 err = cyberpro_vl_probe();
1737 if (!err) {
1738 ret = 0;
1739 __module_get(THIS_MODULE);
1740 }
1741 #endif
1742 #ifdef CONFIG_PCI
1743 err = pci_register_driver(&cyberpro_driver);
1744 if (!err)
1745 ret = 0;
1746 #endif
1747
1748 return ret ? err : 0;
1749 }
1750
1751 static void __exit cyberpro_exit(void)
1752 {
1753 pci_unregister_driver(&cyberpro_driver);
1754 }
1755
1756 module_init(cyber2000fb_init);
1757 module_exit(cyberpro_exit);
1758
1759 MODULE_AUTHOR("Russell King");
1760 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
1761 MODULE_LICENSE("GPL");
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