2 * linux/drivers/video/cyber2000fb.c
4 * Copyright (C) 1998-2002 Russell King
6 * MIPS and 50xx clock support
7 * Copyright (C) 2001 Bradley D. LaRonde <brad@ltc.com>
9 * 32 bit support, text color and panning fixes for modes != 8 bit
10 * Copyright (C) 2002 Denis Oliver Kropp <dok@directfb.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
16 * Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
20 * Note that we now use the new fbcon fix, var and cmap scheme. We do
21 * still have to check which console is the currently displayed one
22 * however, especially for the colourmap stuff.
24 * We also use the new hotplug PCI subsystem. I'm not sure if there
25 * are any such cards, but I'm erring on the side of caution. We don't
26 * want to go pop just because someone does have one.
28 * Note that this doesn't work fully in the case of multiple CyberPro
29 * cards with grabbers. We currently can only attach to the first
30 * CyberPro card found.
32 * When we're in truecolour mode, we power down the LUT RAM as a power
33 * saving feature. Also, when we enter any of the powersaving modes
34 * (except soft blanking) we power down the RAMDACs. This saves about
35 * 1W, which is roughly 8% of the power consumption of a NetWinder
36 * (which, incidentally, is about the same saving as a 2.5in hard disk
37 * entering standby mode.)
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
51 #include <linux/i2c.h>
52 #include <linux/i2c-algo-bit.h>
54 #include <asm/pgtable.h>
55 #include <asm/system.h>
58 #include <asm/mach-types.h>
61 #include "cyber2000fb.h"
65 struct display_switch
*dispsw
;
66 struct display
*display
;
68 unsigned char __iomem
*region
;
69 unsigned char __iomem
*regs
;
81 } palette
[NR_PALETTE
];
88 * RAMDAC control register is both of these or'ed together
91 u_char ramdac_powerdown
;
93 u32 pseudo_palette
[16];
95 spinlock_t reg_b0_lock
;
97 #ifdef CONFIG_FB_CYBER2000_DDC
99 struct i2c_adapter ddc_adapter
;
100 struct i2c_algo_bit_data ddc_algo
;
104 static char *default_font
= "Acorn8x8";
105 module_param(default_font
, charp
, 0);
106 MODULE_PARM_DESC(default_font
, "Default font name");
109 * Our access methods.
111 #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg))
112 #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg))
113 #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg))
115 #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg))
118 cyber2000_crtcw(unsigned int reg
, unsigned int val
, struct cfb_info
*cfb
)
120 cyber2000fb_writew((reg
& 255) | val
<< 8, 0x3d4, cfb
);
124 cyber2000_grphw(unsigned int reg
, unsigned int val
, struct cfb_info
*cfb
)
126 cyber2000fb_writew((reg
& 255) | val
<< 8, 0x3ce, cfb
);
129 static inline unsigned int
130 cyber2000_grphr(unsigned int reg
, struct cfb_info
*cfb
)
132 cyber2000fb_writeb(reg
, 0x3ce, cfb
);
133 return cyber2000fb_readb(0x3cf, cfb
);
137 cyber2000_attrw(unsigned int reg
, unsigned int val
, struct cfb_info
*cfb
)
139 cyber2000fb_readb(0x3da, cfb
);
140 cyber2000fb_writeb(reg
, 0x3c0, cfb
);
141 cyber2000fb_readb(0x3c1, cfb
);
142 cyber2000fb_writeb(val
, 0x3c0, cfb
);
146 cyber2000_seqw(unsigned int reg
, unsigned int val
, struct cfb_info
*cfb
)
148 cyber2000fb_writew((reg
& 255) | val
<< 8, 0x3c4, cfb
);
151 /* -------------------- Hardware specific routines ------------------------- */
154 * Hardware Cyber2000 Acceleration
157 cyber2000fb_fillrect(struct fb_info
*info
, const struct fb_fillrect
*rect
)
159 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
160 unsigned long dst
, col
;
162 if (!(cfb
->fb
.var
.accel_flags
& FB_ACCELF_TEXT
)) {
163 cfb_fillrect(info
, rect
);
167 cyber2000fb_writeb(0, CO_REG_CONTROL
, cfb
);
168 cyber2000fb_writew(rect
->width
- 1, CO_REG_PIXWIDTH
, cfb
);
169 cyber2000fb_writew(rect
->height
- 1, CO_REG_PIXHEIGHT
, cfb
);
172 if (cfb
->fb
.var
.bits_per_pixel
> 8)
173 col
= ((u32
*)cfb
->fb
.pseudo_palette
)[col
];
174 cyber2000fb_writel(col
, CO_REG_FGCOLOUR
, cfb
);
176 dst
= rect
->dx
+ rect
->dy
* cfb
->fb
.var
.xres_virtual
;
177 if (cfb
->fb
.var
.bits_per_pixel
== 24) {
178 cyber2000fb_writeb(dst
, CO_REG_X_PHASE
, cfb
);
182 cyber2000fb_writel(dst
, CO_REG_DEST_PTR
, cfb
);
183 cyber2000fb_writeb(CO_FG_MIX_SRC
, CO_REG_FGMIX
, cfb
);
184 cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL
, CO_REG_CMD_L
, cfb
);
185 cyber2000fb_writew(CO_CMD_H_BLITTER
, CO_REG_CMD_H
, cfb
);
189 cyber2000fb_copyarea(struct fb_info
*info
, const struct fb_copyarea
*region
)
191 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
192 unsigned int cmd
= CO_CMD_L_PATTERN_FGCOL
;
193 unsigned long src
, dst
;
195 if (!(cfb
->fb
.var
.accel_flags
& FB_ACCELF_TEXT
)) {
196 cfb_copyarea(info
, region
);
200 cyber2000fb_writeb(0, CO_REG_CONTROL
, cfb
);
201 cyber2000fb_writew(region
->width
- 1, CO_REG_PIXWIDTH
, cfb
);
202 cyber2000fb_writew(region
->height
- 1, CO_REG_PIXHEIGHT
, cfb
);
204 src
= region
->sx
+ region
->sy
* cfb
->fb
.var
.xres_virtual
;
205 dst
= region
->dx
+ region
->dy
* cfb
->fb
.var
.xres_virtual
;
207 if (region
->sx
< region
->dx
) {
208 src
+= region
->width
- 1;
209 dst
+= region
->width
- 1;
210 cmd
|= CO_CMD_L_INC_LEFT
;
213 if (region
->sy
< region
->dy
) {
214 src
+= (region
->height
- 1) * cfb
->fb
.var
.xres_virtual
;
215 dst
+= (region
->height
- 1) * cfb
->fb
.var
.xres_virtual
;
216 cmd
|= CO_CMD_L_INC_UP
;
219 if (cfb
->fb
.var
.bits_per_pixel
== 24) {
220 cyber2000fb_writeb(dst
, CO_REG_X_PHASE
, cfb
);
224 cyber2000fb_writel(src
, CO_REG_SRC1_PTR
, cfb
);
225 cyber2000fb_writel(dst
, CO_REG_DEST_PTR
, cfb
);
226 cyber2000fb_writew(CO_FG_MIX_SRC
, CO_REG_FGMIX
, cfb
);
227 cyber2000fb_writew(cmd
, CO_REG_CMD_L
, cfb
);
228 cyber2000fb_writew(CO_CMD_H_FGSRCMAP
| CO_CMD_H_BLITTER
,
233 cyber2000fb_imageblit(struct fb_info
*info
, const struct fb_image
*image
)
235 cfb_imageblit(info
, image
);
239 static int cyber2000fb_sync(struct fb_info
*info
)
241 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
244 if (!(cfb
->fb
.var
.accel_flags
& FB_ACCELF_TEXT
))
247 while (cyber2000fb_readb(CO_REG_CONTROL
, cfb
) & CO_CTRL_BUSY
) {
249 debug_printf("accel_wait timed out\n");
250 cyber2000fb_writeb(0, CO_REG_CONTROL
, cfb
);
259 * ===========================================================================
262 static inline u32
convert_bitfield(u_int val
, struct fb_bitfield
*bf
)
264 u_int mask
= (1 << bf
->length
) - 1;
266 return (val
>> (16 - bf
->length
) & mask
) << bf
->offset
;
270 * Set a single color register. Return != 0 for invalid regno.
273 cyber2000fb_setcolreg(u_int regno
, u_int red
, u_int green
, u_int blue
,
274 u_int transp
, struct fb_info
*info
)
276 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
277 struct fb_var_screeninfo
*var
= &cfb
->fb
.var
;
281 switch (cfb
->fb
.fix
.visual
) {
288 * pixel --/--+--/--> red lut --> red dac
290 * +--/--> green lut --> green dac
292 * +--/--> blue lut --> blue dac
294 case FB_VISUAL_PSEUDOCOLOR
:
295 if (regno
>= NR_PALETTE
)
302 cfb
->palette
[regno
].red
= red
;
303 cfb
->palette
[regno
].green
= green
;
304 cfb
->palette
[regno
].blue
= blue
;
306 cyber2000fb_writeb(regno
, 0x3c8, cfb
);
307 cyber2000fb_writeb(red
, 0x3c9, cfb
);
308 cyber2000fb_writeb(green
, 0x3c9, cfb
);
309 cyber2000fb_writeb(blue
, 0x3c9, cfb
);
315 * pixel --/--+--/--> red lut --> red dac
317 * +--/--> green lut --> green dac
319 * +--/--> blue lut --> blue dac
320 * n = bpp, rl = red length, gl = green length, bl = blue length
322 case FB_VISUAL_DIRECTCOLOR
:
327 if (var
->green
.length
== 6 && regno
< 64) {
328 cfb
->palette
[regno
<< 2].green
= green
;
331 * The 6 bits of the green component are applied
332 * to the high 6 bits of the LUT.
334 cyber2000fb_writeb(regno
<< 2, 0x3c8, cfb
);
335 cyber2000fb_writeb(cfb
->palette
[regno
>> 1].red
,
337 cyber2000fb_writeb(green
, 0x3c9, cfb
);
338 cyber2000fb_writeb(cfb
->palette
[regno
>> 1].blue
,
341 green
= cfb
->palette
[regno
<< 3].green
;
346 if (var
->green
.length
>= 5 && regno
< 32) {
347 cfb
->palette
[regno
<< 3].red
= red
;
348 cfb
->palette
[regno
<< 3].green
= green
;
349 cfb
->palette
[regno
<< 3].blue
= blue
;
352 * The 5 bits of each colour component are
353 * applied to the high 5 bits of the LUT.
355 cyber2000fb_writeb(regno
<< 3, 0x3c8, cfb
);
356 cyber2000fb_writeb(red
, 0x3c9, cfb
);
357 cyber2000fb_writeb(green
, 0x3c9, cfb
);
358 cyber2000fb_writeb(blue
, 0x3c9, cfb
);
362 if (var
->green
.length
== 4 && regno
< 16) {
363 cfb
->palette
[regno
<< 4].red
= red
;
364 cfb
->palette
[regno
<< 4].green
= green
;
365 cfb
->palette
[regno
<< 4].blue
= blue
;
368 * The 5 bits of each colour component are
369 * applied to the high 5 bits of the LUT.
371 cyber2000fb_writeb(regno
<< 4, 0x3c8, cfb
);
372 cyber2000fb_writeb(red
, 0x3c9, cfb
);
373 cyber2000fb_writeb(green
, 0x3c9, cfb
);
374 cyber2000fb_writeb(blue
, 0x3c9, cfb
);
379 * Since this is only used for the first 16 colours, we
380 * don't have to care about overflowing for regno >= 32
382 pseudo_val
= regno
<< var
->red
.offset
|
383 regno
<< var
->green
.offset
|
384 regno
<< var
->blue
.offset
;
390 * pixel --/--+--/--> red dac
395 * n = bpp, rl = red length, gl = green length, bl = blue length
397 case FB_VISUAL_TRUECOLOR
:
398 pseudo_val
= convert_bitfield(transp
^ 0xffff, &var
->transp
);
399 pseudo_val
|= convert_bitfield(red
, &var
->red
);
400 pseudo_val
|= convert_bitfield(green
, &var
->green
);
401 pseudo_val
|= convert_bitfield(blue
, &var
->blue
);
407 * Now set our pseudo palette for the CFB16/24/32 drivers.
410 ((u32
*)cfb
->fb
.pseudo_palette
)[regno
] = pseudo_val
;
435 static const u_char crtc_idx
[] = {
436 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
438 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
441 static void cyber2000fb_write_ramdac_ctrl(struct cfb_info
*cfb
)
444 unsigned int val
= cfb
->ramdac_ctrl
| cfb
->ramdac_powerdown
;
446 cyber2000fb_writeb(0x56, 0x3ce, cfb
);
447 i
= cyber2000fb_readb(0x3cf, cfb
);
448 cyber2000fb_writeb(i
| 4, 0x3cf, cfb
);
449 cyber2000fb_writeb(val
, 0x3c6, cfb
);
450 cyber2000fb_writeb(i
, 0x3cf, cfb
);
451 /* prevent card lock-up observed on x86 with CyberPro 2000 */
452 cyber2000fb_readb(0x3cf, cfb
);
455 static void cyber2000fb_set_timing(struct cfb_info
*cfb
, struct par_info
*hw
)
462 for (i
= 0; i
< NR_PALETTE
; i
++) {
463 cyber2000fb_writeb(i
, 0x3c8, cfb
);
464 cyber2000fb_writeb(0, 0x3c9, cfb
);
465 cyber2000fb_writeb(0, 0x3c9, cfb
);
466 cyber2000fb_writeb(0, 0x3c9, cfb
);
469 cyber2000fb_writeb(0xef, 0x3c2, cfb
);
470 cyber2000_crtcw(0x11, 0x0b, cfb
);
471 cyber2000_attrw(0x11, 0x00, cfb
);
473 cyber2000_seqw(0x00, 0x01, cfb
);
474 cyber2000_seqw(0x01, 0x01, cfb
);
475 cyber2000_seqw(0x02, 0x0f, cfb
);
476 cyber2000_seqw(0x03, 0x00, cfb
);
477 cyber2000_seqw(0x04, 0x0e, cfb
);
478 cyber2000_seqw(0x00, 0x03, cfb
);
480 for (i
= 0; i
< sizeof(crtc_idx
); i
++)
481 cyber2000_crtcw(crtc_idx
[i
], hw
->crtc
[i
], cfb
);
483 for (i
= 0x0a; i
< 0x10; i
++)
484 cyber2000_crtcw(i
, 0, cfb
);
486 cyber2000_grphw(EXT_CRT_VRTOFL
, hw
->crtc_ofl
, cfb
);
487 cyber2000_grphw(0x00, 0x00, cfb
);
488 cyber2000_grphw(0x01, 0x00, cfb
);
489 cyber2000_grphw(0x02, 0x00, cfb
);
490 cyber2000_grphw(0x03, 0x00, cfb
);
491 cyber2000_grphw(0x04, 0x00, cfb
);
492 cyber2000_grphw(0x05, 0x60, cfb
);
493 cyber2000_grphw(0x06, 0x05, cfb
);
494 cyber2000_grphw(0x07, 0x0f, cfb
);
495 cyber2000_grphw(0x08, 0xff, cfb
);
497 /* Attribute controller registers */
498 for (i
= 0; i
< 16; i
++)
499 cyber2000_attrw(i
, i
, cfb
);
501 cyber2000_attrw(0x10, 0x01, cfb
);
502 cyber2000_attrw(0x11, 0x00, cfb
);
503 cyber2000_attrw(0x12, 0x0f, cfb
);
504 cyber2000_attrw(0x13, 0x00, cfb
);
505 cyber2000_attrw(0x14, 0x00, cfb
);
508 spin_lock(&cfb
->reg_b0_lock
);
509 cyber2000_grphw(EXT_DCLK_MULT
, hw
->clock_mult
, cfb
);
510 cyber2000_grphw(EXT_DCLK_DIV
, hw
->clock_div
, cfb
);
511 cyber2000_grphw(EXT_MCLK_MULT
, cfb
->mclk_mult
, cfb
);
512 cyber2000_grphw(EXT_MCLK_DIV
, cfb
->mclk_div
, cfb
);
513 cyber2000_grphw(0x90, 0x01, cfb
);
514 cyber2000_grphw(0xb9, 0x80, cfb
);
515 cyber2000_grphw(0xb9, 0x00, cfb
);
516 spin_unlock(&cfb
->reg_b0_lock
);
518 cfb
->ramdac_ctrl
= hw
->ramdac
;
519 cyber2000fb_write_ramdac_ctrl(cfb
);
521 cyber2000fb_writeb(0x20, 0x3c0, cfb
);
522 cyber2000fb_writeb(0xff, 0x3c6, cfb
);
524 cyber2000_grphw(0x14, hw
->fetch
, cfb
);
525 cyber2000_grphw(0x15, ((hw
->fetch
>> 8) & 0x03) |
526 ((hw
->pitch
>> 4) & 0x30), cfb
);
527 cyber2000_grphw(EXT_SEQ_MISC
, hw
->extseqmisc
, cfb
);
530 * Set up accelerator registers
532 cyber2000fb_writew(hw
->width
, CO_REG_SRC_WIDTH
, cfb
);
533 cyber2000fb_writew(hw
->width
, CO_REG_DEST_WIDTH
, cfb
);
534 cyber2000fb_writeb(hw
->co_pixfmt
, CO_REG_PIXFMT
, cfb
);
538 cyber2000fb_update_start(struct cfb_info
*cfb
, struct fb_var_screeninfo
*var
)
540 u_int base
= var
->yoffset
* var
->xres_virtual
+ var
->xoffset
;
542 base
*= var
->bits_per_pixel
;
545 * Convert to bytes and shift two extra bits because DAC
546 * can only start on 4 byte aligned data.
553 cyber2000_grphw(0x10, base
>> 16 | 0x10, cfb
);
554 cyber2000_crtcw(0x0c, base
>> 8, cfb
);
555 cyber2000_crtcw(0x0d, base
, cfb
);
561 cyber2000fb_decode_crtc(struct par_info
*hw
, struct cfb_info
*cfb
,
562 struct fb_var_screeninfo
*var
)
564 u_int Htotal
, Hblankend
, Hsyncend
;
565 u_int Vtotal
, Vdispend
, Vblankstart
, Vblankend
, Vsyncstart
, Vsyncend
;
566 #define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2))
568 hw
->crtc
[13] = hw
->pitch
;
573 Htotal
= var
->xres
+ var
->right_margin
+
574 var
->hsync_len
+ var
->left_margin
;
579 hw
->crtc
[0] = (Htotal
>> 3) - 5;
580 hw
->crtc
[1] = (var
->xres
>> 3) - 1;
581 hw
->crtc
[2] = var
->xres
>> 3;
582 hw
->crtc
[4] = (var
->xres
+ var
->right_margin
) >> 3;
584 Hblankend
= (Htotal
- 4 * 8) >> 3;
586 hw
->crtc
[3] = ENCODE_BIT(Hblankend
, 0, 0x1f, 0) |
587 ENCODE_BIT(1, 0, 0x01, 7);
589 Hsyncend
= (var
->xres
+ var
->right_margin
+ var
->hsync_len
) >> 3;
591 hw
->crtc
[5] = ENCODE_BIT(Hsyncend
, 0, 0x1f, 0) |
592 ENCODE_BIT(Hblankend
, 5, 0x01, 7);
594 Vdispend
= var
->yres
- 1;
595 Vsyncstart
= var
->yres
+ var
->lower_margin
;
596 Vsyncend
= var
->yres
+ var
->lower_margin
+ var
->vsync_len
;
597 Vtotal
= var
->yres
+ var
->lower_margin
+ var
->vsync_len
+
598 var
->upper_margin
- 2;
603 Vblankstart
= var
->yres
+ 6;
604 Vblankend
= Vtotal
- 10;
606 hw
->crtc
[6] = Vtotal
;
607 hw
->crtc
[7] = ENCODE_BIT(Vtotal
, 8, 0x01, 0) |
608 ENCODE_BIT(Vdispend
, 8, 0x01, 1) |
609 ENCODE_BIT(Vsyncstart
, 8, 0x01, 2) |
610 ENCODE_BIT(Vblankstart
, 8, 0x01, 3) |
611 ENCODE_BIT(1, 0, 0x01, 4) |
612 ENCODE_BIT(Vtotal
, 9, 0x01, 5) |
613 ENCODE_BIT(Vdispend
, 9, 0x01, 6) |
614 ENCODE_BIT(Vsyncstart
, 9, 0x01, 7);
615 hw
->crtc
[9] = ENCODE_BIT(0, 0, 0x1f, 0) |
616 ENCODE_BIT(Vblankstart
, 9, 0x01, 5) |
617 ENCODE_BIT(1, 0, 0x01, 6);
618 hw
->crtc
[10] = Vsyncstart
;
619 hw
->crtc
[11] = ENCODE_BIT(Vsyncend
, 0, 0x0f, 0) |
620 ENCODE_BIT(1, 0, 0x01, 7);
621 hw
->crtc
[12] = Vdispend
;
622 hw
->crtc
[15] = Vblankstart
;
623 hw
->crtc
[16] = Vblankend
;
627 * overflow - graphics reg 0x11
628 * 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
629 * 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
632 ENCODE_BIT(Vtotal
, 10, 0x01, 0) |
633 ENCODE_BIT(Vdispend
, 10, 0x01, 1) |
634 ENCODE_BIT(Vsyncstart
, 10, 0x01, 2) |
635 ENCODE_BIT(Vblankstart
, 10, 0x01, 3) |
636 EXT_CRT_VRTOFL_LINECOMP10
;
638 /* woody: set the interlaced bit... */
639 /* FIXME: what about doublescan? */
640 if ((var
->vmode
& FB_VMODE_MASK
) == FB_VMODE_INTERLACED
)
641 hw
->crtc_ofl
|= EXT_CRT_VRTOFL_INTERLACE
;
647 * The following was discovered by a good monitor, bit twiddling, theorising
648 * and but mostly luck. Strangely, it looks like everyone elses' PLL!
651 * fclock = fpll / div2
652 * fpll = fref * mult / div1
654 * fref = 14.318MHz (69842ps)
656 * div1 = (reg0xb1.5:0 + 1)
657 * div2 = 2^(reg0xb1.7:6)
658 * fpll should be between 115 and 260 MHz
659 * (8696ps and 3846ps)
662 cyber2000fb_decode_clock(struct par_info
*hw
, struct cfb_info
*cfb
,
663 struct fb_var_screeninfo
*var
)
665 u_long pll_ps
= var
->pixclock
;
666 const u_long ref_ps
= cfb
->ref_ps
;
667 u_int div2
, t_div1
, best_div1
, best_mult
;
673 * find div2 such that 115MHz < fpll < 260MHz
676 for (div2
= 0; div2
< 4; div2
++) {
679 new_pll
= pll_ps
/ cfb
->divisors
[div2
];
680 if (8696 > new_pll
&& new_pll
> 3846) {
691 * Given pll_ps and ref_ps, find:
692 * pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
693 * where { 1 < best_div1 < 32, 1 < best_mult < 256 }
694 * pll_ps_calc = best_div1 / (ref_ps * best_mult)
696 best_diff
= 0x7fffffff;
699 for (t_div1
= 2; t_div1
< 32; t_div1
+= 1) {
700 u_int rr
, t_mult
, t_pll_ps
;
704 * Find the multiplier for this divisor
706 rr
= ref_ps
* t_div1
;
707 t_mult
= (rr
+ pll_ps
/ 2) / pll_ps
;
710 * Is the multiplier within the correct range?
712 if (t_mult
> 256 || t_mult
< 2)
716 * Calculate the actual clock period from this multiplier
717 * and divisor, and estimate the error.
719 t_pll_ps
= (rr
+ t_mult
/ 2) / t_mult
;
720 diff
= pll_ps
- t_pll_ps
;
724 if (diff
< best_diff
) {
731 * If we hit an exact value, there is no point in continuing.
741 hw
->clock_mult
= best_mult
- 1;
742 hw
->clock_div
= div2
<< 6 | (best_div1
- 1);
744 vco
= ref_ps
* best_div1
/ best_mult
;
745 if ((ref_ps
== 40690) && (vco
< 5556))
746 /* Set VFSEL when VCO > 180MHz (5.556 ps). */
747 hw
->clock_div
|= EXT_DCLK_DIV_VFSEL
;
753 * Set the User Defined Part of the Display
756 cyber2000fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
758 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
763 var
->transp
.msb_right
= 0;
764 var
->red
.msb_right
= 0;
765 var
->green
.msb_right
= 0;
766 var
->blue
.msb_right
= 0;
767 var
->transp
.offset
= 0;
768 var
->transp
.length
= 0;
770 switch (var
->bits_per_pixel
) {
771 case 8: /* PSEUDOCOLOUR, 256 */
774 var
->green
.offset
= 0;
775 var
->green
.length
= 8;
776 var
->blue
.offset
= 0;
777 var
->blue
.length
= 8;
780 case 16:/* DIRECTCOLOUR, 64k or 32k */
781 switch (var
->green
.length
) {
782 case 6: /* RGB565, 64k */
783 var
->red
.offset
= 11;
785 var
->green
.offset
= 5;
786 var
->green
.length
= 6;
787 var
->blue
.offset
= 0;
788 var
->blue
.length
= 5;
792 case 5: /* RGB555, 32k */
793 var
->red
.offset
= 10;
795 var
->green
.offset
= 5;
796 var
->green
.length
= 5;
797 var
->blue
.offset
= 0;
798 var
->blue
.length
= 5;
801 case 4: /* RGB444, 4k + transparency? */
802 var
->transp
.offset
= 12;
803 var
->transp
.length
= 4;
806 var
->green
.offset
= 4;
807 var
->green
.length
= 4;
808 var
->blue
.offset
= 0;
809 var
->blue
.length
= 4;
814 case 24:/* TRUECOLOUR, 16m */
815 var
->red
.offset
= 16;
817 var
->green
.offset
= 8;
818 var
->green
.length
= 8;
819 var
->blue
.offset
= 0;
820 var
->blue
.length
= 8;
823 case 32:/* TRUECOLOUR, 16m */
824 var
->transp
.offset
= 24;
825 var
->transp
.length
= 8;
826 var
->red
.offset
= 16;
828 var
->green
.offset
= 8;
829 var
->green
.length
= 8;
830 var
->blue
.offset
= 0;
831 var
->blue
.length
= 8;
838 mem
= var
->xres_virtual
* var
->yres_virtual
* (var
->bits_per_pixel
/ 8);
839 if (mem
> cfb
->fb
.fix
.smem_len
)
840 var
->yres_virtual
= cfb
->fb
.fix
.smem_len
* 8 /
841 (var
->bits_per_pixel
* var
->xres_virtual
);
843 if (var
->yres
> var
->yres_virtual
)
844 var
->yres
= var
->yres_virtual
;
845 if (var
->xres
> var
->xres_virtual
)
846 var
->xres
= var
->xres_virtual
;
848 err
= cyber2000fb_decode_clock(&hw
, cfb
, var
);
852 err
= cyber2000fb_decode_crtc(&hw
, cfb
, var
);
859 static int cyber2000fb_set_par(struct fb_info
*info
)
861 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
862 struct fb_var_screeninfo
*var
= &cfb
->fb
.var
;
866 hw
.width
= var
->xres_virtual
;
867 hw
.ramdac
= RAMDAC_VREFEN
| RAMDAC_DAC8BIT
;
869 switch (var
->bits_per_pixel
) {
871 hw
.co_pixfmt
= CO_PIXFMT_8BPP
;
872 hw
.pitch
= hw
.width
>> 3;
873 hw
.extseqmisc
= EXT_SEQ_MISC_8
;
877 hw
.co_pixfmt
= CO_PIXFMT_16BPP
;
878 hw
.pitch
= hw
.width
>> 2;
880 switch (var
->green
.length
) {
881 case 6: /* RGB565, 64k */
882 hw
.extseqmisc
= EXT_SEQ_MISC_16_RGB565
;
884 case 5: /* RGB555, 32k */
885 hw
.extseqmisc
= EXT_SEQ_MISC_16_RGB555
;
887 case 4: /* RGB444, 4k + transparency? */
888 hw
.extseqmisc
= EXT_SEQ_MISC_16_RGB444
;
895 case 24:/* TRUECOLOUR, 16m */
896 hw
.co_pixfmt
= CO_PIXFMT_24BPP
;
898 hw
.pitch
= hw
.width
>> 3;
899 hw
.ramdac
|= (RAMDAC_BYPASS
| RAMDAC_RAMPWRDN
);
900 hw
.extseqmisc
= EXT_SEQ_MISC_24_RGB888
;
903 case 32:/* TRUECOLOUR, 16m */
904 hw
.co_pixfmt
= CO_PIXFMT_32BPP
;
905 hw
.pitch
= hw
.width
>> 1;
906 hw
.ramdac
|= (RAMDAC_BYPASS
| RAMDAC_RAMPWRDN
);
907 hw
.extseqmisc
= EXT_SEQ_MISC_32
;
915 * Sigh, this is absolutely disgusting, but caused by
916 * the way the fbcon developers want to separate out
917 * the "checking" and the "setting" of the video mode.
919 * If the mode is not suitable for the hardware here,
920 * we can't prevent it being set by returning an error.
922 * In theory, since NetWinders contain just one VGA card,
923 * we should never end up hitting this problem.
925 BUG_ON(cyber2000fb_decode_clock(&hw
, cfb
, var
) != 0);
926 BUG_ON(cyber2000fb_decode_crtc(&hw
, cfb
, var
) != 0);
930 if (!(cfb
->mem_ctl2
& MEM_CTL2_64BIT
))
934 cfb
->fb
.fix
.line_length
= var
->xres_virtual
* var
->bits_per_pixel
/ 8;
937 * Same here - if the size of the video mode exceeds the
938 * available RAM, we can't prevent this mode being set.
940 * In theory, since NetWinders contain just one VGA card,
941 * we should never end up hitting this problem.
943 mem
= cfb
->fb
.fix
.line_length
* var
->yres_virtual
;
944 BUG_ON(mem
> cfb
->fb
.fix
.smem_len
);
947 * 8bpp displays are always pseudo colour. 16bpp and above
948 * are direct colour or true colour, depending on whether
949 * the RAMDAC palettes are bypassed. (Direct colour has
950 * palettes, true colour does not.)
952 if (var
->bits_per_pixel
== 8)
953 cfb
->fb
.fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
954 else if (hw
.ramdac
& RAMDAC_BYPASS
)
955 cfb
->fb
.fix
.visual
= FB_VISUAL_TRUECOLOR
;
957 cfb
->fb
.fix
.visual
= FB_VISUAL_DIRECTCOLOR
;
959 cyber2000fb_set_timing(cfb
, &hw
);
960 cyber2000fb_update_start(cfb
, var
);
966 * Pan or Wrap the Display
969 cyber2000fb_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
971 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
973 if (cyber2000fb_update_start(cfb
, var
))
976 cfb
->fb
.var
.xoffset
= var
->xoffset
;
977 cfb
->fb
.var
.yoffset
= var
->yoffset
;
979 if (var
->vmode
& FB_VMODE_YWRAP
) {
980 cfb
->fb
.var
.vmode
|= FB_VMODE_YWRAP
;
982 cfb
->fb
.var
.vmode
&= ~FB_VMODE_YWRAP
;
989 * (Un)Blank the display.
991 * Blank the screen if blank_mode != 0, else unblank. If
992 * blank == NULL then the caller blanks by setting the CLUT
993 * (Color Look Up Table) to all black. Return 0 if blanking
994 * succeeded, != 0 if un-/blanking failed due to e.g. a
995 * video mode which doesn't support it. Implements VESA
996 * suspend and powerdown modes on hardware that supports
997 * disabling hsync/vsync:
998 * blank_mode == 2: suspend vsync
999 * blank_mode == 3: suspend hsync
1000 * blank_mode == 4: powerdown
1002 * wms...Enable VESA DMPS compatible powerdown mode
1003 * run "setterm -powersave powerdown" to take advantage
1005 static int cyber2000fb_blank(int blank
, struct fb_info
*info
)
1007 struct cfb_info
*cfb
= (struct cfb_info
*)info
;
1008 unsigned int sync
= 0;
1012 case FB_BLANK_POWERDOWN
: /* powerdown - both sync lines down */
1013 sync
= EXT_SYNC_CTL_VS_0
| EXT_SYNC_CTL_HS_0
;
1015 case FB_BLANK_HSYNC_SUSPEND
: /* hsync off */
1016 sync
= EXT_SYNC_CTL_VS_NORMAL
| EXT_SYNC_CTL_HS_0
;
1018 case FB_BLANK_VSYNC_SUSPEND
: /* vsync off */
1019 sync
= EXT_SYNC_CTL_VS_0
| EXT_SYNC_CTL_HS_NORMAL
;
1021 case FB_BLANK_NORMAL
: /* soft blank */
1022 default: /* unblank */
1026 cyber2000_grphw(EXT_SYNC_CTL
, sync
, cfb
);
1029 /* turn on ramdacs */
1030 cfb
->ramdac_powerdown
&= ~(RAMDAC_DACPWRDN
| RAMDAC_BYPASS
|
1032 cyber2000fb_write_ramdac_ctrl(cfb
);
1036 * Soft blank/unblank the display.
1038 if (blank
) { /* soft blank */
1039 for (i
= 0; i
< NR_PALETTE
; i
++) {
1040 cyber2000fb_writeb(i
, 0x3c8, cfb
);
1041 cyber2000fb_writeb(0, 0x3c9, cfb
);
1042 cyber2000fb_writeb(0, 0x3c9, cfb
);
1043 cyber2000fb_writeb(0, 0x3c9, cfb
);
1045 } else { /* unblank */
1046 for (i
= 0; i
< NR_PALETTE
; i
++) {
1047 cyber2000fb_writeb(i
, 0x3c8, cfb
);
1048 cyber2000fb_writeb(cfb
->palette
[i
].red
, 0x3c9, cfb
);
1049 cyber2000fb_writeb(cfb
->palette
[i
].green
, 0x3c9, cfb
);
1050 cyber2000fb_writeb(cfb
->palette
[i
].blue
, 0x3c9, cfb
);
1055 /* turn off ramdacs */
1056 cfb
->ramdac_powerdown
|= RAMDAC_DACPWRDN
| RAMDAC_BYPASS
|
1058 cyber2000fb_write_ramdac_ctrl(cfb
);
1064 static struct fb_ops cyber2000fb_ops
= {
1065 .owner
= THIS_MODULE
,
1066 .fb_check_var
= cyber2000fb_check_var
,
1067 .fb_set_par
= cyber2000fb_set_par
,
1068 .fb_setcolreg
= cyber2000fb_setcolreg
,
1069 .fb_blank
= cyber2000fb_blank
,
1070 .fb_pan_display
= cyber2000fb_pan_display
,
1071 .fb_fillrect
= cyber2000fb_fillrect
,
1072 .fb_copyarea
= cyber2000fb_copyarea
,
1073 .fb_imageblit
= cyber2000fb_imageblit
,
1074 .fb_sync
= cyber2000fb_sync
,
1078 * This is the only "static" reference to the internal data structures
1079 * of this driver. It is here solely at the moment to support the other
1080 * CyberPro modules external to this driver.
1082 static struct cfb_info
*int_cfb_info
;
1085 * Enable access to the extended registers
1087 void cyber2000fb_enable_extregs(struct cfb_info
*cfb
)
1089 cfb
->func_use_count
+= 1;
1091 if (cfb
->func_use_count
== 1) {
1094 old
= cyber2000_grphr(EXT_FUNC_CTL
, cfb
);
1095 old
|= EXT_FUNC_CTL_EXTREGENBL
;
1096 cyber2000_grphw(EXT_FUNC_CTL
, old
, cfb
);
1099 EXPORT_SYMBOL(cyber2000fb_enable_extregs
);
1102 * Disable access to the extended registers
1104 void cyber2000fb_disable_extregs(struct cfb_info
*cfb
)
1106 if (cfb
->func_use_count
== 1) {
1109 old
= cyber2000_grphr(EXT_FUNC_CTL
, cfb
);
1110 old
&= ~EXT_FUNC_CTL_EXTREGENBL
;
1111 cyber2000_grphw(EXT_FUNC_CTL
, old
, cfb
);
1114 if (cfb
->func_use_count
== 0)
1115 printk(KERN_ERR
"disable_extregs: count = 0\n");
1117 cfb
->func_use_count
-= 1;
1119 EXPORT_SYMBOL(cyber2000fb_disable_extregs
);
1121 void cyber2000fb_get_fb_var(struct cfb_info
*cfb
, struct fb_var_screeninfo
*var
)
1123 memcpy(var
, &cfb
->fb
.var
, sizeof(struct fb_var_screeninfo
));
1125 EXPORT_SYMBOL(cyber2000fb_get_fb_var
);
1128 * Attach a capture/tv driver to the core CyberX0X0 driver.
1130 int cyber2000fb_attach(struct cyberpro_info
*info
, int idx
)
1132 if (int_cfb_info
!= NULL
) {
1133 info
->dev
= int_cfb_info
->dev
;
1134 info
->regs
= int_cfb_info
->regs
;
1135 info
->fb
= int_cfb_info
->fb
.screen_base
;
1136 info
->fb_size
= int_cfb_info
->fb
.fix
.smem_len
;
1137 info
->enable_extregs
= cyber2000fb_enable_extregs
;
1138 info
->disable_extregs
= cyber2000fb_disable_extregs
;
1139 info
->info
= int_cfb_info
;
1141 strlcpy(info
->dev_name
, int_cfb_info
->fb
.fix
.id
,
1142 sizeof(info
->dev_name
));
1145 return int_cfb_info
!= NULL
;
1147 EXPORT_SYMBOL(cyber2000fb_attach
);
1150 * Detach a capture/tv driver from the core CyberX0X0 driver.
1152 void cyber2000fb_detach(int idx
)
1155 EXPORT_SYMBOL(cyber2000fb_detach
);
1157 #ifdef CONFIG_FB_CYBER2000_DDC
1159 #define DDC_REG 0xb0
1160 #define DDC_SCL_OUT (1 << 0)
1161 #define DDC_SDA_OUT (1 << 4)
1162 #define DDC_SCL_IN (1 << 2)
1163 #define DDC_SDA_IN (1 << 6)
1165 static void cyber2000fb_enable_ddc(struct cfb_info
*cfb
)
1167 spin_lock(&cfb
->reg_b0_lock
);
1168 cyber2000fb_writew(0x1bf, 0x3ce, cfb
);
1171 static void cyber2000fb_disable_ddc(struct cfb_info
*cfb
)
1173 cyber2000fb_writew(0x0bf, 0x3ce, cfb
);
1174 spin_unlock(&cfb
->reg_b0_lock
);
1178 static void cyber2000fb_ddc_setscl(void *data
, int val
)
1180 struct cfb_info
*cfb
= data
;
1183 cyber2000fb_enable_ddc(cfb
);
1184 reg
= cyber2000_grphr(DDC_REG
, cfb
);
1185 if (!val
) /* bit is inverted */
1188 reg
&= ~DDC_SCL_OUT
;
1189 cyber2000_grphw(DDC_REG
, reg
, cfb
);
1190 cyber2000fb_disable_ddc(cfb
);
1193 static void cyber2000fb_ddc_setsda(void *data
, int val
)
1195 struct cfb_info
*cfb
= data
;
1198 cyber2000fb_enable_ddc(cfb
);
1199 reg
= cyber2000_grphr(DDC_REG
, cfb
);
1200 if (!val
) /* bit is inverted */
1203 reg
&= ~DDC_SDA_OUT
;
1204 cyber2000_grphw(DDC_REG
, reg
, cfb
);
1205 cyber2000fb_disable_ddc(cfb
);
1208 static int cyber2000fb_ddc_getscl(void *data
)
1210 struct cfb_info
*cfb
= data
;
1213 cyber2000fb_enable_ddc(cfb
);
1214 retval
= !!(cyber2000_grphr(DDC_REG
, cfb
) & DDC_SCL_IN
);
1215 cyber2000fb_disable_ddc(cfb
);
1220 static int cyber2000fb_ddc_getsda(void *data
)
1222 struct cfb_info
*cfb
= data
;
1225 cyber2000fb_enable_ddc(cfb
);
1226 retval
= !!(cyber2000_grphr(DDC_REG
, cfb
) & DDC_SDA_IN
);
1227 cyber2000fb_disable_ddc(cfb
);
1232 static int __devinit
cyber2000fb_setup_ddc_bus(struct cfb_info
*cfb
)
1234 strlcpy(cfb
->ddc_adapter
.name
, cfb
->fb
.fix
.id
,
1235 sizeof(cfb
->ddc_adapter
.name
));
1236 cfb
->ddc_adapter
.owner
= THIS_MODULE
;
1237 cfb
->ddc_adapter
.class = I2C_CLASS_DDC
;
1238 cfb
->ddc_adapter
.algo_data
= &cfb
->ddc_algo
;
1239 cfb
->ddc_adapter
.dev
.parent
= &cfb
->dev
->dev
;
1240 cfb
->ddc_algo
.setsda
= cyber2000fb_ddc_setsda
;
1241 cfb
->ddc_algo
.setscl
= cyber2000fb_ddc_setscl
;
1242 cfb
->ddc_algo
.getsda
= cyber2000fb_ddc_getsda
;
1243 cfb
->ddc_algo
.getscl
= cyber2000fb_ddc_getscl
;
1244 cfb
->ddc_algo
.udelay
= 10;
1245 cfb
->ddc_algo
.timeout
= 20;
1246 cfb
->ddc_algo
.data
= cfb
;
1248 i2c_set_adapdata(&cfb
->ddc_adapter
, cfb
);
1250 return i2c_bit_add_bus(&cfb
->ddc_adapter
);
1252 #endif /* CONFIG_FB_CYBER2000_DDC */
1255 * These parameters give
1256 * 640x480, hsync 31.5kHz, vsync 60Hz
1258 static struct fb_videomode __devinitdata cyber2000fb_default_mode
= {
1269 .sync
= FB_SYNC_COMP_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
1270 .vmode
= FB_VMODE_NONINTERLACED
1273 static char igs_regs
[] = {
1277 EXT_SEG_WRITE_PTR
, 0,
1278 EXT_SEG_READ_PTR
, 0,
1279 EXT_BIU_MISC
, EXT_BIU_MISC_LIN_ENABLE
|
1280 EXT_BIU_MISC_COP_ENABLE
|
1281 EXT_BIU_MISC_COP_BFC
,
1284 CURS_H_START
+ 1, 0,
1287 CURS_V_START
+ 1, 0,
1290 EXT_ATTRIB_CTL
, EXT_ATTRIB_CTL_EXT
,
1291 EXT_OVERSCAN_RED
, 0,
1292 EXT_OVERSCAN_GREEN
, 0,
1293 EXT_OVERSCAN_BLUE
, 0,
1295 /* some of these are questionable when we have a BIOS */
1296 EXT_MEM_CTL0
, EXT_MEM_CTL0_7CLK
|
1297 EXT_MEM_CTL0_RAS_1
|
1298 EXT_MEM_CTL0_MULTCAS
,
1299 EXT_HIDDEN_CTL1
, 0x30,
1301 EXT_FIFO_CTL
+ 1, 0x17,
1303 EXT_HIDDEN_CTL4
, 0xc8
1307 * Initialise the CyberPro hardware. On the CyberPro5XXXX,
1308 * ensure that we're using the correct PLL (5XXX's may be
1309 * programmed to use an additional set of PLLs.)
1311 static void cyberpro_init_hw(struct cfb_info
*cfb
)
1315 for (i
= 0; i
< sizeof(igs_regs
); i
+= 2)
1316 cyber2000_grphw(igs_regs
[i
], igs_regs
[i
+ 1], cfb
);
1318 if (cfb
->id
== ID_CYBERPRO_5000
) {
1320 cyber2000fb_writeb(0xba, 0x3ce, cfb
);
1321 val
= cyber2000fb_readb(0x3cf, cfb
) & 0x80;
1322 cyber2000fb_writeb(val
, 0x3cf, cfb
);
1326 static struct cfb_info __devinit
*cyberpro_alloc_fb_info(unsigned int id
,
1329 struct cfb_info
*cfb
;
1331 cfb
= kzalloc(sizeof(struct cfb_info
), GFP_KERNEL
);
1338 if (id
== ID_CYBERPRO_5000
)
1339 cfb
->ref_ps
= 40690; /* 24.576 MHz */
1341 cfb
->ref_ps
= 69842; /* 14.31818 MHz (69841?) */
1343 cfb
->divisors
[0] = 1;
1344 cfb
->divisors
[1] = 2;
1345 cfb
->divisors
[2] = 4;
1347 if (id
== ID_CYBERPRO_2000
)
1348 cfb
->divisors
[3] = 8;
1350 cfb
->divisors
[3] = 6;
1352 strcpy(cfb
->fb
.fix
.id
, name
);
1354 cfb
->fb
.fix
.type
= FB_TYPE_PACKED_PIXELS
;
1355 cfb
->fb
.fix
.type_aux
= 0;
1356 cfb
->fb
.fix
.xpanstep
= 0;
1357 cfb
->fb
.fix
.ypanstep
= 1;
1358 cfb
->fb
.fix
.ywrapstep
= 0;
1362 cfb
->fb
.fix
.accel
= 0;
1365 case ID_CYBERPRO_2000
:
1366 cfb
->fb
.fix
.accel
= FB_ACCEL_IGS_CYBER2000
;
1369 case ID_CYBERPRO_2010
:
1370 cfb
->fb
.fix
.accel
= FB_ACCEL_IGS_CYBER2010
;
1373 case ID_CYBERPRO_5000
:
1374 cfb
->fb
.fix
.accel
= FB_ACCEL_IGS_CYBER5000
;
1378 cfb
->fb
.var
.nonstd
= 0;
1379 cfb
->fb
.var
.activate
= FB_ACTIVATE_NOW
;
1380 cfb
->fb
.var
.height
= -1;
1381 cfb
->fb
.var
.width
= -1;
1382 cfb
->fb
.var
.accel_flags
= FB_ACCELF_TEXT
;
1384 cfb
->fb
.fbops
= &cyber2000fb_ops
;
1385 cfb
->fb
.flags
= FBINFO_DEFAULT
| FBINFO_HWACCEL_YPAN
;
1386 cfb
->fb
.pseudo_palette
= cfb
->pseudo_palette
;
1388 spin_lock_init(&cfb
->reg_b0_lock
);
1390 fb_alloc_cmap(&cfb
->fb
.cmap
, NR_PALETTE
, 0);
1395 static void cyberpro_free_fb_info(struct cfb_info
*cfb
)
1399 * Free the colourmap
1401 fb_alloc_cmap(&cfb
->fb
.cmap
, 0, 0);
1408 * Parse Cyber2000fb options. Usage:
1409 * video=cyber2000:font:fontname
1412 static int cyber2000fb_setup(char *options
)
1416 if (!options
|| !*options
)
1419 while ((opt
= strsep(&options
, ",")) != NULL
) {
1423 if (strncmp(opt
, "font:", 5) == 0) {
1424 static char default_font_storage
[40];
1426 strlcpy(default_font_storage
, opt
+ 5,
1427 sizeof(default_font_storage
));
1428 default_font
= default_font_storage
;
1432 printk(KERN_ERR
"CyberPro20x0: unknown parameter: %s\n", opt
);
1439 * The CyberPro chips can be placed on many different bus types.
1440 * This probe function is common to all bus types. The bus-specific
1441 * probe function is expected to have:
1442 * - enabled access to the linear memory region
1443 * - memory mapped access to the registers
1444 * - initialised mem_ctl1 and mem_ctl2 appropriately.
1446 static int __devinit
cyberpro_common_probe(struct cfb_info
*cfb
)
1449 u_int h_sync
, v_sync
;
1452 cyberpro_init_hw(cfb
);
1455 * Get the video RAM size and width from the VGA register.
1456 * This should have been already initialised by the BIOS,
1457 * but if it's garbage, claim default 1MB VRAM (woody)
1459 cfb
->mem_ctl1
= cyber2000_grphr(EXT_MEM_CTL1
, cfb
);
1460 cfb
->mem_ctl2
= cyber2000_grphr(EXT_MEM_CTL2
, cfb
);
1463 * Determine the size of the memory.
1465 switch (cfb
->mem_ctl2
& MEM_CTL2_SIZE_MASK
) {
1466 case MEM_CTL2_SIZE_4MB
:
1467 smem_size
= 0x00400000;
1469 case MEM_CTL2_SIZE_2MB
:
1470 smem_size
= 0x00200000;
1472 case MEM_CTL2_SIZE_1MB
:
1473 smem_size
= 0x00100000;
1476 smem_size
= 0x00100000;
1480 cfb
->fb
.fix
.smem_len
= smem_size
;
1481 cfb
->fb
.fix
.mmio_len
= MMIO_SIZE
;
1482 cfb
->fb
.screen_base
= cfb
->region
;
1484 #ifdef CONFIG_FB_CYBER2000_DDC
1485 if (cyber2000fb_setup_ddc_bus(cfb
) == 0)
1486 cfb
->ddc_registered
= true;
1490 if (!fb_find_mode(&cfb
->fb
.var
, &cfb
->fb
, NULL
, NULL
, 0,
1491 &cyber2000fb_default_mode
, 8)) {
1492 printk(KERN_ERR
"%s: no valid mode found\n", cfb
->fb
.fix
.id
);
1496 cfb
->fb
.var
.yres_virtual
= cfb
->fb
.fix
.smem_len
* 8 /
1497 (cfb
->fb
.var
.bits_per_pixel
* cfb
->fb
.var
.xres_virtual
);
1499 if (cfb
->fb
.var
.yres_virtual
< cfb
->fb
.var
.yres
)
1500 cfb
->fb
.var
.yres_virtual
= cfb
->fb
.var
.yres
;
1502 /* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */
1505 * Calculate the hsync and vsync frequencies. Note that
1506 * we split the 1e12 constant up so that we can preserve
1507 * the precision and fit the results into 32-bit registers.
1508 * (1953125000 * 512 = 1e12)
1510 h_sync
= 1953125000 / cfb
->fb
.var
.pixclock
;
1511 h_sync
= h_sync
* 512 / (cfb
->fb
.var
.xres
+ cfb
->fb
.var
.left_margin
+
1512 cfb
->fb
.var
.right_margin
+ cfb
->fb
.var
.hsync_len
);
1513 v_sync
= h_sync
/ (cfb
->fb
.var
.yres
+ cfb
->fb
.var
.upper_margin
+
1514 cfb
->fb
.var
.lower_margin
+ cfb
->fb
.var
.vsync_len
);
1516 printk(KERN_INFO
"%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
1517 cfb
->fb
.fix
.id
, cfb
->fb
.fix
.smem_len
>> 10,
1518 cfb
->fb
.var
.xres
, cfb
->fb
.var
.yres
,
1519 h_sync
/ 1000, h_sync
% 1000, v_sync
);
1522 cfb
->fb
.device
= &cfb
->dev
->dev
;
1523 err
= register_framebuffer(&cfb
->fb
);
1526 #ifdef CONFIG_FB_CYBER2000_DDC
1527 if (err
&& cfb
->ddc_registered
)
1528 i2c_del_adapter(&cfb
->ddc_adapter
);
1533 static void cyberpro_common_resume(struct cfb_info
*cfb
)
1535 cyberpro_init_hw(cfb
);
1538 * Reprogram the MEM_CTL1 and MEM_CTL2 registers
1540 cyber2000_grphw(EXT_MEM_CTL1
, cfb
->mem_ctl1
, cfb
);
1541 cyber2000_grphw(EXT_MEM_CTL2
, cfb
->mem_ctl2
, cfb
);
1544 * Restore the old video mode and the palette.
1545 * We also need to tell fbcon to redraw the console.
1547 cyber2000fb_set_par(&cfb
->fb
);
1550 #ifdef CONFIG_ARCH_SHARK
1552 #include <mach/framebuffer.h>
1554 static int __devinit
cyberpro_vl_probe(void)
1556 struct cfb_info
*cfb
;
1559 if (!request_mem_region(FB_START
, FB_SIZE
, "CyberPro2010"))
1562 cfb
= cyberpro_alloc_fb_info(ID_CYBERPRO_2010
, "CyberPro2010");
1564 goto failed_release
;
1567 cfb
->region
= ioremap(FB_START
, FB_SIZE
);
1569 goto failed_ioremap
;
1571 cfb
->regs
= cfb
->region
+ MMIO_OFFSET
;
1572 cfb
->fb
.fix
.mmio_start
= FB_START
+ MMIO_OFFSET
;
1573 cfb
->fb
.fix
.smem_start
= FB_START
;
1576 * Bring up the hardware. This is expected to enable access
1577 * to the linear memory region, and allow access to the memory
1578 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
1581 cyber2000fb_writeb(0x18, 0x46e8, cfb
);
1582 cyber2000fb_writeb(0x01, 0x102, cfb
);
1583 cyber2000fb_writeb(0x08, 0x46e8, cfb
);
1584 cyber2000fb_writeb(EXT_BIU_MISC
, 0x3ce, cfb
);
1585 cyber2000fb_writeb(EXT_BIU_MISC_LIN_ENABLE
, 0x3cf, cfb
);
1587 cfb
->mclk_mult
= 0xdb;
1588 cfb
->mclk_div
= 0x54;
1590 err
= cyberpro_common_probe(cfb
);
1594 if (int_cfb_info
== NULL
)
1600 iounmap(cfb
->region
);
1602 cyberpro_free_fb_info(cfb
);
1604 release_mem_region(FB_START
, FB_SIZE
);
1608 #endif /* CONFIG_ARCH_SHARK */
1611 * PCI specific support.
1615 * We need to wake up the CyberPro, and make sure its in linear memory
1616 * mode. Unfortunately, this is specific to the platform and card that
1617 * we are running on.
1619 * On x86 and ARM, should we be initialising the CyberPro first via the
1620 * IO registers, and then the MMIO registers to catch all cases? Can we
1621 * end up in the situation where the chip is in MMIO mode, but not awake
1624 static int cyberpro_pci_enable_mmio(struct cfb_info
*cfb
)
1628 #if defined(__sparc_v9__)
1629 #error "You lose, consult DaveM."
1630 #elif defined(__sparc__)
1632 * SPARC does not have an "outb" instruction, so we generate
1633 * I/O cycles storing into a reserved memory space at
1634 * physical address 0x3000000
1636 unsigned char __iomem
*iop
;
1638 iop
= ioremap(0x3000000, 0x5000);
1640 printk(KERN_ERR
"iga5000: cannot map I/O\n");
1644 writeb(0x18, iop
+ 0x46e8);
1645 writeb(0x01, iop
+ 0x102);
1646 writeb(0x08, iop
+ 0x46e8);
1647 writeb(EXT_BIU_MISC
, iop
+ 0x3ce);
1648 writeb(EXT_BIU_MISC_LIN_ENABLE
, iop
+ 0x3cf);
1653 * Most other machine types are "normal", so
1654 * we use the standard IO-based wakeup.
1659 outb(EXT_BIU_MISC
, 0x3ce);
1660 outb(EXT_BIU_MISC_LIN_ENABLE
, 0x3cf);
1664 * Allow the CyberPro to accept PCI burst accesses
1666 if (cfb
->id
== ID_CYBERPRO_2010
) {
1667 printk(KERN_INFO
"%s: NOT enabling PCI bursts\n",
1670 val
= cyber2000_grphr(EXT_BUS_CTL
, cfb
);
1671 if (!(val
& EXT_BUS_CTL_PCIBURST_WRITE
)) {
1672 printk(KERN_INFO
"%s: enabling PCI bursts\n",
1675 val
|= EXT_BUS_CTL_PCIBURST_WRITE
;
1677 if (cfb
->id
== ID_CYBERPRO_5000
)
1678 val
|= EXT_BUS_CTL_PCIBURST_READ
;
1680 cyber2000_grphw(EXT_BUS_CTL
, val
, cfb
);
1687 static int __devinit
1688 cyberpro_pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1690 struct cfb_info
*cfb
;
1694 sprintf(name
, "CyberPro%4X", id
->device
);
1696 err
= pci_enable_device(dev
);
1701 cfb
= cyberpro_alloc_fb_info(id
->driver_data
, name
);
1703 goto failed_release
;
1705 err
= pci_request_regions(dev
, cfb
->fb
.fix
.id
);
1707 goto failed_regions
;
1710 cfb
->region
= pci_ioremap_bar(dev
, 0);
1712 goto failed_ioremap
;
1714 cfb
->regs
= cfb
->region
+ MMIO_OFFSET
;
1715 cfb
->fb
.fix
.mmio_start
= pci_resource_start(dev
, 0) + MMIO_OFFSET
;
1716 cfb
->fb
.fix
.smem_start
= pci_resource_start(dev
, 0);
1719 * Bring up the hardware. This is expected to enable access
1720 * to the linear memory region, and allow access to the memory
1721 * mapped registers. Also, mem_ctl1 and mem_ctl2 must be
1724 err
= cyberpro_pci_enable_mmio(cfb
);
1729 * Use MCLK from BIOS. FIXME: what about hotplug?
1731 cfb
->mclk_mult
= cyber2000_grphr(EXT_MCLK_MULT
, cfb
);
1732 cfb
->mclk_div
= cyber2000_grphr(EXT_MCLK_DIV
, cfb
);
1736 * MCLK on the NetWinder and the Shark is fixed at 75MHz
1738 if (machine_is_netwinder()) {
1739 cfb
->mclk_mult
= 0xdb;
1740 cfb
->mclk_div
= 0x54;
1744 err
= cyberpro_common_probe(cfb
);
1751 pci_set_drvdata(dev
, cfb
);
1752 if (int_cfb_info
== NULL
)
1758 iounmap(cfb
->region
);
1760 pci_release_regions(dev
);
1762 cyberpro_free_fb_info(cfb
);
1767 static void __devexit
cyberpro_pci_remove(struct pci_dev
*dev
)
1769 struct cfb_info
*cfb
= pci_get_drvdata(dev
);
1773 * If unregister_framebuffer fails, then
1774 * we will be leaving hooks that could cause
1775 * oopsen laying around.
1777 if (unregister_framebuffer(&cfb
->fb
))
1778 printk(KERN_WARNING
"%s: danger Will Robinson, "
1779 "danger danger! Oopsen imminent!\n",
1781 #ifdef CONFIG_FB_CYBER2000_DDC
1782 if (cfb
->ddc_registered
)
1783 i2c_del_adapter(&cfb
->ddc_adapter
);
1785 iounmap(cfb
->region
);
1786 cyberpro_free_fb_info(cfb
);
1789 * Ensure that the driver data is no longer
1792 pci_set_drvdata(dev
, NULL
);
1793 if (cfb
== int_cfb_info
)
1794 int_cfb_info
= NULL
;
1796 pci_release_regions(dev
);
1800 static int cyberpro_pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
1806 * Re-initialise the CyberPro hardware
1808 static int cyberpro_pci_resume(struct pci_dev
*dev
)
1810 struct cfb_info
*cfb
= pci_get_drvdata(dev
);
1813 cyberpro_pci_enable_mmio(cfb
);
1814 cyberpro_common_resume(cfb
);
1820 static struct pci_device_id cyberpro_pci_table
[] = {
1822 * { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
1823 * PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
1825 { PCI_VENDOR_ID_INTERG
, PCI_DEVICE_ID_INTERG_2000
,
1826 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ID_CYBERPRO_2000
},
1827 { PCI_VENDOR_ID_INTERG
, PCI_DEVICE_ID_INTERG_2010
,
1828 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ID_CYBERPRO_2010
},
1829 { PCI_VENDOR_ID_INTERG
, PCI_DEVICE_ID_INTERG_5000
,
1830 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ID_CYBERPRO_5000
},
1834 MODULE_DEVICE_TABLE(pci
, cyberpro_pci_table
);
1836 static struct pci_driver cyberpro_driver
= {
1838 .probe
= cyberpro_pci_probe
,
1839 .remove
= __devexit_p(cyberpro_pci_remove
),
1840 .suspend
= cyberpro_pci_suspend
,
1841 .resume
= cyberpro_pci_resume
,
1842 .id_table
= cyberpro_pci_table
1847 * I don't think we can use the "module_init" stuff here because
1848 * the fbcon stuff may not be initialised yet. Hence the #ifdef
1849 * around module_init.
1851 * Tony: "module_init" is now required
1853 static int __init
cyber2000fb_init(void)
1858 char *option
= NULL
;
1860 if (fb_get_options("cyber2000fb", &option
))
1862 cyber2000fb_setup(option
);
1865 #ifdef CONFIG_ARCH_SHARK
1866 err
= cyberpro_vl_probe();
1871 err
= pci_register_driver(&cyberpro_driver
);
1876 return ret
? err
: 0;
1878 module_init(cyber2000fb_init
);
1880 #ifndef CONFIG_ARCH_SHARK
1881 static void __exit
cyberpro_exit(void)
1883 pci_unregister_driver(&cyberpro_driver
);
1885 module_exit(cyberpro_exit
);
1888 MODULE_AUTHOR("Russell King");
1889 MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
1890 MODULE_LICENSE("GPL");