2 * Samsung SoC DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
22 #include <video/exynos_dp.h>
24 #include "exynos_dp_core.h"
26 static int exynos_dp_init_dp(struct exynos_dp_device
*dp
)
30 exynos_dp_swreset(dp
);
32 exynos_dp_init_analog_param(dp
);
33 exynos_dp_init_interrupt(dp
);
35 /* SW defined function Normal operation */
36 exynos_dp_enable_sw_function(dp
);
38 exynos_dp_config_interrupt(dp
);
39 exynos_dp_init_analog_func(dp
);
41 exynos_dp_init_hpd(dp
);
42 exynos_dp_init_aux(dp
);
47 static int exynos_dp_detect_hpd(struct exynos_dp_device
*dp
)
51 exynos_dp_init_hpd(dp
);
53 usleep_range(200, 210);
55 while (exynos_dp_get_plug_in_status(dp
) != 0) {
57 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
58 dev_err(dp
->dev
, "failed to get hpd plug status\n");
67 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data
)
70 unsigned char sum
= 0;
72 for (i
= 0; i
< EDID_BLOCK_LENGTH
; i
++)
73 sum
= sum
+ edid_data
[i
];
78 static int exynos_dp_read_edid(struct exynos_dp_device
*dp
)
80 unsigned char edid
[EDID_BLOCK_LENGTH
* 2];
81 unsigned int extend_block
= 0;
83 unsigned char test_vector
;
87 * EDID device address is 0x50.
88 * However, if necessary, you must have set upper address
89 * into E-EDID in I2C device, 0x30.
92 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
93 exynos_dp_read_byte_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
97 if (extend_block
> 0) {
98 dev_dbg(dp
->dev
, "EDID data includes a single extension!\n");
101 retval
= exynos_dp_read_bytes_from_i2c(dp
, I2C_EDID_DEVICE_ADDR
,
104 &edid
[EDID_HEADER_PATTERN
]);
106 dev_err(dp
->dev
, "EDID Read failed!\n");
109 sum
= exynos_dp_calc_edid_check_sum(edid
);
111 dev_err(dp
->dev
, "EDID bad checksum!\n");
115 /* Read additional EDID data */
116 retval
= exynos_dp_read_bytes_from_i2c(dp
,
117 I2C_EDID_DEVICE_ADDR
,
120 &edid
[EDID_BLOCK_LENGTH
]);
122 dev_err(dp
->dev
, "EDID Read failed!\n");
125 sum
= exynos_dp_calc_edid_check_sum(&edid
[EDID_BLOCK_LENGTH
]);
127 dev_err(dp
->dev
, "EDID bad checksum!\n");
131 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_TEST_REQUEST
,
133 if (test_vector
& DPCD_TEST_EDID_READ
) {
134 exynos_dp_write_byte_to_dpcd(dp
,
135 DPCD_ADDR_TEST_EDID_CHECKSUM
,
136 edid
[EDID_BLOCK_LENGTH
+ EDID_CHECKSUM
]);
137 exynos_dp_write_byte_to_dpcd(dp
,
138 DPCD_ADDR_TEST_RESPONSE
,
139 DPCD_TEST_EDID_CHECKSUM_WRITE
);
142 dev_info(dp
->dev
, "EDID data does not include any extensions.\n");
145 retval
= exynos_dp_read_bytes_from_i2c(dp
,
146 I2C_EDID_DEVICE_ADDR
,
149 &edid
[EDID_HEADER_PATTERN
]);
151 dev_err(dp
->dev
, "EDID Read failed!\n");
154 sum
= exynos_dp_calc_edid_check_sum(edid
);
156 dev_err(dp
->dev
, "EDID bad checksum!\n");
160 exynos_dp_read_byte_from_dpcd(dp
,
161 DPCD_ADDR_TEST_REQUEST
,
163 if (test_vector
& DPCD_TEST_EDID_READ
) {
164 exynos_dp_write_byte_to_dpcd(dp
,
165 DPCD_ADDR_TEST_EDID_CHECKSUM
,
166 edid
[EDID_CHECKSUM
]);
167 exynos_dp_write_byte_to_dpcd(dp
,
168 DPCD_ADDR_TEST_RESPONSE
,
169 DPCD_TEST_EDID_CHECKSUM_WRITE
);
173 dev_err(dp
->dev
, "EDID Read success!\n");
177 static int exynos_dp_handle_edid(struct exynos_dp_device
*dp
)
183 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
184 exynos_dp_read_bytes_from_dpcd(dp
,
189 for (i
= 0; i
< 3; i
++) {
190 retval
= exynos_dp_read_edid(dp
);
198 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device
*dp
,
203 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_LANE_COUNT_SET
, &data
);
206 exynos_dp_write_byte_to_dpcd(dp
, DPCD_ADDR_LANE_COUNT_SET
,
207 DPCD_ENHANCED_FRAME_EN
|
208 DPCD_LANE_COUNT_SET(data
));
210 exynos_dp_write_byte_to_dpcd(dp
, DPCD_ADDR_LANE_COUNT_SET
,
211 DPCD_LANE_COUNT_SET(data
));
214 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device
*dp
)
219 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_MAX_LANE_COUNT
, &data
);
220 retval
= DPCD_ENHANCED_FRAME_CAP(data
);
225 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device
*dp
)
229 data
= exynos_dp_is_enhanced_mode_available(dp
);
230 exynos_dp_enable_rx_to_enhanced_mode(dp
, data
);
231 exynos_dp_enable_enhanced_mode(dp
, data
);
234 static void exynos_dp_training_pattern_dis(struct exynos_dp_device
*dp
)
236 exynos_dp_set_training_pattern(dp
, DP_NONE
);
238 exynos_dp_write_byte_to_dpcd(dp
,
239 DPCD_ADDR_TRAINING_PATTERN_SET
,
240 DPCD_TRAINING_PATTERN_DISABLED
);
243 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device
*dp
,
244 int pre_emphasis
, int lane
)
248 exynos_dp_set_lane0_pre_emphasis(dp
, pre_emphasis
);
251 exynos_dp_set_lane1_pre_emphasis(dp
, pre_emphasis
);
255 exynos_dp_set_lane2_pre_emphasis(dp
, pre_emphasis
);
259 exynos_dp_set_lane3_pre_emphasis(dp
, pre_emphasis
);
264 static void exynos_dp_link_start(struct exynos_dp_device
*dp
)
270 lane_count
= dp
->link_train
.lane_count
;
272 dp
->link_train
.lt_state
= CLOCK_RECOVERY
;
273 dp
->link_train
.eq_loop
= 0;
275 for (lane
= 0; lane
< lane_count
; lane
++)
276 dp
->link_train
.cr_loop
[lane
] = 0;
278 /* Set sink to D0 (Sink Not Ready) mode. */
279 exynos_dp_write_byte_to_dpcd(dp
, DPCD_ADDR_SINK_POWER_STATE
,
280 DPCD_SET_POWER_STATE_D0
);
282 /* Set link rate and count as you want to establish*/
283 exynos_dp_set_link_bandwidth(dp
, dp
->link_train
.link_rate
);
284 exynos_dp_set_lane_count(dp
, dp
->link_train
.lane_count
);
286 /* Setup RX configuration */
287 buf
[0] = dp
->link_train
.link_rate
;
288 buf
[1] = dp
->link_train
.lane_count
;
289 exynos_dp_write_bytes_to_dpcd(dp
, DPCD_ADDR_LINK_BW_SET
,
292 /* Set TX pre-emphasis to minimum */
293 for (lane
= 0; lane
< lane_count
; lane
++)
294 exynos_dp_set_lane_lane_pre_emphasis(dp
,
295 PRE_EMPHASIS_LEVEL_0
, lane
);
297 /* Set training pattern 1 */
298 exynos_dp_set_training_pattern(dp
, TRAINING_PTN1
);
300 /* Set RX training pattern */
301 exynos_dp_write_byte_to_dpcd(dp
,
302 DPCD_ADDR_TRAINING_PATTERN_SET
,
303 DPCD_SCRAMBLING_DISABLED
|
304 DPCD_TRAINING_PATTERN_1
);
306 for (lane
= 0; lane
< lane_count
; lane
++)
307 buf
[lane
] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0
|
308 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0
;
309 exynos_dp_write_bytes_to_dpcd(dp
,
310 DPCD_ADDR_TRAINING_LANE0_SET
,
314 static unsigned char exynos_dp_get_lane_status(u8 link_status
[2], int lane
)
316 int shift
= (lane
& 1) * 4;
317 u8 link_value
= link_status
[lane
>>1];
319 return (link_value
>> shift
) & 0xf;
322 static int exynos_dp_clock_recovery_ok(u8 link_status
[2], int lane_count
)
327 for (lane
= 0; lane
< lane_count
; lane
++) {
328 lane_status
= exynos_dp_get_lane_status(link_status
, lane
);
329 if ((lane_status
& DPCD_LANE_CR_DONE
) == 0)
335 static int exynos_dp_channel_eq_ok(u8 link_align
[3], int lane_count
)
341 lane_align
= link_align
[2];
342 if ((lane_align
& DPCD_INTERLANE_ALIGN_DONE
) == 0)
345 for (lane
= 0; lane
< lane_count
; lane
++) {
346 lane_status
= exynos_dp_get_lane_status(link_align
, lane
);
347 lane_status
&= DPCD_CHANNEL_EQ_BITS
;
348 if (lane_status
!= DPCD_CHANNEL_EQ_BITS
)
355 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request
[2],
358 int shift
= (lane
& 1) * 4;
359 u8 link_value
= adjust_request
[lane
>>1];
361 return (link_value
>> shift
) & 0x3;
364 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
365 u8 adjust_request
[2],
368 int shift
= (lane
& 1) * 4;
369 u8 link_value
= adjust_request
[lane
>>1];
371 return ((link_value
>> shift
) & 0xc) >> 2;
374 static void exynos_dp_set_lane_link_training(struct exynos_dp_device
*dp
,
375 u8 training_lane_set
, int lane
)
379 exynos_dp_set_lane0_link_training(dp
, training_lane_set
);
382 exynos_dp_set_lane1_link_training(dp
, training_lane_set
);
386 exynos_dp_set_lane2_link_training(dp
, training_lane_set
);
390 exynos_dp_set_lane3_link_training(dp
, training_lane_set
);
395 static unsigned int exynos_dp_get_lane_link_training(
396 struct exynos_dp_device
*dp
,
403 reg
= exynos_dp_get_lane0_link_training(dp
);
406 reg
= exynos_dp_get_lane1_link_training(dp
);
409 reg
= exynos_dp_get_lane2_link_training(dp
);
412 reg
= exynos_dp_get_lane3_link_training(dp
);
422 static void exynos_dp_reduce_link_rate(struct exynos_dp_device
*dp
)
424 exynos_dp_training_pattern_dis(dp
);
425 exynos_dp_set_enhanced_mode(dp
);
427 dp
->link_train
.lt_state
= FAILED
;
430 static int exynos_dp_process_clock_recovery(struct exynos_dp_device
*dp
)
436 u8 adjust_request
[2];
441 usleep_range(100, 101);
443 lane_count
= dp
->link_train
.lane_count
;
445 exynos_dp_read_bytes_from_dpcd(dp
, DPCD_ADDR_LANE0_1_STATUS
,
448 if (exynos_dp_clock_recovery_ok(link_status
, lane_count
) == 0) {
449 /* set training pattern 2 for EQ */
450 exynos_dp_set_training_pattern(dp
, TRAINING_PTN2
);
452 for (lane
= 0; lane
< lane_count
; lane
++) {
453 exynos_dp_read_bytes_from_dpcd(dp
,
454 DPCD_ADDR_ADJUST_REQUEST_LANE0_1
,
456 voltage_swing
= exynos_dp_get_adjust_request_voltage(
457 adjust_request
, lane
);
458 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
459 adjust_request
, lane
);
460 training_lane
= DPCD_VOLTAGE_SWING_SET(voltage_swing
) |
461 DPCD_PRE_EMPHASIS_SET(pre_emphasis
);
463 if (voltage_swing
== VOLTAGE_LEVEL_3
)
464 training_lane
|= DPCD_MAX_SWING_REACHED
;
465 if (pre_emphasis
== PRE_EMPHASIS_LEVEL_3
)
466 training_lane
|= DPCD_MAX_PRE_EMPHASIS_REACHED
;
468 dp
->link_train
.training_lane
[lane
] = training_lane
;
470 exynos_dp_set_lane_link_training(dp
,
471 dp
->link_train
.training_lane
[lane
],
475 exynos_dp_write_byte_to_dpcd(dp
,
476 DPCD_ADDR_TRAINING_PATTERN_SET
,
477 DPCD_SCRAMBLING_DISABLED
|
478 DPCD_TRAINING_PATTERN_2
);
480 exynos_dp_write_bytes_to_dpcd(dp
,
481 DPCD_ADDR_TRAINING_LANE0_SET
,
483 dp
->link_train
.training_lane
);
485 dev_info(dp
->dev
, "Link Training Clock Recovery success\n");
486 dp
->link_train
.lt_state
= EQUALIZER_TRAINING
;
488 for (lane
= 0; lane
< lane_count
; lane
++) {
489 training_lane
= exynos_dp_get_lane_link_training(
491 exynos_dp_read_bytes_from_dpcd(dp
,
492 DPCD_ADDR_ADJUST_REQUEST_LANE0_1
,
494 voltage_swing
= exynos_dp_get_adjust_request_voltage(
495 adjust_request
, lane
);
496 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
497 adjust_request
, lane
);
499 if (voltage_swing
== VOLTAGE_LEVEL_3
||
500 pre_emphasis
== PRE_EMPHASIS_LEVEL_3
) {
501 dev_err(dp
->dev
, "voltage or pre emphasis reached max level\n");
502 goto reduce_link_rate
;
505 if ((DPCD_VOLTAGE_SWING_GET(training_lane
) ==
507 (DPCD_PRE_EMPHASIS_GET(training_lane
) ==
509 dp
->link_train
.cr_loop
[lane
]++;
510 if (dp
->link_train
.cr_loop
[lane
] == MAX_CR_LOOP
) {
511 dev_err(dp
->dev
, "CR Max loop\n");
512 goto reduce_link_rate
;
516 training_lane
= DPCD_VOLTAGE_SWING_SET(voltage_swing
) |
517 DPCD_PRE_EMPHASIS_SET(pre_emphasis
);
519 if (voltage_swing
== VOLTAGE_LEVEL_3
)
520 training_lane
|= DPCD_MAX_SWING_REACHED
;
521 if (pre_emphasis
== PRE_EMPHASIS_LEVEL_3
)
522 training_lane
|= DPCD_MAX_PRE_EMPHASIS_REACHED
;
524 dp
->link_train
.training_lane
[lane
] = training_lane
;
526 exynos_dp_set_lane_link_training(dp
,
527 dp
->link_train
.training_lane
[lane
], lane
);
530 exynos_dp_write_bytes_to_dpcd(dp
,
531 DPCD_ADDR_TRAINING_LANE0_SET
,
533 dp
->link_train
.training_lane
);
539 exynos_dp_reduce_link_rate(dp
);
543 static int exynos_dp_process_equalizer_training(struct exynos_dp_device
*dp
)
551 u8 adjust_request
[2];
556 usleep_range(400, 401);
558 lane_count
= dp
->link_train
.lane_count
;
560 exynos_dp_read_bytes_from_dpcd(dp
, DPCD_ADDR_LANE0_1_STATUS
,
563 if (exynos_dp_clock_recovery_ok(link_status
, lane_count
) == 0) {
564 link_align
[0] = link_status
[0];
565 link_align
[1] = link_status
[1];
567 exynos_dp_read_byte_from_dpcd(dp
,
568 DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED
,
571 for (lane
= 0; lane
< lane_count
; lane
++) {
572 exynos_dp_read_bytes_from_dpcd(dp
,
573 DPCD_ADDR_ADJUST_REQUEST_LANE0_1
,
575 voltage_swing
= exynos_dp_get_adjust_request_voltage(
576 adjust_request
, lane
);
577 pre_emphasis
= exynos_dp_get_adjust_request_pre_emphasis(
578 adjust_request
, lane
);
579 training_lane
= DPCD_VOLTAGE_SWING_SET(voltage_swing
) |
580 DPCD_PRE_EMPHASIS_SET(pre_emphasis
);
582 if (voltage_swing
== VOLTAGE_LEVEL_3
)
583 training_lane
|= DPCD_MAX_SWING_REACHED
;
584 if (pre_emphasis
== PRE_EMPHASIS_LEVEL_3
)
585 training_lane
|= DPCD_MAX_PRE_EMPHASIS_REACHED
;
587 dp
->link_train
.training_lane
[lane
] = training_lane
;
590 if (exynos_dp_channel_eq_ok(link_align
, lane_count
) == 0) {
591 /* traing pattern Set to Normal */
592 exynos_dp_training_pattern_dis(dp
);
594 dev_info(dp
->dev
, "Link Training success!\n");
596 exynos_dp_get_link_bandwidth(dp
, ®
);
597 dp
->link_train
.link_rate
= reg
;
598 dev_dbg(dp
->dev
, "final bandwidth = %.2x\n",
599 dp
->link_train
.link_rate
);
601 exynos_dp_get_lane_count(dp
, ®
);
602 dp
->link_train
.lane_count
= reg
;
603 dev_dbg(dp
->dev
, "final lane count = %.2x\n",
604 dp
->link_train
.lane_count
);
606 /* set enhanced mode if available */
607 exynos_dp_set_enhanced_mode(dp
);
608 dp
->link_train
.lt_state
= FINISHED
;
611 dp
->link_train
.eq_loop
++;
613 if (dp
->link_train
.eq_loop
> MAX_EQ_LOOP
) {
614 dev_err(dp
->dev
, "EQ Max loop\n");
615 goto reduce_link_rate
;
618 for (lane
= 0; lane
< lane_count
; lane
++)
619 exynos_dp_set_lane_link_training(dp
,
620 dp
->link_train
.training_lane
[lane
],
623 exynos_dp_write_bytes_to_dpcd(dp
,
624 DPCD_ADDR_TRAINING_LANE0_SET
,
626 dp
->link_train
.training_lane
);
629 goto reduce_link_rate
;
635 exynos_dp_reduce_link_rate(dp
);
639 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device
*dp
,
645 * For DP rev.1.1, Maximum link rate of Main Link lanes
646 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
648 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_MAX_LINK_RATE
, &data
);
652 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device
*dp
,
658 * For DP rev.1.1, Maximum number of Main Link lanes
659 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
661 exynos_dp_read_byte_from_dpcd(dp
, DPCD_ADDR_MAX_LANE_COUNT
, &data
);
662 *lane_count
= DPCD_MAX_LANE_COUNT(data
);
665 static void exynos_dp_init_training(struct exynos_dp_device
*dp
,
666 enum link_lane_count_type max_lane
,
667 enum link_rate_type max_rate
)
670 * MACRO_RST must be applied after the PLL_LOCK to avoid
671 * the DP inter pair skew issue for at least 10 us
673 exynos_dp_reset_macro(dp
);
675 /* Initialize by reading RX's DPCD */
676 exynos_dp_get_max_rx_bandwidth(dp
, &dp
->link_train
.link_rate
);
677 exynos_dp_get_max_rx_lane_count(dp
, &dp
->link_train
.lane_count
);
679 if ((dp
->link_train
.link_rate
!= LINK_RATE_1_62GBPS
) &&
680 (dp
->link_train
.link_rate
!= LINK_RATE_2_70GBPS
)) {
681 dev_err(dp
->dev
, "Rx Max Link Rate is abnormal :%x !\n",
682 dp
->link_train
.link_rate
);
683 dp
->link_train
.link_rate
= LINK_RATE_1_62GBPS
;
686 if (dp
->link_train
.lane_count
== 0) {
687 dev_err(dp
->dev
, "Rx Max Lane count is abnormal :%x !\n",
688 dp
->link_train
.lane_count
);
689 dp
->link_train
.lane_count
= (u8
)LANE_COUNT1
;
692 /* Setup TX lane count & rate */
693 if (dp
->link_train
.lane_count
> max_lane
)
694 dp
->link_train
.lane_count
= max_lane
;
695 if (dp
->link_train
.link_rate
> max_rate
)
696 dp
->link_train
.link_rate
= max_rate
;
698 /* All DP analog module power up */
699 exynos_dp_set_analog_power_down(dp
, POWER_ALL
, 0);
702 static int exynos_dp_sw_link_training(struct exynos_dp_device
*dp
)
705 int training_finished
= 0;
707 dp
->link_train
.lt_state
= START
;
710 while (!training_finished
) {
711 switch (dp
->link_train
.lt_state
) {
713 exynos_dp_link_start(dp
);
716 retval
= exynos_dp_process_clock_recovery(dp
);
718 dev_err(dp
->dev
, "LT CR failed!\n");
720 case EQUALIZER_TRAINING
:
721 retval
= exynos_dp_process_equalizer_training(dp
);
723 dev_err(dp
->dev
, "LT EQ failed!\n");
726 training_finished
= 1;
736 static int exynos_dp_set_link_train(struct exynos_dp_device
*dp
,
743 for (i
= 0; i
< DP_TIMEOUT_LOOP_COUNT
; i
++) {
744 exynos_dp_init_training(dp
, count
, bwtype
);
745 retval
= exynos_dp_sw_link_training(dp
);
749 usleep_range(100, 110);
755 static int exynos_dp_config_video(struct exynos_dp_device
*dp
,
756 struct video_info
*video_info
)
759 int timeout_loop
= 0;
762 exynos_dp_config_video_slave_mode(dp
, video_info
);
764 exynos_dp_set_video_color_format(dp
, video_info
->color_depth
,
765 video_info
->color_space
,
766 video_info
->dynamic_range
,
767 video_info
->ycbcr_coeff
);
769 if (exynos_dp_get_pll_lock_status(dp
) == PLL_UNLOCKED
) {
770 dev_err(dp
->dev
, "PLL is not locked yet.\n");
776 if (exynos_dp_is_slave_video_stream_clock_on(dp
) == 0)
778 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
779 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
786 /* Set to use the register calculated M/N video */
787 exynos_dp_set_video_cr_mn(dp
, CALCULATED_M
, 0, 0);
789 /* For video bist, Video timing must be generated by register */
790 exynos_dp_set_video_timing_mode(dp
, VIDEO_TIMING_FROM_CAPTURE
);
792 /* Disable video mute */
793 exynos_dp_enable_video_mute(dp
, 0);
795 /* Configure video slave mode */
796 exynos_dp_enable_video_master(dp
, 0);
799 exynos_dp_start_video(dp
);
805 if (exynos_dp_is_video_stream_on(dp
) == 0) {
809 } else if (done_count
) {
812 if (DP_TIMEOUT_LOOP_COUNT
< timeout_loop
) {
813 dev_err(dp
->dev
, "Timeout of video streamclk ok\n");
817 usleep_range(1000, 1001);
821 dev_err(dp
->dev
, "Video stream is not detected!\n");
826 static void exynos_dp_enable_scramble(struct exynos_dp_device
*dp
, bool enable
)
831 exynos_dp_enable_scrambling(dp
);
833 exynos_dp_read_byte_from_dpcd(dp
,
834 DPCD_ADDR_TRAINING_PATTERN_SET
,
836 exynos_dp_write_byte_to_dpcd(dp
,
837 DPCD_ADDR_TRAINING_PATTERN_SET
,
838 (u8
)(data
& ~DPCD_SCRAMBLING_DISABLED
));
840 exynos_dp_disable_scrambling(dp
);
842 exynos_dp_read_byte_from_dpcd(dp
,
843 DPCD_ADDR_TRAINING_PATTERN_SET
,
845 exynos_dp_write_byte_to_dpcd(dp
,
846 DPCD_ADDR_TRAINING_PATTERN_SET
,
847 (u8
)(data
| DPCD_SCRAMBLING_DISABLED
));
851 static irqreturn_t
exynos_dp_irq_handler(int irq
, void *arg
)
853 struct exynos_dp_device
*dp
= arg
;
855 dev_err(dp
->dev
, "exynos_dp_irq_handler\n");
859 static int __devinit
exynos_dp_probe(struct platform_device
*pdev
)
861 struct resource
*res
;
862 struct exynos_dp_device
*dp
;
863 struct exynos_dp_platdata
*pdata
;
867 pdata
= pdev
->dev
.platform_data
;
869 dev_err(&pdev
->dev
, "no platform data\n");
873 dp
= devm_kzalloc(&pdev
->dev
, sizeof(struct exynos_dp_device
),
876 dev_err(&pdev
->dev
, "no memory for device data\n");
880 dp
->dev
= &pdev
->dev
;
882 dp
->clock
= devm_clk_get(&pdev
->dev
, "dp");
883 if (IS_ERR(dp
->clock
)) {
884 dev_err(&pdev
->dev
, "failed to get clock\n");
885 return PTR_ERR(dp
->clock
);
888 clk_prepare_enable(dp
->clock
);
890 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
892 dp
->reg_base
= devm_request_and_ioremap(&pdev
->dev
, res
);
894 dev_err(&pdev
->dev
, "failed to ioremap\n");
898 dp
->irq
= platform_get_irq(pdev
, 0);
900 dev_err(&pdev
->dev
, "failed to get irq\n");
904 ret
= devm_request_irq(&pdev
->dev
, dp
->irq
, exynos_dp_irq_handler
, 0,
907 dev_err(&pdev
->dev
, "failed to request irq\n");
911 dp
->video_info
= pdata
->video_info
;
915 exynos_dp_init_dp(dp
);
917 ret
= exynos_dp_detect_hpd(dp
);
919 dev_err(&pdev
->dev
, "unable to detect hpd\n");
923 exynos_dp_handle_edid(dp
);
925 ret
= exynos_dp_set_link_train(dp
, dp
->video_info
->lane_count
,
926 dp
->video_info
->link_rate
);
928 dev_err(&pdev
->dev
, "unable to do link train\n");
932 exynos_dp_enable_scramble(dp
, 1);
933 exynos_dp_enable_rx_to_enhanced_mode(dp
, 1);
934 exynos_dp_enable_enhanced_mode(dp
, 1);
936 exynos_dp_set_lane_count(dp
, dp
->video_info
->lane_count
);
937 exynos_dp_set_link_bandwidth(dp
, dp
->video_info
->link_rate
);
939 exynos_dp_init_video(dp
);
940 ret
= exynos_dp_config_video(dp
, dp
->video_info
);
942 dev_err(&pdev
->dev
, "unable to config video\n");
946 platform_set_drvdata(pdev
, dp
);
951 static int __devexit
exynos_dp_remove(struct platform_device
*pdev
)
953 struct exynos_dp_platdata
*pdata
= pdev
->dev
.platform_data
;
954 struct exynos_dp_device
*dp
= platform_get_drvdata(pdev
);
956 if (pdata
&& pdata
->phy_exit
)
959 clk_disable_unprepare(dp
->clock
);
964 #ifdef CONFIG_PM_SLEEP
965 static int exynos_dp_suspend(struct device
*dev
)
967 struct platform_device
*pdev
= to_platform_device(dev
);
968 struct exynos_dp_platdata
*pdata
= pdev
->dev
.platform_data
;
969 struct exynos_dp_device
*dp
= platform_get_drvdata(pdev
);
971 if (pdata
&& pdata
->phy_exit
)
974 clk_disable_unprepare(dp
->clock
);
979 static int exynos_dp_resume(struct device
*dev
)
981 struct platform_device
*pdev
= to_platform_device(dev
);
982 struct exynos_dp_platdata
*pdata
= pdev
->dev
.platform_data
;
983 struct exynos_dp_device
*dp
= platform_get_drvdata(pdev
);
985 if (pdata
&& pdata
->phy_init
)
988 clk_prepare_enable(dp
->clock
);
990 exynos_dp_init_dp(dp
);
992 exynos_dp_detect_hpd(dp
);
993 exynos_dp_handle_edid(dp
);
995 exynos_dp_set_link_train(dp
, dp
->video_info
->lane_count
,
996 dp
->video_info
->link_rate
);
998 exynos_dp_enable_scramble(dp
, 1);
999 exynos_dp_enable_rx_to_enhanced_mode(dp
, 1);
1000 exynos_dp_enable_enhanced_mode(dp
, 1);
1002 exynos_dp_set_lane_count(dp
, dp
->video_info
->lane_count
);
1003 exynos_dp_set_link_bandwidth(dp
, dp
->video_info
->link_rate
);
1005 exynos_dp_init_video(dp
);
1006 exynos_dp_config_video(dp
, dp
->video_info
);
1012 static const struct dev_pm_ops exynos_dp_pm_ops
= {
1013 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend
, exynos_dp_resume
)
1016 static struct platform_driver exynos_dp_driver
= {
1017 .probe
= exynos_dp_probe
,
1018 .remove
= __devexit_p(exynos_dp_remove
),
1020 .name
= "exynos-dp",
1021 .owner
= THIS_MODULE
,
1022 .pm
= &exynos_dp_pm_ops
,
1026 module_platform_driver(exynos_dp_driver
);
1028 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1029 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1030 MODULE_LICENSE("GPL");