]>
git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - drivers/video/fbdev/amba-clcd.c
2 * linux/drivers/video/amba-clcd.c
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
11 * ARM PrimeCell PL110 Color LCD Controller
13 #include <linux/dma-mapping.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/list.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/clcd.h>
27 #include <linux/bitops.h>
28 #include <linux/clk.h>
29 #include <linux/hardirq.h>
31 #include <linux/of_address.h>
32 #include <linux/of_graph.h>
33 #include <video/display_timing.h>
34 #include <video/of_display_timing.h>
35 #include <video/videomode.h>
37 #include <asm/sizes.h>
39 #define to_clcd(info) container_of(info, struct clcd_fb, fb)
41 /* This is limited to 16 characters when displayed by X startup */
42 static const char *clcd_name
= "CLCD FB";
45 * Unfortunately, the enable/disable functions may be called either from
46 * process or IRQ context, and we _need_ to delay. This is _not_ good.
48 static inline void clcdfb_sleep(unsigned int ms
)
57 static inline void clcdfb_set_start(struct clcd_fb
*fb
)
59 unsigned long ustart
= fb
->fb
.fix
.smem_start
;
62 ustart
+= fb
->fb
.var
.yoffset
* fb
->fb
.fix
.line_length
;
63 lstart
= ustart
+ fb
->fb
.var
.yres
* fb
->fb
.fix
.line_length
/ 2;
65 writel(ustart
, fb
->regs
+ CLCD_UBAS
);
66 writel(lstart
, fb
->regs
+ CLCD_LBAS
);
69 static void clcdfb_disable(struct clcd_fb
*fb
)
73 if (fb
->board
->disable
)
74 fb
->board
->disable(fb
);
76 val
= readl(fb
->regs
+ fb
->off_cntl
);
77 if (val
& CNTL_LCDPWR
) {
79 writel(val
, fb
->regs
+ fb
->off_cntl
);
83 if (val
& CNTL_LCDEN
) {
85 writel(val
, fb
->regs
+ fb
->off_cntl
);
89 * Disable CLCD clock source.
91 if (fb
->clk_enabled
) {
92 fb
->clk_enabled
= false;
97 static void clcdfb_enable(struct clcd_fb
*fb
, u32 cntl
)
100 * Enable the CLCD clock source.
102 if (!fb
->clk_enabled
) {
103 fb
->clk_enabled
= true;
108 * Bring up by first enabling..
111 writel(cntl
, fb
->regs
+ fb
->off_cntl
);
116 * and now apply power.
119 writel(cntl
, fb
->regs
+ fb
->off_cntl
);
122 * finally, enable the interface.
124 if (fb
->board
->enable
)
125 fb
->board
->enable(fb
);
129 clcdfb_set_bitfields(struct clcd_fb
*fb
, struct fb_var_screeninfo
*var
)
134 if (fb
->panel
->caps
&& fb
->board
->caps
)
135 caps
= fb
->panel
->caps
& fb
->board
->caps
;
137 /* Old way of specifying what can be used */
138 caps
= fb
->panel
->cntl
& CNTL_BGR
?
139 CLCD_CAP_BGR
: CLCD_CAP_RGB
;
140 /* But mask out 444 modes as they weren't supported */
141 caps
&= ~CLCD_CAP_444
;
144 /* Only TFT panels can do RGB888/BGR888 */
145 if (!(fb
->panel
->cntl
& CNTL_LCDTFT
))
146 caps
&= ~CLCD_CAP_888
;
148 memset(&var
->transp
, 0, sizeof(var
->transp
));
150 var
->red
.msb_right
= 0;
151 var
->green
.msb_right
= 0;
152 var
->blue
.msb_right
= 0;
154 switch (var
->bits_per_pixel
) {
159 /* If we can't do 5551, reject */
160 caps
&= CLCD_CAP_5551
;
166 var
->red
.length
= var
->bits_per_pixel
;
168 var
->green
.length
= var
->bits_per_pixel
;
169 var
->green
.offset
= 0;
170 var
->blue
.length
= var
->bits_per_pixel
;
171 var
->blue
.offset
= 0;
175 /* If we can't do 444, 5551 or 565, reject */
176 if (!(caps
& (CLCD_CAP_444
| CLCD_CAP_5551
| CLCD_CAP_565
))) {
182 * Green length can be 4, 5 or 6 depending whether
183 * we're operating in 444, 5551 or 565 mode.
185 if (var
->green
.length
== 4 && caps
& CLCD_CAP_444
)
186 caps
&= CLCD_CAP_444
;
187 if (var
->green
.length
== 5 && caps
& CLCD_CAP_5551
)
188 caps
&= CLCD_CAP_5551
;
189 else if (var
->green
.length
== 6 && caps
& CLCD_CAP_565
)
190 caps
&= CLCD_CAP_565
;
193 * PL110 officially only supports RGB555,
194 * but may be wired up to allow RGB565.
196 if (caps
& CLCD_CAP_565
) {
197 var
->green
.length
= 6;
198 caps
&= CLCD_CAP_565
;
199 } else if (caps
& CLCD_CAP_5551
) {
200 var
->green
.length
= 5;
201 caps
&= CLCD_CAP_5551
;
203 var
->green
.length
= 4;
204 caps
&= CLCD_CAP_444
;
208 if (var
->green
.length
>= 5) {
210 var
->blue
.length
= 5;
213 var
->blue
.length
= 4;
217 /* If we can't do 888, reject */
218 caps
&= CLCD_CAP_888
;
225 var
->green
.length
= 8;
226 var
->blue
.length
= 8;
234 * >= 16bpp displays have separate colour component bitfields
235 * encoded in the pixel data. Calculate their position from
236 * the bitfield length defined above.
238 if (ret
== 0 && var
->bits_per_pixel
>= 16) {
241 bgr
= caps
& CLCD_CAP_BGR
&& var
->blue
.offset
== 0;
242 rgb
= caps
& CLCD_CAP_RGB
&& var
->red
.offset
== 0;
246 * The requested format was not possible, try just
247 * our capabilities. One of BGR or RGB must be
250 bgr
= caps
& CLCD_CAP_BGR
;
253 var
->blue
.offset
= 0;
254 var
->green
.offset
= var
->blue
.offset
+ var
->blue
.length
;
255 var
->red
.offset
= var
->green
.offset
+ var
->green
.length
;
258 var
->green
.offset
= var
->red
.offset
+ var
->red
.length
;
259 var
->blue
.offset
= var
->green
.offset
+ var
->green
.length
;
266 static int clcdfb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
268 struct clcd_fb
*fb
= to_clcd(info
);
271 if (fb
->board
->check
)
272 ret
= fb
->board
->check(fb
, var
);
275 var
->xres_virtual
* var
->bits_per_pixel
/ 8 *
276 var
->yres_virtual
> fb
->fb
.fix
.smem_len
)
280 ret
= clcdfb_set_bitfields(fb
, var
);
285 static int clcdfb_set_par(struct fb_info
*info
)
287 struct clcd_fb
*fb
= to_clcd(info
);
288 struct clcd_regs regs
;
290 fb
->fb
.fix
.line_length
= fb
->fb
.var
.xres_virtual
*
291 fb
->fb
.var
.bits_per_pixel
/ 8;
293 if (fb
->fb
.var
.bits_per_pixel
<= 8)
294 fb
->fb
.fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
296 fb
->fb
.fix
.visual
= FB_VISUAL_TRUECOLOR
;
298 fb
->board
->decode(fb
, ®s
);
302 writel(regs
.tim0
, fb
->regs
+ CLCD_TIM0
);
303 writel(regs
.tim1
, fb
->regs
+ CLCD_TIM1
);
304 writel(regs
.tim2
, fb
->regs
+ CLCD_TIM2
);
305 writel(regs
.tim3
, fb
->regs
+ CLCD_TIM3
);
307 clcdfb_set_start(fb
);
309 clk_set_rate(fb
->clk
, (1000000000 / regs
.pixclock
) * 1000);
311 fb
->clcd_cntl
= regs
.cntl
;
313 clcdfb_enable(fb
, regs
.cntl
);
317 "CLCD: Registers set to\n"
318 " %08x %08x %08x %08x\n"
319 " %08x %08x %08x %08x\n",
320 readl(fb
->regs
+ CLCD_TIM0
), readl(fb
->regs
+ CLCD_TIM1
),
321 readl(fb
->regs
+ CLCD_TIM2
), readl(fb
->regs
+ CLCD_TIM3
),
322 readl(fb
->regs
+ CLCD_UBAS
), readl(fb
->regs
+ CLCD_LBAS
),
323 readl(fb
->regs
+ fb
->off_ienb
), readl(fb
->regs
+ fb
->off_cntl
));
329 static inline u32
convert_bitfield(int val
, struct fb_bitfield
*bf
)
331 unsigned int mask
= (1 << bf
->length
) - 1;
333 return (val
>> (16 - bf
->length
) & mask
) << bf
->offset
;
337 * Set a single color register. The values supplied have a 16 bit
338 * magnitude. Return != 0 for invalid regno.
341 clcdfb_setcolreg(unsigned int regno
, unsigned int red
, unsigned int green
,
342 unsigned int blue
, unsigned int transp
, struct fb_info
*info
)
344 struct clcd_fb
*fb
= to_clcd(info
);
347 fb
->cmap
[regno
] = convert_bitfield(transp
, &fb
->fb
.var
.transp
) |
348 convert_bitfield(blue
, &fb
->fb
.var
.blue
) |
349 convert_bitfield(green
, &fb
->fb
.var
.green
) |
350 convert_bitfield(red
, &fb
->fb
.var
.red
);
352 if (fb
->fb
.fix
.visual
== FB_VISUAL_PSEUDOCOLOR
&& regno
< 256) {
353 int hw_reg
= CLCD_PALETTE
+ ((regno
* 2) & ~3);
354 u32 val
, mask
, newval
;
356 newval
= (red
>> 11) & 0x001f;
357 newval
|= (green
>> 6) & 0x03e0;
358 newval
|= (blue
>> 1) & 0x7c00;
361 * 3.2.11: if we're configured for big endian
362 * byte order, the palette entries are swapped.
364 if (fb
->clcd_cntl
& CNTL_BEBO
)
374 val
= readl(fb
->regs
+ hw_reg
) & mask
;
375 writel(val
| newval
, fb
->regs
+ hw_reg
);
382 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
383 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
384 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
385 * to e.g. a video mode which doesn't support it. Implements VESA suspend
386 * and powerdown modes on hardware that supports disabling hsync/vsync:
387 * blank_mode == 2: suspend vsync
388 * blank_mode == 3: suspend hsync
389 * blank_mode == 4: powerdown
391 static int clcdfb_blank(int blank_mode
, struct fb_info
*info
)
393 struct clcd_fb
*fb
= to_clcd(info
);
395 if (blank_mode
!= 0) {
398 clcdfb_enable(fb
, fb
->clcd_cntl
);
403 static int clcdfb_mmap(struct fb_info
*info
,
404 struct vm_area_struct
*vma
)
406 struct clcd_fb
*fb
= to_clcd(info
);
407 unsigned long len
, off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
410 len
= info
->fix
.smem_len
;
412 if (off
<= len
&& vma
->vm_end
- vma
->vm_start
<= len
- off
&&
414 ret
= fb
->board
->mmap(fb
, vma
);
419 static struct fb_ops clcdfb_ops
= {
420 .owner
= THIS_MODULE
,
421 .fb_check_var
= clcdfb_check_var
,
422 .fb_set_par
= clcdfb_set_par
,
423 .fb_setcolreg
= clcdfb_setcolreg
,
424 .fb_blank
= clcdfb_blank
,
425 .fb_fillrect
= cfb_fillrect
,
426 .fb_copyarea
= cfb_copyarea
,
427 .fb_imageblit
= cfb_imageblit
,
428 .fb_mmap
= clcdfb_mmap
,
431 static int clcdfb_register(struct clcd_fb
*fb
)
436 * ARM PL111 always has IENB at 0x1c; it's only PL110
437 * which is reversed on some platforms.
439 if (amba_manf(fb
->dev
) == 0x41 && amba_part(fb
->dev
) == 0x111) {
440 fb
->off_ienb
= CLCD_PL111_IENB
;
441 fb
->off_cntl
= CLCD_PL111_CNTL
;
443 if (of_machine_is_compatible("arm,versatile-ab") ||
444 of_machine_is_compatible("arm,versatile-pb")) {
445 fb
->off_ienb
= CLCD_PL111_IENB
;
446 fb
->off_cntl
= CLCD_PL111_CNTL
;
448 fb
->off_ienb
= CLCD_PL110_IENB
;
449 fb
->off_cntl
= CLCD_PL110_CNTL
;
453 fb
->clk
= clk_get(&fb
->dev
->dev
, NULL
);
454 if (IS_ERR(fb
->clk
)) {
455 ret
= PTR_ERR(fb
->clk
);
459 ret
= clk_prepare(fb
->clk
);
463 fb
->fb
.device
= &fb
->dev
->dev
;
465 fb
->fb
.fix
.mmio_start
= fb
->dev
->res
.start
;
466 fb
->fb
.fix
.mmio_len
= resource_size(&fb
->dev
->res
);
468 fb
->regs
= ioremap(fb
->fb
.fix
.mmio_start
, fb
->fb
.fix
.mmio_len
);
470 printk(KERN_ERR
"CLCD: unable to remap registers\n");
475 fb
->fb
.fbops
= &clcdfb_ops
;
476 fb
->fb
.flags
= FBINFO_FLAG_DEFAULT
;
477 fb
->fb
.pseudo_palette
= fb
->cmap
;
479 strncpy(fb
->fb
.fix
.id
, clcd_name
, sizeof(fb
->fb
.fix
.id
));
480 fb
->fb
.fix
.type
= FB_TYPE_PACKED_PIXELS
;
481 fb
->fb
.fix
.type_aux
= 0;
482 fb
->fb
.fix
.xpanstep
= 0;
483 fb
->fb
.fix
.ypanstep
= 0;
484 fb
->fb
.fix
.ywrapstep
= 0;
485 fb
->fb
.fix
.accel
= FB_ACCEL_NONE
;
487 fb
->fb
.var
.xres
= fb
->panel
->mode
.xres
;
488 fb
->fb
.var
.yres
= fb
->panel
->mode
.yres
;
489 fb
->fb
.var
.xres_virtual
= fb
->panel
->mode
.xres
;
490 fb
->fb
.var
.yres_virtual
= fb
->panel
->mode
.yres
;
491 fb
->fb
.var
.bits_per_pixel
= fb
->panel
->bpp
;
492 fb
->fb
.var
.grayscale
= fb
->panel
->grayscale
;
493 fb
->fb
.var
.pixclock
= fb
->panel
->mode
.pixclock
;
494 fb
->fb
.var
.left_margin
= fb
->panel
->mode
.left_margin
;
495 fb
->fb
.var
.right_margin
= fb
->panel
->mode
.right_margin
;
496 fb
->fb
.var
.upper_margin
= fb
->panel
->mode
.upper_margin
;
497 fb
->fb
.var
.lower_margin
= fb
->panel
->mode
.lower_margin
;
498 fb
->fb
.var
.hsync_len
= fb
->panel
->mode
.hsync_len
;
499 fb
->fb
.var
.vsync_len
= fb
->panel
->mode
.vsync_len
;
500 fb
->fb
.var
.sync
= fb
->panel
->mode
.sync
;
501 fb
->fb
.var
.vmode
= fb
->panel
->mode
.vmode
;
502 fb
->fb
.var
.activate
= FB_ACTIVATE_NOW
;
503 fb
->fb
.var
.nonstd
= 0;
504 fb
->fb
.var
.height
= fb
->panel
->height
;
505 fb
->fb
.var
.width
= fb
->panel
->width
;
506 fb
->fb
.var
.accel_flags
= 0;
508 fb
->fb
.monspecs
.hfmin
= 0;
509 fb
->fb
.monspecs
.hfmax
= 100000;
510 fb
->fb
.monspecs
.vfmin
= 0;
511 fb
->fb
.monspecs
.vfmax
= 400;
512 fb
->fb
.monspecs
.dclkmin
= 1000000;
513 fb
->fb
.monspecs
.dclkmax
= 100000000;
516 * Make sure that the bitfields are set appropriately.
518 clcdfb_set_bitfields(fb
, &fb
->fb
.var
);
521 * Allocate colourmap.
523 ret
= fb_alloc_cmap(&fb
->fb
.cmap
, 256, 0);
528 * Ensure interrupts are disabled.
530 writel(0, fb
->regs
+ fb
->off_ienb
);
532 fb_set_var(&fb
->fb
, &fb
->fb
.var
);
534 dev_info(&fb
->dev
->dev
, "%s hardware, %s display\n",
535 fb
->board
->name
, fb
->panel
->mode
.name
);
537 ret
= register_framebuffer(&fb
->fb
);
541 printk(KERN_ERR
"CLCD: cannot register framebuffer (%d)\n", ret
);
543 fb_dealloc_cmap(&fb
->fb
.cmap
);
547 clk_unprepare(fb
->clk
);
555 static int clcdfb_of_get_dpi_panel_mode(struct device_node
*node
,
556 struct fb_videomode
*mode
)
559 struct display_timing timing
;
560 struct videomode video
;
562 err
= of_get_display_timing(node
, "panel-timing", &timing
);
566 videomode_from_timing(&timing
, &video
);
568 err
= fb_videomode_from_videomode(&video
, mode
);
575 static int clcdfb_snprintf_mode(char *buf
, int size
, struct fb_videomode
*mode
)
577 return snprintf(buf
, size
, "%ux%u@%u", mode
->xres
, mode
->yres
,
581 static int clcdfb_of_get_mode(struct device
*dev
, struct device_node
*endpoint
,
582 struct fb_videomode
*mode
)
585 struct device_node
*panel
;
589 panel
= of_graph_get_remote_port_parent(endpoint
);
593 /* Only directly connected DPI panels supported for now */
594 if (of_device_is_compatible(panel
, "panel-dpi"))
595 err
= clcdfb_of_get_dpi_panel_mode(panel
, mode
);
601 len
= clcdfb_snprintf_mode(NULL
, 0, mode
);
602 name
= devm_kzalloc(dev
, len
+ 1, GFP_KERNEL
);
606 clcdfb_snprintf_mode(name
, len
+ 1, mode
);
612 static int clcdfb_of_init_tft_panel(struct clcd_fb
*fb
, u32 r0
, u32 g0
, u32 b0
)
619 { 0x110, 1, 7, 13, CLCD_CAP_5551
},
620 { 0x110, 0, 8, 16, CLCD_CAP_888
},
621 { 0x111, 4, 14, 20, CLCD_CAP_444
},
622 { 0x111, 3, 11, 19, CLCD_CAP_444
| CLCD_CAP_5551
},
623 { 0x111, 3, 10, 19, CLCD_CAP_444
| CLCD_CAP_5551
|
625 { 0x111, 0, 8, 16, CLCD_CAP_444
| CLCD_CAP_5551
|
626 CLCD_CAP_565
| CLCD_CAP_888
},
630 /* Bypass pixel clock divider, data output on the falling edge */
631 fb
->panel
->tim2
= TIM2_BCD
| TIM2_IPC
;
633 /* TFT display, vert. comp. interrupt at the start of the back porch */
634 fb
->panel
->cntl
|= CNTL_LCDTFT
| CNTL_LCDVCOMP(1);
638 /* Match the setup with known variants */
639 for (i
= 0; i
< ARRAY_SIZE(panels
) && !fb
->panel
->caps
; i
++) {
640 if (amba_part(fb
->dev
) != panels
[i
].part
)
642 if (g0
!= panels
[i
].g0
)
644 if (r0
== panels
[i
].r0
&& b0
== panels
[i
].b0
)
645 fb
->panel
->caps
= panels
[i
].caps
;
648 return fb
->panel
->caps
? 0 : -EINVAL
;
651 static int clcdfb_of_init_display(struct clcd_fb
*fb
)
653 struct device_node
*endpoint
;
659 fb
->panel
= devm_kzalloc(&fb
->dev
->dev
, sizeof(*fb
->panel
), GFP_KERNEL
);
663 endpoint
= of_graph_get_next_endpoint(fb
->dev
->dev
.of_node
, NULL
);
667 err
= clcdfb_of_get_mode(&fb
->dev
->dev
, endpoint
, &fb
->panel
->mode
);
671 err
= of_property_read_u32(fb
->dev
->dev
.of_node
, "max-memory-bandwidth",
675 * max_bandwidth is in bytes per second and pixclock in
676 * pico-seconds, so the maximum allowed bits per pixel is
677 * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
678 * Rearrange this calculation to avoid overflow and then ensure
679 * result is a valid format.
681 bpp
= max_bandwidth
/ (1000 / 8)
682 / PICOS2KHZ(fb
->panel
->mode
.pixclock
);
683 bpp
= rounddown_pow_of_two(bpp
);
688 fb
->panel
->bpp
= bpp
;
690 #ifdef CONFIG_CPU_BIG_ENDIAN
691 fb
->panel
->cntl
|= CNTL_BEBO
;
693 fb
->panel
->width
= -1;
694 fb
->panel
->height
= -1;
696 if (of_property_read_u32_array(endpoint
,
697 "arm,pl11x,tft-r0g0b0-pads",
698 tft_r0b0g0
, ARRAY_SIZE(tft_r0b0g0
)) == 0)
699 return clcdfb_of_init_tft_panel(fb
, tft_r0b0g0
[0],
700 tft_r0b0g0
[1], tft_r0b0g0
[2]);
705 static int clcdfb_of_vram_setup(struct clcd_fb
*fb
)
708 struct device_node
*memory
;
711 err
= clcdfb_of_init_display(fb
);
715 memory
= of_parse_phandle(fb
->dev
->dev
.of_node
, "memory-region", 0);
719 fb
->fb
.screen_base
= of_iomap(memory
, 0);
720 if (!fb
->fb
.screen_base
)
723 fb
->fb
.fix
.smem_start
= of_translate_address(memory
,
724 of_get_address(memory
, 0, &size
, NULL
));
725 fb
->fb
.fix
.smem_len
= size
;
730 static int clcdfb_of_vram_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
732 unsigned long off
, user_size
, kernel_size
;
735 off
= vma
->vm_pgoff
<< PAGE_SHIFT
;
736 user_size
= vma
->vm_end
- vma
->vm_start
;
737 kernel_size
= fb
->fb
.fix
.smem_len
;
739 if (off
>= kernel_size
|| user_size
> (kernel_size
- off
))
742 return remap_pfn_range(vma
, vma
->vm_start
,
743 __phys_to_pfn(fb
->fb
.fix
.smem_start
) + vma
->vm_pgoff
,
745 pgprot_writecombine(vma
->vm_page_prot
));
748 static void clcdfb_of_vram_remove(struct clcd_fb
*fb
)
750 iounmap(fb
->fb
.screen_base
);
753 static int clcdfb_of_dma_setup(struct clcd_fb
*fb
)
755 unsigned long framesize
;
759 err
= clcdfb_of_init_display(fb
);
763 framesize
= fb
->panel
->mode
.xres
* fb
->panel
->mode
.yres
*
765 fb
->fb
.screen_base
= dma_alloc_coherent(&fb
->dev
->dev
, framesize
,
767 if (!fb
->fb
.screen_base
)
770 fb
->fb
.fix
.smem_start
= dma
;
771 fb
->fb
.fix
.smem_len
= framesize
;
776 static int clcdfb_of_dma_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
778 return dma_mmap_wc(&fb
->dev
->dev
, vma
, fb
->fb
.screen_base
,
779 fb
->fb
.fix
.smem_start
, fb
->fb
.fix
.smem_len
);
782 static void clcdfb_of_dma_remove(struct clcd_fb
*fb
)
784 dma_free_coherent(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
785 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
788 static struct clcd_board
*clcdfb_of_get_board(struct amba_device
*dev
)
790 struct clcd_board
*board
= devm_kzalloc(&dev
->dev
, sizeof(*board
),
792 struct device_node
*node
= dev
->dev
.of_node
;
797 board
->name
= of_node_full_name(node
);
798 board
->caps
= CLCD_CAP_ALL
;
799 board
->check
= clcdfb_check
;
800 board
->decode
= clcdfb_decode
;
801 if (of_find_property(node
, "memory-region", NULL
)) {
802 board
->setup
= clcdfb_of_vram_setup
;
803 board
->mmap
= clcdfb_of_vram_mmap
;
804 board
->remove
= clcdfb_of_vram_remove
;
806 board
->setup
= clcdfb_of_dma_setup
;
807 board
->mmap
= clcdfb_of_dma_mmap
;
808 board
->remove
= clcdfb_of_dma_remove
;
814 static struct clcd_board
*clcdfb_of_get_board(struct amba_device
*dev
)
820 static int clcdfb_probe(struct amba_device
*dev
, const struct amba_id
*id
)
822 struct clcd_board
*board
= dev_get_platdata(&dev
->dev
);
827 board
= clcdfb_of_get_board(dev
);
832 ret
= dma_set_mask_and_coherent(&dev
->dev
, DMA_BIT_MASK(32));
836 ret
= amba_request_regions(dev
, NULL
);
838 printk(KERN_ERR
"CLCD: unable to reserve regs region\n");
842 fb
= kzalloc(sizeof(struct clcd_fb
), GFP_KERNEL
);
844 printk(KERN_INFO
"CLCD: could not allocate new clcd_fb struct\n");
852 dev_info(&fb
->dev
->dev
, "PL%03x rev%u at 0x%08llx\n",
853 amba_part(dev
), amba_rev(dev
),
854 (unsigned long long)dev
->res
.start
);
856 ret
= fb
->board
->setup(fb
);
860 ret
= clcdfb_register(fb
);
862 amba_set_drvdata(dev
, fb
);
866 fb
->board
->remove(fb
);
870 amba_release_regions(dev
);
875 static int clcdfb_remove(struct amba_device
*dev
)
877 struct clcd_fb
*fb
= amba_get_drvdata(dev
);
880 unregister_framebuffer(&fb
->fb
);
882 fb_dealloc_cmap(&fb
->fb
.cmap
);
884 clk_unprepare(fb
->clk
);
887 fb
->board
->remove(fb
);
891 amba_release_regions(dev
);
896 static struct amba_id clcdfb_id_table
[] = {
904 MODULE_DEVICE_TABLE(amba
, clcdfb_id_table
);
906 static struct amba_driver clcd_driver
= {
908 .name
= "clcd-pl11x",
910 .probe
= clcdfb_probe
,
911 .remove
= clcdfb_remove
,
912 .id_table
= clcdfb_id_table
,
915 static int __init
amba_clcdfb_init(void)
917 if (fb_get_options("ambafb", NULL
))
920 return amba_driver_register(&clcd_driver
);
923 module_init(amba_clcdfb_init
);
925 static void __exit
amba_clcdfb_exit(void)
927 amba_driver_unregister(&clcd_driver
);
930 module_exit(amba_clcdfb_exit
);
932 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
933 MODULE_LICENSE("GPL");