]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/video/fbdev/fsl-diu-fb.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
scsi: qedf: Fix a potential NULL pointer dereference
[mirror_ubuntu-artful-kernel.git] / drivers / video / fbdev / fsl-diu-fb.c
1 /*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include <linux/init.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/uaccess.h>
32 #include <linux/vmalloc.h>
33 #include <linux/spinlock.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36
37 #include <sysdev/fsl_soc.h>
38 #include <linux/fsl-diu-fb.h>
39 #include "edid.h"
40
41 #define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */
42
43 /* HW cursor parameters */
44 #define MAX_CURS 32
45
46 /* INT_STATUS/INT_MASK field descriptions */
47 #define INT_VSYNC 0x01 /* Vsync interrupt */
48 #define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
49 #define INT_UNDRUN 0x04 /* Under run exception interrupt */
50 #define INT_PARERR 0x08 /* Display parameters error interrupt */
51 #define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
52
53 /*
54 * List of supported video modes
55 *
56 * The first entry is the default video mode. The remain entries are in
57 * order if increasing resolution and frequency. The 320x240-60 mode is
58 * the initial AOI for the second and third planes.
59 */
60 static struct fb_videomode fsl_diu_mode_db[] = {
61 {
62 .refresh = 60,
63 .xres = 1024,
64 .yres = 768,
65 .pixclock = 15385,
66 .left_margin = 160,
67 .right_margin = 24,
68 .upper_margin = 29,
69 .lower_margin = 3,
70 .hsync_len = 136,
71 .vsync_len = 6,
72 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
73 .vmode = FB_VMODE_NONINTERLACED
74 },
75 {
76 .refresh = 60,
77 .xres = 320,
78 .yres = 240,
79 .pixclock = 79440,
80 .left_margin = 16,
81 .right_margin = 16,
82 .upper_margin = 16,
83 .lower_margin = 5,
84 .hsync_len = 48,
85 .vsync_len = 1,
86 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
87 .vmode = FB_VMODE_NONINTERLACED
88 },
89 {
90 .refresh = 60,
91 .xres = 640,
92 .yres = 480,
93 .pixclock = 39722,
94 .left_margin = 48,
95 .right_margin = 16,
96 .upper_margin = 33,
97 .lower_margin = 10,
98 .hsync_len = 96,
99 .vsync_len = 2,
100 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
101 .vmode = FB_VMODE_NONINTERLACED
102 },
103 {
104 .refresh = 72,
105 .xres = 640,
106 .yres = 480,
107 .pixclock = 32052,
108 .left_margin = 128,
109 .right_margin = 24,
110 .upper_margin = 28,
111 .lower_margin = 9,
112 .hsync_len = 40,
113 .vsync_len = 3,
114 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
115 .vmode = FB_VMODE_NONINTERLACED
116 },
117 {
118 .refresh = 75,
119 .xres = 640,
120 .yres = 480,
121 .pixclock = 31747,
122 .left_margin = 120,
123 .right_margin = 16,
124 .upper_margin = 16,
125 .lower_margin = 1,
126 .hsync_len = 64,
127 .vsync_len = 3,
128 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
129 .vmode = FB_VMODE_NONINTERLACED
130 },
131 {
132 .refresh = 90,
133 .xres = 640,
134 .yres = 480,
135 .pixclock = 25057,
136 .left_margin = 120,
137 .right_margin = 32,
138 .upper_margin = 14,
139 .lower_margin = 25,
140 .hsync_len = 40,
141 .vsync_len = 14,
142 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
143 .vmode = FB_VMODE_NONINTERLACED
144 },
145 {
146 .refresh = 100,
147 .xres = 640,
148 .yres = 480,
149 .pixclock = 22272,
150 .left_margin = 48,
151 .right_margin = 32,
152 .upper_margin = 17,
153 .lower_margin = 22,
154 .hsync_len = 128,
155 .vsync_len = 12,
156 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
157 .vmode = FB_VMODE_NONINTERLACED
158 },
159 {
160 .refresh = 60,
161 .xres = 800,
162 .yres = 480,
163 .pixclock = 33805,
164 .left_margin = 96,
165 .right_margin = 24,
166 .upper_margin = 10,
167 .lower_margin = 3,
168 .hsync_len = 72,
169 .vsync_len = 7,
170 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
171 .vmode = FB_VMODE_NONINTERLACED
172 },
173 {
174 .refresh = 60,
175 .xres = 800,
176 .yres = 600,
177 .pixclock = 25000,
178 .left_margin = 88,
179 .right_margin = 40,
180 .upper_margin = 23,
181 .lower_margin = 1,
182 .hsync_len = 128,
183 .vsync_len = 4,
184 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
185 .vmode = FB_VMODE_NONINTERLACED
186 },
187 {
188 .refresh = 60,
189 .xres = 854,
190 .yres = 480,
191 .pixclock = 31518,
192 .left_margin = 104,
193 .right_margin = 16,
194 .upper_margin = 13,
195 .lower_margin = 1,
196 .hsync_len = 88,
197 .vsync_len = 3,
198 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
199 .vmode = FB_VMODE_NONINTERLACED
200 },
201 {
202 .refresh = 70,
203 .xres = 1024,
204 .yres = 768,
205 .pixclock = 16886,
206 .left_margin = 3,
207 .right_margin = 3,
208 .upper_margin = 2,
209 .lower_margin = 2,
210 .hsync_len = 40,
211 .vsync_len = 18,
212 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
213 .vmode = FB_VMODE_NONINTERLACED
214 },
215 {
216 .refresh = 75,
217 .xres = 1024,
218 .yres = 768,
219 .pixclock = 15009,
220 .left_margin = 3,
221 .right_margin = 3,
222 .upper_margin = 2,
223 .lower_margin = 2,
224 .hsync_len = 80,
225 .vsync_len = 32,
226 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
227 .vmode = FB_VMODE_NONINTERLACED
228 },
229 {
230 .refresh = 60,
231 .xres = 1280,
232 .yres = 480,
233 .pixclock = 18939,
234 .left_margin = 353,
235 .right_margin = 47,
236 .upper_margin = 39,
237 .lower_margin = 4,
238 .hsync_len = 8,
239 .vsync_len = 2,
240 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
241 .vmode = FB_VMODE_NONINTERLACED
242 },
243 {
244 .refresh = 60,
245 .xres = 1280,
246 .yres = 720,
247 .pixclock = 13426,
248 .left_margin = 192,
249 .right_margin = 64,
250 .upper_margin = 22,
251 .lower_margin = 1,
252 .hsync_len = 136,
253 .vsync_len = 3,
254 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
255 .vmode = FB_VMODE_NONINTERLACED
256 },
257 {
258 .refresh = 60,
259 .xres = 1280,
260 .yres = 1024,
261 .pixclock = 9375,
262 .left_margin = 38,
263 .right_margin = 128,
264 .upper_margin = 2,
265 .lower_margin = 7,
266 .hsync_len = 216,
267 .vsync_len = 37,
268 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
269 .vmode = FB_VMODE_NONINTERLACED
270 },
271 {
272 .refresh = 70,
273 .xres = 1280,
274 .yres = 1024,
275 .pixclock = 9380,
276 .left_margin = 6,
277 .right_margin = 6,
278 .upper_margin = 4,
279 .lower_margin = 4,
280 .hsync_len = 60,
281 .vsync_len = 94,
282 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
283 .vmode = FB_VMODE_NONINTERLACED
284 },
285 {
286 .refresh = 75,
287 .xres = 1280,
288 .yres = 1024,
289 .pixclock = 9380,
290 .left_margin = 6,
291 .right_margin = 6,
292 .upper_margin = 4,
293 .lower_margin = 4,
294 .hsync_len = 60,
295 .vsync_len = 15,
296 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
297 .vmode = FB_VMODE_NONINTERLACED
298 },
299 {
300 .refresh = 60,
301 .xres = 1920,
302 .yres = 1080,
303 .pixclock = 5787,
304 .left_margin = 328,
305 .right_margin = 120,
306 .upper_margin = 34,
307 .lower_margin = 1,
308 .hsync_len = 208,
309 .vsync_len = 3,
310 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
311 .vmode = FB_VMODE_NONINTERLACED
312 },
313 };
314
315 static char *fb_mode;
316 static unsigned long default_bpp = 32;
317 static enum fsl_diu_monitor_port monitor_port;
318 static char *monitor_string;
319
320 #if defined(CONFIG_NOT_COHERENT_CACHE)
321 static u8 *coherence_data;
322 static size_t coherence_data_size;
323 static unsigned int d_cache_line_size;
324 #endif
325
326 static DEFINE_SPINLOCK(diu_lock);
327
328 enum mfb_index {
329 PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
330 PLANE1_AOI0, /* Plane 1, first AOI */
331 PLANE1_AOI1, /* Plane 1, second AOI */
332 PLANE2_AOI0, /* Plane 2, first AOI */
333 PLANE2_AOI1, /* Plane 2, second AOI */
334 };
335
336 struct mfb_info {
337 enum mfb_index index;
338 char *id;
339 int registered;
340 unsigned long pseudo_palette[16];
341 struct diu_ad *ad;
342 unsigned char g_alpha;
343 unsigned int count;
344 int x_aoi_d; /* aoi display x offset to physical screen */
345 int y_aoi_d; /* aoi display y offset to physical screen */
346 struct fsl_diu_data *parent;
347 };
348
349 /**
350 * struct fsl_diu_data - per-DIU data structure
351 * @dma_addr: DMA address of this structure
352 * @fsl_diu_info: fb_info objects, one per AOI
353 * @dev_attr: sysfs structure
354 * @irq: IRQ
355 * @monitor_port: the monitor port this DIU is connected to
356 * @diu_reg: pointer to the DIU hardware registers
357 * @reg_lock: spinlock for register access
358 * @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI
359 * dummy_ad: DIU Area Descriptor for the dummy AOI
360 * @ad[]: Area Descriptors for each real AOI
361 * @gamma: gamma color table
362 * @cursor: hardware cursor data
363 *
364 * This data structure must be allocated with 32-byte alignment, so that the
365 * internal fields can be aligned properly.
366 */
367 struct fsl_diu_data {
368 dma_addr_t dma_addr;
369 struct fb_info fsl_diu_info[NUM_AOIS];
370 struct mfb_info mfb[NUM_AOIS];
371 struct device_attribute dev_attr;
372 unsigned int irq;
373 enum fsl_diu_monitor_port monitor_port;
374 struct diu __iomem *diu_reg;
375 spinlock_t reg_lock;
376 u8 dummy_aoi[4 * 4 * 4];
377 struct diu_ad dummy_ad __aligned(8);
378 struct diu_ad ad[NUM_AOIS] __aligned(8);
379 u8 gamma[256 * 3] __aligned(32);
380 /* It's easier to parse the cursor data as little-endian */
381 __le16 cursor[MAX_CURS * MAX_CURS] __aligned(32);
382 /* Blank cursor data -- used to hide the cursor */
383 __le16 blank_cursor[MAX_CURS * MAX_CURS] __aligned(32);
384 uint8_t edid_data[EDID_LENGTH];
385 bool has_edid;
386 } __aligned(32);
387
388 /* Determine the DMA address of a member of the fsl_diu_data structure */
389 #define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f))
390
391 static struct mfb_info mfb_template[] = {
392 {
393 .index = PLANE0,
394 .id = "Panel0",
395 .registered = 0,
396 .count = 0,
397 .x_aoi_d = 0,
398 .y_aoi_d = 0,
399 },
400 {
401 .index = PLANE1_AOI0,
402 .id = "Panel1 AOI0",
403 .registered = 0,
404 .g_alpha = 0xff,
405 .count = 0,
406 .x_aoi_d = 0,
407 .y_aoi_d = 0,
408 },
409 {
410 .index = PLANE1_AOI1,
411 .id = "Panel1 AOI1",
412 .registered = 0,
413 .g_alpha = 0xff,
414 .count = 0,
415 .x_aoi_d = 0,
416 .y_aoi_d = 480,
417 },
418 {
419 .index = PLANE2_AOI0,
420 .id = "Panel2 AOI0",
421 .registered = 0,
422 .g_alpha = 0xff,
423 .count = 0,
424 .x_aoi_d = 640,
425 .y_aoi_d = 0,
426 },
427 {
428 .index = PLANE2_AOI1,
429 .id = "Panel2 AOI1",
430 .registered = 0,
431 .g_alpha = 0xff,
432 .count = 0,
433 .x_aoi_d = 640,
434 .y_aoi_d = 480,
435 },
436 };
437
438 #ifdef DEBUG
439 static void __attribute__ ((unused)) fsl_diu_dump(struct diu __iomem *hw)
440 {
441 mb();
442 pr_debug("DIU: desc=%08x,%08x,%08x, gamma=%08x palette=%08x "
443 "cursor=%08x curs_pos=%08x diu_mode=%08x bgnd=%08x "
444 "disp_size=%08x hsyn_para=%08x vsyn_para=%08x syn_pol=%08x "
445 "thresholds=%08x int_mask=%08x plut=%08x\n",
446 hw->desc[0], hw->desc[1], hw->desc[2], hw->gamma,
447 hw->palette, hw->cursor, hw->curs_pos, hw->diu_mode,
448 hw->bgnd, hw->disp_size, hw->hsyn_para, hw->vsyn_para,
449 hw->syn_pol, hw->thresholds, hw->int_mask, hw->plut);
450 rmb();
451 }
452 #endif
453
454 /**
455 * fsl_diu_name_to_port - convert a port name to a monitor port enum
456 *
457 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
458 * the enum fsl_diu_monitor_port that corresponds to that string.
459 *
460 * For compatibility with older versions, a number ("0", "1", or "2") is also
461 * supported.
462 *
463 * If the string is unknown, DVI is assumed.
464 *
465 * If the particular port is not supported by the platform, another port
466 * (platform-specific) is chosen instead.
467 */
468 static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
469 {
470 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
471 unsigned long val;
472
473 if (s) {
474 if (!kstrtoul(s, 10, &val) && (val <= 2))
475 port = (enum fsl_diu_monitor_port) val;
476 else if (strncmp(s, "lvds", 4) == 0)
477 port = FSL_DIU_PORT_LVDS;
478 else if (strncmp(s, "dlvds", 5) == 0)
479 port = FSL_DIU_PORT_DLVDS;
480 }
481
482 if (diu_ops.valid_monitor_port)
483 port = diu_ops.valid_monitor_port(port);
484
485 return port;
486 }
487
488 /*
489 * Workaround for failed writing desc register of planes.
490 * Needed with MPC5121 DIU rev 2.0 silicon.
491 */
492 void wr_reg_wa(u32 *reg, u32 val)
493 {
494 do {
495 out_be32(reg, val);
496 } while (in_be32(reg) != val);
497 }
498
499 static void fsl_diu_enable_panel(struct fb_info *info)
500 {
501 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
502 struct diu_ad *ad = mfbi->ad;
503 struct fsl_diu_data *data = mfbi->parent;
504 struct diu __iomem *hw = data->diu_reg;
505
506 switch (mfbi->index) {
507 case PLANE0:
508 wr_reg_wa(&hw->desc[0], ad->paddr);
509 break;
510 case PLANE1_AOI0:
511 cmfbi = &data->mfb[2];
512 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
513 if (cmfbi->count > 0) /* AOI1 open */
514 ad->next_ad =
515 cpu_to_le32(cmfbi->ad->paddr);
516 else
517 ad->next_ad = 0;
518 wr_reg_wa(&hw->desc[1], ad->paddr);
519 }
520 break;
521 case PLANE2_AOI0:
522 cmfbi = &data->mfb[4];
523 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
524 if (cmfbi->count > 0) /* AOI1 open */
525 ad->next_ad =
526 cpu_to_le32(cmfbi->ad->paddr);
527 else
528 ad->next_ad = 0;
529 wr_reg_wa(&hw->desc[2], ad->paddr);
530 }
531 break;
532 case PLANE1_AOI1:
533 pmfbi = &data->mfb[1];
534 ad->next_ad = 0;
535 if (hw->desc[1] == data->dummy_ad.paddr)
536 wr_reg_wa(&hw->desc[1], ad->paddr);
537 else /* AOI0 open */
538 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
539 break;
540 case PLANE2_AOI1:
541 pmfbi = &data->mfb[3];
542 ad->next_ad = 0;
543 if (hw->desc[2] == data->dummy_ad.paddr)
544 wr_reg_wa(&hw->desc[2], ad->paddr);
545 else /* AOI0 was open */
546 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
547 break;
548 }
549 }
550
551 static void fsl_diu_disable_panel(struct fb_info *info)
552 {
553 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
554 struct diu_ad *ad = mfbi->ad;
555 struct fsl_diu_data *data = mfbi->parent;
556 struct diu __iomem *hw = data->diu_reg;
557
558 switch (mfbi->index) {
559 case PLANE0:
560 wr_reg_wa(&hw->desc[0], 0);
561 break;
562 case PLANE1_AOI0:
563 cmfbi = &data->mfb[2];
564 if (cmfbi->count > 0) /* AOI1 is open */
565 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
566 /* move AOI1 to the first */
567 else /* AOI1 was closed */
568 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
569 /* close AOI 0 */
570 break;
571 case PLANE2_AOI0:
572 cmfbi = &data->mfb[4];
573 if (cmfbi->count > 0) /* AOI1 is open */
574 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
575 /* move AOI1 to the first */
576 else /* AOI1 was closed */
577 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
578 /* close AOI 0 */
579 break;
580 case PLANE1_AOI1:
581 pmfbi = &data->mfb[1];
582 if (hw->desc[1] != ad->paddr) {
583 /* AOI1 is not the first in the chain */
584 if (pmfbi->count > 0)
585 /* AOI0 is open, must be the first */
586 pmfbi->ad->next_ad = 0;
587 } else /* AOI1 is the first in the chain */
588 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
589 /* close AOI 1 */
590 break;
591 case PLANE2_AOI1:
592 pmfbi = &data->mfb[3];
593 if (hw->desc[2] != ad->paddr) {
594 /* AOI1 is not the first in the chain */
595 if (pmfbi->count > 0)
596 /* AOI0 is open, must be the first */
597 pmfbi->ad->next_ad = 0;
598 } else /* AOI1 is the first in the chain */
599 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
600 /* close AOI 1 */
601 break;
602 }
603 }
604
605 static void enable_lcdc(struct fb_info *info)
606 {
607 struct mfb_info *mfbi = info->par;
608 struct fsl_diu_data *data = mfbi->parent;
609 struct diu __iomem *hw = data->diu_reg;
610
611 out_be32(&hw->diu_mode, MFB_MODE1);
612 }
613
614 static void disable_lcdc(struct fb_info *info)
615 {
616 struct mfb_info *mfbi = info->par;
617 struct fsl_diu_data *data = mfbi->parent;
618 struct diu __iomem *hw = data->diu_reg;
619
620 out_be32(&hw->diu_mode, 0);
621 }
622
623 static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
624 struct fb_info *info)
625 {
626 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
627 struct fsl_diu_data *data = mfbi->parent;
628 int available_height, upper_aoi_bottom;
629 enum mfb_index index = mfbi->index;
630 int lower_aoi_is_open, upper_aoi_is_open;
631 __u32 base_plane_width, base_plane_height, upper_aoi_height;
632
633 base_plane_width = data->fsl_diu_info[0].var.xres;
634 base_plane_height = data->fsl_diu_info[0].var.yres;
635
636 if (mfbi->x_aoi_d < 0)
637 mfbi->x_aoi_d = 0;
638 if (mfbi->y_aoi_d < 0)
639 mfbi->y_aoi_d = 0;
640 switch (index) {
641 case PLANE0:
642 if (mfbi->x_aoi_d != 0)
643 mfbi->x_aoi_d = 0;
644 if (mfbi->y_aoi_d != 0)
645 mfbi->y_aoi_d = 0;
646 break;
647 case PLANE1_AOI0:
648 case PLANE2_AOI0:
649 lower_aoi_mfbi = data->fsl_diu_info[index+1].par;
650 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
651 if (var->xres > base_plane_width)
652 var->xres = base_plane_width;
653 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
654 mfbi->x_aoi_d = base_plane_width - var->xres;
655
656 if (lower_aoi_is_open)
657 available_height = lower_aoi_mfbi->y_aoi_d;
658 else
659 available_height = base_plane_height;
660 if (var->yres > available_height)
661 var->yres = available_height;
662 if ((mfbi->y_aoi_d + var->yres) > available_height)
663 mfbi->y_aoi_d = available_height - var->yres;
664 break;
665 case PLANE1_AOI1:
666 case PLANE2_AOI1:
667 upper_aoi_mfbi = data->fsl_diu_info[index-1].par;
668 upper_aoi_height = data->fsl_diu_info[index-1].var.yres;
669 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
670 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
671 if (var->xres > base_plane_width)
672 var->xres = base_plane_width;
673 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
674 mfbi->x_aoi_d = base_plane_width - var->xres;
675 if (mfbi->y_aoi_d < 0)
676 mfbi->y_aoi_d = 0;
677 if (upper_aoi_is_open) {
678 if (mfbi->y_aoi_d < upper_aoi_bottom)
679 mfbi->y_aoi_d = upper_aoi_bottom;
680 available_height = base_plane_height
681 - upper_aoi_bottom;
682 } else
683 available_height = base_plane_height;
684 if (var->yres > available_height)
685 var->yres = available_height;
686 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
687 mfbi->y_aoi_d = base_plane_height - var->yres;
688 break;
689 }
690 }
691 /*
692 * Checks to see if the hardware supports the state requested by var passed
693 * in. This function does not alter the hardware state! If the var passed in
694 * is slightly off by what the hardware can support then we alter the var
695 * PASSED in to what we can do. If the hardware doesn't support mode change
696 * a -EINVAL will be returned by the upper layers.
697 */
698 static int fsl_diu_check_var(struct fb_var_screeninfo *var,
699 struct fb_info *info)
700 {
701 if (var->xres_virtual < var->xres)
702 var->xres_virtual = var->xres;
703 if (var->yres_virtual < var->yres)
704 var->yres_virtual = var->yres;
705
706 if (var->xoffset + info->var.xres > info->var.xres_virtual)
707 var->xoffset = info->var.xres_virtual - info->var.xres;
708
709 if (var->yoffset + info->var.yres > info->var.yres_virtual)
710 var->yoffset = info->var.yres_virtual - info->var.yres;
711
712 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
713 (var->bits_per_pixel != 16))
714 var->bits_per_pixel = default_bpp;
715
716 switch (var->bits_per_pixel) {
717 case 16:
718 var->red.length = 5;
719 var->red.offset = 11;
720 var->red.msb_right = 0;
721
722 var->green.length = 6;
723 var->green.offset = 5;
724 var->green.msb_right = 0;
725
726 var->blue.length = 5;
727 var->blue.offset = 0;
728 var->blue.msb_right = 0;
729
730 var->transp.length = 0;
731 var->transp.offset = 0;
732 var->transp.msb_right = 0;
733 break;
734 case 24:
735 var->red.length = 8;
736 var->red.offset = 0;
737 var->red.msb_right = 0;
738
739 var->green.length = 8;
740 var->green.offset = 8;
741 var->green.msb_right = 0;
742
743 var->blue.length = 8;
744 var->blue.offset = 16;
745 var->blue.msb_right = 0;
746
747 var->transp.length = 0;
748 var->transp.offset = 0;
749 var->transp.msb_right = 0;
750 break;
751 case 32:
752 var->red.length = 8;
753 var->red.offset = 16;
754 var->red.msb_right = 0;
755
756 var->green.length = 8;
757 var->green.offset = 8;
758 var->green.msb_right = 0;
759
760 var->blue.length = 8;
761 var->blue.offset = 0;
762 var->blue.msb_right = 0;
763
764 var->transp.length = 8;
765 var->transp.offset = 24;
766 var->transp.msb_right = 0;
767
768 break;
769 }
770
771 var->height = -1;
772 var->width = -1;
773 var->grayscale = 0;
774
775 /* Copy nonstd field to/from sync for fbset usage */
776 var->sync |= var->nonstd;
777 var->nonstd |= var->sync;
778
779 adjust_aoi_size_position(var, info);
780 return 0;
781 }
782
783 static void set_fix(struct fb_info *info)
784 {
785 struct fb_fix_screeninfo *fix = &info->fix;
786 struct fb_var_screeninfo *var = &info->var;
787 struct mfb_info *mfbi = info->par;
788
789 strncpy(fix->id, mfbi->id, sizeof(fix->id));
790 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
791 fix->type = FB_TYPE_PACKED_PIXELS;
792 fix->accel = FB_ACCEL_NONE;
793 fix->visual = FB_VISUAL_TRUECOLOR;
794 fix->xpanstep = 1;
795 fix->ypanstep = 1;
796 }
797
798 static void update_lcdc(struct fb_info *info)
799 {
800 struct fb_var_screeninfo *var = &info->var;
801 struct mfb_info *mfbi = info->par;
802 struct fsl_diu_data *data = mfbi->parent;
803 struct diu __iomem *hw;
804 int i, j;
805 u8 *gamma_table_base;
806
807 u32 temp;
808
809 hw = data->diu_reg;
810
811 if (diu_ops.set_monitor_port)
812 diu_ops.set_monitor_port(data->monitor_port);
813 gamma_table_base = data->gamma;
814
815 /* Prep for DIU init - gamma table, cursor table */
816
817 for (i = 0; i <= 2; i++)
818 for (j = 0; j <= 255; j++)
819 *gamma_table_base++ = j;
820
821 if (diu_ops.set_gamma_table)
822 diu_ops.set_gamma_table(data->monitor_port, data->gamma);
823
824 disable_lcdc(info);
825
826 /* Program DIU registers */
827
828 out_be32(&hw->gamma, DMA_ADDR(data, gamma));
829
830 out_be32(&hw->bgnd, 0x007F7F7F); /* Set background to grey */
831 out_be32(&hw->disp_size, (var->yres << 16) | var->xres);
832
833 /* Horizontal and vertical configuration register */
834 temp = var->left_margin << 22 | /* BP_H */
835 var->hsync_len << 11 | /* PW_H */
836 var->right_margin; /* FP_H */
837
838 out_be32(&hw->hsyn_para, temp);
839
840 temp = var->upper_margin << 22 | /* BP_V */
841 var->vsync_len << 11 | /* PW_V */
842 var->lower_margin; /* FP_V */
843
844 out_be32(&hw->vsyn_para, temp);
845
846 diu_ops.set_pixel_clock(var->pixclock);
847
848 #ifndef CONFIG_PPC_MPC512x
849 /*
850 * The PLUT register is defined differently on the MPC5121 than it
851 * is on other SOCs. Unfortunately, there's no documentation that
852 * explains how it's supposed to be programmed, so for now, we leave
853 * it at the default value on the MPC5121.
854 *
855 * For other SOCs, program it for the highest priority, which will
856 * reduce the chance of underrun. Technically, we should scale the
857 * priority to match the screen resolution, but doing that properly
858 * requires delicate fine-tuning for each use-case.
859 */
860 out_be32(&hw->plut, 0x01F5F666);
861 #endif
862
863 /* Enable the DIU */
864 enable_lcdc(info);
865 }
866
867 static int map_video_memory(struct fb_info *info)
868 {
869 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
870 void *p;
871
872 p = alloc_pages_exact(smem_len, GFP_DMA | __GFP_ZERO);
873 if (!p) {
874 dev_err(info->dev, "unable to allocate fb memory\n");
875 return -ENOMEM;
876 }
877 mutex_lock(&info->mm_lock);
878 info->screen_base = p;
879 info->fix.smem_start = virt_to_phys(info->screen_base);
880 info->fix.smem_len = smem_len;
881 mutex_unlock(&info->mm_lock);
882 info->screen_size = info->fix.smem_len;
883
884 return 0;
885 }
886
887 static void unmap_video_memory(struct fb_info *info)
888 {
889 void *p = info->screen_base;
890 size_t l = info->fix.smem_len;
891
892 mutex_lock(&info->mm_lock);
893 info->screen_base = NULL;
894 info->fix.smem_start = 0;
895 info->fix.smem_len = 0;
896 mutex_unlock(&info->mm_lock);
897
898 if (p)
899 free_pages_exact(p, l);
900 }
901
902 /*
903 * Using the fb_var_screeninfo in fb_info we set the aoi of this
904 * particular framebuffer. It is a light version of fsl_diu_set_par.
905 */
906 static int fsl_diu_set_aoi(struct fb_info *info)
907 {
908 struct fb_var_screeninfo *var = &info->var;
909 struct mfb_info *mfbi = info->par;
910 struct diu_ad *ad = mfbi->ad;
911
912 /* AOI should not be greater than display size */
913 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
914 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
915 return 0;
916 }
917
918 /**
919 * fsl_diu_get_pixel_format: return the pixel format for a given color depth
920 *
921 * The pixel format is a 32-bit value that determine which bits in each
922 * pixel are to be used for each color. This is the default function used
923 * if the platform does not define its own version.
924 */
925 static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
926 {
927 #define PF_BYTE_F 0x10000000
928 #define PF_ALPHA_C_MASK 0x0E000000
929 #define PF_ALPHA_C_SHIFT 25
930 #define PF_BLUE_C_MASK 0x01800000
931 #define PF_BLUE_C_SHIFT 23
932 #define PF_GREEN_C_MASK 0x00600000
933 #define PF_GREEN_C_SHIFT 21
934 #define PF_RED_C_MASK 0x00180000
935 #define PF_RED_C_SHIFT 19
936 #define PF_PALETTE 0x00040000
937 #define PF_PIXEL_S_MASK 0x00030000
938 #define PF_PIXEL_S_SHIFT 16
939 #define PF_COMP_3_MASK 0x0000F000
940 #define PF_COMP_3_SHIFT 12
941 #define PF_COMP_2_MASK 0x00000F00
942 #define PF_COMP_2_SHIFT 8
943 #define PF_COMP_1_MASK 0x000000F0
944 #define PF_COMP_1_SHIFT 4
945 #define PF_COMP_0_MASK 0x0000000F
946 #define PF_COMP_0_SHIFT 0
947
948 #define MAKE_PF(alpha, red, green, blue, size, c0, c1, c2, c3) \
949 cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
950 (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
951 (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
952 (c2 << PF_COMP_2_SHIFT) | (c1 << PF_COMP_1_SHIFT) | \
953 (c0 << PF_COMP_0_SHIFT) | (size << PF_PIXEL_S_SHIFT))
954
955 switch (bits_per_pixel) {
956 case 32:
957 /* 0x88883316 */
958 return MAKE_PF(3, 2, 1, 0, 3, 8, 8, 8, 8);
959 case 24:
960 /* 0x88082219 */
961 return MAKE_PF(4, 0, 1, 2, 2, 8, 8, 8, 0);
962 case 16:
963 /* 0x65053118 */
964 return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
965 default:
966 pr_err("fsl-diu: unsupported color depth %u\n", bits_per_pixel);
967 return 0;
968 }
969 }
970
971 /*
972 * Copies a cursor image from user space to the proper place in driver
973 * memory so that the hardware can display the cursor image.
974 *
975 * Cursor data is represented as a sequence of 'width' bits packed into bytes.
976 * That is, the first 8 bits are in the first byte, the second 8 bits in the
977 * second byte, and so on. Therefore, the each row of the cursor is (width +
978 * 7) / 8 bytes of 'data'
979 *
980 * The DIU only supports cursors up to 32x32 (MAX_CURS). We reject cursors
981 * larger than this, so we already know that 'width' <= 32. Therefore, we can
982 * simplify our code by using a 32-bit big-endian integer ("line") to read in
983 * a single line of pixels, and only look at the top 'width' bits of that
984 * integer.
985 *
986 * This could result in an unaligned 32-bit read. For example, if the cursor
987 * is 24x24, then the first three bytes of 'image' contain the pixel data for
988 * the top line of the cursor. We do a 32-bit read of 'image', but we look
989 * only at the top 24 bits. Then we increment 'image' by 3 bytes. The next
990 * read is unaligned. The only problem is that we might read past the end of
991 * 'image' by 1-3 bytes, but that should not cause any problems.
992 */
993 static void fsl_diu_load_cursor_image(struct fb_info *info,
994 const void *image, uint16_t bg, uint16_t fg,
995 unsigned int width, unsigned int height)
996 {
997 struct mfb_info *mfbi = info->par;
998 struct fsl_diu_data *data = mfbi->parent;
999 __le16 *cursor = data->cursor;
1000 __le16 _fg = cpu_to_le16(fg);
1001 __le16 _bg = cpu_to_le16(bg);
1002 unsigned int h, w;
1003
1004 for (h = 0; h < height; h++) {
1005 uint32_t mask = 1 << 31;
1006 uint32_t line = be32_to_cpup(image);
1007
1008 for (w = 0; w < width; w++) {
1009 cursor[w] = (line & mask) ? _fg : _bg;
1010 mask >>= 1;
1011 }
1012
1013 cursor += MAX_CURS;
1014 image += DIV_ROUND_UP(width, 8);
1015 }
1016 }
1017
1018 /*
1019 * Set a hardware cursor. The image data for the cursor is passed via the
1020 * fb_cursor object.
1021 */
1022 static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor)
1023 {
1024 struct mfb_info *mfbi = info->par;
1025 struct fsl_diu_data *data = mfbi->parent;
1026 struct diu __iomem *hw = data->diu_reg;
1027
1028 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1029 return -EINVAL;
1030
1031 /* The cursor size has changed */
1032 if (cursor->set & FB_CUR_SETSIZE) {
1033 /*
1034 * The DIU cursor is a fixed size, so when we get this
1035 * message, instead of resizing the cursor, we just clear
1036 * all the image data, in expectation of new data. However,
1037 * in tests this control does not appear to be normally
1038 * called.
1039 */
1040 memset(data->cursor, 0, sizeof(data->cursor));
1041 }
1042
1043 /* The cursor position has changed (cursor->image.dx|dy) */
1044 if (cursor->set & FB_CUR_SETPOS) {
1045 uint32_t xx, yy;
1046
1047 yy = (cursor->image.dy - info->var.yoffset) & 0x7ff;
1048 xx = (cursor->image.dx - info->var.xoffset) & 0x7ff;
1049
1050 out_be32(&hw->curs_pos, yy << 16 | xx);
1051 }
1052
1053 /*
1054 * FB_CUR_SETIMAGE - the cursor image has changed
1055 * FB_CUR_SETCMAP - the cursor colors has changed
1056 * FB_CUR_SETSHAPE - the cursor bitmask has changed
1057 */
1058 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1059 unsigned int image_size =
1060 DIV_ROUND_UP(cursor->image.width, 8) * cursor->image.height;
1061 unsigned int image_words =
1062 DIV_ROUND_UP(image_size, sizeof(uint32_t));
1063 unsigned int bg_idx = cursor->image.bg_color;
1064 unsigned int fg_idx = cursor->image.fg_color;
1065 uint8_t buffer[image_size];
1066 uint32_t *image, *source, *mask;
1067 uint16_t fg, bg;
1068 unsigned int i;
1069
1070 if (info->state != FBINFO_STATE_RUNNING)
1071 return 0;
1072
1073 /*
1074 * Determine the size of the cursor image data. Normally,
1075 * it's 8x16.
1076 */
1077 image_size = DIV_ROUND_UP(cursor->image.width, 8) *
1078 cursor->image.height;
1079
1080 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1081 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1082 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1083 1 << 15;
1084
1085 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1086 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1087 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1088 1 << 15;
1089
1090 /* Use 32-bit operations on the data to improve performance */
1091 image = (uint32_t *)buffer;
1092 source = (uint32_t *)cursor->image.data;
1093 mask = (uint32_t *)cursor->mask;
1094
1095 if (cursor->rop == ROP_XOR)
1096 for (i = 0; i < image_words; i++)
1097 image[i] = source[i] ^ mask[i];
1098 else
1099 for (i = 0; i < image_words; i++)
1100 image[i] = source[i] & mask[i];
1101
1102 fsl_diu_load_cursor_image(info, image, bg, fg,
1103 cursor->image.width, cursor->image.height);
1104 }
1105
1106 /*
1107 * Show or hide the cursor. The cursor data is always stored in the
1108 * 'cursor' memory block, and the actual cursor position is always in
1109 * the DIU's CURS_POS register. To hide the cursor, we redirect the
1110 * CURSOR register to a blank cursor. The show the cursor, we
1111 * redirect the CURSOR register to the real cursor data.
1112 */
1113 if (cursor->enable)
1114 out_be32(&hw->cursor, DMA_ADDR(data, cursor));
1115 else
1116 out_be32(&hw->cursor, DMA_ADDR(data, blank_cursor));
1117
1118 return 0;
1119 }
1120
1121 /*
1122 * Using the fb_var_screeninfo in fb_info we set the resolution of this
1123 * particular framebuffer. This function alters the fb_fix_screeninfo stored
1124 * in fb_info. It does not alter var in fb_info since we are using that
1125 * data. This means we depend on the data in var inside fb_info to be
1126 * supported by the hardware. fsl_diu_check_var is always called before
1127 * fsl_diu_set_par to ensure this.
1128 */
1129 static int fsl_diu_set_par(struct fb_info *info)
1130 {
1131 unsigned long len;
1132 struct fb_var_screeninfo *var = &info->var;
1133 struct mfb_info *mfbi = info->par;
1134 struct fsl_diu_data *data = mfbi->parent;
1135 struct diu_ad *ad = mfbi->ad;
1136 struct diu __iomem *hw;
1137
1138 hw = data->diu_reg;
1139
1140 set_fix(info);
1141
1142 len = info->var.yres_virtual * info->fix.line_length;
1143 /* Alloc & dealloc each time resolution/bpp change */
1144 if (len != info->fix.smem_len) {
1145 if (info->fix.smem_start)
1146 unmap_video_memory(info);
1147
1148 /* Memory allocation for framebuffer */
1149 if (map_video_memory(info)) {
1150 dev_err(info->dev, "unable to allocate fb memory 1\n");
1151 return -ENOMEM;
1152 }
1153 }
1154
1155 if (diu_ops.get_pixel_format)
1156 ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port,
1157 var->bits_per_pixel);
1158 else
1159 ad->pix_fmt = fsl_diu_get_pixel_format(var->bits_per_pixel);
1160
1161 ad->addr = cpu_to_le32(info->fix.smem_start);
1162 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
1163 var->xres_virtual) | mfbi->g_alpha;
1164 /* AOI should not be greater than display size */
1165 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
1166 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
1167 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
1168
1169 /* Disable chroma keying function */
1170 ad->ckmax_r = 0;
1171 ad->ckmax_g = 0;
1172 ad->ckmax_b = 0;
1173
1174 ad->ckmin_r = 255;
1175 ad->ckmin_g = 255;
1176 ad->ckmin_b = 255;
1177
1178 if (mfbi->index == PLANE0)
1179 update_lcdc(info);
1180 return 0;
1181 }
1182
1183 static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
1184 {
1185 return ((val << width) + 0x7FFF - val) >> 16;
1186 }
1187
1188 /*
1189 * Set a single color register. The values supplied have a 16 bit magnitude
1190 * which needs to be scaled in this function for the hardware. Things to take
1191 * into consideration are how many color registers, if any, are supported with
1192 * the current color visual. With truecolor mode no color palettes are
1193 * supported. Here a pseudo palette is created which we store the value in
1194 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
1195 * color palette.
1196 */
1197 static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
1198 unsigned int green, unsigned int blue,
1199 unsigned int transp, struct fb_info *info)
1200 {
1201 int ret = 1;
1202
1203 /*
1204 * If greyscale is true, then we convert the RGB value
1205 * to greyscale no matter what visual we are using.
1206 */
1207 if (info->var.grayscale)
1208 red = green = blue = (19595 * red + 38470 * green +
1209 7471 * blue) >> 16;
1210 switch (info->fix.visual) {
1211 case FB_VISUAL_TRUECOLOR:
1212 /*
1213 * 16-bit True Colour. We encode the RGB value
1214 * according to the RGB bitfield information.
1215 */
1216 if (regno < 16) {
1217 u32 *pal = info->pseudo_palette;
1218 u32 v;
1219
1220 red = CNVT_TOHW(red, info->var.red.length);
1221 green = CNVT_TOHW(green, info->var.green.length);
1222 blue = CNVT_TOHW(blue, info->var.blue.length);
1223 transp = CNVT_TOHW(transp, info->var.transp.length);
1224
1225 v = (red << info->var.red.offset) |
1226 (green << info->var.green.offset) |
1227 (blue << info->var.blue.offset) |
1228 (transp << info->var.transp.offset);
1229
1230 pal[regno] = v;
1231 ret = 0;
1232 }
1233 break;
1234 }
1235
1236 return ret;
1237 }
1238
1239 /*
1240 * Pan (or wrap, depending on the `vmode' field) the display using the
1241 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
1242 * don't fit, return -EINVAL.
1243 */
1244 static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
1245 struct fb_info *info)
1246 {
1247 if ((info->var.xoffset == var->xoffset) &&
1248 (info->var.yoffset == var->yoffset))
1249 return 0; /* No change, do nothing */
1250
1251 if (var->xoffset + info->var.xres > info->var.xres_virtual
1252 || var->yoffset + info->var.yres > info->var.yres_virtual)
1253 return -EINVAL;
1254
1255 info->var.xoffset = var->xoffset;
1256 info->var.yoffset = var->yoffset;
1257
1258 if (var->vmode & FB_VMODE_YWRAP)
1259 info->var.vmode |= FB_VMODE_YWRAP;
1260 else
1261 info->var.vmode &= ~FB_VMODE_YWRAP;
1262
1263 fsl_diu_set_aoi(info);
1264
1265 return 0;
1266 }
1267
1268 static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
1269 unsigned long arg)
1270 {
1271 struct mfb_info *mfbi = info->par;
1272 struct diu_ad *ad = mfbi->ad;
1273 struct mfb_chroma_key ck;
1274 unsigned char global_alpha;
1275 struct aoi_display_offset aoi_d;
1276 __u32 pix_fmt;
1277 void __user *buf = (void __user *)arg;
1278
1279 if (!arg)
1280 return -EINVAL;
1281
1282 dev_dbg(info->dev, "ioctl %08x (dir=%s%s type=%u nr=%u size=%u)\n", cmd,
1283 _IOC_DIR(cmd) & _IOC_READ ? "R" : "",
1284 _IOC_DIR(cmd) & _IOC_WRITE ? "W" : "",
1285 _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
1286
1287 switch (cmd) {
1288 case MFB_SET_PIXFMT_OLD:
1289 dev_warn(info->dev,
1290 "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
1291 MFB_SET_PIXFMT_OLD);
1292 case MFB_SET_PIXFMT:
1293 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
1294 return -EFAULT;
1295 ad->pix_fmt = pix_fmt;
1296 break;
1297 case MFB_GET_PIXFMT_OLD:
1298 dev_warn(info->dev,
1299 "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
1300 MFB_GET_PIXFMT_OLD);
1301 case MFB_GET_PIXFMT:
1302 pix_fmt = ad->pix_fmt;
1303 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
1304 return -EFAULT;
1305 break;
1306 case MFB_SET_AOID:
1307 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
1308 return -EFAULT;
1309 mfbi->x_aoi_d = aoi_d.x_aoi_d;
1310 mfbi->y_aoi_d = aoi_d.y_aoi_d;
1311 fsl_diu_check_var(&info->var, info);
1312 fsl_diu_set_aoi(info);
1313 break;
1314 case MFB_GET_AOID:
1315 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1316 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1317 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1318 return -EFAULT;
1319 break;
1320 case MFB_GET_ALPHA:
1321 global_alpha = mfbi->g_alpha;
1322 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1323 return -EFAULT;
1324 break;
1325 case MFB_SET_ALPHA:
1326 /* set panel information */
1327 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1328 return -EFAULT;
1329 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1330 (global_alpha & 0xff);
1331 mfbi->g_alpha = global_alpha;
1332 break;
1333 case MFB_SET_CHROMA_KEY:
1334 /* set panel winformation */
1335 if (copy_from_user(&ck, buf, sizeof(ck)))
1336 return -EFAULT;
1337
1338 if (ck.enable &&
1339 (ck.red_max < ck.red_min ||
1340 ck.green_max < ck.green_min ||
1341 ck.blue_max < ck.blue_min))
1342 return -EINVAL;
1343
1344 if (!ck.enable) {
1345 ad->ckmax_r = 0;
1346 ad->ckmax_g = 0;
1347 ad->ckmax_b = 0;
1348 ad->ckmin_r = 255;
1349 ad->ckmin_g = 255;
1350 ad->ckmin_b = 255;
1351 } else {
1352 ad->ckmax_r = ck.red_max;
1353 ad->ckmax_g = ck.green_max;
1354 ad->ckmax_b = ck.blue_max;
1355 ad->ckmin_r = ck.red_min;
1356 ad->ckmin_g = ck.green_min;
1357 ad->ckmin_b = ck.blue_min;
1358 }
1359 break;
1360 #ifdef CONFIG_PPC_MPC512x
1361 case MFB_SET_GAMMA: {
1362 struct fsl_diu_data *data = mfbi->parent;
1363
1364 if (copy_from_user(data->gamma, buf, sizeof(data->gamma)))
1365 return -EFAULT;
1366 setbits32(&data->diu_reg->gamma, 0); /* Force table reload */
1367 break;
1368 }
1369 case MFB_GET_GAMMA: {
1370 struct fsl_diu_data *data = mfbi->parent;
1371
1372 if (copy_to_user(buf, data->gamma, sizeof(data->gamma)))
1373 return -EFAULT;
1374 break;
1375 }
1376 #endif
1377 default:
1378 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
1379 return -ENOIOCTLCMD;
1380 }
1381
1382 return 0;
1383 }
1384
1385 static inline void fsl_diu_enable_interrupts(struct fsl_diu_data *data)
1386 {
1387 u32 int_mask = INT_UNDRUN; /* enable underrun detection */
1388
1389 if (IS_ENABLED(CONFIG_NOT_COHERENT_CACHE))
1390 int_mask |= INT_VSYNC; /* enable vertical sync */
1391
1392 clrbits32(&data->diu_reg->int_mask, int_mask);
1393 }
1394
1395 /* turn on fb if count == 1
1396 */
1397 static int fsl_diu_open(struct fb_info *info, int user)
1398 {
1399 struct mfb_info *mfbi = info->par;
1400 int res = 0;
1401
1402 /* free boot splash memory on first /dev/fb0 open */
1403 if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
1404 diu_ops.release_bootmem();
1405
1406 spin_lock(&diu_lock);
1407 mfbi->count++;
1408 if (mfbi->count == 1) {
1409 fsl_diu_check_var(&info->var, info);
1410 res = fsl_diu_set_par(info);
1411 if (res < 0)
1412 mfbi->count--;
1413 else {
1414 fsl_diu_enable_interrupts(mfbi->parent);
1415 fsl_diu_enable_panel(info);
1416 }
1417 }
1418
1419 spin_unlock(&diu_lock);
1420 return res;
1421 }
1422
1423 /* turn off fb if count == 0
1424 */
1425 static int fsl_diu_release(struct fb_info *info, int user)
1426 {
1427 struct mfb_info *mfbi = info->par;
1428 int res = 0;
1429
1430 spin_lock(&diu_lock);
1431 mfbi->count--;
1432 if (mfbi->count == 0) {
1433 struct fsl_diu_data *data = mfbi->parent;
1434 bool disable = true;
1435 int i;
1436
1437 /* Disable interrupts only if all AOIs are closed */
1438 for (i = 0; i < NUM_AOIS; i++) {
1439 struct mfb_info *mi = data->fsl_diu_info[i].par;
1440
1441 if (mi->count)
1442 disable = false;
1443 }
1444 if (disable)
1445 out_be32(&data->diu_reg->int_mask, 0xffffffff);
1446 fsl_diu_disable_panel(info);
1447 }
1448
1449 spin_unlock(&diu_lock);
1450 return res;
1451 }
1452
1453 static struct fb_ops fsl_diu_ops = {
1454 .owner = THIS_MODULE,
1455 .fb_check_var = fsl_diu_check_var,
1456 .fb_set_par = fsl_diu_set_par,
1457 .fb_setcolreg = fsl_diu_setcolreg,
1458 .fb_pan_display = fsl_diu_pan_display,
1459 .fb_fillrect = cfb_fillrect,
1460 .fb_copyarea = cfb_copyarea,
1461 .fb_imageblit = cfb_imageblit,
1462 .fb_ioctl = fsl_diu_ioctl,
1463 .fb_open = fsl_diu_open,
1464 .fb_release = fsl_diu_release,
1465 .fb_cursor = fsl_diu_cursor,
1466 };
1467
1468 static int install_fb(struct fb_info *info)
1469 {
1470 int rc;
1471 struct mfb_info *mfbi = info->par;
1472 struct fsl_diu_data *data = mfbi->parent;
1473 const char *aoi_mode, *init_aoi_mode = "320x240";
1474 struct fb_videomode *db = fsl_diu_mode_db;
1475 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1476 int has_default_mode = 1;
1477
1478 info->var.activate = FB_ACTIVATE_NOW;
1479 info->fbops = &fsl_diu_ops;
1480 info->flags = FBINFO_DEFAULT | FBINFO_VIRTFB | FBINFO_PARTIAL_PAN_OK |
1481 FBINFO_READS_FAST;
1482 info->pseudo_palette = mfbi->pseudo_palette;
1483
1484 rc = fb_alloc_cmap(&info->cmap, 16, 0);
1485 if (rc)
1486 return rc;
1487
1488 if (mfbi->index == PLANE0) {
1489 if (data->has_edid) {
1490 /* Now build modedb from EDID */
1491 fb_edid_to_monspecs(data->edid_data, &info->monspecs);
1492 fb_videomode_to_modelist(info->monspecs.modedb,
1493 info->monspecs.modedb_len,
1494 &info->modelist);
1495 db = info->monspecs.modedb;
1496 dbsize = info->monspecs.modedb_len;
1497 }
1498 aoi_mode = fb_mode;
1499 } else {
1500 aoi_mode = init_aoi_mode;
1501 }
1502 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
1503 default_bpp);
1504 if (!rc) {
1505 /*
1506 * For plane 0 we continue and look into
1507 * driver's internal modedb.
1508 */
1509 if ((mfbi->index == PLANE0) && data->has_edid)
1510 has_default_mode = 0;
1511 else
1512 return -EINVAL;
1513 }
1514
1515 if (!has_default_mode) {
1516 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
1517 ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
1518 if (rc)
1519 has_default_mode = 1;
1520 }
1521
1522 /* Still not found, use preferred mode from database if any */
1523 if (!has_default_mode && info->monspecs.modedb) {
1524 struct fb_monspecs *specs = &info->monspecs;
1525 struct fb_videomode *modedb = &specs->modedb[0];
1526
1527 /*
1528 * Get preferred timing. If not found,
1529 * first mode in database will be used.
1530 */
1531 if (specs->misc & FB_MISC_1ST_DETAIL) {
1532 int i;
1533
1534 for (i = 0; i < specs->modedb_len; i++) {
1535 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1536 modedb = &specs->modedb[i];
1537 break;
1538 }
1539 }
1540 }
1541
1542 info->var.bits_per_pixel = default_bpp;
1543 fb_videomode_to_var(&info->var, modedb);
1544 }
1545
1546 if (fsl_diu_check_var(&info->var, info)) {
1547 dev_err(info->dev, "fsl_diu_check_var failed\n");
1548 unmap_video_memory(info);
1549 fb_dealloc_cmap(&info->cmap);
1550 return -EINVAL;
1551 }
1552
1553 if (register_framebuffer(info) < 0) {
1554 dev_err(info->dev, "register_framebuffer failed\n");
1555 unmap_video_memory(info);
1556 fb_dealloc_cmap(&info->cmap);
1557 return -EINVAL;
1558 }
1559
1560 mfbi->registered = 1;
1561 dev_info(info->dev, "%s registered successfully\n", mfbi->id);
1562
1563 return 0;
1564 }
1565
1566 static void uninstall_fb(struct fb_info *info)
1567 {
1568 struct mfb_info *mfbi = info->par;
1569
1570 if (!mfbi->registered)
1571 return;
1572
1573 unregister_framebuffer(info);
1574 unmap_video_memory(info);
1575 if (&info->cmap)
1576 fb_dealloc_cmap(&info->cmap);
1577
1578 mfbi->registered = 0;
1579 }
1580
1581 static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1582 {
1583 struct diu __iomem *hw = dev_id;
1584 uint32_t status = in_be32(&hw->int_status);
1585
1586 if (status) {
1587 /* This is the workaround for underrun */
1588 if (status & INT_UNDRUN) {
1589 out_be32(&hw->diu_mode, 0);
1590 udelay(1);
1591 out_be32(&hw->diu_mode, 1);
1592 }
1593 #if defined(CONFIG_NOT_COHERENT_CACHE)
1594 else if (status & INT_VSYNC) {
1595 unsigned int i;
1596
1597 for (i = 0; i < coherence_data_size;
1598 i += d_cache_line_size)
1599 __asm__ __volatile__ (
1600 "dcbz 0, %[input]"
1601 ::[input]"r"(&coherence_data[i]));
1602 }
1603 #endif
1604 return IRQ_HANDLED;
1605 }
1606 return IRQ_NONE;
1607 }
1608
1609 #ifdef CONFIG_PM
1610 /*
1611 * Power management hooks. Note that we won't be called from IRQ context,
1612 * unlike the blank functions above, so we may sleep.
1613 */
1614 static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
1615 {
1616 struct fsl_diu_data *data;
1617
1618 data = dev_get_drvdata(&ofdev->dev);
1619 disable_lcdc(data->fsl_diu_info);
1620
1621 return 0;
1622 }
1623
1624 static int fsl_diu_resume(struct platform_device *ofdev)
1625 {
1626 struct fsl_diu_data *data;
1627 unsigned int i;
1628
1629 data = dev_get_drvdata(&ofdev->dev);
1630
1631 fsl_diu_enable_interrupts(data);
1632 update_lcdc(data->fsl_diu_info);
1633 for (i = 0; i < NUM_AOIS; i++) {
1634 if (data->mfb[i].count)
1635 fsl_diu_enable_panel(&data->fsl_diu_info[i]);
1636 }
1637
1638 return 0;
1639 }
1640
1641 #else
1642 #define fsl_diu_suspend NULL
1643 #define fsl_diu_resume NULL
1644 #endif /* CONFIG_PM */
1645
1646 static ssize_t store_monitor(struct device *device,
1647 struct device_attribute *attr, const char *buf, size_t count)
1648 {
1649 enum fsl_diu_monitor_port old_monitor_port;
1650 struct fsl_diu_data *data =
1651 container_of(attr, struct fsl_diu_data, dev_attr);
1652
1653 old_monitor_port = data->monitor_port;
1654 data->monitor_port = fsl_diu_name_to_port(buf);
1655
1656 if (old_monitor_port != data->monitor_port) {
1657 /* All AOIs need adjust pixel format
1658 * fsl_diu_set_par only change the pixsel format here
1659 * unlikely to fail. */
1660 unsigned int i;
1661
1662 for (i=0; i < NUM_AOIS; i++)
1663 fsl_diu_set_par(&data->fsl_diu_info[i]);
1664 }
1665 return count;
1666 }
1667
1668 static ssize_t show_monitor(struct device *device,
1669 struct device_attribute *attr, char *buf)
1670 {
1671 struct fsl_diu_data *data =
1672 container_of(attr, struct fsl_diu_data, dev_attr);
1673
1674 switch (data->monitor_port) {
1675 case FSL_DIU_PORT_DVI:
1676 return sprintf(buf, "DVI\n");
1677 case FSL_DIU_PORT_LVDS:
1678 return sprintf(buf, "Single-link LVDS\n");
1679 case FSL_DIU_PORT_DLVDS:
1680 return sprintf(buf, "Dual-link LVDS\n");
1681 }
1682
1683 return 0;
1684 }
1685
1686 static int fsl_diu_probe(struct platform_device *pdev)
1687 {
1688 struct device_node *np = pdev->dev.of_node;
1689 struct mfb_info *mfbi;
1690 struct fsl_diu_data *data;
1691 dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */
1692 const void *prop;
1693 unsigned int i;
1694 int ret;
1695
1696 data = dmam_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data),
1697 &dma_addr, GFP_DMA | __GFP_ZERO);
1698 if (!data)
1699 return -ENOMEM;
1700 data->dma_addr = dma_addr;
1701
1702 /*
1703 * dma_alloc_coherent() uses a page allocator, so the address is
1704 * always page-aligned. We need the memory to be 32-byte aligned,
1705 * so that's good. However, if one day the allocator changes, we
1706 * need to catch that. It's not worth the effort to handle unaligned
1707 * alloctions now because it's highly unlikely to ever be a problem.
1708 */
1709 if ((unsigned long)data & 31) {
1710 dev_err(&pdev->dev, "misaligned allocation");
1711 ret = -ENOMEM;
1712 goto error;
1713 }
1714
1715 spin_lock_init(&data->reg_lock);
1716
1717 for (i = 0; i < NUM_AOIS; i++) {
1718 struct fb_info *info = &data->fsl_diu_info[i];
1719
1720 info->device = &pdev->dev;
1721 info->par = &data->mfb[i];
1722
1723 /*
1724 * We store the physical address of the AD in the reserved
1725 * 'paddr' field of the AD itself.
1726 */
1727 data->ad[i].paddr = DMA_ADDR(data, ad[i]);
1728
1729 info->fix.smem_start = 0;
1730
1731 /* Initialize the AOI data structure */
1732 mfbi = info->par;
1733 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
1734 mfbi->parent = data;
1735 mfbi->ad = &data->ad[i];
1736 }
1737
1738 /* Get the EDID data from the device tree, if present */
1739 prop = of_get_property(np, "edid", &ret);
1740 if (prop && ret == EDID_LENGTH) {
1741 memcpy(data->edid_data, prop, EDID_LENGTH);
1742 data->has_edid = true;
1743 }
1744
1745 data->diu_reg = of_iomap(np, 0);
1746 if (!data->diu_reg) {
1747 dev_err(&pdev->dev, "cannot map DIU registers\n");
1748 ret = -EFAULT;
1749 goto error;
1750 }
1751
1752 /* Get the IRQ of the DIU */
1753 data->irq = irq_of_parse_and_map(np, 0);
1754
1755 if (!data->irq) {
1756 dev_err(&pdev->dev, "could not get DIU IRQ\n");
1757 ret = -EINVAL;
1758 goto error;
1759 }
1760 data->monitor_port = monitor_port;
1761
1762 /* Initialize the dummy Area Descriptor */
1763 data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi));
1764 data->dummy_ad.pix_fmt = 0x88882317;
1765 data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1766 data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2);
1767 data->dummy_ad.offset_xyi = 0;
1768 data->dummy_ad.offset_xyd = 0;
1769 data->dummy_ad.next_ad = 0;
1770 data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad);
1771
1772 /*
1773 * Let DIU continue to display splash screen if it was pre-initialized
1774 * by the bootloader; otherwise, clear the display.
1775 */
1776 if (in_be32(&data->diu_reg->diu_mode) == MFB_MODE0)
1777 out_be32(&data->diu_reg->desc[0], 0);
1778
1779 out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
1780 out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
1781
1782 /*
1783 * Older versions of U-Boot leave interrupts enabled, so disable
1784 * all of them and clear the status register.
1785 */
1786 out_be32(&data->diu_reg->int_mask, 0xffffffff);
1787 in_be32(&data->diu_reg->int_status);
1788
1789 ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb",
1790 data->diu_reg);
1791 if (ret) {
1792 dev_err(&pdev->dev, "could not claim irq\n");
1793 goto error;
1794 }
1795
1796 for (i = 0; i < NUM_AOIS; i++) {
1797 ret = install_fb(&data->fsl_diu_info[i]);
1798 if (ret) {
1799 dev_err(&pdev->dev, "could not register fb %d\n", i);
1800 free_irq(data->irq, data->diu_reg);
1801 goto error;
1802 }
1803 }
1804
1805 sysfs_attr_init(&data->dev_attr.attr);
1806 data->dev_attr.attr.name = "monitor";
1807 data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1808 data->dev_attr.show = show_monitor;
1809 data->dev_attr.store = store_monitor;
1810 ret = device_create_file(&pdev->dev, &data->dev_attr);
1811 if (ret) {
1812 dev_err(&pdev->dev, "could not create sysfs file %s\n",
1813 data->dev_attr.attr.name);
1814 }
1815
1816 dev_set_drvdata(&pdev->dev, data);
1817 return 0;
1818
1819 error:
1820 for (i = 0; i < NUM_AOIS; i++)
1821 uninstall_fb(&data->fsl_diu_info[i]);
1822
1823 iounmap(data->diu_reg);
1824
1825 return ret;
1826 }
1827
1828 static int fsl_diu_remove(struct platform_device *pdev)
1829 {
1830 struct fsl_diu_data *data;
1831 int i;
1832
1833 data = dev_get_drvdata(&pdev->dev);
1834 disable_lcdc(&data->fsl_diu_info[0]);
1835
1836 free_irq(data->irq, data->diu_reg);
1837
1838 for (i = 0; i < NUM_AOIS; i++)
1839 uninstall_fb(&data->fsl_diu_info[i]);
1840
1841 iounmap(data->diu_reg);
1842
1843 return 0;
1844 }
1845
1846 #ifndef MODULE
1847 static int __init fsl_diu_setup(char *options)
1848 {
1849 char *opt;
1850 unsigned long val;
1851
1852 if (!options || !*options)
1853 return 0;
1854
1855 while ((opt = strsep(&options, ",")) != NULL) {
1856 if (!*opt)
1857 continue;
1858 if (!strncmp(opt, "monitor=", 8)) {
1859 monitor_port = fsl_diu_name_to_port(opt + 8);
1860 } else if (!strncmp(opt, "bpp=", 4)) {
1861 if (!kstrtoul(opt + 4, 10, &val))
1862 default_bpp = val;
1863 } else
1864 fb_mode = opt;
1865 }
1866
1867 return 0;
1868 }
1869 #endif
1870
1871 static struct of_device_id fsl_diu_match[] = {
1872 #ifdef CONFIG_PPC_MPC512x
1873 {
1874 .compatible = "fsl,mpc5121-diu",
1875 },
1876 #endif
1877 {
1878 .compatible = "fsl,diu",
1879 },
1880 {}
1881 };
1882 MODULE_DEVICE_TABLE(of, fsl_diu_match);
1883
1884 static struct platform_driver fsl_diu_driver = {
1885 .driver = {
1886 .name = "fsl-diu-fb",
1887 .of_match_table = fsl_diu_match,
1888 },
1889 .probe = fsl_diu_probe,
1890 .remove = fsl_diu_remove,
1891 .suspend = fsl_diu_suspend,
1892 .resume = fsl_diu_resume,
1893 };
1894
1895 static int __init fsl_diu_init(void)
1896 {
1897 #ifdef CONFIG_NOT_COHERENT_CACHE
1898 struct device_node *np;
1899 const u32 *prop;
1900 #endif
1901 int ret;
1902 #ifndef MODULE
1903 char *option;
1904
1905 /*
1906 * For kernel boot options (in 'video=xxxfb:<options>' format)
1907 */
1908 if (fb_get_options("fslfb", &option))
1909 return -ENODEV;
1910 fsl_diu_setup(option);
1911 #else
1912 monitor_port = fsl_diu_name_to_port(monitor_string);
1913 #endif
1914
1915 /*
1916 * Must to verify set_pixel_clock. If not implement on platform,
1917 * then that means that there is no platform support for the DIU.
1918 */
1919 if (!diu_ops.set_pixel_clock)
1920 return -ENODEV;
1921
1922 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
1923
1924 #ifdef CONFIG_NOT_COHERENT_CACHE
1925 np = of_find_node_by_type(NULL, "cpu");
1926 if (!np) {
1927 pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
1928 return -ENODEV;
1929 }
1930
1931 prop = of_get_property(np, "d-cache-size", NULL);
1932 if (prop == NULL) {
1933 pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
1934 "in 'cpu' node\n");
1935 of_node_put(np);
1936 return -ENODEV;
1937 }
1938
1939 /*
1940 * Freescale PLRU requires 13/8 times the cache size to do a proper
1941 * displacement flush
1942 */
1943 coherence_data_size = be32_to_cpup(prop) * 13;
1944 coherence_data_size /= 8;
1945
1946 pr_debug("fsl-diu-fb: coherence data size is %zu bytes\n",
1947 coherence_data_size);
1948
1949 prop = of_get_property(np, "d-cache-line-size", NULL);
1950 if (prop == NULL) {
1951 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
1952 "in 'cpu' node\n");
1953 of_node_put(np);
1954 return -ENODEV;
1955 }
1956 d_cache_line_size = be32_to_cpup(prop);
1957
1958 pr_debug("fsl-diu-fb: cache lines size is %u bytes\n",
1959 d_cache_line_size);
1960
1961 of_node_put(np);
1962 coherence_data = vmalloc(coherence_data_size);
1963 if (!coherence_data) {
1964 pr_err("fsl-diu-fb: could not allocate coherence data "
1965 "(size=%zu)\n", coherence_data_size);
1966 return -ENOMEM;
1967 }
1968
1969 #endif
1970
1971 ret = platform_driver_register(&fsl_diu_driver);
1972 if (ret) {
1973 pr_err("fsl-diu-fb: failed to register platform driver\n");
1974 #if defined(CONFIG_NOT_COHERENT_CACHE)
1975 vfree(coherence_data);
1976 #endif
1977 }
1978 return ret;
1979 }
1980
1981 static void __exit fsl_diu_exit(void)
1982 {
1983 platform_driver_unregister(&fsl_diu_driver);
1984 #if defined(CONFIG_NOT_COHERENT_CACHE)
1985 vfree(coherence_data);
1986 #endif
1987 }
1988
1989 module_init(fsl_diu_init);
1990 module_exit(fsl_diu_exit);
1991
1992 MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1993 MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1994 MODULE_LICENSE("GPL");
1995
1996 module_param_named(mode, fb_mode, charp, 0);
1997 MODULE_PARM_DESC(mode,
1998 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1999 module_param_named(bpp, default_bpp, ulong, 0);
2000 MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
2001 module_param_named(monitor, monitor_string, charp, 0);
2002 MODULE_PARM_DESC(monitor, "Specify the monitor port "
2003 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
2004
Ubuntu Artful kernel mirror