drivers/video/fbdev/geode/gxfb.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
   4  *
   5  * Geode GX2 header information
   6  */
   7 #ifndef _GXFB_H_
   8 #define _GXFB_H_
   9
  10 #include <linux/io.h>
  11
  12 #define GP_REG_COUNT   (0x50 / 4)
  13 #define DC_REG_COUNT   (0x90 / 4)
  14 #define VP_REG_COUNT   (0x138 / 8)
  15 #define FP_REG_COUNT   (0x68 / 8)
  16
  17 #define DC_PAL_COUNT   0x104
  18
  19 struct gxfb_par {
  20         int enable_crt;
  21         void __iomem *dc_regs;
  22         void __iomem *vid_regs;
  23         void __iomem *gp_regs;
  24 #ifdef CONFIG_PM
  25         int powered_down;
  26
  27         /* register state, for power management functionality */
  28         struct {
  29                 uint64_t padsel;
  30                 uint64_t dotpll;
  31         } msr;
  32
  33         uint32_t gp[GP_REG_COUNT];
  34         uint32_t dc[DC_REG_COUNT];
  35         uint64_t vp[VP_REG_COUNT];
  36         uint64_t fp[FP_REG_COUNT];
  37
  38         uint32_t pal[DC_PAL_COUNT];
  39 #endif
  40 };
  41
  42 unsigned int gx_frame_buffer_size(void);
  43 int gx_line_delta(int xres, int bpp);
  44 void gx_set_mode(struct fb_info *info);
  45 void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
  46                 unsigned red, unsigned green, unsigned blue);
  47
  48 void gx_set_dclk_frequency(struct fb_info *info);
  49 void gx_configure_display(struct fb_info *info);
  50 int gx_blank_display(struct fb_info *info, int blank_mode);
  51
  52 #ifdef CONFIG_PM
  53 int gx_powerdown(struct fb_info *info);
  54 int gx_powerup(struct fb_info *info);
  55 #endif
  56
  57
  58 /* Graphics Processor registers (table 6-23 from the data book) */
  59 enum gp_registers {
  60         GP_DST_OFFSET = 0,
  61         GP_SRC_OFFSET,
  62         GP_STRIDE,
  63         GP_WID_HEIGHT,
  64
  65         GP_SRC_COLOR_FG,
  66         GP_SRC_COLOR_BG,
  67         GP_PAT_COLOR_0,
  68         GP_PAT_COLOR_1,
  69
  70         GP_PAT_COLOR_2,
  71         GP_PAT_COLOR_3,
  72         GP_PAT_COLOR_4,
  73         GP_PAT_COLOR_5,
  74
  75         GP_PAT_DATA_0,
  76         GP_PAT_DATA_1,
  77         GP_RASTER_MODE,
  78         GP_VECTOR_MODE,
  79
  80         GP_BLT_MODE,
  81         GP_BLT_STATUS,
  82         GP_HST_SRC,
  83         GP_BASE_OFFSET, /* 0x4c */
  84 };
  85
  86 #define GP_BLT_STATUS_BLT_PENDING       (1 << 2)
  87 #define GP_BLT_STATUS_BLT_BUSY          (1 << 0)
  88
  89
  90 /* Display Controller registers (table 6-38 from the data book) */
  91 enum dc_registers {
  92         DC_UNLOCK = 0,
  93         DC_GENERAL_CFG,
  94         DC_DISPLAY_CFG,
  95         DC_RSVD_0,
  96
  97         DC_FB_ST_OFFSET,
  98         DC_CB_ST_OFFSET,
  99         DC_CURS_ST_OFFSET,
 100         DC_ICON_ST_OFFSET,
 101
 102         DC_VID_Y_ST_OFFSET,
 103         DC_VID_U_ST_OFFSET,
 104         DC_VID_V_ST_OFFSET,
 105         DC_RSVD_1,
 106
 107         DC_LINE_SIZE,
 108         DC_GFX_PITCH,
 109         DC_VID_YUV_PITCH,
 110         DC_RSVD_2,
 111
 112         DC_H_ACTIVE_TIMING,
 113         DC_H_BLANK_TIMING,
 114         DC_H_SYNC_TIMING,
 115         DC_RSVD_3,
 116
 117         DC_V_ACTIVE_TIMING,
 118         DC_V_BLANK_TIMING,
 119         DC_V_SYNC_TIMING,
 120         DC_RSVD_4,
 121
 122         DC_CURSOR_X,
 123         DC_CURSOR_Y,
 124         DC_ICON_X,
 125         DC_LINE_CNT,
 126
 127         DC_PAL_ADDRESS,
 128         DC_PAL_DATA,
 129         DC_DFIFO_DIAG,
 130         DC_CFIFO_DIAG,
 131
 132         DC_VID_DS_DELTA,
 133         DC_GLIU0_MEM_OFFSET,
 134         DC_RSVD_5,
 135         DC_DV_ACC, /* 0x8c */
 136 };
 137
 138 #define DC_UNLOCK_LOCK                  0x00000000
 139 #define DC_UNLOCK_UNLOCK                0x00004758      /* magic value */
 140
 141 #define DC_GENERAL_CFG_YUVM             (1 << 20)
 142 #define DC_GENERAL_CFG_VDSE             (1 << 19)
 143 #define DC_GENERAL_CFG_DFHPEL_SHIFT     12
 144 #define DC_GENERAL_CFG_DFHPSL_SHIFT     8
 145 #define DC_GENERAL_CFG_DECE             (1 << 6)
 146 #define DC_GENERAL_CFG_CMPE             (1 << 5)
 147 #define DC_GENERAL_CFG_VIDE             (1 << 3)
 148 #define DC_GENERAL_CFG_ICNE             (1 << 2)
 149 #define DC_GENERAL_CFG_CURE             (1 << 1)
 150 #define DC_GENERAL_CFG_DFLE             (1 << 0)
 151
 152 #define DC_DISPLAY_CFG_A20M             (1 << 31)
 153 #define DC_DISPLAY_CFG_A18M             (1 << 30)
 154 #define DC_DISPLAY_CFG_PALB             (1 << 25)
 155 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
 156 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
 157 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
 158 #define DC_DISPLAY_CFG_VDEN             (1 << 4)
 159 #define DC_DISPLAY_CFG_GDEN             (1 << 3)
 160 #define DC_DISPLAY_CFG_TGEN             (1 << 0)
 161
 162
 163 /*
 164  * Video Processor registers (table 6-54).
 165  * There is space for 64 bit values, but we never use more than the
 166  * lower 32 bits.  The actual register save/restore code only bothers
 167  * to restore those 32 bits.
 168  */
 169 enum vp_registers {
 170         VP_VCFG = 0,
 171         VP_DCFG,
 172
 173         VP_VX,
 174         VP_VY,
 175
 176         VP_VS,
 177         VP_VCK,
 178
 179         VP_VCM,
 180         VP_GAR,
 181
 182         VP_GDR,
 183         VP_RSVD_0,
 184
 185         VP_MISC,
 186         VP_CCS,
 187
 188         VP_RSVD_1,
 189         VP_RSVD_2,
 190
 191         VP_RSVD_3,
 192         VP_VDC,
 193
 194         VP_VCO,
 195         VP_CRC,
 196
 197         VP_CRC32,
 198         VP_VDE,
 199
 200         VP_CCK,
 201         VP_CCM,
 202
 203         VP_CC1,
 204         VP_CC2,
 205
 206         VP_A1X,
 207         VP_A1Y,
 208
 209         VP_A1C,
 210         VP_A1T,
 211
 212         VP_A2X,
 213         VP_A2Y,
 214
 215         VP_A2C,
 216         VP_A2T,
 217
 218         VP_A3X,
 219         VP_A3Y,
 220
 221         VP_A3C,
 222         VP_A3T,
 223
 224         VP_VRR,
 225         VP_AWT,
 226
 227         VP_VTM, /* 0x130 */
 228 };
 229
 230 #define VP_VCFG_VID_EN                  (1 << 0)
 231
 232 #define VP_DCFG_DAC_VREF                (1 << 26)
 233 #define VP_DCFG_GV_GAM                  (1 << 21)
 234 #define VP_DCFG_VG_CK                   (1 << 20)
 235 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
 236 #define VP_DCFG_CRT_SYNC_SKW            ((1 << 14) | (1 << 15) | (1 << 16))
 237 #define VP_DCFG_CRT_VSYNC_POL           (1 << 9)
 238 #define VP_DCFG_CRT_HSYNC_POL           (1 << 8)
 239 #define VP_DCFG_FP_DATA_EN              (1 << 7)        /* undocumented */
 240 #define VP_DCFG_FP_PWR_EN               (1 << 6)        /* undocumented */
 241 #define VP_DCFG_DAC_BL_EN               (1 << 3)
 242 #define VP_DCFG_VSYNC_EN                (1 << 2)
 243 #define VP_DCFG_HSYNC_EN                (1 << 1)
 244 #define VP_DCFG_CRT_EN                  (1 << 0)
 245
 246 #define VP_MISC_GAM_EN                  (1 << 0)
 247 #define VP_MISC_DACPWRDN                (1 << 10)
 248 #define VP_MISC_APWRDN                  (1 << 11)
 249
 250
 251 /*
 252  * Flat Panel registers (table 6-55).
 253  * Also 64 bit registers; see above note about 32-bit handling.
 254  */
 255
 256 /* we're actually in the VP register space, starting at address 0x400 */
 257 #define VP_FP_START             0x400
 258
 259 enum fp_registers {
 260         FP_PT1 = 0,
 261         FP_PT2,
 262
 263         FP_PM,
 264         FP_DFC,
 265
 266         FP_BLFSR,
 267         FP_RLFSR,
 268
 269         FP_FMI,
 270         FP_FMD,
 271
 272         FP_RSVD_0,
 273         FP_DCA,
 274
 275         FP_DMD,
 276         FP_CRC,
 277
 278         FP_FBB, /* 0x460 */
 279 };
 280
 281 #define FP_PT1_VSIZE_SHIFT              16              /* undocumented? */
 282 #define FP_PT1_VSIZE_MASK               0x7FF0000       /* undocumented? */
 283
 284 #define FP_PT2_HSP                      (1 << 22)
 285 #define FP_PT2_VSP                      (1 << 23)
 286
 287 #define FP_PM_P                         (1 << 24)       /* panel power on */
 288 #define FP_PM_PANEL_PWR_UP              (1 << 3)        /* r/o */
 289 #define FP_PM_PANEL_PWR_DOWN            (1 << 2)        /* r/o */
 290 #define FP_PM_PANEL_OFF                 (1 << 1)        /* r/o */
 291 #define FP_PM_PANEL_ON                  (1 << 0)        /* r/o */
 292
 293 #define FP_DFC_NFI                      ((1 << 4) | (1 << 5) | (1 << 6))
 294
 295
 296 /* register access functions */
 297
 298 static inline uint32_t read_gp(struct gxfb_par *par, int reg)
 299 {
 300         return readl(par->gp_regs + 4*reg);
 301 }
 302
 303 static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val)
 304 {
 305         writel(val, par->gp_regs + 4*reg);
 306 }
 307
 308 static inline uint32_t read_dc(struct gxfb_par *par, int reg)
 309 {
 310         return readl(par->dc_regs + 4*reg);
 311 }
 312
 313 static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val)
 314 {
 315         writel(val, par->dc_regs + 4*reg);
 316 }
 317
 318 static inline uint32_t read_vp(struct gxfb_par *par, int reg)
 319 {
 320         return readl(par->vid_regs + 8*reg);
 321 }
 322
 323 static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val)
 324 {
 325         writel(val, par->vid_regs + 8*reg);
 326 }
 327
 328 static inline uint32_t read_fp(struct gxfb_par *par, int reg)
 329 {
 330         return readl(par->vid_regs + 8*reg + VP_FP_START);
 331 }
 332
 333 static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val)
 334 {
 335         writel(val, par->vid_regs + 8*reg + VP_FP_START);
 336 }
 337
 338
 339 /* MSRs are defined in linux/cs5535.h; their bitfields are here */
 340
 341 #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3)
 342 #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2)
 343 #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2  (1 << 1)
 344
 345 #define MSR_GLCP_DOTPLL_LOCK            (1 << 25)       /* r/o */
 346 #define MSR_GLCP_DOTPLL_BYPASS          (1 << 15)
 347 #define MSR_GLCP_DOTPLL_DOTRESET        (1 << 0)
 348
 349 #define MSR_GX_MSR_PADSEL_MASK          0x3FFFFFFF      /* undocumented? */
 350 #define MSR_GX_MSR_PADSEL_TFT           0x1FFFFFFF      /* undocumented? */
 351
 352 #define MSR_GX_GLD_MSR_CONFIG_FP        (1 << 3)
 353
 354 #endif