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Linux 3.16-rc2
[mirror_ubuntu-zesty-kernel.git] / drivers / video / fbdev / mx3fb.c
1 /*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/errno.h>
17 #include <linux/string.h>
18 #include <linux/interrupt.h>
19 #include <linux/slab.h>
20 #include <linux/fb.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/console.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/dma/ipu-dma.h>
30 #include <linux/backlight.h>
31
32 #include <linux/platform_data/dma-imx.h>
33 #include <linux/platform_data/video-mx3fb.h>
34
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37
38 #define MX3FB_NAME "mx3_sdc_fb"
39
40 #define MX3FB_REG_OFFSET 0xB4
41
42 /* SDC Registers */
43 #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
44 #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
45 #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
46 #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
47 #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
48 #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
49 #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
50 #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
51 #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
52 #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
53 #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
54
55 /* Register bits */
56 #define SDC_COM_TFT_COLOR 0x00000001UL
57 #define SDC_COM_FG_EN 0x00000010UL
58 #define SDC_COM_GWSEL 0x00000020UL
59 #define SDC_COM_GLB_A 0x00000040UL
60 #define SDC_COM_KEY_COLOR_G 0x00000080UL
61 #define SDC_COM_BG_EN 0x00000200UL
62 #define SDC_COM_SHARP 0x00001000UL
63
64 #define SDC_V_SYNC_WIDTH_L 0x00000001UL
65
66 /* Display Interface registers */
67 #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
68 #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
69 #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
70 #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
71 #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
72 #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
73 #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
74 #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
75 #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
76 #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
77 #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
78 #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
79 #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
80 #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
81 #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
82 #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
83 #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
84 #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
85 #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
86 #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
87 #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
88 #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
89 #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
90 #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
91 #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
92 #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
93 #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
94 #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
95 #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
96 #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
97 #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
98 #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
99 #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
100 #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
101 #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
102 #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
103 #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
104 #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
105 #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
106
107 /* DI_DISP_SIG_POL bits */
108 #define DI_D3_VSYNC_POL_SHIFT 28
109 #define DI_D3_HSYNC_POL_SHIFT 27
110 #define DI_D3_DRDY_SHARP_POL_SHIFT 26
111 #define DI_D3_CLK_POL_SHIFT 25
112 #define DI_D3_DATA_POL_SHIFT 24
113
114 /* DI_DISP_IF_CONF bits */
115 #define DI_D3_CLK_IDLE_SHIFT 26
116 #define DI_D3_CLK_SEL_SHIFT 25
117 #define DI_D3_DATAMSK_SHIFT 24
118
119 enum ipu_panel {
120 IPU_PANEL_SHARP_TFT,
121 IPU_PANEL_TFT,
122 };
123
124 struct ipu_di_signal_cfg {
125 unsigned datamask_en:1;
126 unsigned clksel_en:1;
127 unsigned clkidle_en:1;
128 unsigned data_pol:1; /* true = inverted */
129 unsigned clk_pol:1; /* true = rising edge */
130 unsigned enable_pol:1;
131 unsigned Hsync_pol:1; /* true = active high */
132 unsigned Vsync_pol:1;
133 };
134
135 static const struct fb_videomode mx3fb_modedb[] = {
136 {
137 /* 240x320 @ 60 Hz */
138 .name = "Sharp-QVGA",
139 .refresh = 60,
140 .xres = 240,
141 .yres = 320,
142 .pixclock = 185925,
143 .left_margin = 9,
144 .right_margin = 16,
145 .upper_margin = 7,
146 .lower_margin = 9,
147 .hsync_len = 1,
148 .vsync_len = 1,
149 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
150 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
151 FB_SYNC_CLK_IDLE_EN,
152 .vmode = FB_VMODE_NONINTERLACED,
153 .flag = 0,
154 }, {
155 /* 240x33 @ 60 Hz */
156 .name = "Sharp-CLI",
157 .refresh = 60,
158 .xres = 240,
159 .yres = 33,
160 .pixclock = 185925,
161 .left_margin = 9,
162 .right_margin = 16,
163 .upper_margin = 7,
164 .lower_margin = 9 + 287,
165 .hsync_len = 1,
166 .vsync_len = 1,
167 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
168 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
169 FB_SYNC_CLK_IDLE_EN,
170 .vmode = FB_VMODE_NONINTERLACED,
171 .flag = 0,
172 }, {
173 /* 640x480 @ 60 Hz */
174 .name = "NEC-VGA",
175 .refresh = 60,
176 .xres = 640,
177 .yres = 480,
178 .pixclock = 38255,
179 .left_margin = 144,
180 .right_margin = 0,
181 .upper_margin = 34,
182 .lower_margin = 40,
183 .hsync_len = 1,
184 .vsync_len = 1,
185 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
186 .vmode = FB_VMODE_NONINTERLACED,
187 .flag = 0,
188 }, {
189 /* NTSC TV output */
190 .name = "TV-NTSC",
191 .refresh = 60,
192 .xres = 640,
193 .yres = 480,
194 .pixclock = 37538,
195 .left_margin = 38,
196 .right_margin = 858 - 640 - 38 - 3,
197 .upper_margin = 36,
198 .lower_margin = 518 - 480 - 36 - 1,
199 .hsync_len = 3,
200 .vsync_len = 1,
201 .sync = 0,
202 .vmode = FB_VMODE_NONINTERLACED,
203 .flag = 0,
204 }, {
205 /* PAL TV output */
206 .name = "TV-PAL",
207 .refresh = 50,
208 .xres = 640,
209 .yres = 480,
210 .pixclock = 37538,
211 .left_margin = 38,
212 .right_margin = 960 - 640 - 38 - 32,
213 .upper_margin = 32,
214 .lower_margin = 555 - 480 - 32 - 3,
215 .hsync_len = 32,
216 .vsync_len = 3,
217 .sync = 0,
218 .vmode = FB_VMODE_NONINTERLACED,
219 .flag = 0,
220 }, {
221 /* TV output VGA mode, 640x480 @ 65 Hz */
222 .name = "TV-VGA",
223 .refresh = 60,
224 .xres = 640,
225 .yres = 480,
226 .pixclock = 40574,
227 .left_margin = 35,
228 .right_margin = 45,
229 .upper_margin = 9,
230 .lower_margin = 1,
231 .hsync_len = 46,
232 .vsync_len = 5,
233 .sync = 0,
234 .vmode = FB_VMODE_NONINTERLACED,
235 .flag = 0,
236 },
237 };
238
239 struct mx3fb_data {
240 struct fb_info *fbi;
241 int backlight_level;
242 void __iomem *reg_base;
243 spinlock_t lock;
244 struct device *dev;
245 struct backlight_device *bl;
246
247 uint32_t h_start_width;
248 uint32_t v_start_width;
249 enum disp_data_mapping disp_data_fmt;
250 };
251
252 struct dma_chan_request {
253 struct mx3fb_data *mx3fb;
254 enum ipu_channel id;
255 };
256
257 /* MX3 specific framebuffer information. */
258 struct mx3fb_info {
259 int blank;
260 enum ipu_channel ipu_ch;
261 uint32_t cur_ipu_buf;
262
263 u32 pseudo_palette[16];
264
265 struct completion flip_cmpl;
266 struct mutex mutex; /* Protects fb-ops */
267 struct mx3fb_data *mx3fb;
268 struct idmac_channel *idmac_channel;
269 struct dma_async_tx_descriptor *txd;
270 dma_cookie_t cookie;
271 struct scatterlist sg[2];
272
273 struct fb_var_screeninfo cur_var; /* current var info */
274 };
275
276 static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value);
277 static u32 sdc_get_brightness(struct mx3fb_data *mx3fb);
278
279 static int mx3fb_bl_get_brightness(struct backlight_device *bl)
280 {
281 struct mx3fb_data *fbd = bl_get_data(bl);
282
283 return sdc_get_brightness(fbd);
284 }
285
286 static int mx3fb_bl_update_status(struct backlight_device *bl)
287 {
288 struct mx3fb_data *fbd = bl_get_data(bl);
289 int brightness = bl->props.brightness;
290
291 if (bl->props.power != FB_BLANK_UNBLANK)
292 brightness = 0;
293 if (bl->props.fb_blank != FB_BLANK_UNBLANK)
294 brightness = 0;
295
296 fbd->backlight_level = (fbd->backlight_level & ~0xFF) | brightness;
297
298 sdc_set_brightness(fbd, fbd->backlight_level);
299
300 return 0;
301 }
302
303 static const struct backlight_ops mx3fb_lcdc_bl_ops = {
304 .update_status = mx3fb_bl_update_status,
305 .get_brightness = mx3fb_bl_get_brightness,
306 };
307
308 static void mx3fb_init_backlight(struct mx3fb_data *fbd)
309 {
310 struct backlight_properties props;
311 struct backlight_device *bl;
312
313 if (fbd->bl)
314 return;
315
316 memset(&props, 0, sizeof(struct backlight_properties));
317 props.max_brightness = 0xff;
318 props.type = BACKLIGHT_RAW;
319 sdc_set_brightness(fbd, fbd->backlight_level);
320
321 bl = backlight_device_register("mx3fb-bl", fbd->dev, fbd,
322 &mx3fb_lcdc_bl_ops, &props);
323 if (IS_ERR(bl)) {
324 dev_err(fbd->dev, "error %ld on backlight register\n",
325 PTR_ERR(bl));
326 return;
327 }
328
329 fbd->bl = bl;
330 bl->props.power = FB_BLANK_UNBLANK;
331 bl->props.fb_blank = FB_BLANK_UNBLANK;
332 bl->props.brightness = mx3fb_bl_get_brightness(bl);
333 }
334
335 static void mx3fb_exit_backlight(struct mx3fb_data *fbd)
336 {
337 if (fbd->bl)
338 backlight_device_unregister(fbd->bl);
339 }
340
341 static void mx3fb_dma_done(void *);
342
343 /* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
344 static const char *fb_mode;
345 static unsigned long default_bpp = 16;
346
347 static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
348 {
349 return __raw_readl(mx3fb->reg_base + reg);
350 }
351
352 static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
353 {
354 __raw_writel(value, mx3fb->reg_base + reg);
355 }
356
357 struct di_mapping {
358 uint32_t b0, b1, b2;
359 };
360
361 static const struct di_mapping di_mappings[] = {
362 [IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f },
363 [IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f },
364 [IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 },
365 };
366
367 static void sdc_fb_init(struct mx3fb_info *fbi)
368 {
369 struct mx3fb_data *mx3fb = fbi->mx3fb;
370 uint32_t reg;
371
372 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
373
374 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
375 }
376
377 /* Returns enabled flag before uninit */
378 static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
379 {
380 struct mx3fb_data *mx3fb = fbi->mx3fb;
381 uint32_t reg;
382
383 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
384
385 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
386
387 return reg & SDC_COM_BG_EN;
388 }
389
390 static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
391 {
392 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
393 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
394 struct dma_chan *dma_chan = &ichan->dma_chan;
395 unsigned long flags;
396 dma_cookie_t cookie;
397
398 if (mx3_fbi->txd)
399 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
400 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
401 else
402 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
403
404 /* This enables the channel */
405 if (mx3_fbi->cookie < 0) {
406 mx3_fbi->txd = dmaengine_prep_slave_sg(dma_chan,
407 &mx3_fbi->sg[0], 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
408 if (!mx3_fbi->txd) {
409 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
410 dma_chan->chan_id);
411 return;
412 }
413
414 mx3_fbi->txd->callback_param = mx3_fbi->txd;
415 mx3_fbi->txd->callback = mx3fb_dma_done;
416
417 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
418 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
419 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
420 } else {
421 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
422 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
423 dma_chan->chan_id);
424 return;
425 }
426
427 /* Just re-activate the same buffer */
428 dma_async_issue_pending(dma_chan);
429 cookie = mx3_fbi->cookie;
430 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
431 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
432 }
433
434 if (cookie >= 0) {
435 spin_lock_irqsave(&mx3fb->lock, flags);
436 sdc_fb_init(mx3_fbi);
437 mx3_fbi->cookie = cookie;
438 spin_unlock_irqrestore(&mx3fb->lock, flags);
439 }
440
441 /*
442 * Attention! Without this msleep the channel keeps generating
443 * interrupts. Next sdc_set_brightness() is going to be called
444 * from mx3fb_blank().
445 */
446 msleep(2);
447 }
448
449 static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
450 {
451 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
452 uint32_t enabled;
453 unsigned long flags;
454
455 if (mx3_fbi->txd == NULL)
456 return;
457
458 spin_lock_irqsave(&mx3fb->lock, flags);
459
460 enabled = sdc_fb_uninit(mx3_fbi);
461
462 spin_unlock_irqrestore(&mx3fb->lock, flags);
463
464 mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan,
465 DMA_TERMINATE_ALL, 0);
466 mx3_fbi->txd = NULL;
467 mx3_fbi->cookie = -EINVAL;
468 }
469
470 /**
471 * sdc_set_window_pos() - set window position of the respective plane.
472 * @mx3fb: mx3fb context.
473 * @channel: IPU DMAC channel ID.
474 * @x_pos: X coordinate relative to the top left corner to place window at.
475 * @y_pos: Y coordinate relative to the top left corner to place window at.
476 * @return: 0 on success or negative error code on failure.
477 */
478 static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
479 int16_t x_pos, int16_t y_pos)
480 {
481 if (channel != IDMAC_SDC_0)
482 return -EINVAL;
483
484 x_pos += mx3fb->h_start_width;
485 y_pos += mx3fb->v_start_width;
486
487 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
488 return 0;
489 }
490
491 /**
492 * sdc_init_panel() - initialize a synchronous LCD panel.
493 * @mx3fb: mx3fb context.
494 * @panel: panel type.
495 * @pixel_clk: desired pixel clock frequency in Hz.
496 * @width: width of panel in pixels.
497 * @height: height of panel in pixels.
498 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
499 * and the start of valid data.
500 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
501 * @h_end_width: number of pixel clocks between the end of valid data
502 * and the HSYNC signal for next line.
503 * @v_start_width: number of lines between the VSYNC signal pulse and the
504 * start of valid data.
505 * @v_sync_width: width of the VSYNC signal in units of lines
506 * @v_end_width: number of lines between the end of valid data and the
507 * VSYNC signal for next frame.
508 * @sig: bitfield of signal polarities for LCD interface.
509 * @return: 0 on success or negative error code on failure.
510 */
511 static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
512 uint32_t pixel_clk,
513 uint16_t width, uint16_t height,
514 uint16_t h_start_width, uint16_t h_sync_width,
515 uint16_t h_end_width, uint16_t v_start_width,
516 uint16_t v_sync_width, uint16_t v_end_width,
517 struct ipu_di_signal_cfg sig)
518 {
519 unsigned long lock_flags;
520 uint32_t reg;
521 uint32_t old_conf;
522 uint32_t div;
523 struct clk *ipu_clk;
524 const struct di_mapping *map;
525
526 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
527
528 if (v_sync_width == 0 || h_sync_width == 0)
529 return -EINVAL;
530
531 /* Init panel size and blanking periods */
532 reg = ((uint32_t) (h_sync_width - 1) << 26) |
533 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
534 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
535
536 #ifdef DEBUG
537 printk(KERN_CONT " hor_conf %x,", reg);
538 #endif
539
540 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
541 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
542 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
543
544 #ifdef DEBUG
545 printk(KERN_CONT " ver_conf %x\n", reg);
546 #endif
547
548 mx3fb->h_start_width = h_start_width;
549 mx3fb->v_start_width = v_start_width;
550
551 switch (panel) {
552 case IPU_PANEL_SHARP_TFT:
553 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
554 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
555 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
556 break;
557 case IPU_PANEL_TFT:
558 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 /* Init clocking */
565
566 /*
567 * Calculate divider: fractional part is 4 bits so simply multiple by
568 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
569 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
570 */
571 ipu_clk = clk_get(mx3fb->dev, NULL);
572 if (!IS_ERR(ipu_clk)) {
573 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
574 clk_put(ipu_clk);
575 } else {
576 div = 0;
577 }
578
579 if (div < 0x40) { /* Divider less than 4 */
580 dev_dbg(mx3fb->dev,
581 "InitPanel() - Pixel clock divider less than 4\n");
582 div = 0x40;
583 }
584
585 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
586 pixel_clk, div >> 4, (div & 7) * 125);
587
588 spin_lock_irqsave(&mx3fb->lock, lock_flags);
589
590 /*
591 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
592 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
593 * debug. DISP3_IF_CLK_UP_WR is 0
594 */
595 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
596
597 /* DI settings */
598 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
599 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
600 sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
601 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
602 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
603
604 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
605 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
606 sig.clk_pol << DI_D3_CLK_POL_SHIFT |
607 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
608 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
609 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
610 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
611
612 map = &di_mappings[mx3fb->disp_data_fmt];
613 mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP);
614 mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP);
615 mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP);
616
617 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
618
619 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
620 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
621 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
622 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
623 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
624 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
625
626 return 0;
627 }
628
629 /**
630 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
631 * @mx3fb: mx3fb context.
632 * @channel: IPU DMAC channel ID.
633 * @enable: boolean to enable or disable color keyl.
634 * @color_key: 24-bit RGB color to use as transparent color key.
635 * @return: 0 on success or negative error code on failure.
636 */
637 static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
638 bool enable, uint32_t color_key)
639 {
640 uint32_t reg, sdc_conf;
641 unsigned long lock_flags;
642
643 spin_lock_irqsave(&mx3fb->lock, lock_flags);
644
645 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
646 if (channel == IDMAC_SDC_0)
647 sdc_conf &= ~SDC_COM_GWSEL;
648 else
649 sdc_conf |= SDC_COM_GWSEL;
650
651 if (enable) {
652 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
653 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
654 SDC_GW_CTRL);
655
656 sdc_conf |= SDC_COM_KEY_COLOR_G;
657 } else {
658 sdc_conf &= ~SDC_COM_KEY_COLOR_G;
659 }
660 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
661
662 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
663
664 return 0;
665 }
666
667 /**
668 * sdc_set_global_alpha() - set global alpha blending modes.
669 * @mx3fb: mx3fb context.
670 * @enable: boolean to enable or disable global alpha blending. If disabled,
671 * per pixel blending is used.
672 * @alpha: global alpha value.
673 * @return: 0 on success or negative error code on failure.
674 */
675 static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
676 {
677 uint32_t reg;
678 unsigned long lock_flags;
679
680 spin_lock_irqsave(&mx3fb->lock, lock_flags);
681
682 if (enable) {
683 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
684 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
685
686 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
687 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
688 } else {
689 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
690 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
691 }
692
693 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
694
695 return 0;
696 }
697
698 static u32 sdc_get_brightness(struct mx3fb_data *mx3fb)
699 {
700 u32 brightness;
701
702 brightness = mx3fb_read_reg(mx3fb, SDC_PWM_CTRL);
703 brightness = (brightness >> 16) & 0xFF;
704
705 return brightness;
706 }
707
708 static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
709 {
710 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
711 /* This might be board-specific */
712 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
713 return;
714 }
715
716 static uint32_t bpp_to_pixfmt(int bpp)
717 {
718 uint32_t pixfmt = 0;
719 switch (bpp) {
720 case 24:
721 pixfmt = IPU_PIX_FMT_BGR24;
722 break;
723 case 32:
724 pixfmt = IPU_PIX_FMT_BGR32;
725 break;
726 case 16:
727 pixfmt = IPU_PIX_FMT_RGB565;
728 break;
729 }
730 return pixfmt;
731 }
732
733 static int mx3fb_blank(int blank, struct fb_info *fbi);
734 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
735 bool lock);
736 static int mx3fb_unmap_video_memory(struct fb_info *fbi);
737
738 /**
739 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
740 * @info: framebuffer information pointer
741 * @return: 0 on success or negative error code on failure.
742 */
743 static int mx3fb_set_fix(struct fb_info *fbi)
744 {
745 struct fb_fix_screeninfo *fix = &fbi->fix;
746 struct fb_var_screeninfo *var = &fbi->var;
747
748 strncpy(fix->id, "DISP3 BG", 8);
749
750 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
751
752 fix->type = FB_TYPE_PACKED_PIXELS;
753 fix->accel = FB_ACCEL_NONE;
754 fix->visual = FB_VISUAL_TRUECOLOR;
755 fix->xpanstep = 1;
756 fix->ypanstep = 1;
757
758 return 0;
759 }
760
761 static void mx3fb_dma_done(void *arg)
762 {
763 struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
764 struct dma_chan *chan = tx_desc->txd.chan;
765 struct idmac_channel *ichannel = to_idmac_chan(chan);
766 struct mx3fb_data *mx3fb = ichannel->client;
767 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
768
769 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
770
771 /* We only need one interrupt, it will be re-enabled as needed */
772 disable_irq_nosync(ichannel->eof_irq);
773
774 complete(&mx3_fbi->flip_cmpl);
775 }
776
777 static bool mx3fb_must_set_par(struct fb_info *fbi)
778 {
779 struct mx3fb_info *mx3_fbi = fbi->par;
780 struct fb_var_screeninfo old_var = mx3_fbi->cur_var;
781 struct fb_var_screeninfo new_var = fbi->var;
782
783 if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
784 (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
785 return true;
786
787 /*
788 * Ignore xoffset and yoffset update,
789 * because pan display handles this case.
790 */
791 old_var.xoffset = new_var.xoffset;
792 old_var.yoffset = new_var.yoffset;
793
794 return !!memcmp(&old_var, &new_var, sizeof(struct fb_var_screeninfo));
795 }
796
797 static int __set_par(struct fb_info *fbi, bool lock)
798 {
799 u32 mem_len, cur_xoffset, cur_yoffset;
800 struct ipu_di_signal_cfg sig_cfg;
801 enum ipu_panel mode = IPU_PANEL_TFT;
802 struct mx3fb_info *mx3_fbi = fbi->par;
803 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
804 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
805 struct idmac_video_param *video = &ichan->params.video;
806 struct scatterlist *sg = mx3_fbi->sg;
807
808 /* Total cleanup */
809 if (mx3_fbi->txd)
810 sdc_disable_channel(mx3_fbi);
811
812 mx3fb_set_fix(fbi);
813
814 mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
815 if (mem_len > fbi->fix.smem_len) {
816 if (fbi->fix.smem_start)
817 mx3fb_unmap_video_memory(fbi);
818
819 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
820 return -ENOMEM;
821 }
822
823 sg_init_table(&sg[0], 1);
824 sg_init_table(&sg[1], 1);
825
826 sg_dma_address(&sg[0]) = fbi->fix.smem_start;
827 sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
828 fbi->fix.smem_len,
829 offset_in_page(fbi->screen_base));
830
831 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
832 memset(&sig_cfg, 0, sizeof(sig_cfg));
833 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
834 sig_cfg.Hsync_pol = true;
835 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
836 sig_cfg.Vsync_pol = true;
837 if (fbi->var.sync & FB_SYNC_CLK_INVERT)
838 sig_cfg.clk_pol = true;
839 if (fbi->var.sync & FB_SYNC_DATA_INVERT)
840 sig_cfg.data_pol = true;
841 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
842 sig_cfg.enable_pol = true;
843 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
844 sig_cfg.clkidle_en = true;
845 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
846 sig_cfg.clksel_en = true;
847 if (fbi->var.sync & FB_SYNC_SHARP_MODE)
848 mode = IPU_PANEL_SHARP_TFT;
849
850 dev_dbg(fbi->device, "pixclock = %ul Hz\n",
851 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
852
853 if (sdc_init_panel(mx3fb, mode,
854 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
855 fbi->var.xres, fbi->var.yres,
856 fbi->var.left_margin,
857 fbi->var.hsync_len,
858 fbi->var.right_margin +
859 fbi->var.hsync_len,
860 fbi->var.upper_margin,
861 fbi->var.vsync_len,
862 fbi->var.lower_margin +
863 fbi->var.vsync_len, sig_cfg) != 0) {
864 dev_err(fbi->device,
865 "mx3fb: Error initializing panel.\n");
866 return -EINVAL;
867 }
868 }
869
870 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
871
872 mx3_fbi->cur_ipu_buf = 0;
873
874 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
875 video->out_width = fbi->var.xres;
876 video->out_height = fbi->var.yres;
877 video->out_stride = fbi->var.xres_virtual;
878
879 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
880 sdc_enable_channel(mx3_fbi);
881 /*
882 * sg[0] points to fb smem_start address
883 * and is actually active in controller.
884 */
885 mx3_fbi->cur_var.xoffset = 0;
886 mx3_fbi->cur_var.yoffset = 0;
887 }
888
889 /*
890 * Preserve xoffset and yoffest in case they are
891 * inactive in controller as fb is blanked.
892 */
893 cur_xoffset = mx3_fbi->cur_var.xoffset;
894 cur_yoffset = mx3_fbi->cur_var.yoffset;
895 mx3_fbi->cur_var = fbi->var;
896 mx3_fbi->cur_var.xoffset = cur_xoffset;
897 mx3_fbi->cur_var.yoffset = cur_yoffset;
898
899 return 0;
900 }
901
902 /**
903 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
904 * @fbi: framebuffer information pointer.
905 * @return: 0 on success or negative error code on failure.
906 */
907 static int mx3fb_set_par(struct fb_info *fbi)
908 {
909 struct mx3fb_info *mx3_fbi = fbi->par;
910 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
911 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
912 int ret;
913
914 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
915
916 mutex_lock(&mx3_fbi->mutex);
917
918 ret = mx3fb_must_set_par(fbi) ? __set_par(fbi, true) : 0;
919
920 mutex_unlock(&mx3_fbi->mutex);
921
922 return ret;
923 }
924
925 /**
926 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
927 * @var: framebuffer variable parameters
928 * @fbi: framebuffer information pointer
929 */
930 static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
931 {
932 struct mx3fb_info *mx3_fbi = fbi->par;
933 u32 vtotal;
934 u32 htotal;
935
936 dev_dbg(fbi->device, "%s\n", __func__);
937
938 if (var->xres_virtual < var->xres)
939 var->xres_virtual = var->xres;
940 if (var->yres_virtual < var->yres)
941 var->yres_virtual = var->yres;
942
943 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
944 (var->bits_per_pixel != 16))
945 var->bits_per_pixel = default_bpp;
946
947 switch (var->bits_per_pixel) {
948 case 16:
949 var->red.length = 5;
950 var->red.offset = 11;
951 var->red.msb_right = 0;
952
953 var->green.length = 6;
954 var->green.offset = 5;
955 var->green.msb_right = 0;
956
957 var->blue.length = 5;
958 var->blue.offset = 0;
959 var->blue.msb_right = 0;
960
961 var->transp.length = 0;
962 var->transp.offset = 0;
963 var->transp.msb_right = 0;
964 break;
965 case 24:
966 var->red.length = 8;
967 var->red.offset = 16;
968 var->red.msb_right = 0;
969
970 var->green.length = 8;
971 var->green.offset = 8;
972 var->green.msb_right = 0;
973
974 var->blue.length = 8;
975 var->blue.offset = 0;
976 var->blue.msb_right = 0;
977
978 var->transp.length = 0;
979 var->transp.offset = 0;
980 var->transp.msb_right = 0;
981 break;
982 case 32:
983 var->red.length = 8;
984 var->red.offset = 16;
985 var->red.msb_right = 0;
986
987 var->green.length = 8;
988 var->green.offset = 8;
989 var->green.msb_right = 0;
990
991 var->blue.length = 8;
992 var->blue.offset = 0;
993 var->blue.msb_right = 0;
994
995 var->transp.length = 8;
996 var->transp.offset = 24;
997 var->transp.msb_right = 0;
998 break;
999 }
1000
1001 if (var->pixclock < 1000) {
1002 htotal = var->xres + var->right_margin + var->hsync_len +
1003 var->left_margin;
1004 vtotal = var->yres + var->lower_margin + var->vsync_len +
1005 var->upper_margin;
1006 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
1007 var->pixclock = KHZ2PICOS(var->pixclock);
1008 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
1009 var->pixclock);
1010 }
1011
1012 var->height = -1;
1013 var->width = -1;
1014 var->grayscale = 0;
1015
1016 /* Preserve sync flags */
1017 var->sync |= mx3_fbi->cur_var.sync;
1018 mx3_fbi->cur_var.sync |= var->sync;
1019
1020 return 0;
1021 }
1022
1023 static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
1024 {
1025 chan &= 0xffff;
1026 chan >>= 16 - bf->length;
1027 return chan << bf->offset;
1028 }
1029
1030 static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
1031 unsigned int green, unsigned int blue,
1032 unsigned int trans, struct fb_info *fbi)
1033 {
1034 struct mx3fb_info *mx3_fbi = fbi->par;
1035 u32 val;
1036 int ret = 1;
1037
1038 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
1039
1040 mutex_lock(&mx3_fbi->mutex);
1041 /*
1042 * If greyscale is true, then we convert the RGB value
1043 * to greyscale no matter what visual we are using.
1044 */
1045 if (fbi->var.grayscale)
1046 red = green = blue = (19595 * red + 38470 * green +
1047 7471 * blue) >> 16;
1048 switch (fbi->fix.visual) {
1049 case FB_VISUAL_TRUECOLOR:
1050 /*
1051 * 16-bit True Colour. We encode the RGB value
1052 * according to the RGB bitfield information.
1053 */
1054 if (regno < 16) {
1055 u32 *pal = fbi->pseudo_palette;
1056
1057 val = chan_to_field(red, &fbi->var.red);
1058 val |= chan_to_field(green, &fbi->var.green);
1059 val |= chan_to_field(blue, &fbi->var.blue);
1060
1061 pal[regno] = val;
1062
1063 ret = 0;
1064 }
1065 break;
1066
1067 case FB_VISUAL_STATIC_PSEUDOCOLOR:
1068 case FB_VISUAL_PSEUDOCOLOR:
1069 break;
1070 }
1071 mutex_unlock(&mx3_fbi->mutex);
1072
1073 return ret;
1074 }
1075
1076 static void __blank(int blank, struct fb_info *fbi)
1077 {
1078 struct mx3fb_info *mx3_fbi = fbi->par;
1079 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
1080 int was_blank = mx3_fbi->blank;
1081
1082 mx3_fbi->blank = blank;
1083
1084 /* Attention!
1085 * Do not call sdc_disable_channel() for a channel that is disabled
1086 * already! This will result in a kernel NULL pointer dereference
1087 * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are
1088 * handled equally by this driver.
1089 */
1090 if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK)
1091 return;
1092
1093 switch (blank) {
1094 case FB_BLANK_POWERDOWN:
1095 case FB_BLANK_VSYNC_SUSPEND:
1096 case FB_BLANK_HSYNC_SUSPEND:
1097 case FB_BLANK_NORMAL:
1098 sdc_set_brightness(mx3fb, 0);
1099 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1100 /* Give LCD time to update - enough for 50 and 60 Hz */
1101 msleep(25);
1102 sdc_disable_channel(mx3_fbi);
1103 break;
1104 case FB_BLANK_UNBLANK:
1105 sdc_enable_channel(mx3_fbi);
1106 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1107 break;
1108 }
1109 }
1110
1111 /**
1112 * mx3fb_blank() - blank the display.
1113 */
1114 static int mx3fb_blank(int blank, struct fb_info *fbi)
1115 {
1116 struct mx3fb_info *mx3_fbi = fbi->par;
1117
1118 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1119 blank, fbi->screen_base, fbi->fix.smem_len);
1120
1121 if (mx3_fbi->blank == blank)
1122 return 0;
1123
1124 mutex_lock(&mx3_fbi->mutex);
1125 __blank(blank, fbi);
1126 mutex_unlock(&mx3_fbi->mutex);
1127
1128 return 0;
1129 }
1130
1131 /**
1132 * mx3fb_pan_display() - pan or wrap the display
1133 * @var: variable screen buffer information.
1134 * @info: framebuffer information pointer.
1135 *
1136 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1137 */
1138 static int mx3fb_pan_display(struct fb_var_screeninfo *var,
1139 struct fb_info *fbi)
1140 {
1141 struct mx3fb_info *mx3_fbi = fbi->par;
1142 u32 y_bottom;
1143 unsigned long base;
1144 off_t offset;
1145 dma_cookie_t cookie;
1146 struct scatterlist *sg = mx3_fbi->sg;
1147 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1148 struct dma_async_tx_descriptor *txd;
1149 int ret;
1150
1151 dev_dbg(fbi->device, "%s [%c]\n", __func__,
1152 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1153
1154 if (var->xoffset > 0) {
1155 dev_dbg(fbi->device, "x panning not supported\n");
1156 return -EINVAL;
1157 }
1158
1159 if (mx3_fbi->cur_var.xoffset == var->xoffset &&
1160 mx3_fbi->cur_var.yoffset == var->yoffset)
1161 return 0; /* No change, do nothing */
1162
1163 y_bottom = var->yoffset;
1164
1165 if (!(var->vmode & FB_VMODE_YWRAP))
1166 y_bottom += fbi->var.yres;
1167
1168 if (y_bottom > fbi->var.yres_virtual)
1169 return -EINVAL;
1170
1171 mutex_lock(&mx3_fbi->mutex);
1172
1173 offset = var->yoffset * fbi->fix.line_length
1174 + var->xoffset * (fbi->var.bits_per_pixel / 8);
1175 base = fbi->fix.smem_start + offset;
1176
1177 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1178 mx3_fbi->cur_ipu_buf, base);
1179
1180 /*
1181 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1182 * which we will need for the next device_prep_slave_sg(). The
1183 * IRQ-handler will disable the IRQ again.
1184 */
1185 init_completion(&mx3_fbi->flip_cmpl);
1186 enable_irq(mx3_fbi->idmac_channel->eof_irq);
1187
1188 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1189 if (ret <= 0) {
1190 mutex_unlock(&mx3_fbi->mutex);
1191 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1192 "user interrupt" : "timeout");
1193 disable_irq(mx3_fbi->idmac_channel->eof_irq);
1194 return ret ? : -ETIMEDOUT;
1195 }
1196
1197 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1198
1199 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1200 sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1201 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1202 offset_in_page(fbi->screen_base + offset));
1203
1204 if (mx3_fbi->txd)
1205 async_tx_ack(mx3_fbi->txd);
1206
1207 txd = dmaengine_prep_slave_sg(dma_chan, sg +
1208 mx3_fbi->cur_ipu_buf, 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
1209 if (!txd) {
1210 dev_err(fbi->device,
1211 "Error preparing a DMA transaction descriptor.\n");
1212 mutex_unlock(&mx3_fbi->mutex);
1213 return -EIO;
1214 }
1215
1216 txd->callback_param = txd;
1217 txd->callback = mx3fb_dma_done;
1218
1219 /*
1220 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1221 * should switch to another buffer
1222 */
1223 cookie = txd->tx_submit(txd);
1224 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1225 if (cookie < 0) {
1226 dev_err(fbi->device,
1227 "Error updating SDC buf %d to address=0x%08lX\n",
1228 mx3_fbi->cur_ipu_buf, base);
1229 mutex_unlock(&mx3_fbi->mutex);
1230 return -EIO;
1231 }
1232
1233 mx3_fbi->txd = txd;
1234
1235 fbi->var.xoffset = var->xoffset;
1236 fbi->var.yoffset = var->yoffset;
1237
1238 if (var->vmode & FB_VMODE_YWRAP)
1239 fbi->var.vmode |= FB_VMODE_YWRAP;
1240 else
1241 fbi->var.vmode &= ~FB_VMODE_YWRAP;
1242
1243 mx3_fbi->cur_var = fbi->var;
1244
1245 mutex_unlock(&mx3_fbi->mutex);
1246
1247 dev_dbg(fbi->device, "Update complete\n");
1248
1249 return 0;
1250 }
1251
1252 /*
1253 * This structure contains the pointers to the control functions that are
1254 * invoked by the core framebuffer driver to perform operations like
1255 * blitting, rectangle filling, copy regions and cursor definition.
1256 */
1257 static struct fb_ops mx3fb_ops = {
1258 .owner = THIS_MODULE,
1259 .fb_set_par = mx3fb_set_par,
1260 .fb_check_var = mx3fb_check_var,
1261 .fb_setcolreg = mx3fb_setcolreg,
1262 .fb_pan_display = mx3fb_pan_display,
1263 .fb_fillrect = cfb_fillrect,
1264 .fb_copyarea = cfb_copyarea,
1265 .fb_imageblit = cfb_imageblit,
1266 .fb_blank = mx3fb_blank,
1267 };
1268
1269 #ifdef CONFIG_PM
1270 /*
1271 * Power management hooks. Note that we won't be called from IRQ context,
1272 * unlike the blank functions above, so we may sleep.
1273 */
1274
1275 /*
1276 * Suspends the framebuffer and blanks the screen. Power management support
1277 */
1278 static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1279 {
1280 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1281 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1282
1283 console_lock();
1284 fb_set_suspend(mx3fb->fbi, 1);
1285 console_unlock();
1286
1287 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1288 sdc_disable_channel(mx3_fbi);
1289 sdc_set_brightness(mx3fb, 0);
1290
1291 }
1292 return 0;
1293 }
1294
1295 /*
1296 * Resumes the framebuffer and unblanks the screen. Power management support
1297 */
1298 static int mx3fb_resume(struct platform_device *pdev)
1299 {
1300 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1301 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
1302
1303 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1304 sdc_enable_channel(mx3_fbi);
1305 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1306 }
1307
1308 console_lock();
1309 fb_set_suspend(mx3fb->fbi, 0);
1310 console_unlock();
1311
1312 return 0;
1313 }
1314 #else
1315 #define mx3fb_suspend NULL
1316 #define mx3fb_resume NULL
1317 #endif
1318
1319 /*
1320 * Main framebuffer functions
1321 */
1322
1323 /**
1324 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
1325 * @fbi: framebuffer information pointer
1326 * @mem_len: length of mapped memory
1327 * @lock: do not lock during initialisation
1328 * @return: Error code indicating success or failure
1329 *
1330 * This buffer is remapped into a non-cached, non-buffered, memory region to
1331 * allow palette and pixel writes to occur without flushing the cache. Once this
1332 * area is remapped, all virtual memory access to the video memory should occur
1333 * at the new region.
1334 */
1335 static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1336 bool lock)
1337 {
1338 int retval = 0;
1339 dma_addr_t addr;
1340
1341 fbi->screen_base = dma_alloc_writecombine(fbi->device,
1342 mem_len,
1343 &addr, GFP_DMA | GFP_KERNEL);
1344
1345 if (!fbi->screen_base) {
1346 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
1347 mem_len);
1348 retval = -EBUSY;
1349 goto err0;
1350 }
1351
1352 if (lock)
1353 mutex_lock(&fbi->mm_lock);
1354 fbi->fix.smem_start = addr;
1355 fbi->fix.smem_len = mem_len;
1356 if (lock)
1357 mutex_unlock(&fbi->mm_lock);
1358
1359 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1360 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
1361
1362 fbi->screen_size = fbi->fix.smem_len;
1363
1364 /* Clear the screen */
1365 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1366
1367 return 0;
1368
1369 err0:
1370 fbi->fix.smem_len = 0;
1371 fbi->fix.smem_start = 0;
1372 fbi->screen_base = NULL;
1373 return retval;
1374 }
1375
1376 /**
1377 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
1378 * @fbi: framebuffer information pointer
1379 * @return: error code indicating success or failure
1380 */
1381 static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1382 {
1383 dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1384 fbi->screen_base, fbi->fix.smem_start);
1385
1386 fbi->screen_base = NULL;
1387 mutex_lock(&fbi->mm_lock);
1388 fbi->fix.smem_start = 0;
1389 fbi->fix.smem_len = 0;
1390 mutex_unlock(&fbi->mm_lock);
1391 return 0;
1392 }
1393
1394 /**
1395 * mx3fb_init_fbinfo() - initialize framebuffer information object.
1396 * @return: initialized framebuffer structure.
1397 */
1398 static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1399 {
1400 struct fb_info *fbi;
1401 struct mx3fb_info *mx3fbi;
1402 int ret;
1403
1404 /* Allocate sufficient memory for the fb structure */
1405 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1406 if (!fbi)
1407 return NULL;
1408
1409 mx3fbi = fbi->par;
1410 mx3fbi->cookie = -EINVAL;
1411 mx3fbi->cur_ipu_buf = 0;
1412
1413 fbi->var.activate = FB_ACTIVATE_NOW;
1414
1415 fbi->fbops = ops;
1416 fbi->flags = FBINFO_FLAG_DEFAULT;
1417 fbi->pseudo_palette = mx3fbi->pseudo_palette;
1418
1419 mutex_init(&mx3fbi->mutex);
1420
1421 /* Allocate colormap */
1422 ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1423 if (ret < 0) {
1424 framebuffer_release(fbi);
1425 return NULL;
1426 }
1427
1428 return fbi;
1429 }
1430
1431 static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1432 {
1433 struct device *dev = mx3fb->dev;
1434 struct mx3fb_platform_data *mx3fb_pdata = dev_get_platdata(dev);
1435 const char *name = mx3fb_pdata->name;
1436 unsigned int irq;
1437 struct fb_info *fbi;
1438 struct mx3fb_info *mx3fbi;
1439 const struct fb_videomode *mode;
1440 int ret, num_modes;
1441
1442 if (mx3fb_pdata->disp_data_fmt >= ARRAY_SIZE(di_mappings)) {
1443 dev_err(dev, "Illegal display data format %d\n",
1444 mx3fb_pdata->disp_data_fmt);
1445 return -EINVAL;
1446 }
1447
1448 ichan->client = mx3fb;
1449 irq = ichan->eof_irq;
1450
1451 if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1452 return -EINVAL;
1453
1454 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1455 if (!fbi)
1456 return -ENOMEM;
1457
1458 if (!fb_mode)
1459 fb_mode = name;
1460
1461 if (!fb_mode) {
1462 ret = -EINVAL;
1463 goto emode;
1464 }
1465
1466 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1467 mode = mx3fb_pdata->mode;
1468 num_modes = mx3fb_pdata->num_modes;
1469 } else {
1470 mode = mx3fb_modedb;
1471 num_modes = ARRAY_SIZE(mx3fb_modedb);
1472 }
1473
1474 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1475 num_modes, NULL, default_bpp)) {
1476 ret = -EBUSY;
1477 goto emode;
1478 }
1479
1480 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
1481
1482 /* Default Y virtual size is 2x panel size */
1483 fbi->var.yres_virtual = fbi->var.yres * 2;
1484
1485 mx3fb->fbi = fbi;
1486
1487 /* set Display Interface clock period */
1488 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1489 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
1490
1491 sdc_set_brightness(mx3fb, 255);
1492 sdc_set_global_alpha(mx3fb, true, 0xFF);
1493 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
1494
1495 mx3fbi = fbi->par;
1496 mx3fbi->idmac_channel = ichan;
1497 mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
1498 mx3fbi->mx3fb = mx3fb;
1499 mx3fbi->blank = FB_BLANK_NORMAL;
1500
1501 mx3fb->disp_data_fmt = mx3fb_pdata->disp_data_fmt;
1502
1503 init_completion(&mx3fbi->flip_cmpl);
1504 disable_irq(ichan->eof_irq);
1505 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
1506 ret = __set_par(fbi, false);
1507 if (ret < 0)
1508 goto esetpar;
1509
1510 __blank(FB_BLANK_UNBLANK, fbi);
1511
1512 dev_info(dev, "registered, using mode %s\n", fb_mode);
1513
1514 ret = register_framebuffer(fbi);
1515 if (ret < 0)
1516 goto erfb;
1517
1518 return 0;
1519
1520 erfb:
1521 esetpar:
1522 emode:
1523 fb_dealloc_cmap(&fbi->cmap);
1524 framebuffer_release(fbi);
1525
1526 return ret;
1527 }
1528
1529 static bool chan_filter(struct dma_chan *chan, void *arg)
1530 {
1531 struct dma_chan_request *rq = arg;
1532 struct device *dev;
1533 struct mx3fb_platform_data *mx3fb_pdata;
1534
1535 if (!imx_dma_is_ipu(chan))
1536 return false;
1537
1538 if (!rq)
1539 return false;
1540
1541 dev = rq->mx3fb->dev;
1542 mx3fb_pdata = dev_get_platdata(dev);
1543
1544 return rq->id == chan->chan_id &&
1545 mx3fb_pdata->dma_dev == chan->device->dev;
1546 }
1547
1548 static void release_fbi(struct fb_info *fbi)
1549 {
1550 mx3fb_unmap_video_memory(fbi);
1551
1552 fb_dealloc_cmap(&fbi->cmap);
1553
1554 unregister_framebuffer(fbi);
1555 framebuffer_release(fbi);
1556 }
1557
1558 static int mx3fb_probe(struct platform_device *pdev)
1559 {
1560 struct device *dev = &pdev->dev;
1561 int ret;
1562 struct resource *sdc_reg;
1563 struct mx3fb_data *mx3fb;
1564 dma_cap_mask_t mask;
1565 struct dma_chan *chan;
1566 struct dma_chan_request rq;
1567
1568 /*
1569 * Display Interface (DI) and Synchronous Display Controller (SDC)
1570 * registers
1571 */
1572 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1573 if (!sdc_reg)
1574 return -EINVAL;
1575
1576 mx3fb = devm_kzalloc(&pdev->dev, sizeof(*mx3fb), GFP_KERNEL);
1577 if (!mx3fb)
1578 return -ENOMEM;
1579
1580 spin_lock_init(&mx3fb->lock);
1581
1582 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1583 if (!mx3fb->reg_base) {
1584 ret = -ENOMEM;
1585 goto eremap;
1586 }
1587
1588 pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
1589
1590 /* IDMAC interface */
1591 dmaengine_get();
1592
1593 mx3fb->dev = dev;
1594 platform_set_drvdata(pdev, mx3fb);
1595
1596 rq.mx3fb = mx3fb;
1597
1598 dma_cap_zero(mask);
1599 dma_cap_set(DMA_SLAVE, mask);
1600 dma_cap_set(DMA_PRIVATE, mask);
1601 rq.id = IDMAC_SDC_0;
1602 chan = dma_request_channel(mask, chan_filter, &rq);
1603 if (!chan) {
1604 ret = -EBUSY;
1605 goto ersdc0;
1606 }
1607
1608 mx3fb->backlight_level = 255;
1609
1610 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1611 if (ret < 0)
1612 goto eisdc0;
1613
1614 mx3fb_init_backlight(mx3fb);
1615
1616 return 0;
1617
1618 eisdc0:
1619 dma_release_channel(chan);
1620 ersdc0:
1621 dmaengine_put();
1622 iounmap(mx3fb->reg_base);
1623 eremap:
1624 dev_err(dev, "mx3fb: failed to register fb\n");
1625 return ret;
1626 }
1627
1628 static int mx3fb_remove(struct platform_device *dev)
1629 {
1630 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1631 struct fb_info *fbi = mx3fb->fbi;
1632 struct mx3fb_info *mx3_fbi = fbi->par;
1633 struct dma_chan *chan;
1634
1635 chan = &mx3_fbi->idmac_channel->dma_chan;
1636 release_fbi(fbi);
1637
1638 mx3fb_exit_backlight(mx3fb);
1639
1640 dma_release_channel(chan);
1641 dmaengine_put();
1642
1643 iounmap(mx3fb->reg_base);
1644 return 0;
1645 }
1646
1647 static struct platform_driver mx3fb_driver = {
1648 .driver = {
1649 .name = MX3FB_NAME,
1650 .owner = THIS_MODULE,
1651 },
1652 .probe = mx3fb_probe,
1653 .remove = mx3fb_remove,
1654 .suspend = mx3fb_suspend,
1655 .resume = mx3fb_resume,
1656 };
1657
1658 /*
1659 * Parse user specified options (`video=mx3fb:')
1660 * example:
1661 * video=mx3fb:bpp=16
1662 */
1663 static int __init mx3fb_setup(void)
1664 {
1665 #ifndef MODULE
1666 char *opt, *options = NULL;
1667
1668 if (fb_get_options("mx3fb", &options))
1669 return -ENODEV;
1670
1671 if (!options || !*options)
1672 return 0;
1673
1674 while ((opt = strsep(&options, ",")) != NULL) {
1675 if (!*opt)
1676 continue;
1677 if (!strncmp(opt, "bpp=", 4))
1678 default_bpp = simple_strtoul(opt + 4, NULL, 0);
1679 else
1680 fb_mode = opt;
1681 }
1682 #endif
1683
1684 return 0;
1685 }
1686
1687 static int __init mx3fb_init(void)
1688 {
1689 int ret = mx3fb_setup();
1690
1691 if (ret < 0)
1692 return ret;
1693
1694 ret = platform_driver_register(&mx3fb_driver);
1695 return ret;
1696 }
1697
1698 static void __exit mx3fb_exit(void)
1699 {
1700 platform_driver_unregister(&mx3fb_driver);
1701 }
1702
1703 module_init(mx3fb_init);
1704 module_exit(mx3fb_exit);
1705
1706 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1707 MODULE_DESCRIPTION("MX3 framebuffer driver");
1708 MODULE_ALIAS("platform:" MX3FB_NAME);
1709 MODULE_LICENSE("GPL v2");
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