2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/of_platform.h>
44 #include <video/omapdss.h>
45 #include <video/mipi_display.h>
48 #include "dss_features.h"
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg
{ u16 module
; u16 idx
; };
54 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
56 /* DSI Protocol Engine */
59 #define DSI_PROTO_SZ 0x200
61 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
62 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
63 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
64 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
65 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
66 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
67 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
68 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
69 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
70 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
71 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
72 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
73 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
74 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
75 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
76 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
77 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
78 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
79 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
80 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
81 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
82 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
83 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
84 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
85 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
86 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
87 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
88 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
89 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
90 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
91 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
92 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
93 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
94 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
99 #define DSI_PHY_OFFSET 0x200
100 #define DSI_PHY_SZ 0x40
102 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
103 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
104 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
105 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
106 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
108 /* DSI_PLL_CTRL_SCP */
111 #define DSI_PLL_OFFSET 0x300
112 #define DSI_PLL_SZ 0x20
114 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
115 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
116 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
117 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
118 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
120 #define REG_GET(dsidev, idx, start, end) \
121 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
123 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
124 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
126 /* Global interrupts */
127 #define DSI_IRQ_VC0 (1 << 0)
128 #define DSI_IRQ_VC1 (1 << 1)
129 #define DSI_IRQ_VC2 (1 << 2)
130 #define DSI_IRQ_VC3 (1 << 3)
131 #define DSI_IRQ_WAKEUP (1 << 4)
132 #define DSI_IRQ_RESYNC (1 << 5)
133 #define DSI_IRQ_PLL_LOCK (1 << 7)
134 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
135 #define DSI_IRQ_PLL_RECALL (1 << 9)
136 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
137 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
138 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
139 #define DSI_IRQ_TE_TRIGGER (1 << 16)
140 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
141 #define DSI_IRQ_SYNC_LOST (1 << 18)
142 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
143 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
144 #define DSI_IRQ_ERROR_MASK \
145 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
146 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
147 #define DSI_IRQ_CHANNEL_MASK 0xf
149 /* Virtual channel interrupts */
150 #define DSI_VC_IRQ_CS (1 << 0)
151 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
152 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
153 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
154 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
155 #define DSI_VC_IRQ_BTA (1 << 5)
156 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
157 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
158 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
159 #define DSI_VC_IRQ_ERROR_MASK \
160 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
161 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
162 DSI_VC_IRQ_FIFO_TX_UDF)
164 /* ComplexIO interrupts */
165 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
166 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
167 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
168 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
169 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
170 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
171 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
172 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
173 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
174 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
175 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
176 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
177 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
178 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
179 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
180 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
181 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
182 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
183 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
184 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
185 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
186 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
187 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
188 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
193 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
194 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
195 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
197 #define DSI_CIO_IRQ_ERROR_MASK \
198 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
199 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
200 DSI_CIO_IRQ_ERRSYNCESC5 | \
201 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
202 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
203 DSI_CIO_IRQ_ERRESC5 | \
204 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
205 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
206 DSI_CIO_IRQ_ERRCONTROL5 | \
207 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
208 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
209 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
210 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
211 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
213 typedef void (*omap_dsi_isr_t
) (void *arg
, u32 mask
);
215 static int dsi_display_init_dispc(struct platform_device
*dsidev
,
216 struct omap_overlay_manager
*mgr
);
217 static void dsi_display_uninit_dispc(struct platform_device
*dsidev
,
218 struct omap_overlay_manager
*mgr
);
220 static int dsi_vc_send_null(struct omap_dss_device
*dssdev
, int channel
);
222 #define DSI_MAX_NR_ISRS 2
223 #define DSI_MAX_NR_LANES 5
225 enum dsi_lane_function
{
234 struct dsi_lane_config
{
235 enum dsi_lane_function function
;
239 struct dsi_isr_data
{
247 DSI_FIFO_SIZE_32
= 1,
248 DSI_FIFO_SIZE_64
= 2,
249 DSI_FIFO_SIZE_96
= 3,
250 DSI_FIFO_SIZE_128
= 4,
254 DSI_VC_SOURCE_L4
= 0,
258 struct dsi_irq_stats
{
259 unsigned long last_reset
;
261 unsigned dsi_irqs
[32];
262 unsigned vc_irqs
[4][32];
263 unsigned cio_irqs
[32];
266 struct dsi_isr_tables
{
267 struct dsi_isr_data isr_table
[DSI_MAX_NR_ISRS
];
268 struct dsi_isr_data isr_table_vc
[4][DSI_MAX_NR_ISRS
];
269 struct dsi_isr_data isr_table_cio
[DSI_MAX_NR_ISRS
];
272 struct dsi_clk_calc_ctx
{
273 struct platform_device
*dsidev
;
277 const struct omap_dss_dsi_config
*config
;
279 unsigned long req_pck_min
, req_pck_nom
, req_pck_max
;
283 struct dsi_clock_info dsi_cinfo
;
284 struct dispc_clock_info dispc_cinfo
;
286 struct omap_video_timings dispc_vm
;
287 struct omap_dss_dsi_videomode_timings dsi_vm
;
291 struct platform_device
*pdev
;
292 void __iomem
*proto_base
;
293 void __iomem
*phy_base
;
294 void __iomem
*pll_base
;
305 struct dispc_clock_info user_dispc_cinfo
;
306 struct dsi_clock_info user_dsi_cinfo
;
308 struct dsi_clock_info current_cinfo
;
310 bool vdds_dsi_enabled
;
311 struct regulator
*vdds_dsi_reg
;
314 enum dsi_vc_source source
;
315 struct omap_dss_device
*dssdev
;
316 enum fifo_size tx_fifo_size
;
317 enum fifo_size rx_fifo_size
;
322 struct semaphore bus_lock
;
327 struct dsi_isr_tables isr_tables
;
328 /* space for a copy used by the interrupt handler */
329 struct dsi_isr_tables isr_tables_copy
;
332 #ifdef DSI_PERF_MEASURE
333 unsigned update_bytes
;
339 void (*framedone_callback
)(int, void *);
340 void *framedone_data
;
342 struct delayed_work framedone_timeout_work
;
344 #ifdef DSI_CATCH_MISSING_TE
345 struct timer_list te_timer
;
348 unsigned long cache_req_pck
;
349 unsigned long cache_clk_freq
;
350 struct dsi_clock_info cache_cinfo
;
353 spinlock_t errors_lock
;
354 #ifdef DSI_PERF_MEASURE
355 ktime_t perf_setup_time
;
356 ktime_t perf_start_time
;
361 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
362 spinlock_t irq_stats_lock
;
363 struct dsi_irq_stats irq_stats
;
365 /* DSI PLL Parameter Ranges */
366 unsigned long regm_max
, regn_max
;
367 unsigned long regm_dispc_max
, regm_dsi_max
;
368 unsigned long fint_min
, fint_max
;
369 unsigned long lpdiv_max
;
371 unsigned num_lanes_supported
;
372 unsigned line_buffer_size
;
374 struct dsi_lane_config lanes
[DSI_MAX_NR_LANES
];
375 unsigned num_lanes_used
;
377 unsigned scp_clk_refcount
;
379 struct dss_lcd_mgr_config mgr_config
;
380 struct omap_video_timings timings
;
381 enum omap_dss_dsi_pixel_format pix_fmt
;
382 enum omap_dss_dsi_mode mode
;
383 struct omap_dss_dsi_videomode_timings vm_timings
;
385 struct omap_dss_device output
;
388 struct dsi_packet_sent_handler_data
{
389 struct platform_device
*dsidev
;
390 struct completion
*completion
;
393 struct dsi_module_id_data
{
398 static const struct of_device_id dsi_of_match
[];
400 #ifdef DSI_PERF_MEASURE
401 static bool dsi_perf
;
402 module_param(dsi_perf
, bool, 0644);
405 static inline struct dsi_data
*dsi_get_dsidrv_data(struct platform_device
*dsidev
)
407 return dev_get_drvdata(&dsidev
->dev
);
410 static inline struct platform_device
*dsi_get_dsidev_from_dssdev(struct omap_dss_device
*dssdev
)
412 return to_platform_device(dssdev
->dev
);
415 struct platform_device
*dsi_get_dsidev_from_id(int module
)
417 struct omap_dss_device
*out
;
418 enum omap_dss_output_id id
;
422 id
= OMAP_DSS_OUTPUT_DSI1
;
425 id
= OMAP_DSS_OUTPUT_DSI2
;
431 out
= omap_dss_get_output(id
);
433 return out
? to_platform_device(out
->dev
) : NULL
;
436 static inline void dsi_write_reg(struct platform_device
*dsidev
,
437 const struct dsi_reg idx
, u32 val
)
439 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
443 case DSI_PROTO
: base
= dsi
->proto_base
; break;
444 case DSI_PHY
: base
= dsi
->phy_base
; break;
445 case DSI_PLL
: base
= dsi
->pll_base
; break;
449 __raw_writel(val
, base
+ idx
.idx
);
452 static inline u32
dsi_read_reg(struct platform_device
*dsidev
,
453 const struct dsi_reg idx
)
455 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
459 case DSI_PROTO
: base
= dsi
->proto_base
; break;
460 case DSI_PHY
: base
= dsi
->phy_base
; break;
461 case DSI_PLL
: base
= dsi
->pll_base
; break;
465 return __raw_readl(base
+ idx
.idx
);
468 static void dsi_bus_lock(struct omap_dss_device
*dssdev
)
470 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
471 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
473 down(&dsi
->bus_lock
);
476 static void dsi_bus_unlock(struct omap_dss_device
*dssdev
)
478 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
479 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
484 static bool dsi_bus_is_locked(struct platform_device
*dsidev
)
486 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
488 return dsi
->bus_lock
.count
== 0;
491 static void dsi_completion_handler(void *data
, u32 mask
)
493 complete((struct completion
*)data
);
496 static inline int wait_for_bit_change(struct platform_device
*dsidev
,
497 const struct dsi_reg idx
, int bitnum
, int value
)
499 unsigned long timeout
;
503 /* first busyloop to see if the bit changes right away */
506 if (REG_GET(dsidev
, idx
, bitnum
, bitnum
) == value
)
510 /* then loop for 500ms, sleeping for 1ms in between */
511 timeout
= jiffies
+ msecs_to_jiffies(500);
512 while (time_before(jiffies
, timeout
)) {
513 if (REG_GET(dsidev
, idx
, bitnum
, bitnum
) == value
)
516 wait
= ns_to_ktime(1000 * 1000);
517 set_current_state(TASK_UNINTERRUPTIBLE
);
518 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
524 u8
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt
)
527 case OMAP_DSS_DSI_FMT_RGB888
:
528 case OMAP_DSS_DSI_FMT_RGB666
:
530 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
532 case OMAP_DSS_DSI_FMT_RGB565
:
540 #ifdef DSI_PERF_MEASURE
541 static void dsi_perf_mark_setup(struct platform_device
*dsidev
)
543 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
544 dsi
->perf_setup_time
= ktime_get();
547 static void dsi_perf_mark_start(struct platform_device
*dsidev
)
549 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
550 dsi
->perf_start_time
= ktime_get();
553 static void dsi_perf_show(struct platform_device
*dsidev
, const char *name
)
555 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
556 ktime_t t
, setup_time
, trans_time
;
558 u32 setup_us
, trans_us
, total_us
;
565 setup_time
= ktime_sub(dsi
->perf_start_time
, dsi
->perf_setup_time
);
566 setup_us
= (u32
)ktime_to_us(setup_time
);
570 trans_time
= ktime_sub(t
, dsi
->perf_start_time
);
571 trans_us
= (u32
)ktime_to_us(trans_time
);
575 total_us
= setup_us
+ trans_us
;
577 total_bytes
= dsi
->update_bytes
;
579 printk(KERN_INFO
"DSI(%s): %u us + %u us = %u us (%uHz), "
580 "%u bytes, %u kbytes/sec\n",
585 1000*1000 / total_us
,
587 total_bytes
* 1000 / total_us
);
590 static inline void dsi_perf_mark_setup(struct platform_device
*dsidev
)
594 static inline void dsi_perf_mark_start(struct platform_device
*dsidev
)
598 static inline void dsi_perf_show(struct platform_device
*dsidev
,
604 static int verbose_irq
;
606 static void print_irq_status(u32 status
)
611 if (!verbose_irq
&& (status
& ~DSI_IRQ_CHANNEL_MASK
) == 0)
614 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
616 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
618 verbose_irq
? PIS(VC0
) : "",
619 verbose_irq
? PIS(VC1
) : "",
620 verbose_irq
? PIS(VC2
) : "",
621 verbose_irq
? PIS(VC3
) : "",
638 static void print_irq_status_vc(int channel
, u32 status
)
643 if (!verbose_irq
&& (status
& ~DSI_VC_IRQ_PACKET_SENT
) == 0)
646 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
648 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
654 verbose_irq
? PIS(PACKET_SENT
) : "",
659 PIS(PP_BUSY_CHANGE
));
663 static void print_irq_status_cio(u32 status
)
668 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
670 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
684 PIS(ERRCONTENTIONLP0_1
),
685 PIS(ERRCONTENTIONLP1_1
),
686 PIS(ERRCONTENTIONLP0_2
),
687 PIS(ERRCONTENTIONLP1_2
),
688 PIS(ERRCONTENTIONLP0_3
),
689 PIS(ERRCONTENTIONLP1_3
),
690 PIS(ULPSACTIVENOT_ALL0
),
691 PIS(ULPSACTIVENOT_ALL1
));
695 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
696 static void dsi_collect_irq_stats(struct platform_device
*dsidev
, u32 irqstatus
,
697 u32
*vcstatus
, u32 ciostatus
)
699 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
702 spin_lock(&dsi
->irq_stats_lock
);
704 dsi
->irq_stats
.irq_count
++;
705 dss_collect_irq_stats(irqstatus
, dsi
->irq_stats
.dsi_irqs
);
707 for (i
= 0; i
< 4; ++i
)
708 dss_collect_irq_stats(vcstatus
[i
], dsi
->irq_stats
.vc_irqs
[i
]);
710 dss_collect_irq_stats(ciostatus
, dsi
->irq_stats
.cio_irqs
);
712 spin_unlock(&dsi
->irq_stats_lock
);
715 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
718 static int debug_irq
;
720 static void dsi_handle_irq_errors(struct platform_device
*dsidev
, u32 irqstatus
,
721 u32
*vcstatus
, u32 ciostatus
)
723 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
726 if (irqstatus
& DSI_IRQ_ERROR_MASK
) {
727 DSSERR("DSI error, irqstatus %x\n", irqstatus
);
728 print_irq_status(irqstatus
);
729 spin_lock(&dsi
->errors_lock
);
730 dsi
->errors
|= irqstatus
& DSI_IRQ_ERROR_MASK
;
731 spin_unlock(&dsi
->errors_lock
);
732 } else if (debug_irq
) {
733 print_irq_status(irqstatus
);
736 for (i
= 0; i
< 4; ++i
) {
737 if (vcstatus
[i
] & DSI_VC_IRQ_ERROR_MASK
) {
738 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
740 print_irq_status_vc(i
, vcstatus
[i
]);
741 } else if (debug_irq
) {
742 print_irq_status_vc(i
, vcstatus
[i
]);
746 if (ciostatus
& DSI_CIO_IRQ_ERROR_MASK
) {
747 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus
);
748 print_irq_status_cio(ciostatus
);
749 } else if (debug_irq
) {
750 print_irq_status_cio(ciostatus
);
754 static void dsi_call_isrs(struct dsi_isr_data
*isr_array
,
755 unsigned isr_array_size
, u32 irqstatus
)
757 struct dsi_isr_data
*isr_data
;
760 for (i
= 0; i
< isr_array_size
; i
++) {
761 isr_data
= &isr_array
[i
];
762 if (isr_data
->isr
&& isr_data
->mask
& irqstatus
)
763 isr_data
->isr(isr_data
->arg
, irqstatus
);
767 static void dsi_handle_isrs(struct dsi_isr_tables
*isr_tables
,
768 u32 irqstatus
, u32
*vcstatus
, u32 ciostatus
)
772 dsi_call_isrs(isr_tables
->isr_table
,
773 ARRAY_SIZE(isr_tables
->isr_table
),
776 for (i
= 0; i
< 4; ++i
) {
777 if (vcstatus
[i
] == 0)
779 dsi_call_isrs(isr_tables
->isr_table_vc
[i
],
780 ARRAY_SIZE(isr_tables
->isr_table_vc
[i
]),
785 dsi_call_isrs(isr_tables
->isr_table_cio
,
786 ARRAY_SIZE(isr_tables
->isr_table_cio
),
790 static irqreturn_t
omap_dsi_irq_handler(int irq
, void *arg
)
792 struct platform_device
*dsidev
;
793 struct dsi_data
*dsi
;
794 u32 irqstatus
, vcstatus
[4], ciostatus
;
797 dsidev
= (struct platform_device
*) arg
;
798 dsi
= dsi_get_dsidrv_data(dsidev
);
800 if (!dsi
->is_enabled
)
803 spin_lock(&dsi
->irq_lock
);
805 irqstatus
= dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
807 /* IRQ is not for us */
809 spin_unlock(&dsi
->irq_lock
);
813 dsi_write_reg(dsidev
, DSI_IRQSTATUS
, irqstatus
& ~DSI_IRQ_CHANNEL_MASK
);
814 /* flush posted write */
815 dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
817 for (i
= 0; i
< 4; ++i
) {
818 if ((irqstatus
& (1 << i
)) == 0) {
823 vcstatus
[i
] = dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
825 dsi_write_reg(dsidev
, DSI_VC_IRQSTATUS(i
), vcstatus
[i
]);
826 /* flush posted write */
827 dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
830 if (irqstatus
& DSI_IRQ_COMPLEXIO_ERR
) {
831 ciostatus
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
833 dsi_write_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
, ciostatus
);
834 /* flush posted write */
835 dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
840 #ifdef DSI_CATCH_MISSING_TE
841 if (irqstatus
& DSI_IRQ_TE_TRIGGER
)
842 del_timer(&dsi
->te_timer
);
845 /* make a copy and unlock, so that isrs can unregister
847 memcpy(&dsi
->isr_tables_copy
, &dsi
->isr_tables
,
848 sizeof(dsi
->isr_tables
));
850 spin_unlock(&dsi
->irq_lock
);
852 dsi_handle_isrs(&dsi
->isr_tables_copy
, irqstatus
, vcstatus
, ciostatus
);
854 dsi_handle_irq_errors(dsidev
, irqstatus
, vcstatus
, ciostatus
);
856 dsi_collect_irq_stats(dsidev
, irqstatus
, vcstatus
, ciostatus
);
861 /* dsi->irq_lock has to be locked by the caller */
862 static void _omap_dsi_configure_irqs(struct platform_device
*dsidev
,
863 struct dsi_isr_data
*isr_array
,
864 unsigned isr_array_size
, u32 default_mask
,
865 const struct dsi_reg enable_reg
,
866 const struct dsi_reg status_reg
)
868 struct dsi_isr_data
*isr_data
;
875 for (i
= 0; i
< isr_array_size
; i
++) {
876 isr_data
= &isr_array
[i
];
878 if (isr_data
->isr
== NULL
)
881 mask
|= isr_data
->mask
;
884 old_mask
= dsi_read_reg(dsidev
, enable_reg
);
885 /* clear the irqstatus for newly enabled irqs */
886 dsi_write_reg(dsidev
, status_reg
, (mask
^ old_mask
) & mask
);
887 dsi_write_reg(dsidev
, enable_reg
, mask
);
889 /* flush posted writes */
890 dsi_read_reg(dsidev
, enable_reg
);
891 dsi_read_reg(dsidev
, status_reg
);
894 /* dsi->irq_lock has to be locked by the caller */
895 static void _omap_dsi_set_irqs(struct platform_device
*dsidev
)
897 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
898 u32 mask
= DSI_IRQ_ERROR_MASK
;
899 #ifdef DSI_CATCH_MISSING_TE
900 mask
|= DSI_IRQ_TE_TRIGGER
;
902 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table
,
903 ARRAY_SIZE(dsi
->isr_tables
.isr_table
), mask
,
904 DSI_IRQENABLE
, DSI_IRQSTATUS
);
907 /* dsi->irq_lock has to be locked by the caller */
908 static void _omap_dsi_set_irqs_vc(struct platform_device
*dsidev
, int vc
)
910 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
912 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_vc
[vc
],
913 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[vc
]),
914 DSI_VC_IRQ_ERROR_MASK
,
915 DSI_VC_IRQENABLE(vc
), DSI_VC_IRQSTATUS(vc
));
918 /* dsi->irq_lock has to be locked by the caller */
919 static void _omap_dsi_set_irqs_cio(struct platform_device
*dsidev
)
921 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
923 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_cio
,
924 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
),
925 DSI_CIO_IRQ_ERROR_MASK
,
926 DSI_COMPLEXIO_IRQ_ENABLE
, DSI_COMPLEXIO_IRQ_STATUS
);
929 static void _dsi_initialize_irq(struct platform_device
*dsidev
)
931 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
935 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
937 memset(&dsi
->isr_tables
, 0, sizeof(dsi
->isr_tables
));
939 _omap_dsi_set_irqs(dsidev
);
940 for (vc
= 0; vc
< 4; ++vc
)
941 _omap_dsi_set_irqs_vc(dsidev
, vc
);
942 _omap_dsi_set_irqs_cio(dsidev
);
944 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
947 static int _dsi_register_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
948 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
950 struct dsi_isr_data
*isr_data
;
956 /* check for duplicate entry and find a free slot */
958 for (i
= 0; i
< isr_array_size
; i
++) {
959 isr_data
= &isr_array
[i
];
961 if (isr_data
->isr
== isr
&& isr_data
->arg
== arg
&&
962 isr_data
->mask
== mask
) {
966 if (isr_data
->isr
== NULL
&& free_idx
== -1)
973 isr_data
= &isr_array
[free_idx
];
976 isr_data
->mask
= mask
;
981 static int _dsi_unregister_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
982 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
984 struct dsi_isr_data
*isr_data
;
987 for (i
= 0; i
< isr_array_size
; i
++) {
988 isr_data
= &isr_array
[i
];
989 if (isr_data
->isr
!= isr
|| isr_data
->arg
!= arg
||
990 isr_data
->mask
!= mask
)
993 isr_data
->isr
= NULL
;
994 isr_data
->arg
= NULL
;
1003 static int dsi_register_isr(struct platform_device
*dsidev
, omap_dsi_isr_t isr
,
1004 void *arg
, u32 mask
)
1006 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1007 unsigned long flags
;
1010 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1012 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
1013 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
1016 _omap_dsi_set_irqs(dsidev
);
1018 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1023 static int dsi_unregister_isr(struct platform_device
*dsidev
,
1024 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1026 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1027 unsigned long flags
;
1030 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1032 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
1033 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
1036 _omap_dsi_set_irqs(dsidev
);
1038 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1043 static int dsi_register_isr_vc(struct platform_device
*dsidev
, int channel
,
1044 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1046 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1047 unsigned long flags
;
1050 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1052 r
= _dsi_register_isr(isr
, arg
, mask
,
1053 dsi
->isr_tables
.isr_table_vc
[channel
],
1054 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
1057 _omap_dsi_set_irqs_vc(dsidev
, channel
);
1059 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1064 static int dsi_unregister_isr_vc(struct platform_device
*dsidev
, int channel
,
1065 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1067 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1068 unsigned long flags
;
1071 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1073 r
= _dsi_unregister_isr(isr
, arg
, mask
,
1074 dsi
->isr_tables
.isr_table_vc
[channel
],
1075 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
1078 _omap_dsi_set_irqs_vc(dsidev
, channel
);
1080 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1085 static int dsi_register_isr_cio(struct platform_device
*dsidev
,
1086 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1088 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1089 unsigned long flags
;
1092 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1094 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1095 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1098 _omap_dsi_set_irqs_cio(dsidev
);
1100 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1105 static int dsi_unregister_isr_cio(struct platform_device
*dsidev
,
1106 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1108 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1109 unsigned long flags
;
1112 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1114 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1115 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1118 _omap_dsi_set_irqs_cio(dsidev
);
1120 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1125 static u32
dsi_get_errors(struct platform_device
*dsidev
)
1127 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1128 unsigned long flags
;
1130 spin_lock_irqsave(&dsi
->errors_lock
, flags
);
1133 spin_unlock_irqrestore(&dsi
->errors_lock
, flags
);
1137 int dsi_runtime_get(struct platform_device
*dsidev
)
1140 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1142 DSSDBG("dsi_runtime_get\n");
1144 r
= pm_runtime_get_sync(&dsi
->pdev
->dev
);
1146 return r
< 0 ? r
: 0;
1149 void dsi_runtime_put(struct platform_device
*dsidev
)
1151 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1154 DSSDBG("dsi_runtime_put\n");
1156 r
= pm_runtime_put_sync(&dsi
->pdev
->dev
);
1157 WARN_ON(r
< 0 && r
!= -ENOSYS
);
1160 static int dsi_regulator_init(struct platform_device
*dsidev
)
1162 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1163 struct regulator
*vdds_dsi
;
1166 if (dsi
->vdds_dsi_reg
!= NULL
)
1169 vdds_dsi
= devm_regulator_get(&dsi
->pdev
->dev
, "vdd");
1171 if (IS_ERR(vdds_dsi
)) {
1172 if (PTR_ERR(vdds_dsi
) != -EPROBE_DEFER
)
1173 DSSERR("can't get DSI VDD regulator\n");
1174 return PTR_ERR(vdds_dsi
);
1177 if (regulator_can_change_voltage(vdds_dsi
)) {
1178 r
= regulator_set_voltage(vdds_dsi
, 1800000, 1800000);
1180 devm_regulator_put(vdds_dsi
);
1181 DSSERR("can't set the DSI regulator voltage\n");
1186 dsi
->vdds_dsi_reg
= vdds_dsi
;
1191 /* source clock for DSI PLL. this could also be PCLKFREE */
1192 static inline void dsi_enable_pll_clock(struct platform_device
*dsidev
,
1195 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1198 clk_prepare_enable(dsi
->sys_clk
);
1200 clk_disable_unprepare(dsi
->sys_clk
);
1202 if (enable
&& dsi
->pll_locked
) {
1203 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1)
1204 DSSERR("cannot lock PLL when enabling clocks\n");
1208 static void _dsi_print_reset_status(struct platform_device
*dsidev
)
1213 /* A dummy read using the SCP interface to any DSIPHY register is
1214 * required after DSIPHY reset to complete the reset of the DSI complex
1216 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
1218 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
)) {
1228 #define DSI_FLD_GET(fld, start, end)\
1229 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1231 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1232 DSI_FLD_GET(PLL_STATUS
, 0, 0),
1233 DSI_FLD_GET(COMPLEXIO_CFG1
, 29, 29),
1234 DSI_FLD_GET(DSIPHY_CFG5
, b0
, b0
),
1235 DSI_FLD_GET(DSIPHY_CFG5
, b1
, b1
),
1236 DSI_FLD_GET(DSIPHY_CFG5
, b2
, b2
),
1237 DSI_FLD_GET(DSIPHY_CFG5
, 29, 29),
1238 DSI_FLD_GET(DSIPHY_CFG5
, 30, 30),
1239 DSI_FLD_GET(DSIPHY_CFG5
, 31, 31));
1244 static inline int dsi_if_enable(struct platform_device
*dsidev
, bool enable
)
1246 DSSDBG("dsi_if_enable(%d)\n", enable
);
1248 enable
= enable
? 1 : 0;
1249 REG_FLD_MOD(dsidev
, DSI_CTRL
, enable
, 0, 0); /* IF_EN */
1251 if (wait_for_bit_change(dsidev
, DSI_CTRL
, 0, enable
) != enable
) {
1252 DSSERR("Failed to set dsi_if_enable to %d\n", enable
);
1259 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device
*dsidev
)
1261 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1263 return dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
;
1266 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device
*dsidev
)
1268 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1270 return dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
;
1273 static unsigned long dsi_get_txbyteclkhs(struct platform_device
*dsidev
)
1275 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1277 return dsi
->current_cinfo
.clkin4ddr
/ 16;
1280 static unsigned long dsi_fclk_rate(struct platform_device
*dsidev
)
1283 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1285 if (dss_get_dsi_clk_source(dsi
->module_id
) == OMAP_DSS_CLK_SRC_FCK
) {
1286 /* DSI FCLK source is DSS_CLK_FCK */
1287 r
= clk_get_rate(dsi
->dss_clk
);
1289 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1290 r
= dsi_get_pll_hsdiv_dsi_rate(dsidev
);
1296 static int dsi_lp_clock_calc(struct dsi_clock_info
*cinfo
,
1297 unsigned long lp_clk_min
, unsigned long lp_clk_max
)
1299 unsigned long dsi_fclk
= cinfo
->dsi_pll_hsdiv_dsi_clk
;
1300 unsigned lp_clk_div
;
1301 unsigned long lp_clk
;
1303 lp_clk_div
= DIV_ROUND_UP(dsi_fclk
, lp_clk_max
* 2);
1304 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
1306 if (lp_clk
< lp_clk_min
|| lp_clk
> lp_clk_max
)
1309 cinfo
->lp_clk_div
= lp_clk_div
;
1310 cinfo
->lp_clk
= lp_clk
;
1315 static int dsi_set_lp_clk_divisor(struct platform_device
*dsidev
)
1317 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1318 unsigned long dsi_fclk
;
1319 unsigned lp_clk_div
;
1320 unsigned long lp_clk
;
1322 lp_clk_div
= dsi
->user_dsi_cinfo
.lp_clk_div
;
1324 if (lp_clk_div
== 0 || lp_clk_div
> dsi
->lpdiv_max
)
1327 dsi_fclk
= dsi_fclk_rate(dsidev
);
1329 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
1331 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div
, lp_clk
);
1332 dsi
->current_cinfo
.lp_clk
= lp_clk
;
1333 dsi
->current_cinfo
.lp_clk_div
= lp_clk_div
;
1335 /* LP_CLK_DIVISOR */
1336 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, lp_clk_div
, 12, 0);
1338 /* LP_RX_SYNCHRO_ENABLE */
1339 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, dsi_fclk
> 30000000 ? 1 : 0, 21, 21);
1344 static void dsi_enable_scp_clk(struct platform_device
*dsidev
)
1346 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1348 if (dsi
->scp_clk_refcount
++ == 0)
1349 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 14, 14); /* CIO_CLK_ICG */
1352 static void dsi_disable_scp_clk(struct platform_device
*dsidev
)
1354 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1356 WARN_ON(dsi
->scp_clk_refcount
== 0);
1357 if (--dsi
->scp_clk_refcount
== 0)
1358 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 14, 14); /* CIO_CLK_ICG */
1361 enum dsi_pll_power_state
{
1362 DSI_PLL_POWER_OFF
= 0x0,
1363 DSI_PLL_POWER_ON_HSCLK
= 0x1,
1364 DSI_PLL_POWER_ON_ALL
= 0x2,
1365 DSI_PLL_POWER_ON_DIV
= 0x3,
1368 static int dsi_pll_power(struct platform_device
*dsidev
,
1369 enum dsi_pll_power_state state
)
1373 /* DSI-PLL power command 0x3 is not working */
1374 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG
) &&
1375 state
== DSI_PLL_POWER_ON_DIV
)
1376 state
= DSI_PLL_POWER_ON_ALL
;
1379 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, state
, 31, 30);
1381 /* PLL_PWR_STATUS */
1382 while (FLD_GET(dsi_read_reg(dsidev
, DSI_CLK_CTRL
), 29, 28) != state
) {
1384 DSSERR("Failed to set DSI PLL power mode to %d\n",
1394 unsigned long dsi_get_pll_clkin(struct platform_device
*dsidev
)
1396 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1397 return clk_get_rate(dsi
->sys_clk
);
1400 bool dsi_hsdiv_calc(struct platform_device
*dsidev
, unsigned long pll
,
1401 unsigned long out_min
, dsi_hsdiv_calc_func func
, void *data
)
1403 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1404 int regm
, regm_start
, regm_stop
;
1405 unsigned long out_max
;
1408 out_min
= out_min
? out_min
: 1;
1409 out_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
1411 regm_start
= max(DIV_ROUND_UP(pll
, out_max
), 1ul);
1412 regm_stop
= min(pll
/ out_min
, dsi
->regm_dispc_max
);
1414 for (regm
= regm_start
; regm
<= regm_stop
; ++regm
) {
1417 if (func(regm
, out
, data
))
1424 bool dsi_pll_calc(struct platform_device
*dsidev
, unsigned long clkin
,
1425 unsigned long pll_min
, unsigned long pll_max
,
1426 dsi_pll_calc_func func
, void *data
)
1428 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1429 int regn
, regn_start
, regn_stop
;
1430 int regm
, regm_start
, regm_stop
;
1431 unsigned long fint
, pll
;
1432 const unsigned long pll_hw_max
= 1800000000;
1433 unsigned long fint_hw_min
, fint_hw_max
;
1435 fint_hw_min
= dsi
->fint_min
;
1436 fint_hw_max
= dsi
->fint_max
;
1438 regn_start
= max(DIV_ROUND_UP(clkin
, fint_hw_max
), 1ul);
1439 regn_stop
= min(clkin
/ fint_hw_min
, dsi
->regn_max
);
1441 pll_max
= pll_max
? pll_max
: ULONG_MAX
;
1443 for (regn
= regn_start
; regn
<= regn_stop
; ++regn
) {
1444 fint
= clkin
/ regn
;
1446 regm_start
= max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min
, fint
), 2),
1448 regm_stop
= min3(pll_max
/ fint
/ 2,
1449 pll_hw_max
/ fint
/ 2,
1452 for (regm
= regm_start
; regm
<= regm_stop
; ++regm
) {
1453 pll
= 2 * regm
* fint
;
1455 if (func(regn
, regm
, fint
, pll
, data
))
1463 /* calculate clock rates using dividers in cinfo */
1464 static int dsi_calc_clock_rates(struct platform_device
*dsidev
,
1465 struct dsi_clock_info
*cinfo
)
1467 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1469 if (cinfo
->regn
== 0 || cinfo
->regn
> dsi
->regn_max
)
1472 if (cinfo
->regm
== 0 || cinfo
->regm
> dsi
->regm_max
)
1475 if (cinfo
->regm_dispc
> dsi
->regm_dispc_max
)
1478 if (cinfo
->regm_dsi
> dsi
->regm_dsi_max
)
1481 cinfo
->clkin
= clk_get_rate(dsi
->sys_clk
);
1482 cinfo
->fint
= cinfo
->clkin
/ cinfo
->regn
;
1484 if (cinfo
->fint
> dsi
->fint_max
|| cinfo
->fint
< dsi
->fint_min
)
1487 cinfo
->clkin4ddr
= 2 * cinfo
->regm
* cinfo
->fint
;
1489 if (cinfo
->clkin4ddr
> 1800 * 1000 * 1000)
1492 if (cinfo
->regm_dispc
> 0)
1493 cinfo
->dsi_pll_hsdiv_dispc_clk
=
1494 cinfo
->clkin4ddr
/ cinfo
->regm_dispc
;
1496 cinfo
->dsi_pll_hsdiv_dispc_clk
= 0;
1498 if (cinfo
->regm_dsi
> 0)
1499 cinfo
->dsi_pll_hsdiv_dsi_clk
=
1500 cinfo
->clkin4ddr
/ cinfo
->regm_dsi
;
1502 cinfo
->dsi_pll_hsdiv_dsi_clk
= 0;
1507 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info
*cinfo
)
1509 unsigned long max_dsi_fck
;
1511 max_dsi_fck
= dss_feat_get_param_max(FEAT_PARAM_DSI_FCK
);
1513 cinfo
->regm_dsi
= DIV_ROUND_UP(cinfo
->clkin4ddr
, max_dsi_fck
);
1514 cinfo
->dsi_pll_hsdiv_dsi_clk
= cinfo
->clkin4ddr
/ cinfo
->regm_dsi
;
1517 int dsi_pll_set_clock_div(struct platform_device
*dsidev
,
1518 struct dsi_clock_info
*cinfo
)
1520 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1524 u8 regn_start
, regn_end
, regm_start
, regm_end
;
1525 u8 regm_dispc_start
, regm_dispc_end
, regm_dsi_start
, regm_dsi_end
;
1527 DSSDBG("DSI PLL clock config starts");
1529 dsi
->current_cinfo
.clkin
= cinfo
->clkin
;
1530 dsi
->current_cinfo
.fint
= cinfo
->fint
;
1531 dsi
->current_cinfo
.clkin4ddr
= cinfo
->clkin4ddr
;
1532 dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
=
1533 cinfo
->dsi_pll_hsdiv_dispc_clk
;
1534 dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
=
1535 cinfo
->dsi_pll_hsdiv_dsi_clk
;
1537 dsi
->current_cinfo
.regn
= cinfo
->regn
;
1538 dsi
->current_cinfo
.regm
= cinfo
->regm
;
1539 dsi
->current_cinfo
.regm_dispc
= cinfo
->regm_dispc
;
1540 dsi
->current_cinfo
.regm_dsi
= cinfo
->regm_dsi
;
1542 DSSDBG("DSI Fint %ld\n", cinfo
->fint
);
1544 DSSDBG("clkin rate %ld\n", cinfo
->clkin
);
1546 /* DSIPHY == CLKIN4DDR */
1547 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1553 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1554 cinfo
->clkin4ddr
/ 1000 / 1000 / 2);
1556 DSSDBG("Clock lane freq %ld Hz\n", cinfo
->clkin4ddr
/ 4);
1558 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo
->regm_dispc
,
1559 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1560 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1561 cinfo
->dsi_pll_hsdiv_dispc_clk
);
1562 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo
->regm_dsi
,
1563 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1564 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1565 cinfo
->dsi_pll_hsdiv_dsi_clk
);
1567 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN
, ®n_start
, ®n_end
);
1568 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM
, ®m_start
, ®m_end
);
1569 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC
, ®m_dispc_start
,
1571 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI
, ®m_dsi_start
,
1574 /* DSI_PLL_AUTOMODE = manual */
1575 REG_FLD_MOD(dsidev
, DSI_PLL_CONTROL
, 0, 0, 0);
1577 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION1
);
1578 l
= FLD_MOD(l
, 1, 0, 0); /* DSI_PLL_STOPMODE */
1580 l
= FLD_MOD(l
, cinfo
->regn
- 1, regn_start
, regn_end
);
1582 l
= FLD_MOD(l
, cinfo
->regm
, regm_start
, regm_end
);
1584 l
= FLD_MOD(l
, cinfo
->regm_dispc
> 0 ? cinfo
->regm_dispc
- 1 : 0,
1585 regm_dispc_start
, regm_dispc_end
);
1586 /* DSIPROTO_CLOCK_DIV */
1587 l
= FLD_MOD(l
, cinfo
->regm_dsi
> 0 ? cinfo
->regm_dsi
- 1 : 0,
1588 regm_dsi_start
, regm_dsi_end
);
1589 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION1
, l
);
1591 BUG_ON(cinfo
->fint
< dsi
->fint_min
|| cinfo
->fint
> dsi
->fint_max
);
1593 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1595 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL
)) {
1596 f
= cinfo
->fint
< 1000000 ? 0x3 :
1597 cinfo
->fint
< 1250000 ? 0x4 :
1598 cinfo
->fint
< 1500000 ? 0x5 :
1599 cinfo
->fint
< 1750000 ? 0x6 :
1602 l
= FLD_MOD(l
, f
, 4, 1); /* DSI_PLL_FREQSEL */
1603 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO
)) {
1604 f
= cinfo
->clkin4ddr
< 1000000000 ? 0x2 : 0x4;
1606 l
= FLD_MOD(l
, f
, 3, 1); /* PLL_SELFREQDCO */
1609 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1610 l
= FLD_MOD(l
, 0, 14, 14); /* DSIPHY_CLKINEN */
1611 l
= FLD_MOD(l
, 1, 20, 20); /* DSI_HSDIVBYPASS */
1612 if (dss_has_feature(FEAT_DSI_PLL_REFSEL
))
1613 l
= FLD_MOD(l
, 3, 22, 21); /* REF_SYSCLK = sysclk */
1614 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1616 REG_FLD_MOD(dsidev
, DSI_PLL_GO
, 1, 0, 0); /* DSI_PLL_GO */
1618 if (wait_for_bit_change(dsidev
, DSI_PLL_GO
, 0, 0) != 0) {
1619 DSSERR("dsi pll go bit not going down.\n");
1624 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1) {
1625 DSSERR("cannot lock PLL\n");
1630 dsi
->pll_locked
= 1;
1632 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1633 l
= FLD_MOD(l
, 0, 0, 0); /* DSI_PLL_IDLE */
1634 l
= FLD_MOD(l
, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1635 l
= FLD_MOD(l
, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1636 l
= FLD_MOD(l
, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1637 l
= FLD_MOD(l
, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1638 l
= FLD_MOD(l
, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1639 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1640 l
= FLD_MOD(l
, 1, 14, 14); /* DSIPHY_CLKINEN */
1641 l
= FLD_MOD(l
, 0, 15, 15); /* DSI_BYPASSEN */
1642 l
= FLD_MOD(l
, 1, 16, 16); /* DSS_CLOCK_EN */
1643 l
= FLD_MOD(l
, 0, 17, 17); /* DSS_CLOCK_PWDN */
1644 l
= FLD_MOD(l
, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1645 l
= FLD_MOD(l
, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1646 l
= FLD_MOD(l
, 0, 20, 20); /* DSI_HSDIVBYPASS */
1647 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1649 DSSDBG("PLL config done\n");
1654 int dsi_pll_init(struct platform_device
*dsidev
, bool enable_hsclk
,
1657 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1659 enum dsi_pll_power_state pwstate
;
1661 DSSDBG("PLL init\n");
1664 * It seems that on many OMAPs we need to enable both to have a
1665 * functional HSDivider.
1667 enable_hsclk
= enable_hsdiv
= true;
1669 r
= dsi_regulator_init(dsidev
);
1673 dsi_enable_pll_clock(dsidev
, 1);
1675 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1677 dsi_enable_scp_clk(dsidev
);
1679 if (!dsi
->vdds_dsi_enabled
) {
1680 r
= regulator_enable(dsi
->vdds_dsi_reg
);
1683 dsi
->vdds_dsi_enabled
= true;
1686 /* XXX PLL does not come out of reset without this... */
1687 dispc_pck_free_enable(1);
1689 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 0, 1) != 1) {
1690 DSSERR("PLL not coming out of reset.\n");
1692 dispc_pck_free_enable(0);
1696 /* XXX ... but if left on, we get problems when planes do not
1697 * fill the whole display. No idea about this */
1698 dispc_pck_free_enable(0);
1700 if (enable_hsclk
&& enable_hsdiv
)
1701 pwstate
= DSI_PLL_POWER_ON_ALL
;
1702 else if (enable_hsclk
)
1703 pwstate
= DSI_PLL_POWER_ON_HSCLK
;
1704 else if (enable_hsdiv
)
1705 pwstate
= DSI_PLL_POWER_ON_DIV
;
1707 pwstate
= DSI_PLL_POWER_OFF
;
1709 r
= dsi_pll_power(dsidev
, pwstate
);
1714 DSSDBG("PLL init done\n");
1718 if (dsi
->vdds_dsi_enabled
) {
1719 regulator_disable(dsi
->vdds_dsi_reg
);
1720 dsi
->vdds_dsi_enabled
= false;
1723 dsi_disable_scp_clk(dsidev
);
1724 dsi_enable_pll_clock(dsidev
, 0);
1728 void dsi_pll_uninit(struct platform_device
*dsidev
, bool disconnect_lanes
)
1730 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1732 dsi
->pll_locked
= 0;
1733 dsi_pll_power(dsidev
, DSI_PLL_POWER_OFF
);
1734 if (disconnect_lanes
) {
1735 WARN_ON(!dsi
->vdds_dsi_enabled
);
1736 regulator_disable(dsi
->vdds_dsi_reg
);
1737 dsi
->vdds_dsi_enabled
= false;
1740 dsi_disable_scp_clk(dsidev
);
1741 dsi_enable_pll_clock(dsidev
, 0);
1743 DSSDBG("PLL uninit done\n");
1746 static void dsi_dump_dsidev_clocks(struct platform_device
*dsidev
,
1749 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1750 struct dsi_clock_info
*cinfo
= &dsi
->current_cinfo
;
1751 enum omap_dss_clk_source dispc_clk_src
, dsi_clk_src
;
1752 int dsi_module
= dsi
->module_id
;
1754 dispc_clk_src
= dss_get_dispc_clk_source();
1755 dsi_clk_src
= dss_get_dsi_clk_source(dsi_module
);
1757 if (dsi_runtime_get(dsidev
))
1760 seq_printf(s
, "- DSI%d PLL -\n", dsi_module
+ 1);
1762 seq_printf(s
, "dsi pll clkin\t%lu\n", cinfo
->clkin
);
1764 seq_printf(s
, "Fint\t\t%-16luregn %u\n", cinfo
->fint
, cinfo
->regn
);
1766 seq_printf(s
, "CLKIN4DDR\t%-16luregm %u\n",
1767 cinfo
->clkin4ddr
, cinfo
->regm
);
1769 seq_printf(s
, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1770 dss_feat_get_clk_source_name(dsi_module
== 0 ?
1771 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
1772 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
),
1773 cinfo
->dsi_pll_hsdiv_dispc_clk
,
1775 dispc_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1778 seq_printf(s
, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1779 dss_feat_get_clk_source_name(dsi_module
== 0 ?
1780 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
:
1781 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
),
1782 cinfo
->dsi_pll_hsdiv_dsi_clk
,
1784 dsi_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1787 seq_printf(s
, "- DSI%d -\n", dsi_module
+ 1);
1789 seq_printf(s
, "dsi fclk source = %s (%s)\n",
1790 dss_get_generic_clk_source_name(dsi_clk_src
),
1791 dss_feat_get_clk_source_name(dsi_clk_src
));
1793 seq_printf(s
, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev
));
1795 seq_printf(s
, "DDR_CLK\t\t%lu\n",
1796 cinfo
->clkin4ddr
/ 4);
1798 seq_printf(s
, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev
));
1800 seq_printf(s
, "LP_CLK\t\t%lu\n", cinfo
->lp_clk
);
1802 dsi_runtime_put(dsidev
);
1805 void dsi_dump_clocks(struct seq_file
*s
)
1807 struct platform_device
*dsidev
;
1810 for (i
= 0; i
< MAX_NUM_DSI
; i
++) {
1811 dsidev
= dsi_get_dsidev_from_id(i
);
1813 dsi_dump_dsidev_clocks(dsidev
, s
);
1817 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1818 static void dsi_dump_dsidev_irqs(struct platform_device
*dsidev
,
1821 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1822 unsigned long flags
;
1823 struct dsi_irq_stats stats
;
1825 spin_lock_irqsave(&dsi
->irq_stats_lock
, flags
);
1827 stats
= dsi
->irq_stats
;
1828 memset(&dsi
->irq_stats
, 0, sizeof(dsi
->irq_stats
));
1829 dsi
->irq_stats
.last_reset
= jiffies
;
1831 spin_unlock_irqrestore(&dsi
->irq_stats_lock
, flags
);
1833 seq_printf(s
, "period %u ms\n",
1834 jiffies_to_msecs(jiffies
- stats
.last_reset
));
1836 seq_printf(s
, "irqs %d\n", stats
.irq_count
);
1838 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1840 seq_printf(s
, "-- DSI%d interrupts --\n", dsi
->module_id
+ 1);
1856 PIS(LDO_POWER_GOOD
);
1861 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1862 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1863 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1864 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1865 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1867 seq_printf(s
, "-- VC interrupts --\n");
1876 PIS(PP_BUSY_CHANGE
);
1880 seq_printf(s, "%-20s %10d\n", #x, \
1881 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1883 seq_printf(s
, "-- CIO interrupts --\n");
1896 PIS(ERRCONTENTIONLP0_1
);
1897 PIS(ERRCONTENTIONLP1_1
);
1898 PIS(ERRCONTENTIONLP0_2
);
1899 PIS(ERRCONTENTIONLP1_2
);
1900 PIS(ERRCONTENTIONLP0_3
);
1901 PIS(ERRCONTENTIONLP1_3
);
1902 PIS(ULPSACTIVENOT_ALL0
);
1903 PIS(ULPSACTIVENOT_ALL1
);
1907 static void dsi1_dump_irqs(struct seq_file
*s
)
1909 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1911 dsi_dump_dsidev_irqs(dsidev
, s
);
1914 static void dsi2_dump_irqs(struct seq_file
*s
)
1916 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
1918 dsi_dump_dsidev_irqs(dsidev
, s
);
1922 static void dsi_dump_dsidev_regs(struct platform_device
*dsidev
,
1925 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1927 if (dsi_runtime_get(dsidev
))
1929 dsi_enable_scp_clk(dsidev
);
1931 DUMPREG(DSI_REVISION
);
1932 DUMPREG(DSI_SYSCONFIG
);
1933 DUMPREG(DSI_SYSSTATUS
);
1934 DUMPREG(DSI_IRQSTATUS
);
1935 DUMPREG(DSI_IRQENABLE
);
1937 DUMPREG(DSI_COMPLEXIO_CFG1
);
1938 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS
);
1939 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE
);
1940 DUMPREG(DSI_CLK_CTRL
);
1941 DUMPREG(DSI_TIMING1
);
1942 DUMPREG(DSI_TIMING2
);
1943 DUMPREG(DSI_VM_TIMING1
);
1944 DUMPREG(DSI_VM_TIMING2
);
1945 DUMPREG(DSI_VM_TIMING3
);
1946 DUMPREG(DSI_CLK_TIMING
);
1947 DUMPREG(DSI_TX_FIFO_VC_SIZE
);
1948 DUMPREG(DSI_RX_FIFO_VC_SIZE
);
1949 DUMPREG(DSI_COMPLEXIO_CFG2
);
1950 DUMPREG(DSI_RX_FIFO_VC_FULLNESS
);
1951 DUMPREG(DSI_VM_TIMING4
);
1952 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS
);
1953 DUMPREG(DSI_VM_TIMING5
);
1954 DUMPREG(DSI_VM_TIMING6
);
1955 DUMPREG(DSI_VM_TIMING7
);
1956 DUMPREG(DSI_STOPCLK_TIMING
);
1958 DUMPREG(DSI_VC_CTRL(0));
1959 DUMPREG(DSI_VC_TE(0));
1960 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1961 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1962 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1963 DUMPREG(DSI_VC_IRQSTATUS(0));
1964 DUMPREG(DSI_VC_IRQENABLE(0));
1966 DUMPREG(DSI_VC_CTRL(1));
1967 DUMPREG(DSI_VC_TE(1));
1968 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1969 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1970 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1971 DUMPREG(DSI_VC_IRQSTATUS(1));
1972 DUMPREG(DSI_VC_IRQENABLE(1));
1974 DUMPREG(DSI_VC_CTRL(2));
1975 DUMPREG(DSI_VC_TE(2));
1976 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1977 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1978 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1979 DUMPREG(DSI_VC_IRQSTATUS(2));
1980 DUMPREG(DSI_VC_IRQENABLE(2));
1982 DUMPREG(DSI_VC_CTRL(3));
1983 DUMPREG(DSI_VC_TE(3));
1984 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1985 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1986 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1987 DUMPREG(DSI_VC_IRQSTATUS(3));
1988 DUMPREG(DSI_VC_IRQENABLE(3));
1990 DUMPREG(DSI_DSIPHY_CFG0
);
1991 DUMPREG(DSI_DSIPHY_CFG1
);
1992 DUMPREG(DSI_DSIPHY_CFG2
);
1993 DUMPREG(DSI_DSIPHY_CFG5
);
1995 DUMPREG(DSI_PLL_CONTROL
);
1996 DUMPREG(DSI_PLL_STATUS
);
1997 DUMPREG(DSI_PLL_GO
);
1998 DUMPREG(DSI_PLL_CONFIGURATION1
);
1999 DUMPREG(DSI_PLL_CONFIGURATION2
);
2001 dsi_disable_scp_clk(dsidev
);
2002 dsi_runtime_put(dsidev
);
2006 static void dsi1_dump_regs(struct seq_file
*s
)
2008 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
2010 dsi_dump_dsidev_regs(dsidev
, s
);
2013 static void dsi2_dump_regs(struct seq_file
*s
)
2015 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
2017 dsi_dump_dsidev_regs(dsidev
, s
);
2020 enum dsi_cio_power_state
{
2021 DSI_COMPLEXIO_POWER_OFF
= 0x0,
2022 DSI_COMPLEXIO_POWER_ON
= 0x1,
2023 DSI_COMPLEXIO_POWER_ULPS
= 0x2,
2026 static int dsi_cio_power(struct platform_device
*dsidev
,
2027 enum dsi_cio_power_state state
)
2032 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG1
, state
, 28, 27);
2035 while (FLD_GET(dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
),
2038 DSSERR("failed to set complexio power state to "
2048 static unsigned dsi_get_line_buf_size(struct platform_device
*dsidev
)
2052 /* line buffer on OMAP3 is 1024 x 24bits */
2053 /* XXX: for some reason using full buffer size causes
2054 * considerable TX slowdown with update sizes that fill the
2056 if (!dss_has_feature(FEAT_DSI_GNQ
))
2059 val
= REG_GET(dsidev
, DSI_GNQ
, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2063 return 512 * 3; /* 512x24 bits */
2065 return 682 * 3; /* 682x24 bits */
2067 return 853 * 3; /* 853x24 bits */
2069 return 1024 * 3; /* 1024x24 bits */
2071 return 1194 * 3; /* 1194x24 bits */
2073 return 1365 * 3; /* 1365x24 bits */
2075 return 1920 * 3; /* 1920x24 bits */
2082 static int dsi_set_lane_config(struct platform_device
*dsidev
)
2084 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2085 static const u8 offsets
[] = { 0, 4, 8, 12, 16 };
2086 static const enum dsi_lane_function functions
[] = {
2096 r
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
);
2098 for (i
= 0; i
< dsi
->num_lanes_used
; ++i
) {
2099 unsigned offset
= offsets
[i
];
2100 unsigned polarity
, lane_number
;
2103 for (t
= 0; t
< dsi
->num_lanes_supported
; ++t
)
2104 if (dsi
->lanes
[t
].function
== functions
[i
])
2107 if (t
== dsi
->num_lanes_supported
)
2111 polarity
= dsi
->lanes
[t
].polarity
;
2113 r
= FLD_MOD(r
, lane_number
+ 1, offset
+ 2, offset
);
2114 r
= FLD_MOD(r
, polarity
, offset
+ 3, offset
+ 3);
2117 /* clear the unused lanes */
2118 for (; i
< dsi
->num_lanes_supported
; ++i
) {
2119 unsigned offset
= offsets
[i
];
2121 r
= FLD_MOD(r
, 0, offset
+ 2, offset
);
2122 r
= FLD_MOD(r
, 0, offset
+ 3, offset
+ 3);
2125 dsi_write_reg(dsidev
, DSI_COMPLEXIO_CFG1
, r
);
2130 static inline unsigned ns2ddr(struct platform_device
*dsidev
, unsigned ns
)
2132 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2134 /* convert time in ns to ddr ticks, rounding up */
2135 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2136 return (ns
* (ddr_clk
/ 1000 / 1000) + 999) / 1000;
2139 static inline unsigned ddr2ns(struct platform_device
*dsidev
, unsigned ddr
)
2141 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2143 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2144 return ddr
* 1000 * 1000 / (ddr_clk
/ 1000);
2147 static void dsi_cio_timings(struct platform_device
*dsidev
)
2150 u32 ths_prepare
, ths_prepare_ths_zero
, ths_trail
, ths_exit
;
2151 u32 tlpx_half
, tclk_trail
, tclk_zero
;
2154 /* calculate timings */
2156 /* 1 * DDR_CLK = 2 * UI */
2158 /* min 40ns + 4*UI max 85ns + 6*UI */
2159 ths_prepare
= ns2ddr(dsidev
, 70) + 2;
2161 /* min 145ns + 10*UI */
2162 ths_prepare_ths_zero
= ns2ddr(dsidev
, 175) + 2;
2164 /* min max(8*UI, 60ns+4*UI) */
2165 ths_trail
= ns2ddr(dsidev
, 60) + 5;
2168 ths_exit
= ns2ddr(dsidev
, 145);
2171 tlpx_half
= ns2ddr(dsidev
, 25);
2174 tclk_trail
= ns2ddr(dsidev
, 60) + 2;
2176 /* min 38ns, max 95ns */
2177 tclk_prepare
= ns2ddr(dsidev
, 65);
2179 /* min tclk-prepare + tclk-zero = 300ns */
2180 tclk_zero
= ns2ddr(dsidev
, 260);
2182 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2183 ths_prepare
, ddr2ns(dsidev
, ths_prepare
),
2184 ths_prepare_ths_zero
, ddr2ns(dsidev
, ths_prepare_ths_zero
));
2185 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2186 ths_trail
, ddr2ns(dsidev
, ths_trail
),
2187 ths_exit
, ddr2ns(dsidev
, ths_exit
));
2189 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2190 "tclk_zero %u (%uns)\n",
2191 tlpx_half
, ddr2ns(dsidev
, tlpx_half
),
2192 tclk_trail
, ddr2ns(dsidev
, tclk_trail
),
2193 tclk_zero
, ddr2ns(dsidev
, tclk_zero
));
2194 DSSDBG("tclk_prepare %u (%uns)\n",
2195 tclk_prepare
, ddr2ns(dsidev
, tclk_prepare
));
2197 /* program timings */
2199 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
2200 r
= FLD_MOD(r
, ths_prepare
, 31, 24);
2201 r
= FLD_MOD(r
, ths_prepare_ths_zero
, 23, 16);
2202 r
= FLD_MOD(r
, ths_trail
, 15, 8);
2203 r
= FLD_MOD(r
, ths_exit
, 7, 0);
2204 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG0
, r
);
2206 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
2207 r
= FLD_MOD(r
, tlpx_half
, 20, 16);
2208 r
= FLD_MOD(r
, tclk_trail
, 15, 8);
2209 r
= FLD_MOD(r
, tclk_zero
, 7, 0);
2211 if (dss_has_feature(FEAT_DSI_PHY_DCC
)) {
2212 r
= FLD_MOD(r
, 0, 21, 21); /* DCCEN = disable */
2213 r
= FLD_MOD(r
, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2214 r
= FLD_MOD(r
, 1, 23, 23); /* CLKINP_SEL = enable */
2217 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG1
, r
);
2219 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
2220 r
= FLD_MOD(r
, tclk_prepare
, 7, 0);
2221 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG2
, r
);
2224 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2225 static void dsi_cio_enable_lane_override(struct platform_device
*dsidev
,
2226 unsigned mask_p
, unsigned mask_n
)
2228 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2231 u8 lptxscp_start
= dsi
->num_lanes_supported
== 3 ? 22 : 26;
2235 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2236 unsigned p
= dsi
->lanes
[i
].polarity
;
2238 if (mask_p
& (1 << i
))
2239 l
|= 1 << (i
* 2 + (p
? 0 : 1));
2241 if (mask_n
& (1 << i
))
2242 l
|= 1 << (i
* 2 + (p
? 1 : 0));
2246 * Bits in REGLPTXSCPDAT4TO0DXDY:
2254 /* Set the lane override configuration */
2256 /* REGLPTXSCPDAT4TO0DXDY */
2257 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, l
, lptxscp_start
, 17);
2259 /* Enable lane override */
2262 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 1, 27, 27);
2265 static void dsi_cio_disable_lane_override(struct platform_device
*dsidev
)
2267 /* Disable lane override */
2268 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 27, 27); /* ENLPTXSCPDAT */
2269 /* Reset the lane override configuration */
2270 /* REGLPTXSCPDAT4TO0DXDY */
2271 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 22, 17);
2274 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device
*dsidev
)
2276 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2278 bool in_use
[DSI_MAX_NR_LANES
];
2279 static const u8 offsets_old
[] = { 28, 27, 26 };
2280 static const u8 offsets_new
[] = { 24, 25, 26, 27, 28 };
2283 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
))
2284 offsets
= offsets_old
;
2286 offsets
= offsets_new
;
2288 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
)
2289 in_use
[i
] = dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
;
2296 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2299 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2300 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2304 if (ok
== dsi
->num_lanes_supported
)
2308 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2309 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2312 DSSERR("CIO TXCLKESC%d domain not coming " \
2313 "out of reset\n", i
);
2322 /* return bitmask of enabled lanes, lane0 being the lsb */
2323 static unsigned dsi_get_lane_mask(struct platform_device
*dsidev
)
2325 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2329 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2330 if (dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
)
2337 static int dsi_cio_init(struct platform_device
*dsidev
)
2339 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2343 DSSDBG("DSI CIO init starts");
2345 r
= dss_dsi_enable_pads(dsi
->module_id
, dsi_get_lane_mask(dsidev
));
2349 dsi_enable_scp_clk(dsidev
);
2351 /* A dummy read using the SCP interface to any DSIPHY register is
2352 * required after DSIPHY reset to complete the reset of the DSI complex
2354 dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2356 if (wait_for_bit_change(dsidev
, DSI_DSIPHY_CFG5
, 30, 1) != 1) {
2357 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2359 goto err_scp_clk_dom
;
2362 r
= dsi_set_lane_config(dsidev
);
2364 goto err_scp_clk_dom
;
2366 /* set TX STOP MODE timer to maximum for this operation */
2367 l
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2368 l
= FLD_MOD(l
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2369 l
= FLD_MOD(l
, 1, 14, 14); /* STOP_STATE_X16_IO */
2370 l
= FLD_MOD(l
, 1, 13, 13); /* STOP_STATE_X4_IO */
2371 l
= FLD_MOD(l
, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2372 dsi_write_reg(dsidev
, DSI_TIMING1
, l
);
2374 if (dsi
->ulps_enabled
) {
2378 DSSDBG("manual ulps exit\n");
2380 /* ULPS is exited by Mark-1 state for 1ms, followed by
2381 * stop state. DSS HW cannot do this via the normal
2382 * ULPS exit sequence, as after reset the DSS HW thinks
2383 * that we are not in ULPS mode, and refuses to send the
2384 * sequence. So we need to send the ULPS exit sequence
2385 * manually by setting positive lines high and negative lines
2391 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2392 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
2397 dsi_cio_enable_lane_override(dsidev
, mask_p
, 0);
2400 r
= dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ON
);
2404 if (wait_for_bit_change(dsidev
, DSI_COMPLEXIO_CFG1
, 29, 1) != 1) {
2405 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2407 goto err_cio_pwr_dom
;
2410 dsi_if_enable(dsidev
, true);
2411 dsi_if_enable(dsidev
, false);
2412 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 20, 20); /* LP_CLK_ENABLE */
2414 r
= dsi_cio_wait_tx_clk_esc_reset(dsidev
);
2416 goto err_tx_clk_esc_rst
;
2418 if (dsi
->ulps_enabled
) {
2419 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2420 ktime_t wait
= ns_to_ktime(1000 * 1000);
2421 set_current_state(TASK_UNINTERRUPTIBLE
);
2422 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
2424 /* Disable the override. The lanes should be set to Mark-11
2425 * state by the HW */
2426 dsi_cio_disable_lane_override(dsidev
);
2429 /* FORCE_TX_STOP_MODE_IO */
2430 REG_FLD_MOD(dsidev
, DSI_TIMING1
, 0, 15, 15);
2432 dsi_cio_timings(dsidev
);
2434 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
2435 /* DDR_CLK_ALWAYS_ON */
2436 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
,
2437 dsi
->vm_timings
.ddr_clk_always_on
, 13, 13);
2440 dsi
->ulps_enabled
= false;
2442 DSSDBG("CIO init done\n");
2447 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 20, 20); /* LP_CLK_ENABLE */
2449 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2451 if (dsi
->ulps_enabled
)
2452 dsi_cio_disable_lane_override(dsidev
);
2454 dsi_disable_scp_clk(dsidev
);
2455 dss_dsi_disable_pads(dsi
->module_id
, dsi_get_lane_mask(dsidev
));
2459 static void dsi_cio_uninit(struct platform_device
*dsidev
)
2461 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2463 /* DDR_CLK_ALWAYS_ON */
2464 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
2466 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2467 dsi_disable_scp_clk(dsidev
);
2468 dss_dsi_disable_pads(dsi
->module_id
, dsi_get_lane_mask(dsidev
));
2471 static void dsi_config_tx_fifo(struct platform_device
*dsidev
,
2472 enum fifo_size size1
, enum fifo_size size2
,
2473 enum fifo_size size3
, enum fifo_size size4
)
2475 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2480 dsi
->vc
[0].tx_fifo_size
= size1
;
2481 dsi
->vc
[1].tx_fifo_size
= size2
;
2482 dsi
->vc
[2].tx_fifo_size
= size3
;
2483 dsi
->vc
[3].tx_fifo_size
= size4
;
2485 for (i
= 0; i
< 4; i
++) {
2487 int size
= dsi
->vc
[i
].tx_fifo_size
;
2489 if (add
+ size
> 4) {
2490 DSSERR("Illegal FIFO configuration\n");
2495 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2497 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2501 dsi_write_reg(dsidev
, DSI_TX_FIFO_VC_SIZE
, r
);
2504 static void dsi_config_rx_fifo(struct platform_device
*dsidev
,
2505 enum fifo_size size1
, enum fifo_size size2
,
2506 enum fifo_size size3
, enum fifo_size size4
)
2508 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2513 dsi
->vc
[0].rx_fifo_size
= size1
;
2514 dsi
->vc
[1].rx_fifo_size
= size2
;
2515 dsi
->vc
[2].rx_fifo_size
= size3
;
2516 dsi
->vc
[3].rx_fifo_size
= size4
;
2518 for (i
= 0; i
< 4; i
++) {
2520 int size
= dsi
->vc
[i
].rx_fifo_size
;
2522 if (add
+ size
> 4) {
2523 DSSERR("Illegal FIFO configuration\n");
2528 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2530 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2534 dsi_write_reg(dsidev
, DSI_RX_FIFO_VC_SIZE
, r
);
2537 static int dsi_force_tx_stop_mode_io(struct platform_device
*dsidev
)
2541 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2542 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2543 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
2545 if (wait_for_bit_change(dsidev
, DSI_TIMING1
, 15, 0) != 0) {
2546 DSSERR("TX_STOP bit not going down\n");
2553 static bool dsi_vc_is_enabled(struct platform_device
*dsidev
, int channel
)
2555 return REG_GET(dsidev
, DSI_VC_CTRL(channel
), 0, 0);
2558 static void dsi_packet_sent_handler_vp(void *data
, u32 mask
)
2560 struct dsi_packet_sent_handler_data
*vp_data
=
2561 (struct dsi_packet_sent_handler_data
*) data
;
2562 struct dsi_data
*dsi
= dsi_get_dsidrv_data(vp_data
->dsidev
);
2563 const int channel
= dsi
->update_channel
;
2564 u8 bit
= dsi
->te_enabled
? 30 : 31;
2566 if (REG_GET(vp_data
->dsidev
, DSI_VC_TE(channel
), bit
, bit
) == 0)
2567 complete(vp_data
->completion
);
2570 static int dsi_sync_vc_vp(struct platform_device
*dsidev
, int channel
)
2572 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2573 DECLARE_COMPLETION_ONSTACK(completion
);
2574 struct dsi_packet_sent_handler_data vp_data
= {
2576 .completion
= &completion
2581 bit
= dsi
->te_enabled
? 30 : 31;
2583 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2584 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2588 /* Wait for completion only if TE_EN/TE_START is still set */
2589 if (REG_GET(dsidev
, DSI_VC_TE(channel
), bit
, bit
)) {
2590 if (wait_for_completion_timeout(&completion
,
2591 msecs_to_jiffies(10)) == 0) {
2592 DSSERR("Failed to complete previous frame transfer\n");
2598 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2599 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2603 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2604 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2609 static void dsi_packet_sent_handler_l4(void *data
, u32 mask
)
2611 struct dsi_packet_sent_handler_data
*l4_data
=
2612 (struct dsi_packet_sent_handler_data
*) data
;
2613 struct dsi_data
*dsi
= dsi_get_dsidrv_data(l4_data
->dsidev
);
2614 const int channel
= dsi
->update_channel
;
2616 if (REG_GET(l4_data
->dsidev
, DSI_VC_CTRL(channel
), 5, 5) == 0)
2617 complete(l4_data
->completion
);
2620 static int dsi_sync_vc_l4(struct platform_device
*dsidev
, int channel
)
2622 DECLARE_COMPLETION_ONSTACK(completion
);
2623 struct dsi_packet_sent_handler_data l4_data
= {
2625 .completion
= &completion
2629 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2630 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2634 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2635 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 5, 5)) {
2636 if (wait_for_completion_timeout(&completion
,
2637 msecs_to_jiffies(10)) == 0) {
2638 DSSERR("Failed to complete previous l4 transfer\n");
2644 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2645 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2649 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2650 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2655 static int dsi_sync_vc(struct platform_device
*dsidev
, int channel
)
2657 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2659 WARN_ON(!dsi_bus_is_locked(dsidev
));
2661 WARN_ON(in_interrupt());
2663 if (!dsi_vc_is_enabled(dsidev
, channel
))
2666 switch (dsi
->vc
[channel
].source
) {
2667 case DSI_VC_SOURCE_VP
:
2668 return dsi_sync_vc_vp(dsidev
, channel
);
2669 case DSI_VC_SOURCE_L4
:
2670 return dsi_sync_vc_l4(dsidev
, channel
);
2677 static int dsi_vc_enable(struct platform_device
*dsidev
, int channel
,
2680 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2683 enable
= enable
? 1 : 0;
2685 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 0, 0);
2687 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
),
2688 0, enable
) != enable
) {
2689 DSSERR("Failed to set dsi_vc_enable to %d\n", enable
);
2696 static void dsi_vc_initial_config(struct platform_device
*dsidev
, int channel
)
2698 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2701 DSSDBG("Initial config of virtual channel %d", channel
);
2703 r
= dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2705 if (FLD_GET(r
, 15, 15)) /* VC_BUSY */
2706 DSSERR("VC(%d) busy when trying to configure it!\n",
2709 r
= FLD_MOD(r
, 0, 1, 1); /* SOURCE, 0 = L4 */
2710 r
= FLD_MOD(r
, 0, 2, 2); /* BTA_SHORT_EN */
2711 r
= FLD_MOD(r
, 0, 3, 3); /* BTA_LONG_EN */
2712 r
= FLD_MOD(r
, 0, 4, 4); /* MODE, 0 = command */
2713 r
= FLD_MOD(r
, 1, 7, 7); /* CS_TX_EN */
2714 r
= FLD_MOD(r
, 1, 8, 8); /* ECC_TX_EN */
2715 r
= FLD_MOD(r
, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2716 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH
))
2717 r
= FLD_MOD(r
, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2719 r
= FLD_MOD(r
, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2720 r
= FLD_MOD(r
, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2722 dsi_write_reg(dsidev
, DSI_VC_CTRL(channel
), r
);
2724 dsi
->vc
[channel
].source
= DSI_VC_SOURCE_L4
;
2727 static int dsi_vc_config_source(struct platform_device
*dsidev
, int channel
,
2728 enum dsi_vc_source source
)
2730 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2732 if (dsi
->vc
[channel
].source
== source
)
2735 DSSDBG("Source config of virtual channel %d", channel
);
2737 dsi_sync_vc(dsidev
, channel
);
2739 dsi_vc_enable(dsidev
, channel
, 0);
2742 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
), 15, 0) != 0) {
2743 DSSERR("vc(%d) busy when trying to config for VP\n", channel
);
2747 /* SOURCE, 0 = L4, 1 = video port */
2748 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), source
, 1, 1);
2750 /* DCS_CMD_ENABLE */
2751 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
2752 bool enable
= source
== DSI_VC_SOURCE_VP
;
2753 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 30, 30);
2756 dsi_vc_enable(dsidev
, channel
, 1);
2758 dsi
->vc
[channel
].source
= source
;
2763 static void dsi_vc_enable_hs(struct omap_dss_device
*dssdev
, int channel
,
2766 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2767 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2769 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel
, enable
);
2771 WARN_ON(!dsi_bus_is_locked(dsidev
));
2773 dsi_vc_enable(dsidev
, channel
, 0);
2774 dsi_if_enable(dsidev
, 0);
2776 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 9, 9);
2778 dsi_vc_enable(dsidev
, channel
, 1);
2779 dsi_if_enable(dsidev
, 1);
2781 dsi_force_tx_stop_mode_io(dsidev
);
2783 /* start the DDR clock by sending a NULL packet */
2784 if (dsi
->vm_timings
.ddr_clk_always_on
&& enable
)
2785 dsi_vc_send_null(dssdev
, channel
);
2788 static void dsi_vc_flush_long_data(struct platform_device
*dsidev
, int channel
)
2790 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2792 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2793 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2797 (val
>> 24) & 0xff);
2801 static void dsi_show_rx_ack_with_err(u16 err
)
2803 DSSERR("\tACK with ERROR (%#x):\n", err
);
2805 DSSERR("\t\tSoT Error\n");
2807 DSSERR("\t\tSoT Sync Error\n");
2809 DSSERR("\t\tEoT Sync Error\n");
2811 DSSERR("\t\tEscape Mode Entry Command Error\n");
2813 DSSERR("\t\tLP Transmit Sync Error\n");
2815 DSSERR("\t\tHS Receive Timeout Error\n");
2817 DSSERR("\t\tFalse Control Error\n");
2819 DSSERR("\t\t(reserved7)\n");
2821 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2823 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2824 if (err
& (1 << 10))
2825 DSSERR("\t\tChecksum Error\n");
2826 if (err
& (1 << 11))
2827 DSSERR("\t\tData type not recognized\n");
2828 if (err
& (1 << 12))
2829 DSSERR("\t\tInvalid VC ID\n");
2830 if (err
& (1 << 13))
2831 DSSERR("\t\tInvalid Transmission Length\n");
2832 if (err
& (1 << 14))
2833 DSSERR("\t\t(reserved14)\n");
2834 if (err
& (1 << 15))
2835 DSSERR("\t\tDSI Protocol Violation\n");
2838 static u16
dsi_vc_flush_receive_data(struct platform_device
*dsidev
,
2841 /* RX_FIFO_NOT_EMPTY */
2842 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2845 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2846 DSSERR("\trawval %#08x\n", val
);
2847 dt
= FLD_GET(val
, 5, 0);
2848 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
2849 u16 err
= FLD_GET(val
, 23, 8);
2850 dsi_show_rx_ack_with_err(err
);
2851 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
) {
2852 DSSERR("\tDCS short response, 1 byte: %#x\n",
2853 FLD_GET(val
, 23, 8));
2854 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
) {
2855 DSSERR("\tDCS short response, 2 byte: %#x\n",
2856 FLD_GET(val
, 23, 8));
2857 } else if (dt
== MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
) {
2858 DSSERR("\tDCS long response, len %d\n",
2859 FLD_GET(val
, 23, 8));
2860 dsi_vc_flush_long_data(dsidev
, channel
);
2862 DSSERR("\tunknown datatype 0x%02x\n", dt
);
2868 static int dsi_vc_send_bta(struct platform_device
*dsidev
, int channel
)
2870 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2872 if (dsi
->debug_write
|| dsi
->debug_read
)
2873 DSSDBG("dsi_vc_send_bta %d\n", channel
);
2875 WARN_ON(!dsi_bus_is_locked(dsidev
));
2877 /* RX_FIFO_NOT_EMPTY */
2878 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2879 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2880 dsi_vc_flush_receive_data(dsidev
, channel
);
2883 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 6, 6); /* BTA_EN */
2885 /* flush posted write */
2886 dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2891 static int dsi_vc_send_bta_sync(struct omap_dss_device
*dssdev
, int channel
)
2893 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2894 DECLARE_COMPLETION_ONSTACK(completion
);
2898 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2899 &completion
, DSI_VC_IRQ_BTA
);
2903 r
= dsi_register_isr(dsidev
, dsi_completion_handler
, &completion
,
2904 DSI_IRQ_ERROR_MASK
);
2908 r
= dsi_vc_send_bta(dsidev
, channel
);
2912 if (wait_for_completion_timeout(&completion
,
2913 msecs_to_jiffies(500)) == 0) {
2914 DSSERR("Failed to receive BTA\n");
2919 err
= dsi_get_errors(dsidev
);
2921 DSSERR("Error while sending BTA: %x\n", err
);
2926 dsi_unregister_isr(dsidev
, dsi_completion_handler
, &completion
,
2927 DSI_IRQ_ERROR_MASK
);
2929 dsi_unregister_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2930 &completion
, DSI_VC_IRQ_BTA
);
2935 static inline void dsi_vc_write_long_header(struct platform_device
*dsidev
,
2936 int channel
, u8 data_type
, u16 len
, u8 ecc
)
2938 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2942 WARN_ON(!dsi_bus_is_locked(dsidev
));
2944 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
2946 val
= FLD_VAL(data_id
, 7, 0) | FLD_VAL(len
, 23, 8) |
2947 FLD_VAL(ecc
, 31, 24);
2949 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_HEADER(channel
), val
);
2952 static inline void dsi_vc_write_long_payload(struct platform_device
*dsidev
,
2953 int channel
, u8 b1
, u8 b2
, u8 b3
, u8 b4
)
2957 val
= b4
<< 24 | b3
<< 16 | b2
<< 8 | b1
<< 0;
2959 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2960 b1, b2, b3, b4, val); */
2962 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_PAYLOAD(channel
), val
);
2965 static int dsi_vc_send_long(struct platform_device
*dsidev
, int channel
,
2966 u8 data_type
, u8
*data
, u16 len
, u8 ecc
)
2969 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2975 if (dsi
->debug_write
)
2976 DSSDBG("dsi_vc_send_long, %d bytes\n", len
);
2979 if (dsi
->vc
[channel
].tx_fifo_size
* 32 * 4 < len
+ 4) {
2980 DSSERR("unable to send long packet: packet too long.\n");
2984 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
2986 dsi_vc_write_long_header(dsidev
, channel
, data_type
, len
, ecc
);
2989 for (i
= 0; i
< len
>> 2; i
++) {
2990 if (dsi
->debug_write
)
2991 DSSDBG("\tsending full packet %d\n", i
);
2998 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, b4
);
3003 b1
= 0; b2
= 0; b3
= 0;
3005 if (dsi
->debug_write
)
3006 DSSDBG("\tsending remainder bytes %d\n", i
);
3023 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, 0);
3029 static int dsi_vc_send_short(struct platform_device
*dsidev
, int channel
,
3030 u8 data_type
, u16 data
, u8 ecc
)
3032 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3036 WARN_ON(!dsi_bus_is_locked(dsidev
));
3038 if (dsi
->debug_write
)
3039 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3041 data_type
, data
& 0xff, (data
>> 8) & 0xff);
3043 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
3045 if (FLD_GET(dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
)), 16, 16)) {
3046 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3050 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
3052 r
= (data_id
<< 0) | (data
<< 8) | (ecc
<< 24);
3054 dsi_write_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
), r
);
3059 static int dsi_vc_send_null(struct omap_dss_device
*dssdev
, int channel
)
3061 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3063 return dsi_vc_send_long(dsidev
, channel
, MIPI_DSI_NULL_PACKET
, NULL
,
3067 static int dsi_vc_write_nosync_common(struct platform_device
*dsidev
,
3068 int channel
, u8
*data
, int len
, enum dss_dsi_content_type type
)
3073 BUG_ON(type
== DSS_DSI_CONTENT_DCS
);
3074 r
= dsi_vc_send_short(dsidev
, channel
,
3075 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
, 0, 0);
3076 } else if (len
== 1) {
3077 r
= dsi_vc_send_short(dsidev
, channel
,
3078 type
== DSS_DSI_CONTENT_GENERIC
?
3079 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
3080 MIPI_DSI_DCS_SHORT_WRITE
, data
[0], 0);
3081 } else if (len
== 2) {
3082 r
= dsi_vc_send_short(dsidev
, channel
,
3083 type
== DSS_DSI_CONTENT_GENERIC
?
3084 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
3085 MIPI_DSI_DCS_SHORT_WRITE_PARAM
,
3086 data
[0] | (data
[1] << 8), 0);
3088 r
= dsi_vc_send_long(dsidev
, channel
,
3089 type
== DSS_DSI_CONTENT_GENERIC
?
3090 MIPI_DSI_GENERIC_LONG_WRITE
:
3091 MIPI_DSI_DCS_LONG_WRITE
, data
, len
, 0);
3097 static int dsi_vc_dcs_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3100 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3102 return dsi_vc_write_nosync_common(dsidev
, channel
, data
, len
,
3103 DSS_DSI_CONTENT_DCS
);
3106 static int dsi_vc_generic_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3109 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3111 return dsi_vc_write_nosync_common(dsidev
, channel
, data
, len
,
3112 DSS_DSI_CONTENT_GENERIC
);
3115 static int dsi_vc_write_common(struct omap_dss_device
*dssdev
, int channel
,
3116 u8
*data
, int len
, enum dss_dsi_content_type type
)
3118 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3121 r
= dsi_vc_write_nosync_common(dsidev
, channel
, data
, len
, type
);
3125 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3129 /* RX_FIFO_NOT_EMPTY */
3130 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
3131 DSSERR("rx fifo not empty after write, dumping data:\n");
3132 dsi_vc_flush_receive_data(dsidev
, channel
);
3139 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3140 channel
, data
[0], len
);
3144 static int dsi_vc_dcs_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3147 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3148 DSS_DSI_CONTENT_DCS
);
3151 static int dsi_vc_generic_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3154 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3155 DSS_DSI_CONTENT_GENERIC
);
3158 static int dsi_vc_dcs_send_read_request(struct platform_device
*dsidev
,
3159 int channel
, u8 dcs_cmd
)
3161 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3164 if (dsi
->debug_read
)
3165 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3168 r
= dsi_vc_send_short(dsidev
, channel
, MIPI_DSI_DCS_READ
, dcs_cmd
, 0);
3170 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3171 " failed\n", channel
, dcs_cmd
);
3178 static int dsi_vc_generic_send_read_request(struct platform_device
*dsidev
,
3179 int channel
, u8
*reqdata
, int reqlen
)
3181 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3186 if (dsi
->debug_read
)
3187 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3191 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
;
3193 } else if (reqlen
== 1) {
3194 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
;
3196 } else if (reqlen
== 2) {
3197 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
;
3198 data
= reqdata
[0] | (reqdata
[1] << 8);
3204 r
= dsi_vc_send_short(dsidev
, channel
, data_type
, data
, 0);
3206 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3207 " failed\n", channel
, reqlen
);
3214 static int dsi_vc_read_rx_fifo(struct platform_device
*dsidev
, int channel
,
3215 u8
*buf
, int buflen
, enum dss_dsi_content_type type
)
3217 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3222 /* RX_FIFO_NOT_EMPTY */
3223 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20) == 0) {
3224 DSSERR("RX fifo empty when trying to read.\n");
3229 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
3230 if (dsi
->debug_read
)
3231 DSSDBG("\theader: %08x\n", val
);
3232 dt
= FLD_GET(val
, 5, 0);
3233 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
3234 u16 err
= FLD_GET(val
, 23, 8);
3235 dsi_show_rx_ack_with_err(err
);
3239 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3240 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE
:
3241 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
)) {
3242 u8 data
= FLD_GET(val
, 15, 8);
3243 if (dsi
->debug_read
)
3244 DSSDBG("\t%s short response, 1 byte: %02x\n",
3245 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3256 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3257 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE
:
3258 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
)) {
3259 u16 data
= FLD_GET(val
, 23, 8);
3260 if (dsi
->debug_read
)
3261 DSSDBG("\t%s short response, 2 byte: %04x\n",
3262 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3270 buf
[0] = data
& 0xff;
3271 buf
[1] = (data
>> 8) & 0xff;
3274 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3275 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
3276 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
)) {
3278 int len
= FLD_GET(val
, 23, 8);
3279 if (dsi
->debug_read
)
3280 DSSDBG("\t%s long response, len %d\n",
3281 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3289 /* two byte checksum ends the packet, not included in len */
3290 for (w
= 0; w
< len
+ 2;) {
3292 val
= dsi_read_reg(dsidev
,
3293 DSI_VC_SHORT_PACKET_HEADER(channel
));
3294 if (dsi
->debug_read
)
3295 DSSDBG("\t\t%02x %02x %02x %02x\n",
3299 (val
>> 24) & 0xff);
3301 for (b
= 0; b
< 4; ++b
) {
3303 buf
[w
] = (val
>> (b
* 8)) & 0xff;
3304 /* we discard the 2 byte checksum */
3311 DSSERR("\tunknown datatype 0x%02x\n", dt
);
3317 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel
,
3318 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" : "DCS");
3323 static int dsi_vc_dcs_read(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3324 u8
*buf
, int buflen
)
3326 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3329 r
= dsi_vc_dcs_send_read_request(dsidev
, channel
, dcs_cmd
);
3333 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3337 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3338 DSS_DSI_CONTENT_DCS
);
3349 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel
, dcs_cmd
);
3353 static int dsi_vc_generic_read(struct omap_dss_device
*dssdev
, int channel
,
3354 u8
*reqdata
, int reqlen
, u8
*buf
, int buflen
)
3356 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3359 r
= dsi_vc_generic_send_read_request(dsidev
, channel
, reqdata
, reqlen
);
3363 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3367 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3368 DSS_DSI_CONTENT_GENERIC
);
3380 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device
*dssdev
, int channel
,
3383 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3385 return dsi_vc_send_short(dsidev
, channel
,
3386 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
, len
, 0);
3389 static int dsi_enter_ulps(struct platform_device
*dsidev
)
3391 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3392 DECLARE_COMPLETION_ONSTACK(completion
);
3396 DSSDBG("Entering ULPS");
3398 WARN_ON(!dsi_bus_is_locked(dsidev
));
3400 WARN_ON(dsi
->ulps_enabled
);
3402 if (dsi
->ulps_enabled
)
3405 /* DDR_CLK_ALWAYS_ON */
3406 if (REG_GET(dsidev
, DSI_CLK_CTRL
, 13, 13)) {
3407 dsi_if_enable(dsidev
, 0);
3408 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
3409 dsi_if_enable(dsidev
, 1);
3412 dsi_sync_vc(dsidev
, 0);
3413 dsi_sync_vc(dsidev
, 1);
3414 dsi_sync_vc(dsidev
, 2);
3415 dsi_sync_vc(dsidev
, 3);
3417 dsi_force_tx_stop_mode_io(dsidev
);
3419 dsi_vc_enable(dsidev
, 0, false);
3420 dsi_vc_enable(dsidev
, 1, false);
3421 dsi_vc_enable(dsidev
, 2, false);
3422 dsi_vc_enable(dsidev
, 3, false);
3424 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 16, 16)) { /* HS_BUSY */
3425 DSSERR("HS busy when enabling ULPS\n");
3429 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 17, 17)) { /* LP_BUSY */
3430 DSSERR("LP busy when enabling ULPS\n");
3434 r
= dsi_register_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3435 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3441 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
3442 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
3446 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3447 /* LANEx_ULPS_SIG2 */
3448 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, mask
, 9, 5);
3450 /* flush posted write and wait for SCP interface to finish the write */
3451 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3453 if (wait_for_completion_timeout(&completion
,
3454 msecs_to_jiffies(1000)) == 0) {
3455 DSSERR("ULPS enable timeout\n");
3460 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3461 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3463 /* Reset LANEx_ULPS_SIG2 */
3464 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, 0, 9, 5);
3466 /* flush posted write and wait for SCP interface to finish the write */
3467 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3469 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ULPS
);
3471 dsi_if_enable(dsidev
, false);
3473 dsi
->ulps_enabled
= true;
3478 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3479 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3483 static void dsi_set_lp_rx_timeout(struct platform_device
*dsidev
,
3484 unsigned ticks
, bool x4
, bool x16
)
3487 unsigned long total_ticks
;
3490 BUG_ON(ticks
> 0x1fff);
3492 /* ticks in DSI_FCK */
3493 fck
= dsi_fclk_rate(dsidev
);
3495 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3496 r
= FLD_MOD(r
, 1, 15, 15); /* LP_RX_TO */
3497 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3498 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3499 r
= FLD_MOD(r
, ticks
, 12, 0); /* LP_RX_COUNTER */
3500 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3502 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3504 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3506 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3507 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3510 static void dsi_set_ta_timeout(struct platform_device
*dsidev
, unsigned ticks
,
3514 unsigned long total_ticks
;
3517 BUG_ON(ticks
> 0x1fff);
3519 /* ticks in DSI_FCK */
3520 fck
= dsi_fclk_rate(dsidev
);
3522 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3523 r
= FLD_MOD(r
, 1, 31, 31); /* TA_TO */
3524 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* TA_TO_X16 */
3525 r
= FLD_MOD(r
, x8
? 1 : 0, 29, 29); /* TA_TO_X8 */
3526 r
= FLD_MOD(r
, ticks
, 28, 16); /* TA_TO_COUNTER */
3527 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3529 total_ticks
= ticks
* (x16
? 16 : 1) * (x8
? 8 : 1);
3531 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3533 ticks
, x8
? " x8" : "", x16
? " x16" : "",
3534 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3537 static void dsi_set_stop_state_counter(struct platform_device
*dsidev
,
3538 unsigned ticks
, bool x4
, bool x16
)
3541 unsigned long total_ticks
;
3544 BUG_ON(ticks
> 0x1fff);
3546 /* ticks in DSI_FCK */
3547 fck
= dsi_fclk_rate(dsidev
);
3549 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3550 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3551 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3552 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3553 r
= FLD_MOD(r
, ticks
, 12, 0); /* STOP_STATE_COUNTER_IO */
3554 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3556 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3558 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3560 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3561 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3564 static void dsi_set_hs_tx_timeout(struct platform_device
*dsidev
,
3565 unsigned ticks
, bool x4
, bool x16
)
3568 unsigned long total_ticks
;
3571 BUG_ON(ticks
> 0x1fff);
3573 /* ticks in TxByteClkHS */
3574 fck
= dsi_get_txbyteclkhs(dsidev
);
3576 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3577 r
= FLD_MOD(r
, 1, 31, 31); /* HS_TX_TO */
3578 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3579 r
= FLD_MOD(r
, x4
? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3580 r
= FLD_MOD(r
, ticks
, 28, 16); /* HS_TX_TO_COUNTER */
3581 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3583 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3585 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3587 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3588 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3591 static void dsi_config_vp_num_line_buffers(struct platform_device
*dsidev
)
3593 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3594 int num_line_buffers
;
3596 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3597 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
3598 struct omap_video_timings
*timings
= &dsi
->timings
;
3600 * Don't use line buffers if width is greater than the video
3601 * port's line buffer size
3603 if (dsi
->line_buffer_size
<= timings
->x_res
* bpp
/ 8)
3604 num_line_buffers
= 0;
3606 num_line_buffers
= 2;
3608 /* Use maximum number of line buffers in command mode */
3609 num_line_buffers
= 2;
3613 REG_FLD_MOD(dsidev
, DSI_CTRL
, num_line_buffers
, 13, 12);
3616 static void dsi_config_vp_sync_events(struct platform_device
*dsidev
)
3618 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3622 if (dsi
->vm_timings
.trans_mode
== OMAP_DSS_DSI_PULSE_MODE
)
3627 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3628 r
= FLD_MOD(r
, 1, 9, 9); /* VP_DE_POL */
3629 r
= FLD_MOD(r
, 1, 10, 10); /* VP_HSYNC_POL */
3630 r
= FLD_MOD(r
, 1, 11, 11); /* VP_VSYNC_POL */
3631 r
= FLD_MOD(r
, 1, 15, 15); /* VP_VSYNC_START */
3632 r
= FLD_MOD(r
, sync_end
, 16, 16); /* VP_VSYNC_END */
3633 r
= FLD_MOD(r
, 1, 17, 17); /* VP_HSYNC_START */
3634 r
= FLD_MOD(r
, sync_end
, 18, 18); /* VP_HSYNC_END */
3635 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3638 static void dsi_config_blanking_modes(struct platform_device
*dsidev
)
3640 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3641 int blanking_mode
= dsi
->vm_timings
.blanking_mode
;
3642 int hfp_blanking_mode
= dsi
->vm_timings
.hfp_blanking_mode
;
3643 int hbp_blanking_mode
= dsi
->vm_timings
.hbp_blanking_mode
;
3644 int hsa_blanking_mode
= dsi
->vm_timings
.hsa_blanking_mode
;
3648 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3649 * 1 = Long blanking packets are sent in corresponding blanking periods
3651 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3652 r
= FLD_MOD(r
, blanking_mode
, 20, 20); /* BLANKING_MODE */
3653 r
= FLD_MOD(r
, hfp_blanking_mode
, 21, 21); /* HFP_BLANKING */
3654 r
= FLD_MOD(r
, hbp_blanking_mode
, 22, 22); /* HBP_BLANKING */
3655 r
= FLD_MOD(r
, hsa_blanking_mode
, 23, 23); /* HSA_BLANKING */
3656 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3660 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3661 * results in maximum transition time for data and clock lanes to enter and
3662 * exit HS mode. Hence, this is the scenario where the least amount of command
3663 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3664 * clock cycles that can be used to interleave command mode data in HS so that
3665 * all scenarios are satisfied.
3667 static int dsi_compute_interleave_hs(int blank
, bool ddr_alwon
, int enter_hs
,
3668 int exit_hs
, int exiths_clk
, int ddr_pre
, int ddr_post
)
3673 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3674 * time of data lanes only, if it isn't set, we need to consider HS
3675 * transition time of both data and clock lanes. HS transition time
3676 * of Scenario 3 is considered.
3679 transition
= enter_hs
+ exit_hs
+ max(enter_hs
, 2) + 1;
3682 trans1
= ddr_pre
+ enter_hs
+ exit_hs
+ max(enter_hs
, 2) + 1;
3683 trans2
= ddr_pre
+ enter_hs
+ exiths_clk
+ ddr_post
+ ddr_pre
+
3685 transition
= max(trans1
, trans2
);
3688 return blank
> transition
? blank
- transition
: 0;
3692 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3693 * results in maximum transition time for data lanes to enter and exit LP mode.
3694 * Hence, this is the scenario where the least amount of command mode data can
3695 * be interleaved. We program the minimum amount of bytes that can be
3696 * interleaved in LP so that all scenarios are satisfied.
3698 static int dsi_compute_interleave_lp(int blank
, int enter_hs
, int exit_hs
,
3699 int lp_clk_div
, int tdsi_fclk
)
3701 int trans_lp
; /* time required for a LP transition, in TXBYTECLKHS */
3702 int tlp_avail
; /* time left for interleaving commands, in CLKIN4DDR */
3703 int ttxclkesc
; /* period of LP transmit escape clock, in CLKIN4DDR */
3704 int thsbyte_clk
= 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3705 int lp_inter
; /* cmd mode data that can be interleaved, in bytes */
3707 /* maximum LP transition time according to Scenario 1 */
3708 trans_lp
= exit_hs
+ max(enter_hs
, 2) + 1;
3710 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3711 tlp_avail
= thsbyte_clk
* (blank
- trans_lp
);
3713 ttxclkesc
= tdsi_fclk
* lp_clk_div
;
3715 lp_inter
= ((tlp_avail
- 8 * thsbyte_clk
- 5 * tdsi_fclk
) / ttxclkesc
-
3718 return max(lp_inter
, 0);
3721 static void dsi_config_cmd_mode_interleaving(struct platform_device
*dsidev
)
3723 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3725 int hfp_blanking_mode
, hbp_blanking_mode
, hsa_blanking_mode
;
3726 int hsa
, hfp
, hbp
, width_bytes
, bllp
, lp_clk_div
;
3727 int ddr_clk_pre
, ddr_clk_post
, enter_hs_mode_lat
, exit_hs_mode_lat
;
3728 int tclk_trail
, ths_exit
, exiths_clk
;
3730 struct omap_video_timings
*timings
= &dsi
->timings
;
3731 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
3732 int ndl
= dsi
->num_lanes_used
- 1;
3733 int dsi_fclk_hsdiv
= dsi
->user_dsi_cinfo
.regm_dsi
+ 1;
3734 int hsa_interleave_hs
= 0, hsa_interleave_lp
= 0;
3735 int hfp_interleave_hs
= 0, hfp_interleave_lp
= 0;
3736 int hbp_interleave_hs
= 0, hbp_interleave_lp
= 0;
3737 int bl_interleave_hs
= 0, bl_interleave_lp
= 0;
3740 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3741 blanking_mode
= FLD_GET(r
, 20, 20);
3742 hfp_blanking_mode
= FLD_GET(r
, 21, 21);
3743 hbp_blanking_mode
= FLD_GET(r
, 22, 22);
3744 hsa_blanking_mode
= FLD_GET(r
, 23, 23);
3746 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING1
);
3747 hbp
= FLD_GET(r
, 11, 0);
3748 hfp
= FLD_GET(r
, 23, 12);
3749 hsa
= FLD_GET(r
, 31, 24);
3751 r
= dsi_read_reg(dsidev
, DSI_CLK_TIMING
);
3752 ddr_clk_post
= FLD_GET(r
, 7, 0);
3753 ddr_clk_pre
= FLD_GET(r
, 15, 8);
3755 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING7
);
3756 exit_hs_mode_lat
= FLD_GET(r
, 15, 0);
3757 enter_hs_mode_lat
= FLD_GET(r
, 31, 16);
3759 r
= dsi_read_reg(dsidev
, DSI_CLK_CTRL
);
3760 lp_clk_div
= FLD_GET(r
, 12, 0);
3761 ddr_alwon
= FLD_GET(r
, 13, 13);
3763 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
3764 ths_exit
= FLD_GET(r
, 7, 0);
3766 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
3767 tclk_trail
= FLD_GET(r
, 15, 8);
3769 exiths_clk
= ths_exit
+ tclk_trail
;
3771 width_bytes
= DIV_ROUND_UP(timings
->x_res
* bpp
, 8);
3772 bllp
= hbp
+ hfp
+ hsa
+ DIV_ROUND_UP(width_bytes
+ 6, ndl
);
3774 if (!hsa_blanking_mode
) {
3775 hsa_interleave_hs
= dsi_compute_interleave_hs(hsa
, ddr_alwon
,
3776 enter_hs_mode_lat
, exit_hs_mode_lat
,
3777 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3778 hsa_interleave_lp
= dsi_compute_interleave_lp(hsa
,
3779 enter_hs_mode_lat
, exit_hs_mode_lat
,
3780 lp_clk_div
, dsi_fclk_hsdiv
);
3783 if (!hfp_blanking_mode
) {
3784 hfp_interleave_hs
= dsi_compute_interleave_hs(hfp
, ddr_alwon
,
3785 enter_hs_mode_lat
, exit_hs_mode_lat
,
3786 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3787 hfp_interleave_lp
= dsi_compute_interleave_lp(hfp
,
3788 enter_hs_mode_lat
, exit_hs_mode_lat
,
3789 lp_clk_div
, dsi_fclk_hsdiv
);
3792 if (!hbp_blanking_mode
) {
3793 hbp_interleave_hs
= dsi_compute_interleave_hs(hbp
, ddr_alwon
,
3794 enter_hs_mode_lat
, exit_hs_mode_lat
,
3795 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3797 hbp_interleave_lp
= dsi_compute_interleave_lp(hbp
,
3798 enter_hs_mode_lat
, exit_hs_mode_lat
,
3799 lp_clk_div
, dsi_fclk_hsdiv
);
3802 if (!blanking_mode
) {
3803 bl_interleave_hs
= dsi_compute_interleave_hs(bllp
, ddr_alwon
,
3804 enter_hs_mode_lat
, exit_hs_mode_lat
,
3805 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3807 bl_interleave_lp
= dsi_compute_interleave_lp(bllp
,
3808 enter_hs_mode_lat
, exit_hs_mode_lat
,
3809 lp_clk_div
, dsi_fclk_hsdiv
);
3812 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3813 hsa_interleave_hs
, hfp_interleave_hs
, hbp_interleave_hs
,
3816 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3817 hsa_interleave_lp
, hfp_interleave_lp
, hbp_interleave_lp
,
3820 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING4
);
3821 r
= FLD_MOD(r
, hsa_interleave_hs
, 23, 16);
3822 r
= FLD_MOD(r
, hfp_interleave_hs
, 15, 8);
3823 r
= FLD_MOD(r
, hbp_interleave_hs
, 7, 0);
3824 dsi_write_reg(dsidev
, DSI_VM_TIMING4
, r
);
3826 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING5
);
3827 r
= FLD_MOD(r
, hsa_interleave_lp
, 23, 16);
3828 r
= FLD_MOD(r
, hfp_interleave_lp
, 15, 8);
3829 r
= FLD_MOD(r
, hbp_interleave_lp
, 7, 0);
3830 dsi_write_reg(dsidev
, DSI_VM_TIMING5
, r
);
3832 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING6
);
3833 r
= FLD_MOD(r
, bl_interleave_hs
, 31, 15);
3834 r
= FLD_MOD(r
, bl_interleave_lp
, 16, 0);
3835 dsi_write_reg(dsidev
, DSI_VM_TIMING6
, r
);
3838 static int dsi_proto_config(struct platform_device
*dsidev
)
3840 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3844 dsi_config_tx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3849 dsi_config_rx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3854 /* XXX what values for the timeouts? */
3855 dsi_set_stop_state_counter(dsidev
, 0x1000, false, false);
3856 dsi_set_ta_timeout(dsidev
, 0x1fff, true, true);
3857 dsi_set_lp_rx_timeout(dsidev
, 0x1fff, true, true);
3858 dsi_set_hs_tx_timeout(dsidev
, 0x1fff, true, true);
3860 switch (dsi_get_pixel_size(dsi
->pix_fmt
)) {
3875 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3876 r
= FLD_MOD(r
, 1, 1, 1); /* CS_RX_EN */
3877 r
= FLD_MOD(r
, 1, 2, 2); /* ECC_RX_EN */
3878 r
= FLD_MOD(r
, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3879 r
= FLD_MOD(r
, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3880 r
= FLD_MOD(r
, buswidth
, 7, 6); /* VP_DATA_BUS_WIDTH */
3881 r
= FLD_MOD(r
, 0, 8, 8); /* VP_CLK_POL */
3882 r
= FLD_MOD(r
, 1, 14, 14); /* TRIGGER_RESET_MODE */
3883 r
= FLD_MOD(r
, 1, 19, 19); /* EOT_ENABLE */
3884 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
3885 r
= FLD_MOD(r
, 1, 24, 24); /* DCS_CMD_ENABLE */
3886 /* DCS_CMD_CODE, 1=start, 0=continue */
3887 r
= FLD_MOD(r
, 0, 25, 25);
3890 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3892 dsi_config_vp_num_line_buffers(dsidev
);
3894 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3895 dsi_config_vp_sync_events(dsidev
);
3896 dsi_config_blanking_modes(dsidev
);
3897 dsi_config_cmd_mode_interleaving(dsidev
);
3900 dsi_vc_initial_config(dsidev
, 0);
3901 dsi_vc_initial_config(dsidev
, 1);
3902 dsi_vc_initial_config(dsidev
, 2);
3903 dsi_vc_initial_config(dsidev
, 3);
3908 static void dsi_proto_timings(struct platform_device
*dsidev
)
3910 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3911 unsigned tlpx
, tclk_zero
, tclk_prepare
, tclk_trail
;
3912 unsigned tclk_pre
, tclk_post
;
3913 unsigned ths_prepare
, ths_prepare_ths_zero
, ths_zero
;
3914 unsigned ths_trail
, ths_exit
;
3915 unsigned ddr_clk_pre
, ddr_clk_post
;
3916 unsigned enter_hs_mode_lat
, exit_hs_mode_lat
;
3918 int ndl
= dsi
->num_lanes_used
- 1;
3921 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
3922 ths_prepare
= FLD_GET(r
, 31, 24);
3923 ths_prepare_ths_zero
= FLD_GET(r
, 23, 16);
3924 ths_zero
= ths_prepare_ths_zero
- ths_prepare
;
3925 ths_trail
= FLD_GET(r
, 15, 8);
3926 ths_exit
= FLD_GET(r
, 7, 0);
3928 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
3929 tlpx
= FLD_GET(r
, 20, 16) * 2;
3930 tclk_trail
= FLD_GET(r
, 15, 8);
3931 tclk_zero
= FLD_GET(r
, 7, 0);
3933 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
3934 tclk_prepare
= FLD_GET(r
, 7, 0);
3938 /* min 60ns + 52*UI */
3939 tclk_post
= ns2ddr(dsidev
, 60) + 26;
3941 ths_eot
= DIV_ROUND_UP(4, ndl
);
3943 ddr_clk_pre
= DIV_ROUND_UP(tclk_pre
+ tlpx
+ tclk_zero
+ tclk_prepare
,
3945 ddr_clk_post
= DIV_ROUND_UP(tclk_post
+ ths_trail
, 4) + ths_eot
;
3947 BUG_ON(ddr_clk_pre
== 0 || ddr_clk_pre
> 255);
3948 BUG_ON(ddr_clk_post
== 0 || ddr_clk_post
> 255);
3950 r
= dsi_read_reg(dsidev
, DSI_CLK_TIMING
);
3951 r
= FLD_MOD(r
, ddr_clk_pre
, 15, 8);
3952 r
= FLD_MOD(r
, ddr_clk_post
, 7, 0);
3953 dsi_write_reg(dsidev
, DSI_CLK_TIMING
, r
);
3955 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3959 enter_hs_mode_lat
= 1 + DIV_ROUND_UP(tlpx
, 4) +
3960 DIV_ROUND_UP(ths_prepare
, 4) +
3961 DIV_ROUND_UP(ths_zero
+ 3, 4);
3963 exit_hs_mode_lat
= DIV_ROUND_UP(ths_trail
+ ths_exit
, 4) + 1 + ths_eot
;
3965 r
= FLD_VAL(enter_hs_mode_lat
, 31, 16) |
3966 FLD_VAL(exit_hs_mode_lat
, 15, 0);
3967 dsi_write_reg(dsidev
, DSI_VM_TIMING7
, r
);
3969 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3970 enter_hs_mode_lat
, exit_hs_mode_lat
);
3972 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3973 /* TODO: Implement a video mode check_timings function */
3974 int hsa
= dsi
->vm_timings
.hsa
;
3975 int hfp
= dsi
->vm_timings
.hfp
;
3976 int hbp
= dsi
->vm_timings
.hbp
;
3977 int vsa
= dsi
->vm_timings
.vsa
;
3978 int vfp
= dsi
->vm_timings
.vfp
;
3979 int vbp
= dsi
->vm_timings
.vbp
;
3980 int window_sync
= dsi
->vm_timings
.window_sync
;
3982 struct omap_video_timings
*timings
= &dsi
->timings
;
3983 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
3984 int tl
, t_he
, width_bytes
;
3986 hsync_end
= dsi
->vm_timings
.trans_mode
== OMAP_DSS_DSI_PULSE_MODE
;
3988 ((hsa
== 0 && ndl
== 3) ? 1 : DIV_ROUND_UP(4, ndl
)) : 0;
3990 width_bytes
= DIV_ROUND_UP(timings
->x_res
* bpp
, 8);
3992 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3993 tl
= DIV_ROUND_UP(4, ndl
) + (hsync_end
? hsa
: 0) + t_he
+ hfp
+
3994 DIV_ROUND_UP(width_bytes
+ 6, ndl
) + hbp
;
3996 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp
,
3997 hfp
, hsync_end
? hsa
: 0, tl
);
3998 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp
, vfp
,
3999 vsa
, timings
->y_res
);
4001 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING1
);
4002 r
= FLD_MOD(r
, hbp
, 11, 0); /* HBP */
4003 r
= FLD_MOD(r
, hfp
, 23, 12); /* HFP */
4004 r
= FLD_MOD(r
, hsync_end
? hsa
: 0, 31, 24); /* HSA */
4005 dsi_write_reg(dsidev
, DSI_VM_TIMING1
, r
);
4007 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING2
);
4008 r
= FLD_MOD(r
, vbp
, 7, 0); /* VBP */
4009 r
= FLD_MOD(r
, vfp
, 15, 8); /* VFP */
4010 r
= FLD_MOD(r
, vsa
, 23, 16); /* VSA */
4011 r
= FLD_MOD(r
, window_sync
, 27, 24); /* WINDOW_SYNC */
4012 dsi_write_reg(dsidev
, DSI_VM_TIMING2
, r
);
4014 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING3
);
4015 r
= FLD_MOD(r
, timings
->y_res
, 14, 0); /* VACT */
4016 r
= FLD_MOD(r
, tl
, 31, 16); /* TL */
4017 dsi_write_reg(dsidev
, DSI_VM_TIMING3
, r
);
4021 static int dsi_configure_pins(struct omap_dss_device
*dssdev
,
4022 const struct omap_dsi_pin_config
*pin_cfg
)
4024 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4025 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4028 struct dsi_lane_config lanes
[DSI_MAX_NR_LANES
];
4032 static const enum dsi_lane_function functions
[] = {
4040 num_pins
= pin_cfg
->num_pins
;
4041 pins
= pin_cfg
->pins
;
4043 if (num_pins
< 4 || num_pins
> dsi
->num_lanes_supported
* 2
4044 || num_pins
% 2 != 0)
4047 for (i
= 0; i
< DSI_MAX_NR_LANES
; ++i
)
4048 lanes
[i
].function
= DSI_LANE_UNUSED
;
4052 for (i
= 0; i
< num_pins
; i
+= 2) {
4059 if (dx
< 0 || dx
>= dsi
->num_lanes_supported
* 2)
4062 if (dy
< 0 || dy
>= dsi
->num_lanes_supported
* 2)
4077 lanes
[lane
].function
= functions
[i
/ 2];
4078 lanes
[lane
].polarity
= pol
;
4082 memcpy(dsi
->lanes
, lanes
, sizeof(dsi
->lanes
));
4083 dsi
->num_lanes_used
= num_lanes
;
4088 static int dsi_enable_video_output(struct omap_dss_device
*dssdev
, int channel
)
4090 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4091 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4092 struct omap_overlay_manager
*mgr
= dsi
->output
.manager
;
4093 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
4094 struct omap_dss_device
*out
= &dsi
->output
;
4099 if (out
== NULL
|| out
->manager
== NULL
) {
4100 DSSERR("failed to enable display: no output/manager\n");
4104 r
= dsi_display_init_dispc(dsidev
, mgr
);
4106 goto err_init_dispc
;
4108 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4109 switch (dsi
->pix_fmt
) {
4110 case OMAP_DSS_DSI_FMT_RGB888
:
4111 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
4113 case OMAP_DSS_DSI_FMT_RGB666
:
4114 data_type
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
4116 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
4117 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
4119 case OMAP_DSS_DSI_FMT_RGB565
:
4120 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
4127 dsi_if_enable(dsidev
, false);
4128 dsi_vc_enable(dsidev
, channel
, false);
4130 /* MODE, 1 = video mode */
4131 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 4, 4);
4133 word_count
= DIV_ROUND_UP(dsi
->timings
.x_res
* bpp
, 8);
4135 dsi_vc_write_long_header(dsidev
, channel
, data_type
,
4138 dsi_vc_enable(dsidev
, channel
, true);
4139 dsi_if_enable(dsidev
, true);
4142 r
= dss_mgr_enable(mgr
);
4144 goto err_mgr_enable
;
4149 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4150 dsi_if_enable(dsidev
, false);
4151 dsi_vc_enable(dsidev
, channel
, false);
4154 dsi_display_uninit_dispc(dsidev
, mgr
);
4159 static void dsi_disable_video_output(struct omap_dss_device
*dssdev
, int channel
)
4161 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4162 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4163 struct omap_overlay_manager
*mgr
= dsi
->output
.manager
;
4165 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4166 dsi_if_enable(dsidev
, false);
4167 dsi_vc_enable(dsidev
, channel
, false);
4169 /* MODE, 0 = command mode */
4170 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 0, 4, 4);
4172 dsi_vc_enable(dsidev
, channel
, true);
4173 dsi_if_enable(dsidev
, true);
4176 dss_mgr_disable(mgr
);
4178 dsi_display_uninit_dispc(dsidev
, mgr
);
4181 static void dsi_update_screen_dispc(struct platform_device
*dsidev
)
4183 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4184 struct omap_overlay_manager
*mgr
= dsi
->output
.manager
;
4189 unsigned packet_payload
;
4190 unsigned packet_len
;
4193 const unsigned channel
= dsi
->update_channel
;
4194 const unsigned line_buf_size
= dsi
->line_buffer_size
;
4195 u16 w
= dsi
->timings
.x_res
;
4196 u16 h
= dsi
->timings
.y_res
;
4198 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w
, h
);
4200 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_VP
);
4202 bytespp
= dsi_get_pixel_size(dsi
->pix_fmt
) / 8;
4203 bytespl
= w
* bytespp
;
4204 bytespf
= bytespl
* h
;
4206 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4207 * number of lines in a packet. See errata about VP_CLK_RATIO */
4209 if (bytespf
< line_buf_size
)
4210 packet_payload
= bytespf
;
4212 packet_payload
= (line_buf_size
) / bytespl
* bytespl
;
4214 packet_len
= packet_payload
+ 1; /* 1 byte for DCS cmd */
4215 total_len
= (bytespf
/ packet_payload
) * packet_len
;
4217 if (bytespf
% packet_payload
)
4218 total_len
+= (bytespf
% packet_payload
) + 1;
4220 l
= FLD_VAL(total_len
, 23, 0); /* TE_SIZE */
4221 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4223 dsi_vc_write_long_header(dsidev
, channel
, MIPI_DSI_DCS_LONG_WRITE
,
4226 if (dsi
->te_enabled
)
4227 l
= FLD_MOD(l
, 1, 30, 30); /* TE_EN */
4229 l
= FLD_MOD(l
, 1, 31, 31); /* TE_START */
4230 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4232 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4233 * because DSS interrupts are not capable of waking up the CPU and the
4234 * framedone interrupt could be delayed for quite a long time. I think
4235 * the same goes for any DSS interrupts, but for some reason I have not
4236 * seen the problem anywhere else than here.
4238 dispc_disable_sidle();
4240 dsi_perf_mark_start(dsidev
);
4242 r
= schedule_delayed_work(&dsi
->framedone_timeout_work
,
4243 msecs_to_jiffies(250));
4246 dss_mgr_set_timings(mgr
, &dsi
->timings
);
4248 dss_mgr_start_update(mgr
);
4250 if (dsi
->te_enabled
) {
4251 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4252 * for TE is longer than the timer allows */
4253 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 0, 15, 15); /* LP_RX_TO */
4255 dsi_vc_send_bta(dsidev
, channel
);
4257 #ifdef DSI_CATCH_MISSING_TE
4258 mod_timer(&dsi
->te_timer
, jiffies
+ msecs_to_jiffies(250));
4263 #ifdef DSI_CATCH_MISSING_TE
4264 static void dsi_te_timeout(unsigned long arg
)
4266 DSSERR("TE not received for 250ms!\n");
4270 static void dsi_handle_framedone(struct platform_device
*dsidev
, int error
)
4272 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4274 /* SIDLEMODE back to smart-idle */
4275 dispc_enable_sidle();
4277 if (dsi
->te_enabled
) {
4278 /* enable LP_RX_TO again after the TE */
4279 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
4282 dsi
->framedone_callback(error
, dsi
->framedone_data
);
4285 dsi_perf_show(dsidev
, "DISPC");
4288 static void dsi_framedone_timeout_work_callback(struct work_struct
*work
)
4290 struct dsi_data
*dsi
= container_of(work
, struct dsi_data
,
4291 framedone_timeout_work
.work
);
4292 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4293 * 250ms which would conflict with this timeout work. What should be
4294 * done is first cancel the transfer on the HW, and then cancel the
4295 * possibly scheduled framedone work. However, cancelling the transfer
4296 * on the HW is buggy, and would probably require resetting the whole
4299 DSSERR("Framedone not received for 250ms!\n");
4301 dsi_handle_framedone(dsi
->pdev
, -ETIMEDOUT
);
4304 static void dsi_framedone_irq_callback(void *data
)
4306 struct platform_device
*dsidev
= (struct platform_device
*) data
;
4307 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4309 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4310 * turns itself off. However, DSI still has the pixels in its buffers,
4311 * and is sending the data.
4314 cancel_delayed_work(&dsi
->framedone_timeout_work
);
4316 dsi_handle_framedone(dsidev
, 0);
4319 static int dsi_update(struct omap_dss_device
*dssdev
, int channel
,
4320 void (*callback
)(int, void *), void *data
)
4322 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4323 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4326 dsi_perf_mark_setup(dsidev
);
4328 dsi
->update_channel
= channel
;
4330 dsi
->framedone_callback
= callback
;
4331 dsi
->framedone_data
= data
;
4333 dw
= dsi
->timings
.x_res
;
4334 dh
= dsi
->timings
.y_res
;
4336 #ifdef DSI_PERF_MEASURE
4337 dsi
->update_bytes
= dw
* dh
*
4338 dsi_get_pixel_size(dsi
->pix_fmt
) / 8;
4340 dsi_update_screen_dispc(dsidev
);
4347 static int dsi_configure_dispc_clocks(struct platform_device
*dsidev
)
4349 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4350 struct dispc_clock_info dispc_cinfo
;
4354 fck
= dsi_get_pll_hsdiv_dispc_rate(dsidev
);
4356 dispc_cinfo
.lck_div
= dsi
->user_dispc_cinfo
.lck_div
;
4357 dispc_cinfo
.pck_div
= dsi
->user_dispc_cinfo
.pck_div
;
4359 r
= dispc_calc_clock_rates(fck
, &dispc_cinfo
);
4361 DSSERR("Failed to calc dispc clocks\n");
4365 dsi
->mgr_config
.clock_info
= dispc_cinfo
;
4370 static int dsi_display_init_dispc(struct platform_device
*dsidev
,
4371 struct omap_overlay_manager
*mgr
)
4373 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4376 dss_select_lcd_clk_source(mgr
->id
, dsi
->module_id
== 0 ?
4377 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
4378 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
);
4380 if (dsi
->mode
== OMAP_DSS_DSI_CMD_MODE
) {
4381 r
= dss_mgr_register_framedone_handler(mgr
,
4382 dsi_framedone_irq_callback
, dsidev
);
4384 DSSERR("can't register FRAMEDONE handler\n");
4388 dsi
->mgr_config
.stallmode
= true;
4389 dsi
->mgr_config
.fifohandcheck
= true;
4391 dsi
->mgr_config
.stallmode
= false;
4392 dsi
->mgr_config
.fifohandcheck
= false;
4396 * override interlace, logic level and edge related parameters in
4397 * omap_video_timings with default values
4399 dsi
->timings
.interlace
= false;
4400 dsi
->timings
.hsync_level
= OMAPDSS_SIG_ACTIVE_HIGH
;
4401 dsi
->timings
.vsync_level
= OMAPDSS_SIG_ACTIVE_HIGH
;
4402 dsi
->timings
.data_pclk_edge
= OMAPDSS_DRIVE_SIG_RISING_EDGE
;
4403 dsi
->timings
.de_level
= OMAPDSS_SIG_ACTIVE_HIGH
;
4404 dsi
->timings
.sync_pclk_edge
= OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES
;
4406 dss_mgr_set_timings(mgr
, &dsi
->timings
);
4408 r
= dsi_configure_dispc_clocks(dsidev
);
4412 dsi
->mgr_config
.io_pad_mode
= DSS_IO_PAD_MODE_BYPASS
;
4413 dsi
->mgr_config
.video_port_width
=
4414 dsi_get_pixel_size(dsi
->pix_fmt
);
4415 dsi
->mgr_config
.lcden_sig_polarity
= 0;
4417 dss_mgr_set_lcd_config(mgr
, &dsi
->mgr_config
);
4421 if (dsi
->mode
== OMAP_DSS_DSI_CMD_MODE
)
4422 dss_mgr_unregister_framedone_handler(mgr
,
4423 dsi_framedone_irq_callback
, dsidev
);
4425 dss_select_lcd_clk_source(mgr
->id
, OMAP_DSS_CLK_SRC_FCK
);
4429 static void dsi_display_uninit_dispc(struct platform_device
*dsidev
,
4430 struct omap_overlay_manager
*mgr
)
4432 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4434 if (dsi
->mode
== OMAP_DSS_DSI_CMD_MODE
)
4435 dss_mgr_unregister_framedone_handler(mgr
,
4436 dsi_framedone_irq_callback
, dsidev
);
4438 dss_select_lcd_clk_source(mgr
->id
, OMAP_DSS_CLK_SRC_FCK
);
4441 static int dsi_configure_dsi_clocks(struct platform_device
*dsidev
)
4443 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4444 struct dsi_clock_info cinfo
;
4447 cinfo
= dsi
->user_dsi_cinfo
;
4449 r
= dsi_calc_clock_rates(dsidev
, &cinfo
);
4451 DSSERR("Failed to calc dsi clocks\n");
4455 r
= dsi_pll_set_clock_div(dsidev
, &cinfo
);
4457 DSSERR("Failed to set dsi clocks\n");
4464 static int dsi_display_init_dsi(struct platform_device
*dsidev
)
4466 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4469 r
= dsi_pll_init(dsidev
, true, true);
4473 r
= dsi_configure_dsi_clocks(dsidev
);
4477 dss_select_dsi_clk_source(dsi
->module_id
, dsi
->module_id
== 0 ?
4478 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
:
4479 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
);
4483 r
= dsi_cio_init(dsidev
);
4487 _dsi_print_reset_status(dsidev
);
4489 dsi_proto_timings(dsidev
);
4490 dsi_set_lp_clk_divisor(dsidev
);
4493 _dsi_print_reset_status(dsidev
);
4495 r
= dsi_proto_config(dsidev
);
4499 /* enable interface */
4500 dsi_vc_enable(dsidev
, 0, 1);
4501 dsi_vc_enable(dsidev
, 1, 1);
4502 dsi_vc_enable(dsidev
, 2, 1);
4503 dsi_vc_enable(dsidev
, 3, 1);
4504 dsi_if_enable(dsidev
, 1);
4505 dsi_force_tx_stop_mode_io(dsidev
);
4509 dsi_cio_uninit(dsidev
);
4511 dss_select_dsi_clk_source(dsi
->module_id
, OMAP_DSS_CLK_SRC_FCK
);
4513 dsi_pll_uninit(dsidev
, true);
4518 static void dsi_display_uninit_dsi(struct platform_device
*dsidev
,
4519 bool disconnect_lanes
, bool enter_ulps
)
4521 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4523 if (enter_ulps
&& !dsi
->ulps_enabled
)
4524 dsi_enter_ulps(dsidev
);
4526 /* disable interface */
4527 dsi_if_enable(dsidev
, 0);
4528 dsi_vc_enable(dsidev
, 0, 0);
4529 dsi_vc_enable(dsidev
, 1, 0);
4530 dsi_vc_enable(dsidev
, 2, 0);
4531 dsi_vc_enable(dsidev
, 3, 0);
4533 dss_select_dsi_clk_source(dsi
->module_id
, OMAP_DSS_CLK_SRC_FCK
);
4534 dsi_cio_uninit(dsidev
);
4535 dsi_pll_uninit(dsidev
, disconnect_lanes
);
4538 static int dsi_display_enable(struct omap_dss_device
*dssdev
)
4540 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4541 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4544 DSSDBG("dsi_display_enable\n");
4546 WARN_ON(!dsi_bus_is_locked(dsidev
));
4548 mutex_lock(&dsi
->lock
);
4550 r
= dsi_runtime_get(dsidev
);
4554 dsi_enable_pll_clock(dsidev
, 1);
4556 _dsi_initialize_irq(dsidev
);
4558 r
= dsi_display_init_dsi(dsidev
);
4562 mutex_unlock(&dsi
->lock
);
4567 dsi_enable_pll_clock(dsidev
, 0);
4568 dsi_runtime_put(dsidev
);
4570 mutex_unlock(&dsi
->lock
);
4571 DSSDBG("dsi_display_enable FAILED\n");
4575 static void dsi_display_disable(struct omap_dss_device
*dssdev
,
4576 bool disconnect_lanes
, bool enter_ulps
)
4578 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4579 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4581 DSSDBG("dsi_display_disable\n");
4583 WARN_ON(!dsi_bus_is_locked(dsidev
));
4585 mutex_lock(&dsi
->lock
);
4587 dsi_sync_vc(dsidev
, 0);
4588 dsi_sync_vc(dsidev
, 1);
4589 dsi_sync_vc(dsidev
, 2);
4590 dsi_sync_vc(dsidev
, 3);
4592 dsi_display_uninit_dsi(dsidev
, disconnect_lanes
, enter_ulps
);
4594 dsi_runtime_put(dsidev
);
4595 dsi_enable_pll_clock(dsidev
, 0);
4597 mutex_unlock(&dsi
->lock
);
4600 static int dsi_enable_te(struct omap_dss_device
*dssdev
, bool enable
)
4602 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4603 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4605 dsi
->te_enabled
= enable
;
4609 #ifdef PRINT_VERBOSE_VM_TIMINGS
4610 static void print_dsi_vm(const char *str
,
4611 const struct omap_dss_dsi_videomode_timings
*t
)
4613 unsigned long byteclk
= t
->hsclk
/ 4;
4614 int bl
, wc
, pps
, tot
;
4616 wc
= DIV_ROUND_UP(t
->hact
* t
->bitspp
, 8);
4617 pps
= DIV_ROUND_UP(wc
+ 6, t
->ndl
); /* pixel packet size */
4618 bl
= t
->hss
+ t
->hsa
+ t
->hse
+ t
->hbp
+ t
->hfp
;
4621 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4623 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4624 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4627 t
->hss
, t
->hsa
, t
->hse
, t
->hbp
, pps
, t
->hfp
,
4643 static void print_dispc_vm(const char *str
, const struct omap_video_timings
*t
)
4645 unsigned long pck
= t
->pixelclock
;
4649 bl
= t
->hsw
+ t
->hbp
+ t
->hfp
;
4652 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4654 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4655 "%u/%u/%u/%u = %u + %u = %u\n",
4658 t
->hsw
, t
->hbp
, hact
, t
->hfp
,
4670 /* note: this is not quite accurate */
4671 static void print_dsi_dispc_vm(const char *str
,
4672 const struct omap_dss_dsi_videomode_timings
*t
)
4674 struct omap_video_timings vm
= { 0 };
4675 unsigned long byteclk
= t
->hsclk
/ 4;
4678 int dsi_hact
, dsi_htot
;
4680 dsi_tput
= (u64
)byteclk
* t
->ndl
* 8;
4681 pck
= (u32
)div64_u64(dsi_tput
, t
->bitspp
);
4682 dsi_hact
= DIV_ROUND_UP(DIV_ROUND_UP(t
->hact
* t
->bitspp
, 8) + 6, t
->ndl
);
4683 dsi_htot
= t
->hss
+ t
->hsa
+ t
->hse
+ t
->hbp
+ dsi_hact
+ t
->hfp
;
4685 vm
.pixelclock
= pck
;
4686 vm
.hsw
= div64_u64((u64
)(t
->hsa
+ t
->hse
) * pck
, byteclk
);
4687 vm
.hbp
= div64_u64((u64
)t
->hbp
* pck
, byteclk
);
4688 vm
.hfp
= div64_u64((u64
)t
->hfp
* pck
, byteclk
);
4691 print_dispc_vm(str
, &vm
);
4693 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4695 static bool dsi_cm_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
4696 unsigned long pck
, void *data
)
4698 struct dsi_clk_calc_ctx
*ctx
= data
;
4699 struct omap_video_timings
*t
= &ctx
->dispc_vm
;
4701 ctx
->dispc_cinfo
.lck_div
= lckd
;
4702 ctx
->dispc_cinfo
.pck_div
= pckd
;
4703 ctx
->dispc_cinfo
.lck
= lck
;
4704 ctx
->dispc_cinfo
.pck
= pck
;
4706 *t
= *ctx
->config
->timings
;
4707 t
->pixelclock
= pck
;
4708 t
->x_res
= ctx
->config
->timings
->x_res
;
4709 t
->y_res
= ctx
->config
->timings
->y_res
;
4710 t
->hsw
= t
->hfp
= t
->hbp
= t
->vsw
= 1;
4711 t
->vfp
= t
->vbp
= 0;
4716 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc
, unsigned long dispc
,
4719 struct dsi_clk_calc_ctx
*ctx
= data
;
4721 ctx
->dsi_cinfo
.regm_dispc
= regm_dispc
;
4722 ctx
->dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
= dispc
;
4724 return dispc_div_calc(dispc
, ctx
->req_pck_min
, ctx
->req_pck_max
,
4725 dsi_cm_calc_dispc_cb
, ctx
);
4728 static bool dsi_cm_calc_pll_cb(int regn
, int regm
, unsigned long fint
,
4729 unsigned long pll
, void *data
)
4731 struct dsi_clk_calc_ctx
*ctx
= data
;
4733 ctx
->dsi_cinfo
.regn
= regn
;
4734 ctx
->dsi_cinfo
.regm
= regm
;
4735 ctx
->dsi_cinfo
.fint
= fint
;
4736 ctx
->dsi_cinfo
.clkin4ddr
= pll
;
4738 return dsi_hsdiv_calc(ctx
->dsidev
, pll
, ctx
->req_pck_min
,
4739 dsi_cm_calc_hsdiv_cb
, ctx
);
4742 static bool dsi_cm_calc(struct dsi_data
*dsi
,
4743 const struct omap_dss_dsi_config
*cfg
,
4744 struct dsi_clk_calc_ctx
*ctx
)
4746 unsigned long clkin
;
4748 unsigned long pll_min
, pll_max
;
4749 unsigned long pck
, txbyteclk
;
4751 clkin
= clk_get_rate(dsi
->sys_clk
);
4752 bitspp
= dsi_get_pixel_size(cfg
->pixel_format
);
4753 ndl
= dsi
->num_lanes_used
- 1;
4756 * Here we should calculate minimum txbyteclk to be able to send the
4757 * frame in time, and also to handle TE. That's not very simple, though,
4758 * especially as we go to LP between each pixel packet due to HW
4759 * "feature". So let's just estimate very roughly and multiply by 1.5.
4761 pck
= cfg
->timings
->pixelclock
;
4763 txbyteclk
= pck
* bitspp
/ 8 / ndl
;
4765 memset(ctx
, 0, sizeof(*ctx
));
4766 ctx
->dsidev
= dsi
->pdev
;
4768 ctx
->req_pck_min
= pck
;
4769 ctx
->req_pck_nom
= pck
;
4770 ctx
->req_pck_max
= pck
* 3 / 2;
4771 ctx
->dsi_cinfo
.clkin
= clkin
;
4773 pll_min
= max(cfg
->hs_clk_min
* 4, txbyteclk
* 4 * 4);
4774 pll_max
= cfg
->hs_clk_max
* 4;
4776 return dsi_pll_calc(dsi
->pdev
, clkin
,
4778 dsi_cm_calc_pll_cb
, ctx
);
4781 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx
*ctx
)
4783 struct dsi_data
*dsi
= dsi_get_dsidrv_data(ctx
->dsidev
);
4784 const struct omap_dss_dsi_config
*cfg
= ctx
->config
;
4785 int bitspp
= dsi_get_pixel_size(cfg
->pixel_format
);
4786 int ndl
= dsi
->num_lanes_used
- 1;
4787 unsigned long hsclk
= ctx
->dsi_cinfo
.clkin4ddr
/ 4;
4788 unsigned long byteclk
= hsclk
/ 4;
4790 unsigned long dispc_pck
, req_pck_min
, req_pck_nom
, req_pck_max
;
4792 int panel_htot
, panel_hbl
; /* pixels */
4793 int dispc_htot
, dispc_hbl
; /* pixels */
4794 int dsi_htot
, dsi_hact
, dsi_hbl
, hss
, hse
; /* byteclks */
4796 const struct omap_video_timings
*req_vm
;
4797 struct omap_video_timings
*dispc_vm
;
4798 struct omap_dss_dsi_videomode_timings
*dsi_vm
;
4799 u64 dsi_tput
, dispc_tput
;
4801 dsi_tput
= (u64
)byteclk
* ndl
* 8;
4803 req_vm
= cfg
->timings
;
4804 req_pck_min
= ctx
->req_pck_min
;
4805 req_pck_max
= ctx
->req_pck_max
;
4806 req_pck_nom
= ctx
->req_pck_nom
;
4808 dispc_pck
= ctx
->dispc_cinfo
.pck
;
4809 dispc_tput
= (u64
)dispc_pck
* bitspp
;
4811 xres
= req_vm
->x_res
;
4813 panel_hbl
= req_vm
->hfp
+ req_vm
->hbp
+ req_vm
->hsw
;
4814 panel_htot
= xres
+ panel_hbl
;
4816 dsi_hact
= DIV_ROUND_UP(DIV_ROUND_UP(xres
* bitspp
, 8) + 6, ndl
);
4819 * When there are no line buffers, DISPC and DSI must have the
4820 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4822 if (dsi
->line_buffer_size
< xres
* bitspp
/ 8) {
4823 if (dispc_tput
!= dsi_tput
)
4826 if (dispc_tput
< dsi_tput
)
4830 /* DSI tput must be over the min requirement */
4831 if (dsi_tput
< (u64
)bitspp
* req_pck_min
)
4834 /* When non-burst mode, DSI tput must be below max requirement. */
4835 if (cfg
->trans_mode
!= OMAP_DSS_DSI_BURST_MODE
) {
4836 if (dsi_tput
> (u64
)bitspp
* req_pck_max
)
4840 hss
= DIV_ROUND_UP(4, ndl
);
4842 if (cfg
->trans_mode
== OMAP_DSS_DSI_PULSE_MODE
) {
4843 if (ndl
== 3 && req_vm
->hsw
== 0)
4846 hse
= DIV_ROUND_UP(4, ndl
);
4851 /* DSI htot to match the panel's nominal pck */
4852 dsi_htot
= div64_u64((u64
)panel_htot
* byteclk
, req_pck_nom
);
4854 /* fail if there would be no time for blanking */
4855 if (dsi_htot
< hss
+ hse
+ dsi_hact
)
4858 /* total DSI blanking needed to achieve panel's TL */
4859 dsi_hbl
= dsi_htot
- dsi_hact
;
4861 /* DISPC htot to match the DSI TL */
4862 dispc_htot
= div64_u64((u64
)dsi_htot
* dispc_pck
, byteclk
);
4864 /* verify that the DSI and DISPC TLs are the same */
4865 if ((u64
)dsi_htot
* dispc_pck
!= (u64
)dispc_htot
* byteclk
)
4868 dispc_hbl
= dispc_htot
- xres
;
4870 /* setup DSI videomode */
4872 dsi_vm
= &ctx
->dsi_vm
;
4873 memset(dsi_vm
, 0, sizeof(*dsi_vm
));
4875 dsi_vm
->hsclk
= hsclk
;
4878 dsi_vm
->bitspp
= bitspp
;
4880 if (cfg
->trans_mode
!= OMAP_DSS_DSI_PULSE_MODE
) {
4882 } else if (ndl
== 3 && req_vm
->hsw
== 0) {
4885 hsa
= div64_u64((u64
)req_vm
->hsw
* byteclk
, req_pck_nom
);
4886 hsa
= max(hsa
- hse
, 1);
4889 hbp
= div64_u64((u64
)req_vm
->hbp
* byteclk
, req_pck_nom
);
4892 hfp
= dsi_hbl
- (hss
+ hsa
+ hse
+ hbp
);
4895 /* we need to take cycles from hbp */
4898 hbp
= max(hbp
- t
, 1);
4899 hfp
= dsi_hbl
- (hss
+ hsa
+ hse
+ hbp
);
4901 if (hfp
< 1 && hsa
> 0) {
4902 /* we need to take cycles from hsa */
4904 hsa
= max(hsa
- t
, 1);
4905 hfp
= dsi_hbl
- (hss
+ hsa
+ hse
+ hbp
);
4916 dsi_vm
->hact
= xres
;
4919 dsi_vm
->vsa
= req_vm
->vsw
;
4920 dsi_vm
->vbp
= req_vm
->vbp
;
4921 dsi_vm
->vact
= req_vm
->y_res
;
4922 dsi_vm
->vfp
= req_vm
->vfp
;
4924 dsi_vm
->trans_mode
= cfg
->trans_mode
;
4926 dsi_vm
->blanking_mode
= 0;
4927 dsi_vm
->hsa_blanking_mode
= 1;
4928 dsi_vm
->hfp_blanking_mode
= 1;
4929 dsi_vm
->hbp_blanking_mode
= 1;
4931 dsi_vm
->ddr_clk_always_on
= cfg
->ddr_clk_always_on
;
4932 dsi_vm
->window_sync
= 4;
4934 /* setup DISPC videomode */
4936 dispc_vm
= &ctx
->dispc_vm
;
4937 *dispc_vm
= *req_vm
;
4938 dispc_vm
->pixelclock
= dispc_pck
;
4940 if (cfg
->trans_mode
== OMAP_DSS_DSI_PULSE_MODE
) {
4941 hsa
= div64_u64((u64
)req_vm
->hsw
* dispc_pck
,
4948 hbp
= div64_u64((u64
)req_vm
->hbp
* dispc_pck
, req_pck_nom
);
4951 hfp
= dispc_hbl
- hsa
- hbp
;
4954 /* we need to take cycles from hbp */
4957 hbp
= max(hbp
- t
, 1);
4958 hfp
= dispc_hbl
- hsa
- hbp
;
4961 /* we need to take cycles from hsa */
4963 hsa
= max(hsa
- t
, 1);
4964 hfp
= dispc_hbl
- hsa
- hbp
;
4971 dispc_vm
->hfp
= hfp
;
4972 dispc_vm
->hsw
= hsa
;
4973 dispc_vm
->hbp
= hbp
;
4979 static bool dsi_vm_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
4980 unsigned long pck
, void *data
)
4982 struct dsi_clk_calc_ctx
*ctx
= data
;
4984 ctx
->dispc_cinfo
.lck_div
= lckd
;
4985 ctx
->dispc_cinfo
.pck_div
= pckd
;
4986 ctx
->dispc_cinfo
.lck
= lck
;
4987 ctx
->dispc_cinfo
.pck
= pck
;
4989 if (dsi_vm_calc_blanking(ctx
) == false)
4992 #ifdef PRINT_VERBOSE_VM_TIMINGS
4993 print_dispc_vm("dispc", &ctx
->dispc_vm
);
4994 print_dsi_vm("dsi ", &ctx
->dsi_vm
);
4995 print_dispc_vm("req ", ctx
->config
->timings
);
4996 print_dsi_dispc_vm("act ", &ctx
->dsi_vm
);
5002 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc
, unsigned long dispc
,
5005 struct dsi_clk_calc_ctx
*ctx
= data
;
5006 unsigned long pck_max
;
5008 ctx
->dsi_cinfo
.regm_dispc
= regm_dispc
;
5009 ctx
->dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
= dispc
;
5012 * In burst mode we can let the dispc pck be arbitrarily high, but it
5013 * limits our scaling abilities. So for now, don't aim too high.
5016 if (ctx
->config
->trans_mode
== OMAP_DSS_DSI_BURST_MODE
)
5017 pck_max
= ctx
->req_pck_max
+ 10000000;
5019 pck_max
= ctx
->req_pck_max
;
5021 return dispc_div_calc(dispc
, ctx
->req_pck_min
, pck_max
,
5022 dsi_vm_calc_dispc_cb
, ctx
);
5025 static bool dsi_vm_calc_pll_cb(int regn
, int regm
, unsigned long fint
,
5026 unsigned long pll
, void *data
)
5028 struct dsi_clk_calc_ctx
*ctx
= data
;
5030 ctx
->dsi_cinfo
.regn
= regn
;
5031 ctx
->dsi_cinfo
.regm
= regm
;
5032 ctx
->dsi_cinfo
.fint
= fint
;
5033 ctx
->dsi_cinfo
.clkin4ddr
= pll
;
5035 return dsi_hsdiv_calc(ctx
->dsidev
, pll
, ctx
->req_pck_min
,
5036 dsi_vm_calc_hsdiv_cb
, ctx
);
5039 static bool dsi_vm_calc(struct dsi_data
*dsi
,
5040 const struct omap_dss_dsi_config
*cfg
,
5041 struct dsi_clk_calc_ctx
*ctx
)
5043 const struct omap_video_timings
*t
= cfg
->timings
;
5044 unsigned long clkin
;
5045 unsigned long pll_min
;
5046 unsigned long pll_max
;
5047 int ndl
= dsi
->num_lanes_used
- 1;
5048 int bitspp
= dsi_get_pixel_size(cfg
->pixel_format
);
5049 unsigned long byteclk_min
;
5051 clkin
= clk_get_rate(dsi
->sys_clk
);
5053 memset(ctx
, 0, sizeof(*ctx
));
5054 ctx
->dsidev
= dsi
->pdev
;
5057 ctx
->dsi_cinfo
.clkin
= clkin
;
5059 /* these limits should come from the panel driver */
5060 ctx
->req_pck_min
= t
->pixelclock
- 1000;
5061 ctx
->req_pck_nom
= t
->pixelclock
;
5062 ctx
->req_pck_max
= t
->pixelclock
+ 1000;
5064 byteclk_min
= div64_u64((u64
)ctx
->req_pck_min
* bitspp
, ndl
* 8);
5065 pll_min
= max(cfg
->hs_clk_min
* 4, byteclk_min
* 4 * 4);
5067 if (cfg
->trans_mode
== OMAP_DSS_DSI_BURST_MODE
) {
5068 pll_max
= cfg
->hs_clk_max
* 4;
5070 unsigned long byteclk_max
;
5071 byteclk_max
= div64_u64((u64
)ctx
->req_pck_max
* bitspp
,
5074 pll_max
= byteclk_max
* 4 * 4;
5077 return dsi_pll_calc(dsi
->pdev
, clkin
,
5079 dsi_vm_calc_pll_cb
, ctx
);
5082 static int dsi_set_config(struct omap_dss_device
*dssdev
,
5083 const struct omap_dss_dsi_config
*config
)
5085 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5086 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5087 struct dsi_clk_calc_ctx ctx
;
5091 mutex_lock(&dsi
->lock
);
5093 dsi
->pix_fmt
= config
->pixel_format
;
5094 dsi
->mode
= config
->mode
;
5096 if (config
->mode
== OMAP_DSS_DSI_VIDEO_MODE
)
5097 ok
= dsi_vm_calc(dsi
, config
, &ctx
);
5099 ok
= dsi_cm_calc(dsi
, config
, &ctx
);
5102 DSSERR("failed to find suitable DSI clock settings\n");
5107 dsi_pll_calc_dsi_fck(&ctx
.dsi_cinfo
);
5109 r
= dsi_lp_clock_calc(&ctx
.dsi_cinfo
, config
->lp_clk_min
,
5110 config
->lp_clk_max
);
5112 DSSERR("failed to find suitable DSI LP clock settings\n");
5116 dsi
->user_dsi_cinfo
= ctx
.dsi_cinfo
;
5117 dsi
->user_dispc_cinfo
= ctx
.dispc_cinfo
;
5119 dsi
->timings
= ctx
.dispc_vm
;
5120 dsi
->vm_timings
= ctx
.dsi_vm
;
5122 mutex_unlock(&dsi
->lock
);
5126 mutex_unlock(&dsi
->lock
);
5132 * Return a hardcoded channel for the DSI output. This should work for
5133 * current use cases, but this can be later expanded to either resolve
5134 * the channel in some more dynamic manner, or get the channel as a user
5137 static enum omap_channel
dsi_get_channel(int module_id
)
5139 switch (omapdss_get_version()) {
5140 case OMAPDSS_VER_OMAP24xx
:
5141 case OMAPDSS_VER_AM43xx
:
5142 DSSWARN("DSI not supported\n");
5143 return OMAP_DSS_CHANNEL_LCD
;
5145 case OMAPDSS_VER_OMAP34xx_ES1
:
5146 case OMAPDSS_VER_OMAP34xx_ES3
:
5147 case OMAPDSS_VER_OMAP3630
:
5148 case OMAPDSS_VER_AM35xx
:
5149 return OMAP_DSS_CHANNEL_LCD
;
5151 case OMAPDSS_VER_OMAP4430_ES1
:
5152 case OMAPDSS_VER_OMAP4430_ES2
:
5153 case OMAPDSS_VER_OMAP4
:
5154 switch (module_id
) {
5156 return OMAP_DSS_CHANNEL_LCD
;
5158 return OMAP_DSS_CHANNEL_LCD2
;
5160 DSSWARN("unsupported module id\n");
5161 return OMAP_DSS_CHANNEL_LCD
;
5164 case OMAPDSS_VER_OMAP5
:
5165 switch (module_id
) {
5167 return OMAP_DSS_CHANNEL_LCD
;
5169 return OMAP_DSS_CHANNEL_LCD3
;
5171 DSSWARN("unsupported module id\n");
5172 return OMAP_DSS_CHANNEL_LCD
;
5176 DSSWARN("unsupported DSS version\n");
5177 return OMAP_DSS_CHANNEL_LCD
;
5181 static int dsi_request_vc(struct omap_dss_device
*dssdev
, int *channel
)
5183 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5184 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5187 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
5188 if (!dsi
->vc
[i
].dssdev
) {
5189 dsi
->vc
[i
].dssdev
= dssdev
;
5195 DSSERR("cannot get VC for display %s", dssdev
->name
);
5199 static int dsi_set_vc_id(struct omap_dss_device
*dssdev
, int channel
, int vc_id
)
5201 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5202 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5204 if (vc_id
< 0 || vc_id
> 3) {
5205 DSSERR("VC ID out of range\n");
5209 if (channel
< 0 || channel
> 3) {
5210 DSSERR("Virtual Channel out of range\n");
5214 if (dsi
->vc
[channel
].dssdev
!= dssdev
) {
5215 DSSERR("Virtual Channel not allocated to display %s\n",
5220 dsi
->vc
[channel
].vc_id
= vc_id
;
5225 static void dsi_release_vc(struct omap_dss_device
*dssdev
, int channel
)
5227 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5228 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5230 if ((channel
>= 0 && channel
<= 3) &&
5231 dsi
->vc
[channel
].dssdev
== dssdev
) {
5232 dsi
->vc
[channel
].dssdev
= NULL
;
5233 dsi
->vc
[channel
].vc_id
= 0;
5237 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device
*dsidev
)
5239 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 7, 1) != 1)
5240 DSSERR("%s (%s) not active\n",
5241 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
5242 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
));
5245 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device
*dsidev
)
5247 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 8, 1) != 1)
5248 DSSERR("%s (%s) not active\n",
5249 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
5250 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
));
5253 static void dsi_calc_clock_param_ranges(struct platform_device
*dsidev
)
5255 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5257 dsi
->regn_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN
);
5258 dsi
->regm_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM
);
5259 dsi
->regm_dispc_max
=
5260 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC
);
5261 dsi
->regm_dsi_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI
);
5262 dsi
->fint_min
= dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT
);
5263 dsi
->fint_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT
);
5264 dsi
->lpdiv_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV
);
5267 static int dsi_get_clocks(struct platform_device
*dsidev
)
5269 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5272 clk
= devm_clk_get(&dsidev
->dev
, "fck");
5274 DSSERR("can't get fck\n");
5275 return PTR_ERR(clk
);
5280 clk
= devm_clk_get(&dsidev
->dev
, "sys_clk");
5282 DSSERR("can't get sys_clk\n");
5283 return PTR_ERR(clk
);
5291 static int dsi_connect(struct omap_dss_device
*dssdev
,
5292 struct omap_dss_device
*dst
)
5294 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5295 struct omap_overlay_manager
*mgr
;
5298 r
= dsi_regulator_init(dsidev
);
5302 mgr
= omap_dss_get_overlay_manager(dssdev
->dispc_channel
);
5306 r
= dss_mgr_connect(mgr
, dssdev
);
5310 r
= omapdss_output_set_device(dssdev
, dst
);
5312 DSSERR("failed to connect output to new device: %s\n",
5314 dss_mgr_disconnect(mgr
, dssdev
);
5321 static void dsi_disconnect(struct omap_dss_device
*dssdev
,
5322 struct omap_dss_device
*dst
)
5324 WARN_ON(dst
!= dssdev
->dst
);
5326 if (dst
!= dssdev
->dst
)
5329 omapdss_output_unset_device(dssdev
);
5331 if (dssdev
->manager
)
5332 dss_mgr_disconnect(dssdev
->manager
, dssdev
);
5335 static const struct omapdss_dsi_ops dsi_ops
= {
5336 .connect
= dsi_connect
,
5337 .disconnect
= dsi_disconnect
,
5339 .bus_lock
= dsi_bus_lock
,
5340 .bus_unlock
= dsi_bus_unlock
,
5342 .enable
= dsi_display_enable
,
5343 .disable
= dsi_display_disable
,
5345 .enable_hs
= dsi_vc_enable_hs
,
5347 .configure_pins
= dsi_configure_pins
,
5348 .set_config
= dsi_set_config
,
5350 .enable_video_output
= dsi_enable_video_output
,
5351 .disable_video_output
= dsi_disable_video_output
,
5353 .update
= dsi_update
,
5355 .enable_te
= dsi_enable_te
,
5357 .request_vc
= dsi_request_vc
,
5358 .set_vc_id
= dsi_set_vc_id
,
5359 .release_vc
= dsi_release_vc
,
5361 .dcs_write
= dsi_vc_dcs_write
,
5362 .dcs_write_nosync
= dsi_vc_dcs_write_nosync
,
5363 .dcs_read
= dsi_vc_dcs_read
,
5365 .gen_write
= dsi_vc_generic_write
,
5366 .gen_write_nosync
= dsi_vc_generic_write_nosync
,
5367 .gen_read
= dsi_vc_generic_read
,
5369 .bta_sync
= dsi_vc_send_bta_sync
,
5371 .set_max_rx_packet_size
= dsi_vc_set_max_rx_packet_size
,
5374 static void dsi_init_output(struct platform_device
*dsidev
)
5376 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5377 struct omap_dss_device
*out
= &dsi
->output
;
5379 out
->dev
= &dsidev
->dev
;
5380 out
->id
= dsi
->module_id
== 0 ?
5381 OMAP_DSS_OUTPUT_DSI1
: OMAP_DSS_OUTPUT_DSI2
;
5383 out
->output_type
= OMAP_DISPLAY_TYPE_DSI
;
5384 out
->name
= dsi
->module_id
== 0 ? "dsi.0" : "dsi.1";
5385 out
->dispc_channel
= dsi_get_channel(dsi
->module_id
);
5386 out
->ops
.dsi
= &dsi_ops
;
5387 out
->owner
= THIS_MODULE
;
5389 omapdss_register_output(out
);
5392 static void dsi_uninit_output(struct platform_device
*dsidev
)
5394 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5395 struct omap_dss_device
*out
= &dsi
->output
;
5397 omapdss_unregister_output(out
);
5400 static int dsi_probe_of(struct platform_device
*pdev
)
5402 struct device_node
*node
= pdev
->dev
.of_node
;
5403 struct dsi_data
*dsi
= dsi_get_dsidrv_data(pdev
);
5404 struct property
*prop
;
5408 struct device_node
*ep
;
5409 struct omap_dsi_pin_config pin_cfg
;
5411 ep
= omapdss_of_get_first_endpoint(node
);
5415 prop
= of_find_property(ep
, "lanes", &len
);
5417 dev_err(&pdev
->dev
, "failed to find lane data\n");
5422 num_pins
= len
/ sizeof(u32
);
5424 if (num_pins
< 4 || num_pins
% 2 != 0 ||
5425 num_pins
> dsi
->num_lanes_supported
* 2) {
5426 dev_err(&pdev
->dev
, "bad number of lanes\n");
5431 r
= of_property_read_u32_array(ep
, "lanes", lane_arr
, num_pins
);
5433 dev_err(&pdev
->dev
, "failed to read lane data\n");
5437 pin_cfg
.num_pins
= num_pins
;
5438 for (i
= 0; i
< num_pins
; ++i
)
5439 pin_cfg
.pins
[i
] = (int)lane_arr
[i
];
5441 r
= dsi_configure_pins(&dsi
->output
, &pin_cfg
);
5443 dev_err(&pdev
->dev
, "failed to configure pins");
5456 /* DSI1 HW IP initialisation */
5457 static int omap_dsihw_probe(struct platform_device
*dsidev
)
5461 struct dsi_data
*dsi
;
5462 struct resource
*dsi_mem
;
5463 struct resource
*res
;
5464 struct resource temp_res
;
5466 dsi
= devm_kzalloc(&dsidev
->dev
, sizeof(*dsi
), GFP_KERNEL
);
5471 dev_set_drvdata(&dsidev
->dev
, dsi
);
5473 spin_lock_init(&dsi
->irq_lock
);
5474 spin_lock_init(&dsi
->errors_lock
);
5477 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5478 spin_lock_init(&dsi
->irq_stats_lock
);
5479 dsi
->irq_stats
.last_reset
= jiffies
;
5482 mutex_init(&dsi
->lock
);
5483 sema_init(&dsi
->bus_lock
, 1);
5485 INIT_DEFERRABLE_WORK(&dsi
->framedone_timeout_work
,
5486 dsi_framedone_timeout_work_callback
);
5488 #ifdef DSI_CATCH_MISSING_TE
5489 init_timer(&dsi
->te_timer
);
5490 dsi
->te_timer
.function
= dsi_te_timeout
;
5491 dsi
->te_timer
.data
= 0;
5494 res
= platform_get_resource_byname(dsidev
, IORESOURCE_MEM
, "proto");
5496 res
= platform_get_resource(dsidev
, IORESOURCE_MEM
, 0);
5498 DSSERR("can't get IORESOURCE_MEM DSI\n");
5502 temp_res
.start
= res
->start
;
5503 temp_res
.end
= temp_res
.start
+ DSI_PROTO_SZ
- 1;
5509 dsi
->proto_base
= devm_ioremap(&dsidev
->dev
, res
->start
,
5510 resource_size(res
));
5511 if (!dsi
->proto_base
) {
5512 DSSERR("can't ioremap DSI protocol engine\n");
5516 res
= platform_get_resource_byname(dsidev
, IORESOURCE_MEM
, "phy");
5518 res
= platform_get_resource(dsidev
, IORESOURCE_MEM
, 0);
5520 DSSERR("can't get IORESOURCE_MEM DSI\n");
5524 temp_res
.start
= res
->start
+ DSI_PHY_OFFSET
;
5525 temp_res
.end
= temp_res
.start
+ DSI_PHY_SZ
- 1;
5529 dsi
->phy_base
= devm_ioremap(&dsidev
->dev
, res
->start
,
5530 resource_size(res
));
5531 if (!dsi
->proto_base
) {
5532 DSSERR("can't ioremap DSI PHY\n");
5536 res
= platform_get_resource_byname(dsidev
, IORESOURCE_MEM
, "pll");
5538 res
= platform_get_resource(dsidev
, IORESOURCE_MEM
, 0);
5540 DSSERR("can't get IORESOURCE_MEM DSI\n");
5544 temp_res
.start
= res
->start
+ DSI_PLL_OFFSET
;
5545 temp_res
.end
= temp_res
.start
+ DSI_PLL_SZ
- 1;
5549 dsi
->pll_base
= devm_ioremap(&dsidev
->dev
, res
->start
,
5550 resource_size(res
));
5551 if (!dsi
->proto_base
) {
5552 DSSERR("can't ioremap DSI PLL\n");
5556 dsi
->irq
= platform_get_irq(dsi
->pdev
, 0);
5558 DSSERR("platform_get_irq failed\n");
5562 r
= devm_request_irq(&dsidev
->dev
, dsi
->irq
, omap_dsi_irq_handler
,
5563 IRQF_SHARED
, dev_name(&dsidev
->dev
), dsi
->pdev
);
5565 DSSERR("request_irq failed\n");
5569 if (dsidev
->dev
.of_node
) {
5570 const struct of_device_id
*match
;
5571 const struct dsi_module_id_data
*d
;
5573 match
= of_match_node(dsi_of_match
, dsidev
->dev
.of_node
);
5575 DSSERR("unsupported DSI module\n");
5581 while (d
->address
!= 0 && d
->address
!= dsi_mem
->start
)
5584 if (d
->address
== 0) {
5585 DSSERR("unsupported DSI module\n");
5589 dsi
->module_id
= d
->id
;
5591 dsi
->module_id
= dsidev
->id
;
5594 /* DSI VCs initialization */
5595 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
5596 dsi
->vc
[i
].source
= DSI_VC_SOURCE_L4
;
5597 dsi
->vc
[i
].dssdev
= NULL
;
5598 dsi
->vc
[i
].vc_id
= 0;
5601 dsi_calc_clock_param_ranges(dsidev
);
5603 r
= dsi_get_clocks(dsidev
);
5607 pm_runtime_enable(&dsidev
->dev
);
5609 r
= dsi_runtime_get(dsidev
);
5611 goto err_runtime_get
;
5613 rev
= dsi_read_reg(dsidev
, DSI_REVISION
);
5614 dev_dbg(&dsidev
->dev
, "OMAP DSI rev %d.%d\n",
5615 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
5617 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5618 * of data to 3 by default */
5619 if (dss_has_feature(FEAT_DSI_GNQ
))
5621 dsi
->num_lanes_supported
= 1 + REG_GET(dsidev
, DSI_GNQ
, 11, 9);
5623 dsi
->num_lanes_supported
= 3;
5625 dsi
->line_buffer_size
= dsi_get_line_buf_size(dsidev
);
5627 dsi_init_output(dsidev
);
5629 if (dsidev
->dev
.of_node
) {
5630 r
= dsi_probe_of(dsidev
);
5632 DSSERR("Invalid DSI DT data\n");
5636 r
= of_platform_populate(dsidev
->dev
.of_node
, NULL
, NULL
,
5639 DSSERR("Failed to populate DSI child devices: %d\n", r
);
5642 dsi_runtime_put(dsidev
);
5644 if (dsi
->module_id
== 0)
5645 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs
);
5646 else if (dsi
->module_id
== 1)
5647 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs
);
5649 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5650 if (dsi
->module_id
== 0)
5651 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs
);
5652 else if (dsi
->module_id
== 1)
5653 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs
);
5659 dsi_uninit_output(dsidev
);
5660 dsi_runtime_put(dsidev
);
5663 pm_runtime_disable(&dsidev
->dev
);
5667 static int __exit
omap_dsihw_remove(struct platform_device
*dsidev
)
5669 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5671 of_platform_depopulate(&dsidev
->dev
);
5673 WARN_ON(dsi
->scp_clk_refcount
> 0);
5675 dsi_uninit_output(dsidev
);
5677 pm_runtime_disable(&dsidev
->dev
);
5679 if (dsi
->vdds_dsi_reg
!= NULL
&& dsi
->vdds_dsi_enabled
) {
5680 regulator_disable(dsi
->vdds_dsi_reg
);
5681 dsi
->vdds_dsi_enabled
= false;
5687 static int dsi_runtime_suspend(struct device
*dev
)
5689 struct platform_device
*pdev
= to_platform_device(dev
);
5690 struct dsi_data
*dsi
= dsi_get_dsidrv_data(pdev
);
5692 dsi
->is_enabled
= false;
5693 /* ensure the irq handler sees the is_enabled value */
5695 /* wait for current handler to finish before turning the DSI off */
5696 synchronize_irq(dsi
->irq
);
5698 dispc_runtime_put();
5703 static int dsi_runtime_resume(struct device
*dev
)
5705 struct platform_device
*pdev
= to_platform_device(dev
);
5706 struct dsi_data
*dsi
= dsi_get_dsidrv_data(pdev
);
5709 r
= dispc_runtime_get();
5713 dsi
->is_enabled
= true;
5714 /* ensure the irq handler sees the is_enabled value */
5720 static const struct dev_pm_ops dsi_pm_ops
= {
5721 .runtime_suspend
= dsi_runtime_suspend
,
5722 .runtime_resume
= dsi_runtime_resume
,
5725 static const struct dsi_module_id_data dsi_of_data_omap3
[] = {
5726 { .address
= 0x4804fc00, .id
= 0, },
5730 static const struct dsi_module_id_data dsi_of_data_omap4
[] = {
5731 { .address
= 0x58004000, .id
= 0, },
5732 { .address
= 0x58005000, .id
= 1, },
5736 static const struct dsi_module_id_data dsi_of_data_omap5
[] = {
5737 { .address
= 0x58004000, .id
= 0, },
5738 { .address
= 0x58009000, .id
= 1, },
5742 static const struct of_device_id dsi_of_match
[] = {
5743 { .compatible
= "ti,omap3-dsi", .data
= dsi_of_data_omap3
, },
5744 { .compatible
= "ti,omap4-dsi", .data
= dsi_of_data_omap4
, },
5745 { .compatible
= "ti,omap5-dsi", .data
= dsi_of_data_omap5
, },
5749 static struct platform_driver omap_dsihw_driver
= {
5750 .probe
= omap_dsihw_probe
,
5751 .remove
= __exit_p(omap_dsihw_remove
),
5753 .name
= "omapdss_dsi",
5754 .owner
= THIS_MODULE
,
5756 .of_match_table
= dsi_of_match
,
5757 .suppress_bind_attrs
= true,
5761 int __init
dsi_init_platform_driver(void)
5763 return platform_driver_register(&omap_dsihw_driver
);
5766 void __exit
dsi_uninit_platform_driver(void)
5768 platform_driver_unregister(&omap_dsihw_driver
);