2 * linux/drivers/video/omap2/dss/venc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * VENC settings from TI's DSS driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "VENC"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
39 #include <video/omapdss.h>
42 #include "dss_features.h"
45 #define VENC_REV_ID 0x00
46 #define VENC_STATUS 0x04
47 #define VENC_F_CONTROL 0x08
48 #define VENC_VIDOUT_CTRL 0x10
49 #define VENC_SYNC_CTRL 0x14
50 #define VENC_LLEN 0x1C
51 #define VENC_FLENS 0x20
52 #define VENC_HFLTR_CTRL 0x24
53 #define VENC_CC_CARR_WSS_CARR 0x28
54 #define VENC_C_PHASE 0x2C
55 #define VENC_GAIN_U 0x30
56 #define VENC_GAIN_V 0x34
57 #define VENC_GAIN_Y 0x38
58 #define VENC_BLACK_LEVEL 0x3C
59 #define VENC_BLANK_LEVEL 0x40
60 #define VENC_X_COLOR 0x44
61 #define VENC_M_CONTROL 0x48
62 #define VENC_BSTAMP_WSS_DATA 0x4C
63 #define VENC_S_CARR 0x50
64 #define VENC_LINE21 0x54
65 #define VENC_LN_SEL 0x58
66 #define VENC_L21__WC_CTL 0x5C
67 #define VENC_HTRIGGER_VTRIGGER 0x60
68 #define VENC_SAVID__EAVID 0x64
69 #define VENC_FLEN__FAL 0x68
70 #define VENC_LAL__PHASE_RESET 0x6C
71 #define VENC_HS_INT_START_STOP_X 0x70
72 #define VENC_HS_EXT_START_STOP_X 0x74
73 #define VENC_VS_INT_START_X 0x78
74 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77 #define VENC_VS_EXT_STOP_Y 0x88
78 #define VENC_AVID_START_STOP_X 0x90
79 #define VENC_AVID_START_STOP_Y 0x94
80 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
84 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85 #define VENC_GEN_CTRL 0xB8
86 #define VENC_OUTPUT_CONTROL 0xC4
87 #define VENC_OUTPUT_TEST 0xC8
88 #define VENC_DAC_B__DAC_C 0xC8
111 u32 htrigger_vtrigger
;
114 u32 lal__phase_reset
;
115 u32 hs_int_start_stop_x
;
116 u32 hs_ext_start_stop_x
;
118 u32 vs_int_stop_x__vs_int_start_y
;
119 u32 vs_int_stop_y__vs_ext_start_x
;
120 u32 vs_ext_stop_x__vs_ext_start_y
;
122 u32 avid_start_stop_x
;
123 u32 avid_start_stop_y
;
124 u32 fid_int_start_x__fid_int_start_y
;
125 u32 fid_int_offset_y__fid_ext_start_x
;
126 u32 fid_ext_start_y__fid_ext_offset_y
;
127 u32 tvdetgp_int_start_stop_x
;
128 u32 tvdetgp_int_start_stop_y
;
133 static const struct venc_config venc_config_pal_trm
= {
137 .llen
= 0x35F, /* 863 */
138 .flens
= 0x270, /* 624 */
140 .cc_carr_wss_carr
= 0x2F7225ED,
149 .bstamp_wss_data
= 0x3F,
150 .s_carr
= 0x2A098ACB,
152 .ln_sel
= 0x01290015,
153 .l21__wc_ctl
= 0x0000F603,
154 .htrigger_vtrigger
= 0,
156 .savid__eavid
= 0x06A70108,
157 .flen__fal
= 0x00180270,
158 .lal__phase_reset
= 0x00040135,
159 .hs_int_start_stop_x
= 0x00880358,
160 .hs_ext_start_stop_x
= 0x000F035F,
161 .vs_int_start_x
= 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y
= 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x
= 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y
= 0x000101AF,
165 .vs_ext_stop_y
= 0x00000025,
166 .avid_start_stop_x
= 0x03530083,
167 .avid_start_stop_y
= 0x026C002E,
168 .fid_int_start_x__fid_int_start_y
= 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x
= 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y
= 0x01380001,
172 .tvdetgp_int_start_stop_x
= 0x00140001,
173 .tvdetgp_int_start_stop_y
= 0x00010001,
174 .gen_ctrl
= 0x00FF0000,
178 static const struct venc_config venc_config_ntsc_trm
= {
185 .cc_carr_wss_carr
= 0x043F2631,
194 .bstamp_wss_data
= 0x38,
195 .s_carr
= 0x21F07C1F,
197 .ln_sel
= 0x01310011,
198 .l21__wc_ctl
= 0x0000F003,
199 .htrigger_vtrigger
= 0,
201 .savid__eavid
= 0x069300F4,
202 .flen__fal
= 0x0016020C,
203 .lal__phase_reset
= 0x00060107,
204 .hs_int_start_stop_x
= 0x008E0350,
205 .hs_ext_start_stop_x
= 0x000F0359,
206 .vs_int_start_x
= 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y
= 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x
= 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y
= 0x020D01AC,
210 .vs_ext_stop_y
= 0x00000006,
211 .avid_start_stop_x
= 0x03480078,
212 .avid_start_stop_y
= 0x02060024,
213 .fid_int_start_x__fid_int_start_y
= 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x
= 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y
= 0x01060006,
217 .tvdetgp_int_start_stop_x
= 0x00140001,
218 .tvdetgp_int_start_stop_y
= 0x00010001,
219 .gen_ctrl
= 0x00F90000,
222 static const struct venc_config venc_config_pal_bdghi
= {
230 .htrigger_vtrigger
= 0,
231 .tvdetgp_int_start_stop_x
= 0x00140001,
232 .tvdetgp_int_start_stop_y
= 0x00010001,
233 .gen_ctrl
= 0x00FB0000,
237 .cc_carr_wss_carr
= 0x2F7625ED,
244 .m_control
= 0<<2 | 1<<1,
245 .bstamp_wss_data
= 0x42,
246 .s_carr
= 0x2a098acb,
247 .l21__wc_ctl
= 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid
= 0x06A70108,
249 .flen__fal
= 23<<16 | 624<<0,
250 .lal__phase_reset
= 2<<17 | 310<<0,
251 .hs_int_start_stop_x
= 0x00920358,
252 .hs_ext_start_stop_x
= 0x000F035F,
253 .vs_int_start_x
= 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y
= 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x
= 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y
= 0x27101af,
257 .vs_ext_stop_y
= 0x05,
258 .avid_start_stop_x
= 0x03530082,
259 .avid_start_stop_y
= 0x0270002E,
260 .fid_int_start_x__fid_int_start_y
= 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x
= 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y
= 0x01380005,
265 const struct omap_video_timings omap_dss_pal_timings
= {
268 .pixelclock
= 13500000,
278 EXPORT_SYMBOL(omap_dss_pal_timings
);
280 const struct omap_video_timings omap_dss_ntsc_timings
= {
283 .pixelclock
= 13500000,
293 EXPORT_SYMBOL(omap_dss_ntsc_timings
);
296 struct platform_device
*pdev
;
298 struct mutex venc_lock
;
300 struct regulator
*vdda_dac_reg
;
302 struct clk
*tv_dac_clk
;
304 struct omap_video_timings timings
;
305 enum omap_dss_venc_type type
;
306 bool invert_polarity
;
308 struct omap_dss_device output
;
311 static inline void venc_write_reg(int idx
, u32 val
)
313 __raw_writel(val
, venc
.base
+ idx
);
316 static inline u32
venc_read_reg(int idx
)
318 u32 l
= __raw_readl(venc
.base
+ idx
);
322 static void venc_write_config(const struct venc_config
*config
)
324 DSSDBG("write venc conf\n");
326 venc_write_reg(VENC_LLEN
, config
->llen
);
327 venc_write_reg(VENC_FLENS
, config
->flens
);
328 venc_write_reg(VENC_CC_CARR_WSS_CARR
, config
->cc_carr_wss_carr
);
329 venc_write_reg(VENC_C_PHASE
, config
->c_phase
);
330 venc_write_reg(VENC_GAIN_U
, config
->gain_u
);
331 venc_write_reg(VENC_GAIN_V
, config
->gain_v
);
332 venc_write_reg(VENC_GAIN_Y
, config
->gain_y
);
333 venc_write_reg(VENC_BLACK_LEVEL
, config
->black_level
);
334 venc_write_reg(VENC_BLANK_LEVEL
, config
->blank_level
);
335 venc_write_reg(VENC_M_CONTROL
, config
->m_control
);
336 venc_write_reg(VENC_BSTAMP_WSS_DATA
, config
->bstamp_wss_data
|
338 venc_write_reg(VENC_S_CARR
, config
->s_carr
);
339 venc_write_reg(VENC_L21__WC_CTL
, config
->l21__wc_ctl
);
340 venc_write_reg(VENC_SAVID__EAVID
, config
->savid__eavid
);
341 venc_write_reg(VENC_FLEN__FAL
, config
->flen__fal
);
342 venc_write_reg(VENC_LAL__PHASE_RESET
, config
->lal__phase_reset
);
343 venc_write_reg(VENC_HS_INT_START_STOP_X
, config
->hs_int_start_stop_x
);
344 venc_write_reg(VENC_HS_EXT_START_STOP_X
, config
->hs_ext_start_stop_x
);
345 venc_write_reg(VENC_VS_INT_START_X
, config
->vs_int_start_x
);
346 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y
,
347 config
->vs_int_stop_x__vs_int_start_y
);
348 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X
,
349 config
->vs_int_stop_y__vs_ext_start_x
);
350 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y
,
351 config
->vs_ext_stop_x__vs_ext_start_y
);
352 venc_write_reg(VENC_VS_EXT_STOP_Y
, config
->vs_ext_stop_y
);
353 venc_write_reg(VENC_AVID_START_STOP_X
, config
->avid_start_stop_x
);
354 venc_write_reg(VENC_AVID_START_STOP_Y
, config
->avid_start_stop_y
);
355 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y
,
356 config
->fid_int_start_x__fid_int_start_y
);
357 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X
,
358 config
->fid_int_offset_y__fid_ext_start_x
);
359 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y
,
360 config
->fid_ext_start_y__fid_ext_offset_y
);
362 venc_write_reg(VENC_DAC_B__DAC_C
, venc_read_reg(VENC_DAC_B__DAC_C
));
363 venc_write_reg(VENC_VIDOUT_CTRL
, config
->vidout_ctrl
);
364 venc_write_reg(VENC_HFLTR_CTRL
, config
->hfltr_ctrl
);
365 venc_write_reg(VENC_X_COLOR
, config
->x_color
);
366 venc_write_reg(VENC_LINE21
, config
->line21
);
367 venc_write_reg(VENC_LN_SEL
, config
->ln_sel
);
368 venc_write_reg(VENC_HTRIGGER_VTRIGGER
, config
->htrigger_vtrigger
);
369 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X
,
370 config
->tvdetgp_int_start_stop_x
);
371 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y
,
372 config
->tvdetgp_int_start_stop_y
);
373 venc_write_reg(VENC_GEN_CTRL
, config
->gen_ctrl
);
374 venc_write_reg(VENC_F_CONTROL
, config
->f_control
);
375 venc_write_reg(VENC_SYNC_CTRL
, config
->sync_ctrl
);
378 static void venc_reset(void)
382 venc_write_reg(VENC_F_CONTROL
, 1<<8);
383 while (venc_read_reg(VENC_F_CONTROL
) & (1<<8)) {
385 DSSERR("Failed to reset venc\n");
390 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
391 /* the magical sleep that makes things work */
392 /* XXX more info? What bug this circumvents? */
397 static int venc_runtime_get(void)
401 DSSDBG("venc_runtime_get\n");
403 r
= pm_runtime_get_sync(&venc
.pdev
->dev
);
405 return r
< 0 ? r
: 0;
408 static void venc_runtime_put(void)
412 DSSDBG("venc_runtime_put\n");
414 r
= pm_runtime_put_sync(&venc
.pdev
->dev
);
415 WARN_ON(r
< 0 && r
!= -ENOSYS
);
418 static const struct venc_config
*venc_timings_to_config(
419 struct omap_video_timings
*timings
)
421 if (memcmp(&omap_dss_pal_timings
, timings
, sizeof(*timings
)) == 0)
422 return &venc_config_pal_trm
;
424 if (memcmp(&omap_dss_ntsc_timings
, timings
, sizeof(*timings
)) == 0)
425 return &venc_config_ntsc_trm
;
431 static int venc_power_on(struct omap_dss_device
*dssdev
)
433 struct omap_overlay_manager
*mgr
= venc
.output
.manager
;
437 r
= venc_runtime_get();
442 venc_write_config(venc_timings_to_config(&venc
.timings
));
444 dss_set_venc_output(venc
.type
);
445 dss_set_dac_pwrdn_bgz(1);
449 if (venc
.type
== OMAP_DSS_VENC_TYPE_COMPOSITE
)
452 l
|= (1 << 0) | (1 << 2);
454 if (venc
.invert_polarity
== false)
457 venc_write_reg(VENC_OUTPUT_CONTROL
, l
);
459 dss_mgr_set_timings(mgr
, &venc
.timings
);
461 r
= regulator_enable(venc
.vdda_dac_reg
);
465 r
= dss_mgr_enable(mgr
);
472 regulator_disable(venc
.vdda_dac_reg
);
474 venc_write_reg(VENC_OUTPUT_CONTROL
, 0);
475 dss_set_dac_pwrdn_bgz(0);
482 static void venc_power_off(struct omap_dss_device
*dssdev
)
484 struct omap_overlay_manager
*mgr
= venc
.output
.manager
;
486 venc_write_reg(VENC_OUTPUT_CONTROL
, 0);
487 dss_set_dac_pwrdn_bgz(0);
489 dss_mgr_disable(mgr
);
491 regulator_disable(venc
.vdda_dac_reg
);
496 static int venc_display_enable(struct omap_dss_device
*dssdev
)
498 struct omap_dss_device
*out
= &venc
.output
;
501 DSSDBG("venc_display_enable\n");
503 mutex_lock(&venc
.venc_lock
);
505 if (out
== NULL
|| out
->manager
== NULL
) {
506 DSSERR("Failed to enable display: no output/manager\n");
511 r
= venc_power_on(dssdev
);
517 mutex_unlock(&venc
.venc_lock
);
521 mutex_unlock(&venc
.venc_lock
);
525 static void venc_display_disable(struct omap_dss_device
*dssdev
)
527 DSSDBG("venc_display_disable\n");
529 mutex_lock(&venc
.venc_lock
);
531 venc_power_off(dssdev
);
533 mutex_unlock(&venc
.venc_lock
);
536 static void venc_set_timings(struct omap_dss_device
*dssdev
,
537 struct omap_video_timings
*timings
)
539 DSSDBG("venc_set_timings\n");
541 mutex_lock(&venc
.venc_lock
);
543 /* Reset WSS data when the TV standard changes. */
544 if (memcmp(&venc
.timings
, timings
, sizeof(*timings
)))
547 venc
.timings
= *timings
;
549 dispc_set_tv_pclk(13500000);
551 mutex_unlock(&venc
.venc_lock
);
554 static int venc_check_timings(struct omap_dss_device
*dssdev
,
555 struct omap_video_timings
*timings
)
557 DSSDBG("venc_check_timings\n");
559 if (memcmp(&omap_dss_pal_timings
, timings
, sizeof(*timings
)) == 0)
562 if (memcmp(&omap_dss_ntsc_timings
, timings
, sizeof(*timings
)) == 0)
568 static void venc_get_timings(struct omap_dss_device
*dssdev
,
569 struct omap_video_timings
*timings
)
571 mutex_lock(&venc
.venc_lock
);
573 *timings
= venc
.timings
;
575 mutex_unlock(&venc
.venc_lock
);
578 static u32
venc_get_wss(struct omap_dss_device
*dssdev
)
580 /* Invert due to VENC_L21_WC_CTL:INV=1 */
581 return (venc
.wss_data
>> 8) ^ 0xfffff;
584 static int venc_set_wss(struct omap_dss_device
*dssdev
, u32 wss
)
586 const struct venc_config
*config
;
589 DSSDBG("venc_set_wss\n");
591 mutex_lock(&venc
.venc_lock
);
593 config
= venc_timings_to_config(&venc
.timings
);
595 /* Invert due to VENC_L21_WC_CTL:INV=1 */
596 venc
.wss_data
= (wss
^ 0xfffff) << 8;
598 r
= venc_runtime_get();
602 venc_write_reg(VENC_BSTAMP_WSS_DATA
, config
->bstamp_wss_data
|
608 mutex_unlock(&venc
.venc_lock
);
613 static void venc_set_type(struct omap_dss_device
*dssdev
,
614 enum omap_dss_venc_type type
)
616 mutex_lock(&venc
.venc_lock
);
620 mutex_unlock(&venc
.venc_lock
);
623 static void venc_invert_vid_out_polarity(struct omap_dss_device
*dssdev
,
624 bool invert_polarity
)
626 mutex_lock(&venc
.venc_lock
);
628 venc
.invert_polarity
= invert_polarity
;
630 mutex_unlock(&venc
.venc_lock
);
633 static int venc_init_regulator(void)
635 struct regulator
*vdda_dac
;
637 if (venc
.vdda_dac_reg
!= NULL
)
640 if (venc
.pdev
->dev
.of_node
)
641 vdda_dac
= devm_regulator_get(&venc
.pdev
->dev
, "vdda");
643 vdda_dac
= devm_regulator_get(&venc
.pdev
->dev
, "vdda_dac");
645 if (IS_ERR(vdda_dac
)) {
646 if (PTR_ERR(vdda_dac
) != -EPROBE_DEFER
)
647 DSSERR("can't get VDDA_DAC regulator\n");
648 return PTR_ERR(vdda_dac
);
651 venc
.vdda_dac_reg
= vdda_dac
;
656 static void venc_dump_regs(struct seq_file
*s
)
658 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
660 if (venc_runtime_get())
663 DUMPREG(VENC_F_CONTROL
);
664 DUMPREG(VENC_VIDOUT_CTRL
);
665 DUMPREG(VENC_SYNC_CTRL
);
668 DUMPREG(VENC_HFLTR_CTRL
);
669 DUMPREG(VENC_CC_CARR_WSS_CARR
);
670 DUMPREG(VENC_C_PHASE
);
671 DUMPREG(VENC_GAIN_U
);
672 DUMPREG(VENC_GAIN_V
);
673 DUMPREG(VENC_GAIN_Y
);
674 DUMPREG(VENC_BLACK_LEVEL
);
675 DUMPREG(VENC_BLANK_LEVEL
);
676 DUMPREG(VENC_X_COLOR
);
677 DUMPREG(VENC_M_CONTROL
);
678 DUMPREG(VENC_BSTAMP_WSS_DATA
);
679 DUMPREG(VENC_S_CARR
);
680 DUMPREG(VENC_LINE21
);
681 DUMPREG(VENC_LN_SEL
);
682 DUMPREG(VENC_L21__WC_CTL
);
683 DUMPREG(VENC_HTRIGGER_VTRIGGER
);
684 DUMPREG(VENC_SAVID__EAVID
);
685 DUMPREG(VENC_FLEN__FAL
);
686 DUMPREG(VENC_LAL__PHASE_RESET
);
687 DUMPREG(VENC_HS_INT_START_STOP_X
);
688 DUMPREG(VENC_HS_EXT_START_STOP_X
);
689 DUMPREG(VENC_VS_INT_START_X
);
690 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y
);
691 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X
);
692 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y
);
693 DUMPREG(VENC_VS_EXT_STOP_Y
);
694 DUMPREG(VENC_AVID_START_STOP_X
);
695 DUMPREG(VENC_AVID_START_STOP_Y
);
696 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y
);
697 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X
);
698 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y
);
699 DUMPREG(VENC_TVDETGP_INT_START_STOP_X
);
700 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y
);
701 DUMPREG(VENC_GEN_CTRL
);
702 DUMPREG(VENC_OUTPUT_CONTROL
);
703 DUMPREG(VENC_OUTPUT_TEST
);
710 static int venc_get_clocks(struct platform_device
*pdev
)
714 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK
)) {
715 clk
= devm_clk_get(&pdev
->dev
, "tv_dac_clk");
717 DSSERR("can't get tv_dac_clk\n");
724 venc
.tv_dac_clk
= clk
;
729 static int venc_connect(struct omap_dss_device
*dssdev
,
730 struct omap_dss_device
*dst
)
732 struct omap_overlay_manager
*mgr
;
735 r
= venc_init_regulator();
739 mgr
= omap_dss_get_overlay_manager(dssdev
->dispc_channel
);
743 r
= dss_mgr_connect(mgr
, dssdev
);
747 r
= omapdss_output_set_device(dssdev
, dst
);
749 DSSERR("failed to connect output to new device: %s\n",
751 dss_mgr_disconnect(mgr
, dssdev
);
758 static void venc_disconnect(struct omap_dss_device
*dssdev
,
759 struct omap_dss_device
*dst
)
761 WARN_ON(dst
!= dssdev
->dst
);
763 if (dst
!= dssdev
->dst
)
766 omapdss_output_unset_device(dssdev
);
769 dss_mgr_disconnect(dssdev
->manager
, dssdev
);
772 static const struct omapdss_atv_ops venc_ops
= {
773 .connect
= venc_connect
,
774 .disconnect
= venc_disconnect
,
776 .enable
= venc_display_enable
,
777 .disable
= venc_display_disable
,
779 .check_timings
= venc_check_timings
,
780 .set_timings
= venc_set_timings
,
781 .get_timings
= venc_get_timings
,
783 .set_type
= venc_set_type
,
784 .invert_vid_out_polarity
= venc_invert_vid_out_polarity
,
786 .set_wss
= venc_set_wss
,
787 .get_wss
= venc_get_wss
,
790 static void venc_init_output(struct platform_device
*pdev
)
792 struct omap_dss_device
*out
= &venc
.output
;
794 out
->dev
= &pdev
->dev
;
795 out
->id
= OMAP_DSS_OUTPUT_VENC
;
796 out
->output_type
= OMAP_DISPLAY_TYPE_VENC
;
797 out
->name
= "venc.0";
798 out
->dispc_channel
= OMAP_DSS_CHANNEL_DIGIT
;
799 out
->ops
.atv
= &venc_ops
;
800 out
->owner
= THIS_MODULE
;
802 omapdss_register_output(out
);
805 static void __exit
venc_uninit_output(struct platform_device
*pdev
)
807 struct omap_dss_device
*out
= &venc
.output
;
809 omapdss_unregister_output(out
);
812 static int venc_probe_of(struct platform_device
*pdev
)
814 struct device_node
*node
= pdev
->dev
.of_node
;
815 struct device_node
*ep
;
819 ep
= omapdss_of_get_first_endpoint(node
);
823 venc
.invert_polarity
= of_property_read_bool(ep
, "ti,invert-polarity");
825 r
= of_property_read_u32(ep
, "ti,channels", &channels
);
828 "failed to read property 'ti,channels': %d\n", r
);
834 venc
.type
= OMAP_DSS_VENC_TYPE_COMPOSITE
;
837 venc
.type
= OMAP_DSS_VENC_TYPE_SVIDEO
;
840 dev_err(&pdev
->dev
, "bad channel propert '%d'\n", channels
);
854 /* VENC HW IP initialisation */
855 static int omap_venchw_probe(struct platform_device
*pdev
)
858 struct resource
*venc_mem
;
863 mutex_init(&venc
.venc_lock
);
867 venc_mem
= platform_get_resource(venc
.pdev
, IORESOURCE_MEM
, 0);
869 DSSERR("can't get IORESOURCE_MEM VENC\n");
873 venc
.base
= devm_ioremap(&pdev
->dev
, venc_mem
->start
,
874 resource_size(venc_mem
));
876 DSSERR("can't ioremap VENC\n");
880 r
= venc_get_clocks(pdev
);
884 pm_runtime_enable(&pdev
->dev
);
886 r
= venc_runtime_get();
888 goto err_runtime_get
;
890 rev_id
= (u8
)(venc_read_reg(VENC_REV_ID
) & 0xff);
891 dev_dbg(&pdev
->dev
, "OMAP VENC rev %d\n", rev_id
);
895 if (pdev
->dev
.of_node
) {
896 r
= venc_probe_of(pdev
);
898 DSSERR("Invalid DT data\n");
903 dss_debugfs_create_file("venc", venc_dump_regs
);
905 venc_init_output(pdev
);
911 pm_runtime_disable(&pdev
->dev
);
915 static int __exit
omap_venchw_remove(struct platform_device
*pdev
)
917 venc_uninit_output(pdev
);
919 pm_runtime_disable(&pdev
->dev
);
924 static int venc_runtime_suspend(struct device
*dev
)
927 clk_disable_unprepare(venc
.tv_dac_clk
);
934 static int venc_runtime_resume(struct device
*dev
)
938 r
= dispc_runtime_get();
943 clk_prepare_enable(venc
.tv_dac_clk
);
948 static const struct dev_pm_ops venc_pm_ops
= {
949 .runtime_suspend
= venc_runtime_suspend
,
950 .runtime_resume
= venc_runtime_resume
,
954 static const struct of_device_id venc_of_match
[] = {
955 { .compatible
= "ti,omap2-venc", },
956 { .compatible
= "ti,omap3-venc", },
957 { .compatible
= "ti,omap4-venc", },
961 static struct platform_driver omap_venchw_driver
= {
962 .probe
= omap_venchw_probe
,
963 .remove
= __exit_p(omap_venchw_remove
),
965 .name
= "omapdss_venc",
966 .owner
= THIS_MODULE
,
968 .of_match_table
= venc_of_match
,
969 .suppress_bind_attrs
= true,
973 int __init
venc_init_platform_driver(void)
975 return platform_driver_register(&omap_venchw_driver
);
978 void __exit
venc_uninit_platform_driver(void)
980 platform_driver_unregister(&omap_venchw_driver
);