drivers/video/geode/video_gx.c

   1 /*
   2  * Geode GX video processor device.
   3  *
   4  *   Copyright (C) 2006 Arcom Control Systems Ltd.
   5  *
   6  *   Portions from AMD's original 2.4 driver:
   7  *     Copyright (C) 2004 Advanced Micro Devices, Inc.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify it
  10  *   under the terms of the GNU General Public License as published by the
  11  *   Free Software Foundation; either version 2 of the License, or (at your
  12  *   option) any later version.
  13  */
  14 #include <linux/fb.h>
  15 #include <linux/delay.h>
  16 #include <asm/io.h>
  17 #include <asm/delay.h>
  18 #include <asm/msr.h>
  19 #include <asm/geode.h>
  20
  21 #include "geodefb.h"
  22 #include "video_gx.h"
  23
  24
  25 /*
  26  * Tables of register settings for various DOTCLKs.
  27  */
  28 struct gx_pll_entry {
  29         long pixclock; /* ps */
  30         u32 sys_rstpll_bits;
  31         u32 dotpll_value;
  32 };
  33
  34 #define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
  35 #define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
  36 #define PREDIV2  ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
  37
  38 static const struct gx_pll_entry gx_pll_table_48MHz[] = {
  39         { 40123, POSTDIV3,          0x00000BF2 },       /*  24.9230 */
  40         { 39721, 0,                 0x00000037 },       /*  25.1750 */
  41         { 35308, POSTDIV3|PREMULT2, 0x00000B1A },       /*  28.3220 */
  42         { 31746, POSTDIV3,          0x000002D2 },       /*  31.5000 */
  43         { 27777, POSTDIV3|PREMULT2, 0x00000FE2 },       /*  36.0000 */
  44         { 26666, POSTDIV3,          0x0000057A },       /*  37.5000 */
  45         { 25000, POSTDIV3,          0x0000030A },       /*  40.0000 */
  46         { 22271, 0,                 0x00000063 },       /*  44.9000 */
  47         { 20202, 0,                 0x0000054B },       /*  49.5000 */
  48         { 20000, 0,                 0x0000026E },       /*  50.0000 */
  49         { 19860, PREMULT2,          0x00000037 },       /*  50.3500 */
  50         { 18518, POSTDIV3|PREMULT2, 0x00000B0D },       /*  54.0000 */
  51         { 17777, 0,                 0x00000577 },       /*  56.2500 */
  52         { 17733, 0,                 0x000007F7 },       /*  56.3916 */
  53         { 17653, 0,                 0x0000057B },       /*  56.6444 */
  54         { 16949, PREMULT2,          0x00000707 },       /*  59.0000 */
  55         { 15873, POSTDIV3|PREMULT2, 0x00000B39 },       /*  63.0000 */
  56         { 15384, POSTDIV3|PREMULT2, 0x00000B45 },       /*  65.0000 */
  57         { 14814, POSTDIV3|PREMULT2, 0x00000FC1 },       /*  67.5000 */
  58         { 14124, POSTDIV3,          0x00000561 },       /*  70.8000 */
  59         { 13888, POSTDIV3,          0x000007E1 },       /*  72.0000 */
  60         { 13426, PREMULT2,          0x00000F4A },       /*  74.4810 */
  61         { 13333, 0,                 0x00000052 },       /*  75.0000 */
  62         { 12698, 0,                 0x00000056 },       /*  78.7500 */
  63         { 12500, POSTDIV3|PREMULT2, 0x00000709 },       /*  80.0000 */
  64         { 11135, PREMULT2,          0x00000262 },       /*  89.8000 */
  65         { 10582, 0,                 0x000002D2 },       /*  94.5000 */
  66         { 10101, PREMULT2,          0x00000B4A },       /*  99.0000 */
  67         { 10000, PREMULT2,          0x00000036 },       /* 100.0000 */
  68         {  9259, 0,                 0x000007E2 },       /* 108.0000 */
  69         {  8888, 0,                 0x000007F6 },       /* 112.5000 */
  70         {  7692, POSTDIV3|PREMULT2, 0x00000FB0 },       /* 130.0000 */
  71         {  7407, POSTDIV3|PREMULT2, 0x00000B50 },       /* 135.0000 */
  72         {  6349, 0,                 0x00000055 },       /* 157.5000 */
  73         {  6172, 0,                 0x000009C1 },       /* 162.0000 */
  74         {  5787, PREMULT2,          0x0000002D },       /* 172.798  */
  75         {  5698, 0,                 0x000002C1 },       /* 175.5000 */
  76         {  5291, 0,                 0x000002D1 },       /* 189.0000 */
  77         {  4938, 0,                 0x00000551 },       /* 202.5000 */
  78         {  4357, 0,                 0x0000057D },       /* 229.5000 */
  79 };
  80
  81 static const struct gx_pll_entry gx_pll_table_14MHz[] = {
  82         { 39721, 0, 0x00000037 },       /*  25.1750 */
  83         { 35308, 0, 0x00000B7B },       /*  28.3220 */
  84         { 31746, 0, 0x000004D3 },       /*  31.5000 */
  85         { 27777, 0, 0x00000BE3 },       /*  36.0000 */
  86         { 26666, 0, 0x0000074F },       /*  37.5000 */
  87         { 25000, 0, 0x0000050B },       /*  40.0000 */
  88         { 22271, 0, 0x00000063 },       /*  44.9000 */
  89         { 20202, 0, 0x0000054B },       /*  49.5000 */
  90         { 20000, 0, 0x0000026E },       /*  50.0000 */
  91         { 19860, 0, 0x000007C3 },       /*  50.3500 */
  92         { 18518, 0, 0x000007E3 },       /*  54.0000 */
  93         { 17777, 0, 0x00000577 },       /*  56.2500 */
  94         { 17733, 0, 0x000002FB },       /*  56.3916 */
  95         { 17653, 0, 0x0000057B },       /*  56.6444 */
  96         { 16949, 0, 0x0000058B },       /*  59.0000 */
  97         { 15873, 0, 0x0000095E },       /*  63.0000 */
  98         { 15384, 0, 0x0000096A },       /*  65.0000 */
  99         { 14814, 0, 0x00000BC2 },       /*  67.5000 */
 100         { 14124, 0, 0x0000098A },       /*  70.8000 */
 101         { 13888, 0, 0x00000BE2 },       /*  72.0000 */
 102         { 13333, 0, 0x00000052 },       /*  75.0000 */
 103         { 12698, 0, 0x00000056 },       /*  78.7500 */
 104         { 12500, 0, 0x0000050A },       /*  80.0000 */
 105         { 11135, 0, 0x0000078E },       /*  89.8000 */
 106         { 10582, 0, 0x000002D2 },       /*  94.5000 */
 107         { 10101, 0, 0x000011F6 },       /*  99.0000 */
 108         { 10000, 0, 0x0000054E },       /* 100.0000 */
 109         {  9259, 0, 0x000007E2 },       /* 108.0000 */
 110         {  8888, 0, 0x000002FA },       /* 112.5000 */
 111         {  7692, 0, 0x00000BB1 },       /* 130.0000 */
 112         {  7407, 0, 0x00000975 },       /* 135.0000 */
 113         {  6349, 0, 0x00000055 },       /* 157.5000 */
 114         {  6172, 0, 0x000009C1 },       /* 162.0000 */
 115         {  5698, 0, 0x000002C1 },       /* 175.5000 */
 116         {  5291, 0, 0x00000539 },       /* 189.0000 */
 117         {  4938, 0, 0x00000551 },       /* 202.5000 */
 118         {  4357, 0, 0x0000057D },       /* 229.5000 */
 119 };
 120
 121 static void gx_set_dclk_frequency(struct fb_info *info)
 122 {
 123         const struct gx_pll_entry *pll_table;
 124         int pll_table_len;
 125         int i, best_i;
 126         long min, diff;
 127         u64 dotpll, sys_rstpll;
 128         int timeout = 1000;
 129
 130         /* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
 131         if (cpu_data(0).x86_mask == 1) {
 132                 pll_table = gx_pll_table_14MHz;
 133                 pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
 134         } else {
 135                 pll_table = gx_pll_table_48MHz;
 136                 pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
 137         }
 138
 139         /* Search the table for the closest pixclock. */
 140         best_i = 0;
 141         min = abs(pll_table[0].pixclock - info->var.pixclock);
 142         for (i = 1; i < pll_table_len; i++) {
 143                 diff = abs(pll_table[i].pixclock - info->var.pixclock);
 144                 if (diff < min) {
 145                         min = diff;
 146                         best_i = i;
 147                 }
 148         }
 149
 150         rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
 151         rdmsrl(MSR_GLCP_DOTPLL, dotpll);
 152
 153         /* Program new M, N and P. */
 154         dotpll &= 0x00000000ffffffffull;
 155         dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
 156         dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
 157         dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
 158
 159         wrmsrl(MSR_GLCP_DOTPLL, dotpll);
 160
 161         /* Program dividers. */
 162         sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
 163                          | MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
 164                          | MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
 165         sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
 166
 167         wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
 168
 169         /* Clear reset bit to start PLL. */
 170         dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
 171         wrmsrl(MSR_GLCP_DOTPLL, dotpll);
 172
 173         /* Wait for LOCK bit. */
 174         do {
 175                 rdmsrl(MSR_GLCP_DOTPLL, dotpll);
 176         } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
 177 }
 178
 179 static void
 180 gx_configure_tft(struct fb_info *info)
 181 {
 182         struct geodefb_par *par = info->par;
 183         unsigned long val;
 184         unsigned long fp;
 185
 186         /* Set up the DF pad select MSR */
 187
 188         rdmsrl(MSR_GX_MSR_PADSEL, val);
 189         val &= ~GX_VP_PAD_SELECT_MASK;
 190         val |= GX_VP_PAD_SELECT_TFT;
 191         wrmsrl(MSR_GX_MSR_PADSEL, val);
 192
 193         /* Turn off the panel */
 194
 195         fp = readl(par->vid_regs + GX_FP_PM);
 196         fp &= ~GX_FP_PM_P;
 197         writel(fp, par->vid_regs + GX_FP_PM);
 198
 199         /* Set timing 1 */
 200
 201         fp = readl(par->vid_regs + GX_FP_PT1);
 202         fp &= GX_FP_PT1_VSIZE_MASK;
 203         fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
 204         writel(fp, par->vid_regs + GX_FP_PT1);
 205
 206         /* Timing 2 */
 207         /* Set bits that are always on for TFT */
 208
 209         fp = 0x0F100000;
 210
 211         /* Configure sync polarity */
 212
 213         if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
 214                 fp |= GX_FP_PT2_VSP;
 215
 216         if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
 217                 fp |= GX_FP_PT2_HSP;
 218
 219         writel(fp, par->vid_regs + GX_FP_PT2);
 220
 221         /*  Set the dither control */
 222         writel(0x70, par->vid_regs + GX_FP_DFC);
 223
 224         /* Enable the FP data and power (in case the BIOS didn't) */
 225
 226         fp = readl(par->vid_regs + GX_DCFG);
 227         fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
 228         writel(fp, par->vid_regs + GX_DCFG);
 229
 230         /* Unblank the panel */
 231
 232         fp = readl(par->vid_regs + GX_FP_PM);
 233         fp |= GX_FP_PM_P;
 234         writel(fp, par->vid_regs + GX_FP_PM);
 235 }
 236
 237 static void gx_configure_display(struct fb_info *info)
 238 {
 239         struct geodefb_par *par = info->par;
 240         u32 dcfg, misc;
 241
 242         /* Set up the MISC register */
 243
 244         misc = readl(par->vid_regs + GX_MISC);
 245
 246         /* Power up the DAC */
 247         misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
 248
 249         /* Disable gamma correction */
 250         misc |= GX_MISC_GAM_EN;
 251
 252         writel(misc, par->vid_regs + GX_MISC);
 253
 254         /* Write the display configuration */
 255         dcfg = readl(par->vid_regs + GX_DCFG);
 256
 257         /* Disable hsync and vsync */
 258         dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
 259         writel(dcfg, par->vid_regs + GX_DCFG);
 260
 261         /* Clear bits from existing mode. */
 262         dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
 263                   | GX_DCFG_CRT_HSYNC_POL   | GX_DCFG_CRT_VSYNC_POL
 264                   | GX_DCFG_VSYNC_EN        | GX_DCFG_HSYNC_EN);
 265
 266         /* Set default sync skew.  */
 267         dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
 268
 269         /* Enable hsync and vsync. */
 270         dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
 271
 272         /* Only change the sync polarities if we are running
 273          * in CRT mode.  The FP polarities will be handled in
 274          * gxfb_configure_tft */
 275         if (par->enable_crt) {
 276                 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
 277                         dcfg |= GX_DCFG_CRT_HSYNC_POL;
 278                 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
 279                         dcfg |= GX_DCFG_CRT_VSYNC_POL;
 280         }
 281
 282         /* Enable the display logic */
 283         /* Set up the DACS to blank normally */
 284
 285         dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
 286
 287         /* Enable the external DAC VREF? */
 288
 289         writel(dcfg, par->vid_regs + GX_DCFG);
 290
 291         /* Set up the flat panel (if it is enabled) */
 292
 293         if (par->enable_crt == 0)
 294                 gx_configure_tft(info);
 295 }
 296
 297 static int gx_blank_display(struct fb_info *info, int blank_mode)
 298 {
 299         struct geodefb_par *par = info->par;
 300         u32 dcfg, fp_pm;
 301         int blank, hsync, vsync;
 302
 303         /* CRT power saving modes. */
 304         switch (blank_mode) {
 305         case FB_BLANK_UNBLANK:
 306                 blank = 0; hsync = 1; vsync = 1;
 307                 break;
 308         case FB_BLANK_NORMAL:
 309                 blank = 1; hsync = 1; vsync = 1;
 310                 break;
 311         case FB_BLANK_VSYNC_SUSPEND:
 312                 blank = 1; hsync = 1; vsync = 0;
 313                 break;
 314         case FB_BLANK_HSYNC_SUSPEND:
 315                 blank = 1; hsync = 0; vsync = 1;
 316                 break;
 317         case FB_BLANK_POWERDOWN:
 318                 blank = 1; hsync = 0; vsync = 0;
 319                 break;
 320         default:
 321                 return -EINVAL;
 322         }
 323         dcfg = readl(par->vid_regs + GX_DCFG);
 324         dcfg &= ~(GX_DCFG_DAC_BL_EN
 325                   | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
 326         if (!blank)
 327                 dcfg |= GX_DCFG_DAC_BL_EN;
 328         if (hsync)
 329                 dcfg |= GX_DCFG_HSYNC_EN;
 330         if (vsync)
 331                 dcfg |= GX_DCFG_VSYNC_EN;
 332         writel(dcfg, par->vid_regs + GX_DCFG);
 333
 334         /* Power on/off flat panel. */
 335
 336         if (par->enable_crt == 0) {
 337                 fp_pm = readl(par->vid_regs + GX_FP_PM);
 338                 if (blank_mode == FB_BLANK_POWERDOWN)
 339                         fp_pm &= ~GX_FP_PM_P;
 340                 else
 341                         fp_pm |= GX_FP_PM_P;
 342                 writel(fp_pm, par->vid_regs + GX_FP_PM);
 343         }
 344
 345         return 0;
 346 }
 347
 348 struct geode_vid_ops gx_vid_ops = {
 349         .set_dclk          = gx_set_dclk_frequency,
 350         .configure_display = gx_configure_display,
 351         .blank_display     = gx_blank_display,
 352 };