2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
4 * This file is derived from the powermac console "imstt" driver:
5 * Copyright (C) 1997 Sigurdur Asgeirsson
6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
7 * Modified by Danilo Beuche 1998
8 * Some register values added by Damien Doligez, INRIA Rocquencourt
9 * Various cleanups by Paul Mundt (lethal@chaoticdreams.org)
11 * This file was written by Ryan Nielsen (ran@krazynet.com)
12 * Most of the frame buffer device stuff was copied from atyfb.c
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file COPYING in the main directory of this archive for
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
24 #include <linux/tty.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
30 #include <linux/init.h>
31 #include <linux/pci.h>
33 #include <asm/uaccess.h>
35 #if defined(CONFIG_PPC)
36 #include <linux/nvram.h>
38 #include <asm/pci-bridge.h>
43 #define eieio() /* Enforce In-order Execution of I/O */
46 /* TwinTurbo (Cosmo) registers */
53 DP_OCTL
= 5, /* 0x14 */
57 BLTCTL
= 10, /* 0x28 */
59 /* Scan Timing Generator Registers */
72 STGCTL
= 24, /* 0x60 */
74 /* Screen Refresh Generator Registers */
79 SRGCTL
= 29, /* 0x74 */
81 /* RAM Refresh Generator Registers */
82 RRCIV
= 30, /* 0x78 */
86 /* System Registers */
90 SSTATUS
= 36, /* 0x90 */
104 /* IBM 624 RAMDAC Direct Registers */
116 /* IBM 624 RAMDAC Indirect Registers */
118 CLKCTL
= 0x02, /* (0x01) Miscellaneous Clock Control */
119 SYNCCTL
= 0x03, /* (0x00) Sync Control */
120 HSYNCPOS
= 0x04, /* (0x00) Horizontal Sync Position */
121 PWRMNGMT
= 0x05, /* (0x00) Power Management */
122 DACOP
= 0x06, /* (0x02) DAC Operation */
123 PALETCTL
= 0x07, /* (0x00) Palette Control */
124 SYSCLKCTL
= 0x08, /* (0x01) System Clock Control */
125 PIXFMT
= 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
126 BPP8
= 0x0b, /* () 8 Bits/Pixel Control */
127 BPP16
= 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
128 BPP24
= 0x0d, /* () 24 Bits/Pixel Control */
129 BPP32
= 0x0e, /* () 32 Bits/Pixel Control */
130 PIXCTL1
= 0x10, /* (0x05) Pixel PLL Control 1 */
131 PIXCTL2
= 0x11, /* (0x00) Pixel PLL Control 2 */
132 SYSCLKN
= 0x15, /* () System Clock N (System PLL Reference Divider) */
133 SYSCLKM
= 0x16, /* () System Clock M (System PLL VCO Divider) */
134 SYSCLKP
= 0x17, /* () System Clock P */
135 SYSCLKC
= 0x18, /* () System Clock C */
137 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
138 * c is charge pump bias which depends on the VCO frequency
140 PIXM0
= 0x20, /* () Pixel M 0 */
141 PIXN0
= 0x21, /* () Pixel N 0 */
142 PIXP0
= 0x22, /* () Pixel P 0 */
143 PIXC0
= 0x23, /* () Pixel C 0 */
144 CURSCTL
= 0x30, /* (0x00) Cursor Control */
145 CURSXLO
= 0x31, /* () Cursor X position, low 8 bits */
146 CURSXHI
= 0x32, /* () Cursor X position, high 8 bits */
147 CURSYLO
= 0x33, /* () Cursor Y position, low 8 bits */
148 CURSYHI
= 0x34, /* () Cursor Y position, high 8 bits */
149 CURSHOTX
= 0x35, /* () Cursor Hot Spot X */
150 CURSHOTY
= 0x36, /* () Cursor Hot Spot Y */
151 CURSACCTL
= 0x37, /* () Advanced Cursor Control Enable */
152 CURSACATTR
= 0x38, /* () Advanced Cursor Attribute */
153 CURS1R
= 0x40, /* () Cursor 1 Red */
154 CURS1G
= 0x41, /* () Cursor 1 Green */
155 CURS1B
= 0x42, /* () Cursor 1 Blue */
156 CURS2R
= 0x43, /* () Cursor 2 Red */
157 CURS2G
= 0x44, /* () Cursor 2 Green */
158 CURS2B
= 0x45, /* () Cursor 2 Blue */
159 CURS3R
= 0x46, /* () Cursor 3 Red */
160 CURS3G
= 0x47, /* () Cursor 3 Green */
161 CURS3B
= 0x48, /* () Cursor 3 Blue */
162 BORDR
= 0x60, /* () Border Color Red */
163 BORDG
= 0x61, /* () Border Color Green */
164 BORDB
= 0x62, /* () Border Color Blue */
165 MISCTL1
= 0x70, /* (0x00) Miscellaneous Control 1 */
166 MISCTL2
= 0x71, /* (0x00) Miscellaneous Control 2 */
167 MISCTL3
= 0x72, /* (0x00) Miscellaneous Control 3 */
168 KEYCTL
= 0x78 /* (0x00) Key Control/DB Operation */
171 /* TI TVP 3030 RAMDAC Direct Registers */
173 TVPADDRW
= 0x00, /* 0 Palette/Cursor RAM Write Address/Index */
174 TVPPDATA
= 0x04, /* 1 Palette Data RAM Data */
175 TVPPMASK
= 0x08, /* 2 Pixel Read-Mask */
176 TVPPADRR
= 0x0c, /* 3 Palette/Cursor RAM Read Address */
177 TVPCADRW
= 0x10, /* 4 Cursor/Overscan Color Write Address */
178 TVPCDATA
= 0x14, /* 5 Cursor/Overscan Color Data */
180 TVPCADRR
= 0x1c, /* 7 Cursor/Overscan Color Read Address */
182 TVPDCCTL
= 0x24, /* 9 Direct Cursor Control */
183 TVPIDATA
= 0x28, /* 10 Index Data */
184 TVPCRDAT
= 0x2c, /* 11 Cursor RAM Data */
185 TVPCXPOL
= 0x30, /* 12 Cursor-Position X LSB */
186 TVPCXPOH
= 0x34, /* 13 Cursor-Position X MSB */
187 TVPCYPOL
= 0x38, /* 14 Cursor-Position Y LSB */
188 TVPCYPOH
= 0x3c, /* 15 Cursor-Position Y MSB */
191 /* TI TVP 3030 RAMDAC Indirect Registers */
193 TVPIRREV
= 0x01, /* Silicon Revision [RO] */
194 TVPIRICC
= 0x06, /* Indirect Cursor Control (0x00) */
195 TVPIRBRC
= 0x07, /* Byte Router Control (0xe4) */
196 TVPIRLAC
= 0x0f, /* Latch Control (0x06) */
197 TVPIRTCC
= 0x18, /* True Color Control (0x80) */
198 TVPIRMXC
= 0x19, /* Multiplex Control (0x98) */
199 TVPIRCLS
= 0x1a, /* Clock Selection (0x07) */
200 TVPIRPPG
= 0x1c, /* Palette Page (0x00) */
201 TVPIRGEC
= 0x1d, /* General Control (0x00) */
202 TVPIRMIC
= 0x1e, /* Miscellaneous Control (0x00) */
203 TVPIRPLA
= 0x2c, /* PLL Address */
204 TVPIRPPD
= 0x2d, /* Pixel Clock PLL Data */
205 TVPIRMPD
= 0x2e, /* Memory Clock PLL Data */
206 TVPIRLPD
= 0x2f, /* Loop Clock PLL Data */
207 TVPIRCKL
= 0x30, /* Color-Key Overlay Low */
208 TVPIRCKH
= 0x31, /* Color-Key Overlay High */
209 TVPIRCRL
= 0x32, /* Color-Key Red Low */
210 TVPIRCRH
= 0x33, /* Color-Key Red High */
211 TVPIRCGL
= 0x34, /* Color-Key Green Low */
212 TVPIRCGH
= 0x35, /* Color-Key Green High */
213 TVPIRCBL
= 0x36, /* Color-Key Blue Low */
214 TVPIRCBH
= 0x37, /* Color-Key Blue High */
215 TVPIRCKC
= 0x38, /* Color-Key Control (0x00) */
216 TVPIRMLC
= 0x39, /* MCLK/Loop Clock Control (0x18) */
217 TVPIRSEN
= 0x3a, /* Sense Test (0x00) */
218 TVPIRTMD
= 0x3b, /* Test Mode Data */
219 TVPIRRML
= 0x3c, /* CRC Remainder LSB [RO] */
220 TVPIRRMM
= 0x3d, /* CRC Remainder MSB [RO] */
221 TVPIRRMS
= 0x3e, /* CRC Bit Select [WO] */
222 TVPIRDID
= 0x3f, /* Device ID [RO] (0x30) */
223 TVPIRRES
= 0xff /* Software Reset [WO] */
230 static struct initvalues ibm_initregs
[] __devinitdata
= {
240 * Note that colors in X are correct only if all video data is
241 * passed through the palette in the DAC. That is, "indirect
242 * color" must be configured. This is the case for the IBM DAC
243 * used in the 2MB and 4MB cards, at least.
258 { CURSACATTR
, 0xa8 },
277 static struct initvalues tvp_initregs
[] __devinitdata
= {
310 struct imstt_regvals
{
312 __u16 hes
, heb
, hsb
, ht
, ves
, veb
, vsb
, vt
, vil
;
313 __u8 pclk_m
, pclk_n
, pclk_p
;
314 /* Values of the tvp which change depending on colormode x resolution */
315 __u8 mlc
[3]; /* Memory Loop Config 0x39 */
316 __u8 lckl_p
[3]; /* P value of LCKL PLL */
320 struct imstt_regvals init
;
321 __u32 __iomem
*dc_regs
;
322 unsigned long cmap_regs_phys
;
333 #define USE_NV_MODES 1
335 #define INIT_XRES 640
336 #define INIT_YRES 480
338 static int inverse
= 0;
339 static char fontname
[40] __initdata
= { 0 };
340 #if defined(CONFIG_PPC)
341 static signed char init_vmode __devinitdata
= -1, init_cmode __devinitdata
= -1;
344 static struct imstt_regvals tvp_reg_init_2
= {
346 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
348 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
351 static struct imstt_regvals tvp_reg_init_6
= {
353 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
355 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
358 static struct imstt_regvals tvp_reg_init_12
= {
360 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
362 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
365 static struct imstt_regvals tvp_reg_init_13
= {
367 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
369 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
372 static struct imstt_regvals tvp_reg_init_17
= {
374 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
376 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
379 static struct imstt_regvals tvp_reg_init_18
= {
381 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
383 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
386 static struct imstt_regvals tvp_reg_init_19
= {
388 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
390 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
393 static struct imstt_regvals tvp_reg_init_20
= {
395 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
397 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
401 * PCI driver prototypes
403 static int imsttfb_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
404 static void imsttfb_remove(struct pci_dev
*pdev
);
409 static inline u32
read_reg_le32(volatile u32 __iomem
*base
, int regindex
)
412 return in_le32(base
+ regindex
);
414 return readl(base
+ regindex
);
418 static inline void write_reg_le32(volatile u32 __iomem
*base
, int regindex
, u32 val
)
421 out_le32(base
+ regindex
, val
);
423 writel(val
, base
+ regindex
);
428 getclkMHz(struct imstt_par
*par
)
430 __u32 clk_m
, clk_n
, clk_p
;
432 clk_m
= par
->init
.pclk_m
;
433 clk_n
= par
->init
.pclk_n
;
434 clk_p
= par
->init
.pclk_p
;
436 return 20 * (clk_m
+ 1) / ((clk_n
+ 1) * (clk_p
? 2 * clk_p
: 1));
440 setclkMHz(struct imstt_par
*par
, __u32 MHz
)
442 __u32 clk_m
, clk_n
, x
, stage
, spilled
;
455 x
= 20 * (clk_m
+ 1) / (clk_n
+ 1);
461 } else if (spilled
&& x
< MHz
) {
466 par
->init
.pclk_m
= clk_m
;
467 par
->init
.pclk_n
= clk_n
;
468 par
->init
.pclk_p
= 0;
471 static struct imstt_regvals
*
472 compute_imstt_regvals_ibm(struct imstt_par
*par
, int xres
, int yres
)
474 struct imstt_regvals
*init
= &par
->init
;
475 __u32 MHz
, hes
, heb
, veb
, htp
, vtp
;
479 hes
= 0x0008; heb
= 0x0012; veb
= 0x002a; htp
= 10; vtp
= 2;
483 hes
= 0x0005; heb
= 0x0020; veb
= 0x0028; htp
= 8; vtp
= 3;
484 MHz
= 57 /* .27_ */ ;
487 hes
= 0x000a; heb
= 0x001c; veb
= 0x0020; htp
= 8; vtp
= 3;
491 hes
= 0x0012; heb
= 0x0022; veb
= 0x0031; htp
= 4; vtp
= 3;
492 MHz
= 101 /* .6_ */ ;
495 hes
= 0x0012; heb
= 0x002f; veb
= 0x0029; htp
= 4; vtp
= 1;
496 MHz
= yres
== 960 ? 126 : 135;
499 hes
= 0x0018; heb
= 0x0040; veb
= 0x002a; htp
= 4; vtp
= 3;
510 init
->hsb
= init
->heb
+ (xres
>> 3);
511 init
->ht
= init
->hsb
+ htp
;
514 init
->vsb
= init
->veb
+ yres
;
515 init
->vt
= init
->vsb
+ vtp
;
516 init
->vil
= init
->vsb
;
522 static struct imstt_regvals
*
523 compute_imstt_regvals_tvp(struct imstt_par
*par
, int xres
, int yres
)
525 struct imstt_regvals
*init
;
529 init
= &tvp_reg_init_2
;
532 init
= &tvp_reg_init_6
;
535 init
= &tvp_reg_init_12
;
538 init
= &tvp_reg_init_13
;
541 init
= &tvp_reg_init_17
;
544 init
= &tvp_reg_init_18
;
547 init
= yres
== 960 ? &tvp_reg_init_19
: &tvp_reg_init_20
;
556 static struct imstt_regvals
*
557 compute_imstt_regvals (struct imstt_par
*par
, u_int xres
, u_int yres
)
559 if (par
->ramdac
== IBM
)
560 return compute_imstt_regvals_ibm(par
, xres
, yres
);
562 return compute_imstt_regvals_tvp(par
, xres
, yres
);
566 set_imstt_regvals_ibm (struct imstt_par
*par
, u_int bpp
)
568 struct imstt_regvals
*init
= &par
->init
;
569 __u8 pformat
= (bpp
>> 3) + 2;
571 par
->cmap_regs
[PIDXHI
] = 0; eieio();
572 par
->cmap_regs
[PIDXLO
] = PIXM0
; eieio();
573 par
->cmap_regs
[PIDXDATA
] = init
->pclk_m
;eieio();
574 par
->cmap_regs
[PIDXLO
] = PIXN0
; eieio();
575 par
->cmap_regs
[PIDXDATA
] = init
->pclk_n
;eieio();
576 par
->cmap_regs
[PIDXLO
] = PIXP0
; eieio();
577 par
->cmap_regs
[PIDXDATA
] = init
->pclk_p
;eieio();
578 par
->cmap_regs
[PIDXLO
] = PIXC0
; eieio();
579 par
->cmap_regs
[PIDXDATA
] = 0x02; eieio();
581 par
->cmap_regs
[PIDXLO
] = PIXFMT
; eieio();
582 par
->cmap_regs
[PIDXDATA
] = pformat
; eieio();
586 set_imstt_regvals_tvp (struct imstt_par
*par
, u_int bpp
)
588 struct imstt_regvals
*init
= &par
->init
;
589 __u8 tcc
, mxc
, lckl_n
, mic
;
599 lckl_p
= init
->lckl_p
[0];
606 lckl_p
= init
->lckl_p
[1];
613 lckl_p
= init
->lckl_p
[2];
620 lckl_p
= init
->lckl_p
[2];
625 par
->cmap_regs
[TVPADDRW
] = TVPIRPLA
; eieio();
626 par
->cmap_regs
[TVPIDATA
] = 0x00; eieio();
627 par
->cmap_regs
[TVPADDRW
] = TVPIRPPD
; eieio();
628 par
->cmap_regs
[TVPIDATA
] = init
->pclk_m
; eieio();
629 par
->cmap_regs
[TVPADDRW
] = TVPIRPPD
; eieio();
630 par
->cmap_regs
[TVPIDATA
] = init
->pclk_n
; eieio();
631 par
->cmap_regs
[TVPADDRW
] = TVPIRPPD
; eieio();
632 par
->cmap_regs
[TVPIDATA
] = init
->pclk_p
; eieio();
634 par
->cmap_regs
[TVPADDRW
] = TVPIRTCC
; eieio();
635 par
->cmap_regs
[TVPIDATA
] = tcc
; eieio();
636 par
->cmap_regs
[TVPADDRW
] = TVPIRMXC
; eieio();
637 par
->cmap_regs
[TVPIDATA
] = mxc
; eieio();
638 par
->cmap_regs
[TVPADDRW
] = TVPIRMIC
; eieio();
639 par
->cmap_regs
[TVPIDATA
] = mic
; eieio();
641 par
->cmap_regs
[TVPADDRW
] = TVPIRPLA
; eieio();
642 par
->cmap_regs
[TVPIDATA
] = 0x00; eieio();
643 par
->cmap_regs
[TVPADDRW
] = TVPIRLPD
; eieio();
644 par
->cmap_regs
[TVPIDATA
] = lckl_n
; eieio();
646 par
->cmap_regs
[TVPADDRW
] = TVPIRPLA
; eieio();
647 par
->cmap_regs
[TVPIDATA
] = 0x15; eieio();
648 par
->cmap_regs
[TVPADDRW
] = TVPIRMLC
; eieio();
649 par
->cmap_regs
[TVPIDATA
] = mlc
; eieio();
651 par
->cmap_regs
[TVPADDRW
] = TVPIRPLA
; eieio();
652 par
->cmap_regs
[TVPIDATA
] = 0x2a; eieio();
653 par
->cmap_regs
[TVPADDRW
] = TVPIRLPD
; eieio();
654 par
->cmap_regs
[TVPIDATA
] = lckl_p
; eieio();
658 set_imstt_regvals (struct fb_info
*info
, u_int bpp
)
660 struct imstt_par
*par
= info
->par
;
661 struct imstt_regvals
*init
= &par
->init
;
662 __u32 ctl
, pitch
, byteswap
, scr
;
664 if (par
->ramdac
== IBM
)
665 set_imstt_regvals_ibm(par
, bpp
);
667 set_imstt_regvals_tvp(par
, bpp
);
670 * From what I (jsk) can gather poking around with MacsBug,
671 * bits 8 and 9 in the SCR register control endianness
672 * correction (byte swapping). These bits must be set according
673 * to the color depth as follows:
674 * Color depth Bit 9 Bit 8
675 * ========== ===== =====
684 pitch
= init
->pitch
>> 2;
689 pitch
= init
->pitch
>> 1;
694 pitch
= init
->pitch
- (init
->pitch
>> 2);
703 if (par
->ramdac
== TVP
)
706 write_reg_le32(par
->dc_regs
, HES
, init
->hes
);
707 write_reg_le32(par
->dc_regs
, HEB
, init
->heb
);
708 write_reg_le32(par
->dc_regs
, HSB
, init
->hsb
);
709 write_reg_le32(par
->dc_regs
, HT
, init
->ht
);
710 write_reg_le32(par
->dc_regs
, VES
, init
->ves
);
711 write_reg_le32(par
->dc_regs
, VEB
, init
->veb
);
712 write_reg_le32(par
->dc_regs
, VSB
, init
->vsb
);
713 write_reg_le32(par
->dc_regs
, VT
, init
->vt
);
714 write_reg_le32(par
->dc_regs
, VIL
, init
->vil
);
715 write_reg_le32(par
->dc_regs
, HCIV
, 1);
716 write_reg_le32(par
->dc_regs
, VCIV
, 1);
717 write_reg_le32(par
->dc_regs
, TCDR
, 4);
718 write_reg_le32(par
->dc_regs
, RRCIV
, 1);
719 write_reg_le32(par
->dc_regs
, RRSC
, 0x980);
720 write_reg_le32(par
->dc_regs
, RRCR
, 0x11);
722 if (par
->ramdac
== IBM
) {
723 write_reg_le32(par
->dc_regs
, HRIR
, 0x0100);
724 write_reg_le32(par
->dc_regs
, CMR
, 0x00ff);
725 write_reg_le32(par
->dc_regs
, SRGCTL
, 0x0073);
727 write_reg_le32(par
->dc_regs
, HRIR
, 0x0200);
728 write_reg_le32(par
->dc_regs
, CMR
, 0x01ff);
729 write_reg_le32(par
->dc_regs
, SRGCTL
, 0x0003);
732 switch (info
->fix
.smem_len
) {
734 scr
= 0x059d | byteswap
;
740 scr
= 0x150dd | byteswap
;
744 write_reg_le32(par
->dc_regs
, SCR
, scr
);
745 write_reg_le32(par
->dc_regs
, SPR
, pitch
);
746 write_reg_le32(par
->dc_regs
, STGCTL
, ctl
);
750 set_offset (struct fb_var_screeninfo
*var
, struct fb_info
*info
)
752 struct imstt_par
*par
= info
->par
;
753 __u32 off
= var
->yoffset
* (info
->fix
.line_length
>> 3)
754 + ((var
->xoffset
* (var
->bits_per_pixel
>> 3)) >> 3);
755 write_reg_le32(par
->dc_regs
, SSR
, off
);
759 set_555 (struct imstt_par
*par
)
761 if (par
->ramdac
== IBM
) {
762 par
->cmap_regs
[PIDXHI
] = 0; eieio();
763 par
->cmap_regs
[PIDXLO
] = BPP16
; eieio();
764 par
->cmap_regs
[PIDXDATA
] = 0x01; eieio();
766 par
->cmap_regs
[TVPADDRW
] = TVPIRTCC
; eieio();
767 par
->cmap_regs
[TVPIDATA
] = 0x44; eieio();
772 set_565 (struct imstt_par
*par
)
774 if (par
->ramdac
== IBM
) {
775 par
->cmap_regs
[PIDXHI
] = 0; eieio();
776 par
->cmap_regs
[PIDXLO
] = BPP16
; eieio();
777 par
->cmap_regs
[PIDXDATA
] = 0x03; eieio();
779 par
->cmap_regs
[TVPADDRW
] = TVPIRTCC
; eieio();
780 par
->cmap_regs
[TVPIDATA
] = 0x45; eieio();
785 imsttfb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
787 if ((var
->bits_per_pixel
!= 8 && var
->bits_per_pixel
!= 16
788 && var
->bits_per_pixel
!= 24 && var
->bits_per_pixel
!= 32)
789 || var
->xres_virtual
< var
->xres
|| var
->yres_virtual
< var
->yres
791 || (var
->vmode
& FB_VMODE_MASK
) != FB_VMODE_NONINTERLACED
)
794 if ((var
->xres
* var
->yres
) * (var
->bits_per_pixel
>> 3) > info
->fix
.smem_len
795 || (var
->xres_virtual
* var
->yres_virtual
) * (var
->bits_per_pixel
>> 3) > info
->fix
.smem_len
)
798 switch (var
->bits_per_pixel
) {
802 var
->green
.offset
= 0;
803 var
->green
.length
= 8;
804 var
->blue
.offset
= 0;
805 var
->blue
.length
= 8;
806 var
->transp
.offset
= 0;
807 var
->transp
.length
= 0;
809 case 16: /* RGB 555 or 565 */
810 if (var
->green
.length
!= 6)
811 var
->red
.offset
= 10;
813 var
->green
.offset
= 5;
814 if (var
->green
.length
!= 6)
815 var
->green
.length
= 5;
816 var
->blue
.offset
= 0;
817 var
->blue
.length
= 5;
818 var
->transp
.offset
= 0;
819 var
->transp
.length
= 0;
821 case 24: /* RGB 888 */
822 var
->red
.offset
= 16;
824 var
->green
.offset
= 8;
825 var
->green
.length
= 8;
826 var
->blue
.offset
= 0;
827 var
->blue
.length
= 8;
828 var
->transp
.offset
= 0;
829 var
->transp
.length
= 0;
831 case 32: /* RGBA 8888 */
832 var
->red
.offset
= 16;
834 var
->green
.offset
= 8;
835 var
->green
.length
= 8;
836 var
->blue
.offset
= 0;
837 var
->blue
.length
= 8;
838 var
->transp
.offset
= 24;
839 var
->transp
.length
= 8;
843 if (var
->yres
== var
->yres_virtual
) {
844 __u32 vram
= (info
->fix
.smem_len
- (PAGE_SIZE
<< 2));
845 var
->yres_virtual
= ((vram
<< 3) / var
->bits_per_pixel
) / var
->xres_virtual
;
846 if (var
->yres_virtual
< var
->yres
)
847 var
->yres_virtual
= var
->yres
;
850 var
->red
.msb_right
= 0;
851 var
->green
.msb_right
= 0;
852 var
->blue
.msb_right
= 0;
853 var
->transp
.msb_right
= 0;
856 var
->vmode
= FB_VMODE_NONINTERLACED
;
857 var
->left_margin
= var
->right_margin
= 16;
858 var
->upper_margin
= var
->lower_margin
= 16;
859 var
->hsync_len
= var
->vsync_len
= 8;
864 imsttfb_set_par(struct fb_info
*info
)
866 struct imstt_par
*par
= info
->par
;
868 if (!compute_imstt_regvals(par
, info
->var
.xres
, info
->var
.yres
))
871 if (info
->var
.green
.length
== 6)
875 set_imstt_regvals(info
, info
->var
.bits_per_pixel
);
876 info
->var
.pixclock
= 1000000 / getclkMHz(par
);
881 imsttfb_setcolreg (u_int regno
, u_int red
, u_int green
, u_int blue
,
882 u_int transp
, struct fb_info
*info
)
884 struct imstt_par
*par
= info
->par
;
885 u_int bpp
= info
->var
.bits_per_pixel
;
894 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
895 if (0 && bpp
== 16) /* screws up X */
896 par
->cmap_regs
[PADDRW
] = regno
<< 3;
898 par
->cmap_regs
[PADDRW
] = regno
;
901 par
->cmap_regs
[PDATA
] = red
; eieio();
902 par
->cmap_regs
[PDATA
] = green
; eieio();
903 par
->cmap_regs
[PDATA
] = blue
; eieio();
908 par
->palette
[regno
] =
909 (regno
<< (info
->var
.green
.length
==
910 5 ? 10 : 11)) | (regno
<< 5) | regno
;
913 par
->palette
[regno
] =
914 (regno
<< 16) | (regno
<< 8) | regno
;
917 int i
= (regno
<< 8) | regno
;
918 par
->palette
[regno
] = (i
<< 16) |i
;
926 imsttfb_pan_display(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
928 if (var
->xoffset
+ info
->var
.xres
> info
->var
.xres_virtual
929 || var
->yoffset
+ info
->var
.yres
> info
->var
.yres_virtual
)
932 info
->var
.xoffset
= var
->xoffset
;
933 info
->var
.yoffset
= var
->yoffset
;
934 set_offset(var
, info
);
939 imsttfb_blank(int blank
, struct fb_info
*info
)
941 struct imstt_par
*par
= info
->par
;
944 ctrl
= read_reg_le32(par
->dc_regs
, STGCTL
);
947 case FB_BLANK_NORMAL
:
948 case FB_BLANK_POWERDOWN
:
950 if (par
->ramdac
== IBM
) {
951 par
->cmap_regs
[PIDXHI
] = 0; eieio();
952 par
->cmap_regs
[PIDXLO
] = MISCTL2
; eieio();
953 par
->cmap_regs
[PIDXDATA
] = 0x55; eieio();
954 par
->cmap_regs
[PIDXLO
] = MISCTL1
; eieio();
955 par
->cmap_regs
[PIDXDATA
] = 0x11; eieio();
956 par
->cmap_regs
[PIDXLO
] = SYNCCTL
; eieio();
957 par
->cmap_regs
[PIDXDATA
] = 0x0f; eieio();
958 par
->cmap_regs
[PIDXLO
] = PWRMNGMT
; eieio();
959 par
->cmap_regs
[PIDXDATA
] = 0x1f; eieio();
960 par
->cmap_regs
[PIDXLO
] = CLKCTL
; eieio();
961 par
->cmap_regs
[PIDXDATA
] = 0xc0;
964 case FB_BLANK_VSYNC_SUSPEND
:
967 case FB_BLANK_HSYNC_SUSPEND
:
972 if (par
->ramdac
== IBM
) {
974 par
->cmap_regs
[PIDXHI
] = 0; eieio();
975 par
->cmap_regs
[PIDXLO
] = CLKCTL
; eieio();
976 par
->cmap_regs
[PIDXDATA
] = 0x01; eieio();
977 par
->cmap_regs
[PIDXLO
] = PWRMNGMT
; eieio();
978 par
->cmap_regs
[PIDXDATA
] = 0x00; eieio();
979 par
->cmap_regs
[PIDXLO
] = SYNCCTL
; eieio();
980 par
->cmap_regs
[PIDXDATA
] = 0x00; eieio();
981 par
->cmap_regs
[PIDXLO
] = MISCTL1
; eieio();
982 par
->cmap_regs
[PIDXDATA
] = 0x01; eieio();
983 par
->cmap_regs
[PIDXLO
] = MISCTL2
; eieio();
984 par
->cmap_regs
[PIDXDATA
] = 0x45; eieio();
988 write_reg_le32(par
->dc_regs
, STGCTL
, ctrl
);
993 imsttfb_fillrect(struct fb_info
*info
, const struct fb_fillrect
*rect
)
995 struct imstt_par
*par
= info
->par
;
996 __u32 Bpp
, line_pitch
, bgc
, dx
, dy
, width
, height
;
1002 Bpp
= info
->var
.bits_per_pixel
>> 3,
1003 line_pitch
= info
->fix
.line_length
;
1005 dy
= rect
->dy
* line_pitch
;
1006 dx
= rect
->dx
* Bpp
;
1007 height
= rect
->height
;
1009 width
= rect
->width
* Bpp
;
1012 if (rect
->rop
== ROP_COPY
) {
1013 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x80);
1014 write_reg_le32(par
->dc_regs
, DSA
, dy
+ dx
);
1015 write_reg_le32(par
->dc_regs
, CNT
, (height
<< 16) | width
);
1016 write_reg_le32(par
->dc_regs
, DP_OCTL
, line_pitch
);
1017 write_reg_le32(par
->dc_regs
, BI
, 0xffffffff);
1018 write_reg_le32(par
->dc_regs
, MBC
, 0xffffffff);
1019 write_reg_le32(par
->dc_regs
, CLR
, bgc
);
1020 write_reg_le32(par
->dc_regs
, BLTCTL
, 0x840); /* 0x200000 */
1021 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x80);
1022 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x40);
1024 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x80);
1025 write_reg_le32(par
->dc_regs
, DSA
, dy
+ dx
);
1026 write_reg_le32(par
->dc_regs
, S1SA
, dy
+ dx
);
1027 write_reg_le32(par
->dc_regs
, CNT
, (height
<< 16) | width
);
1028 write_reg_le32(par
->dc_regs
, DP_OCTL
, line_pitch
);
1029 write_reg_le32(par
->dc_regs
, SP
, line_pitch
);
1030 write_reg_le32(par
->dc_regs
, BLTCTL
, 0x40005);
1031 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x80);
1032 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x40);
1037 imsttfb_copyarea(struct fb_info
*info
, const struct fb_copyarea
*area
)
1039 struct imstt_par
*par
= info
->par
;
1040 __u32 Bpp
, line_pitch
, fb_offset_old
, fb_offset_new
, sp
, dp_octl
;
1041 __u32 cnt
, bltctl
, sx
, sy
, dx
, dy
, height
, width
;
1043 Bpp
= info
->var
.bits_per_pixel
>> 3,
1045 sx
= area
->sx
* Bpp
;
1047 dx
= area
->dx
* Bpp
;
1049 height
= area
->height
;
1051 width
= area
->width
* Bpp
;
1054 line_pitch
= info
->fix
.line_length
;
1056 sp
= line_pitch
<< 16;
1062 sp
|= -(line_pitch
) & 0xffff;
1063 dp_octl
= -(line_pitch
) & 0xffff;
1066 dp_octl
= line_pitch
;
1072 cnt
|= -(width
) & 0xffff;
1076 fb_offset_old
= sy
* line_pitch
+ sx
;
1077 fb_offset_new
= dy
* line_pitch
+ dx
;
1079 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x80);
1080 write_reg_le32(par
->dc_regs
, S1SA
, fb_offset_old
);
1081 write_reg_le32(par
->dc_regs
, SP
, sp
);
1082 write_reg_le32(par
->dc_regs
, DSA
, fb_offset_new
);
1083 write_reg_le32(par
->dc_regs
, CNT
, cnt
);
1084 write_reg_le32(par
->dc_regs
, DP_OCTL
, dp_octl
);
1085 write_reg_le32(par
->dc_regs
, BLTCTL
, bltctl
);
1086 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x80);
1087 while(read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x40);
1092 imsttfb_load_cursor_image(struct imstt_par
*par
, int width
, int height
, __u8 fgc
)
1096 if (width
> 32 || height
> 32)
1099 if (par
->ramdac
== IBM
) {
1100 par
->cmap_regs
[PIDXHI
] = 1; eieio();
1101 for (x
= 0; x
< 0x100; x
++) {
1102 par
->cmap_regs
[PIDXLO
] = x
; eieio();
1103 par
->cmap_regs
[PIDXDATA
] = 0x00; eieio();
1105 par
->cmap_regs
[PIDXHI
] = 1; eieio();
1106 for (y
= 0; y
< height
; y
++)
1107 for (x
= 0; x
< width
>> 2; x
++) {
1108 par
->cmap_regs
[PIDXLO
] = x
+ y
* 8; eieio();
1109 par
->cmap_regs
[PIDXDATA
] = 0xff; eieio();
1111 par
->cmap_regs
[PIDXHI
] = 0; eieio();
1112 par
->cmap_regs
[PIDXLO
] = CURS1R
; eieio();
1113 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1114 par
->cmap_regs
[PIDXLO
] = CURS1G
; eieio();
1115 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1116 par
->cmap_regs
[PIDXLO
] = CURS1B
; eieio();
1117 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1118 par
->cmap_regs
[PIDXLO
] = CURS2R
; eieio();
1119 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1120 par
->cmap_regs
[PIDXLO
] = CURS2G
; eieio();
1121 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1122 par
->cmap_regs
[PIDXLO
] = CURS2B
; eieio();
1123 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1124 par
->cmap_regs
[PIDXLO
] = CURS3R
; eieio();
1125 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1126 par
->cmap_regs
[PIDXLO
] = CURS3G
; eieio();
1127 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1128 par
->cmap_regs
[PIDXLO
] = CURS3B
; eieio();
1129 par
->cmap_regs
[PIDXDATA
] = fgc
; eieio();
1131 par
->cmap_regs
[TVPADDRW
] = TVPIRICC
; eieio();
1132 par
->cmap_regs
[TVPIDATA
] &= 0x03; eieio();
1133 par
->cmap_regs
[TVPADDRW
] = 0; eieio();
1134 for (x
= 0; x
< 0x200; x
++) {
1135 par
->cmap_regs
[TVPCRDAT
] = 0x00; eieio();
1137 for (x
= 0; x
< 0x200; x
++) {
1138 par
->cmap_regs
[TVPCRDAT
] = 0xff; eieio();
1140 par
->cmap_regs
[TVPADDRW
] = TVPIRICC
; eieio();
1141 par
->cmap_regs
[TVPIDATA
] &= 0x03; eieio();
1142 for (y
= 0; y
< height
; y
++)
1143 for (x
= 0; x
< width
>> 3; x
++) {
1144 par
->cmap_regs
[TVPADDRW
] = x
+ y
* 8; eieio();
1145 par
->cmap_regs
[TVPCRDAT
] = 0xff; eieio();
1147 par
->cmap_regs
[TVPADDRW
] = TVPIRICC
; eieio();
1148 par
->cmap_regs
[TVPIDATA
] |= 0x08; eieio();
1149 for (y
= 0; y
< height
; y
++)
1150 for (x
= 0; x
< width
>> 3; x
++) {
1151 par
->cmap_regs
[TVPADDRW
] = x
+ y
* 8; eieio();
1152 par
->cmap_regs
[TVPCRDAT
] = 0xff; eieio();
1154 par
->cmap_regs
[TVPCADRW
] = 0x00; eieio();
1155 for (x
= 0; x
< 12; x
++)
1156 par
->cmap_regs
[TVPCDATA
] = fgc
; eieio();
1162 imstt_set_cursor(struct imstt_par
*par
, struct fb_image
*d
, int on
)
1164 if (par
->ramdac
== IBM
) {
1165 par
->cmap_regs
[PIDXHI
] = 0; eieio();
1167 par
->cmap_regs
[PIDXLO
] = CURSCTL
; eieio();
1168 par
->cmap_regs
[PIDXDATA
] = 0x00; eieio();
1170 par
->cmap_regs
[PIDXLO
] = CURSXHI
; eieio();
1171 par
->cmap_regs
[PIDXDATA
] = d
->dx
>> 8; eieio();
1172 par
->cmap_regs
[PIDXLO
] = CURSXLO
; eieio();
1173 par
->cmap_regs
[PIDXDATA
] = d
->dx
& 0xff;eieio();
1174 par
->cmap_regs
[PIDXLO
] = CURSYHI
; eieio();
1175 par
->cmap_regs
[PIDXDATA
] = d
->dy
>> 8; eieio();
1176 par
->cmap_regs
[PIDXLO
] = CURSYLO
; eieio();
1177 par
->cmap_regs
[PIDXDATA
] = d
->dy
& 0xff;eieio();
1178 par
->cmap_regs
[PIDXLO
] = CURSCTL
; eieio();
1179 par
->cmap_regs
[PIDXDATA
] = 0x02; eieio();
1183 par
->cmap_regs
[TVPADDRW
] = TVPIRICC
; eieio();
1184 par
->cmap_regs
[TVPIDATA
] = 0x00; eieio();
1186 __u16 x
= d
->dx
+ 0x40, y
= d
->dy
+ 0x40;
1188 par
->cmap_regs
[TVPCXPOH
] = x
>> 8; eieio();
1189 par
->cmap_regs
[TVPCXPOL
] = x
& 0xff; eieio();
1190 par
->cmap_regs
[TVPCYPOH
] = y
>> 8; eieio();
1191 par
->cmap_regs
[TVPCYPOL
] = y
& 0xff; eieio();
1192 par
->cmap_regs
[TVPADDRW
] = TVPIRICC
; eieio();
1193 par
->cmap_regs
[TVPIDATA
] = 0x02; eieio();
1199 imsttfb_cursor(struct fb_info
*info
, struct fb_cursor
*cursor
)
1201 struct imstt_par
*par
= info
->par
;
1202 u32 flags
= cursor
->set
, fg
, bg
, xx
, yy
;
1204 if (cursor
->dest
== NULL
&& cursor
->rop
== ROP_XOR
)
1207 imstt_set_cursor(info
, cursor
, 0);
1209 if (flags
& FB_CUR_SETPOS
) {
1210 xx
= cursor
->image
.dx
- info
->var
.xoffset
;
1211 yy
= cursor
->image
.dy
- info
->var
.yoffset
;
1214 if (flags
& FB_CUR_SETSIZE
) {
1217 if (flags
& (FB_CUR_SETSHAPE
| FB_CUR_SETCMAP
)) {
1218 int fg_idx
= cursor
->image
.fg_color
;
1219 int width
= (cursor
->image
.width
+7)/8;
1220 u8
*dat
= (u8
*) cursor
->image
.data
;
1221 u8
*dst
= (u8
*) cursor
->dest
;
1222 u8
*msk
= (u8
*) cursor
->mask
;
1224 switch (cursor
->rop
) {
1226 for (i
= 0; i
< cursor
->image
.height
; i
++) {
1227 for (j
= 0; j
< width
; j
++) {
1228 d_idx
= i
* MAX_CURS
/8 + j
;
1229 data
[d_idx
] = byte_rev
[dat
[s_idx
] ^
1231 mask
[d_idx
] = byte_rev
[msk
[s_idx
]];
1238 for (i
= 0; i
< cursor
->image
.height
; i
++) {
1239 for (j
= 0; j
< width
; j
++) {
1240 d_idx
= i
* MAX_CURS
/8 + j
;
1241 data
[d_idx
] = byte_rev
[dat
[s_idx
]];
1242 mask
[d_idx
] = byte_rev
[msk
[s_idx
]];
1249 fg
= ((info
->cmap
.red
[fg_idx
] & 0xf8) << 7) |
1250 ((info
->cmap
.green
[fg_idx
] & 0xf8) << 2) |
1251 ((info
->cmap
.blue
[fg_idx
] & 0xf8) >> 3) | 1 << 15;
1253 imsttfb_load_cursor_image(par
, xx
, yy
, fgc
);
1256 imstt_set_cursor(info
, cursor
, 1);
1261 #define FBIMSTT_SETREG 0x545401
1262 #define FBIMSTT_GETREG 0x545402
1263 #define FBIMSTT_SETCMAPREG 0x545403
1264 #define FBIMSTT_GETCMAPREG 0x545404
1265 #define FBIMSTT_SETIDXREG 0x545405
1266 #define FBIMSTT_GETIDXREG 0x545406
1269 imsttfb_ioctl(struct fb_info
*info
, u_int cmd
, u_long arg
)
1271 struct imstt_par
*par
= info
->par
;
1272 void __user
*argp
= (void __user
*)arg
;
1277 case FBIMSTT_SETREG
:
1278 if (copy_from_user(reg
, argp
, 8) || reg
[0] > (0x1000 - sizeof(reg
[0])) / sizeof(reg
[0]))
1280 write_reg_le32(par
->dc_regs
, reg
[0], reg
[1]);
1282 case FBIMSTT_GETREG
:
1283 if (copy_from_user(reg
, argp
, 4) || reg
[0] > (0x1000 - sizeof(reg
[0])) / sizeof(reg
[0]))
1285 reg
[1] = read_reg_le32(par
->dc_regs
, reg
[0]);
1286 if (copy_to_user((void __user
*)(arg
+ 4), ®
[1], 4))
1289 case FBIMSTT_SETCMAPREG
:
1290 if (copy_from_user(reg
, argp
, 8) || reg
[0] > (0x1000 - sizeof(reg
[0])) / sizeof(reg
[0]))
1292 write_reg_le32(((u_int __iomem
*)par
->cmap_regs
), reg
[0], reg
[1]);
1294 case FBIMSTT_GETCMAPREG
:
1295 if (copy_from_user(reg
, argp
, 4) || reg
[0] > (0x1000 - sizeof(reg
[0])) / sizeof(reg
[0]))
1297 reg
[1] = read_reg_le32(((u_int __iomem
*)par
->cmap_regs
), reg
[0]);
1298 if (copy_to_user((void __user
*)(arg
+ 4), ®
[1], 4))
1301 case FBIMSTT_SETIDXREG
:
1302 if (copy_from_user(idx
, argp
, 2))
1304 par
->cmap_regs
[PIDXHI
] = 0; eieio();
1305 par
->cmap_regs
[PIDXLO
] = idx
[0]; eieio();
1306 par
->cmap_regs
[PIDXDATA
] = idx
[1]; eieio();
1308 case FBIMSTT_GETIDXREG
:
1309 if (copy_from_user(idx
, argp
, 1))
1311 par
->cmap_regs
[PIDXHI
] = 0; eieio();
1312 par
->cmap_regs
[PIDXLO
] = idx
[0]; eieio();
1313 idx
[1] = par
->cmap_regs
[PIDXDATA
];
1314 if (copy_to_user((void __user
*)(arg
+ 1), &idx
[1], 1))
1318 return -ENOIOCTLCMD
;
1322 static struct pci_device_id imsttfb_pci_tbl
[] = {
1323 { PCI_VENDOR_ID_IMS
, PCI_DEVICE_ID_IMS_TT128
,
1324 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, IBM
},
1325 { PCI_VENDOR_ID_IMS
, PCI_DEVICE_ID_IMS_TT3D
,
1326 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, TVP
},
1330 MODULE_DEVICE_TABLE(pci
, imsttfb_pci_tbl
);
1332 static struct pci_driver imsttfb_pci_driver
= {
1334 .id_table
= imsttfb_pci_tbl
,
1335 .probe
= imsttfb_probe
,
1336 .remove
= __devexit_p(imsttfb_remove
),
1339 static struct fb_ops imsttfb_ops
= {
1340 .owner
= THIS_MODULE
,
1341 .fb_check_var
= imsttfb_check_var
,
1342 .fb_set_par
= imsttfb_set_par
,
1343 .fb_setcolreg
= imsttfb_setcolreg
,
1344 .fb_pan_display
= imsttfb_pan_display
,
1345 .fb_blank
= imsttfb_blank
,
1346 .fb_fillrect
= imsttfb_fillrect
,
1347 .fb_copyarea
= imsttfb_copyarea
,
1348 .fb_imageblit
= cfb_imageblit
,
1349 .fb_ioctl
= imsttfb_ioctl
,
1352 static void __devinit
1353 init_imstt(struct fb_info
*info
)
1355 struct imstt_par
*par
= info
->par
;
1356 __u32 i
, tmp
, *ip
, *end
;
1358 tmp
= read_reg_le32(par
->dc_regs
, PRC
);
1359 if (par
->ramdac
== IBM
)
1360 info
->fix
.smem_len
= (tmp
& 0x0004) ? 0x400000 : 0x200000;
1362 info
->fix
.smem_len
= 0x800000;
1364 ip
= (__u32
*)info
->screen_base
;
1365 end
= (__u32
*)(info
->screen_base
+ info
->fix
.smem_len
);
1369 /* initialize the card */
1370 tmp
= read_reg_le32(par
->dc_regs
, STGCTL
);
1371 write_reg_le32(par
->dc_regs
, STGCTL
, tmp
& ~0x1);
1372 write_reg_le32(par
->dc_regs
, SSR
, 0);
1374 /* set default values for DAC registers */
1375 if (par
->ramdac
== IBM
) {
1376 par
->cmap_regs
[PPMASK
] = 0xff;
1378 par
->cmap_regs
[PIDXHI
] = 0;
1380 for (i
= 0; i
< ARRAY_SIZE(ibm_initregs
); i
++) {
1381 par
->cmap_regs
[PIDXLO
] = ibm_initregs
[i
].addr
;
1383 par
->cmap_regs
[PIDXDATA
] = ibm_initregs
[i
].value
;
1387 for (i
= 0; i
< ARRAY_SIZE(tvp_initregs
); i
++) {
1388 par
->cmap_regs
[TVPADDRW
] = tvp_initregs
[i
].addr
;
1390 par
->cmap_regs
[TVPIDATA
] = tvp_initregs
[i
].value
;
1395 #if USE_NV_MODES && defined(CONFIG_PPC)
1397 int vmode
= init_vmode
, cmode
= init_cmode
;
1400 vmode
= nvram_read_byte(NV_VMODE
);
1401 if (vmode
<= 0 || vmode
> VMODE_MAX
)
1402 vmode
= VMODE_640_480_67
;
1405 cmode
= nvram_read_byte(NV_CMODE
);
1406 if (cmode
< CMODE_8
|| cmode
> CMODE_32
)
1409 if (mac_vmode_to_var(vmode
, cmode
, &info
->var
)) {
1410 info
->var
.xres
= info
->var
.xres_virtual
= INIT_XRES
;
1411 info
->var
.yres
= info
->var
.yres_virtual
= INIT_YRES
;
1412 info
->var
.bits_per_pixel
= INIT_BPP
;
1416 info
->var
.xres
= info
->var
.xres_virtual
= INIT_XRES
;
1417 info
->var
.yres
= info
->var
.yres_virtual
= INIT_YRES
;
1418 info
->var
.bits_per_pixel
= INIT_BPP
;
1421 if ((info
->var
.xres
* info
->var
.yres
) * (info
->var
.bits_per_pixel
>> 3) > info
->fix
.smem_len
1422 || !(compute_imstt_regvals(par
, info
->var
.xres
, info
->var
.yres
))) {
1423 printk("imsttfb: %ux%ux%u not supported\n", info
->var
.xres
, info
->var
.yres
, info
->var
.bits_per_pixel
);
1424 framebuffer_release(info
);
1428 sprintf(info
->fix
.id
, "IMS TT (%s)", par
->ramdac
== IBM
? "IBM" : "TVP");
1429 info
->fix
.mmio_len
= 0x1000;
1430 info
->fix
.accel
= FB_ACCEL_IMS_TWINTURBO
;
1431 info
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
1432 info
->fix
.visual
= info
->var
.bits_per_pixel
== 8 ? FB_VISUAL_PSEUDOCOLOR
1433 : FB_VISUAL_DIRECTCOLOR
;
1434 info
->fix
.line_length
= info
->var
.xres
* (info
->var
.bits_per_pixel
>> 3);
1435 info
->fix
.xpanstep
= 8;
1436 info
->fix
.ypanstep
= 1;
1437 info
->fix
.ywrapstep
= 0;
1439 info
->var
.accel_flags
= FB_ACCELF_TEXT
;
1441 // if (par->ramdac == IBM)
1442 // imstt_cursor_init(info);
1443 if (info
->var
.green
.length
== 6)
1447 set_imstt_regvals(info
, info
->var
.bits_per_pixel
);
1449 info
->var
.pixclock
= 1000000 / getclkMHz(par
);
1451 info
->fbops
= &imsttfb_ops
;
1452 info
->flags
= FBINFO_DEFAULT
|
1453 FBINFO_HWACCEL_COPYAREA
|
1454 FBINFO_HWACCEL_FILLRECT
|
1455 FBINFO_HWACCEL_YPAN
;
1457 fb_alloc_cmap(&info
->cmap
, 0, 0);
1459 if (register_framebuffer(info
) < 0) {
1460 framebuffer_release(info
);
1464 tmp
= (read_reg_le32(par
->dc_regs
, SSTATUS
) & 0x0f00) >> 8;
1465 printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1466 info
->node
, info
->fix
.id
, info
->fix
.smem_len
>> 20, tmp
);
1469 static int __devinit
1470 imsttfb_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1472 unsigned long addr
, size
;
1473 struct imstt_par
*par
;
1474 struct fb_info
*info
;
1475 #ifdef CONFIG_PPC_OF
1476 struct device_node
*dp
;
1478 dp
= pci_device_to_OF_node(pdev
);
1480 printk(KERN_INFO
"%s: OF name %s\n",__FUNCTION__
, dp
->name
);
1482 printk(KERN_ERR
"imsttfb: no OF node for pci device\n");
1483 #endif /* CONFIG_PPC_OF */
1485 info
= framebuffer_alloc(sizeof(struct imstt_par
), &pdev
->dev
);
1488 printk(KERN_ERR
"imsttfb: Can't allocate memory\n");
1494 addr
= pci_resource_start (pdev
, 0);
1495 size
= pci_resource_len (pdev
, 0);
1497 if (!request_mem_region(addr
, size
, "imsttfb")) {
1498 printk(KERN_ERR
"imsttfb: Can't reserve memory region\n");
1499 framebuffer_release(info
);
1503 switch (pdev
->device
) {
1504 case PCI_DEVICE_ID_IMS_TT128
: /* IMS,tt128mbA */
1506 #ifdef CONFIG_PPC_OF
1507 if (dp
&& ((strcmp(dp
->name
, "IMS,tt128mb8") == 0) ||
1508 (strcmp(dp
->name
, "IMS,tt128mb8A") == 0)))
1510 #endif /* CONFIG_PPC_OF */
1512 case PCI_DEVICE_ID_IMS_TT3D
: /* IMS,tt3d */
1516 printk(KERN_INFO
"imsttfb: Device 0x%x unknown, "
1517 "contact maintainer.\n", pdev
->device
);
1518 release_mem_region(addr
, size
);
1519 framebuffer_release(info
);
1523 info
->fix
.smem_start
= addr
;
1524 info
->screen_base
= (__u8
*)ioremap(addr
, par
->ramdac
== IBM
?
1525 0x400000 : 0x800000);
1526 info
->fix
.mmio_start
= addr
+ 0x800000;
1527 par
->dc_regs
= ioremap(addr
+ 0x800000, 0x1000);
1528 par
->cmap_regs_phys
= addr
+ 0x840000;
1529 par
->cmap_regs
= (__u8
*)ioremap(addr
+ 0x840000, 0x1000);
1530 info
->pseudo_palette
= par
->palette
;
1533 pci_set_drvdata(pdev
, info
);
1537 static void __devexit
1538 imsttfb_remove(struct pci_dev
*pdev
)
1540 struct fb_info
*info
= pci_get_drvdata(pdev
);
1541 struct imstt_par
*par
= info
->par
;
1542 int size
= pci_resource_len(pdev
, 0);
1544 unregister_framebuffer(info
);
1545 iounmap(par
->cmap_regs
);
1546 iounmap(par
->dc_regs
);
1547 iounmap(info
->screen_base
);
1548 release_mem_region(info
->fix
.smem_start
, size
);
1549 framebuffer_release(info
);
1554 imsttfb_setup(char *options
)
1558 if (!options
|| !*options
)
1561 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1562 if (!strncmp(this_opt
, "font:", 5)) {
1567 for (i
= 0; i
< sizeof(fontname
) - 1; i
++)
1568 if (!*p
|| *p
== ' ' || *p
== ',')
1570 memcpy(fontname
, this_opt
+ 5, i
);
1572 } else if (!strncmp(this_opt
, "inverse", 7)) {
1576 #if defined(CONFIG_PPC)
1577 else if (!strncmp(this_opt
, "vmode:", 6)) {
1578 int vmode
= simple_strtoul(this_opt
+6, NULL
, 0);
1579 if (vmode
> 0 && vmode
<= VMODE_MAX
)
1581 } else if (!strncmp(this_opt
, "cmode:", 6)) {
1582 int cmode
= simple_strtoul(this_opt
+6, NULL
, 0);
1586 init_cmode
= CMODE_8
;
1591 init_cmode
= CMODE_16
;
1596 init_cmode
= CMODE_32
;
1607 static int __init
imsttfb_init(void)
1610 char *option
= NULL
;
1612 if (fb_get_options("imsttfb", &option
))
1615 imsttfb_setup(option
);
1617 return pci_register_driver(&imsttfb_pci_driver
);
1620 static void __exit
imsttfb_exit(void)
1622 pci_unregister_driver(&imsttfb_pci_driver
);
1625 MODULE_LICENSE("GPL");
1627 module_init(imsttfb_init
);
1628 module_exit(imsttfb_exit
);