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[mirror_ubuntu-artful-kernel.git] / drivers / video / intelfb / intelfbhw.c
1 /*
2 * intelfb
3 *
4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5 *
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
7 * 2004 Sylvain Meyer
8 *
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
15 *
16 * Author: David Dawes
17 *
18 */
19
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/string.h>
26 #include <linux/mm.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/fb.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/pci.h>
33 #include <linux/vmalloc.h>
34 #include <linux/pagemap.h>
35
36 #include <asm/io.h>
37
38 #include "intelfb.h"
39 #include "intelfbhw.h"
40
41 struct pll_min_max {
42 int min_m, max_m, min_m1, max_m1;
43 int min_m2, max_m2, min_n, max_n;
44 int min_p, max_p, min_p1, max_p1;
45 int min_vco, max_vco, p_transition_clk, ref_clk;
46 int p_inc_lo, p_inc_hi;
47 };
48
49 #define PLLS_I8xx 0
50 #define PLLS_I9xx 1
51 #define PLLS_MAX 2
52
53 static struct pll_min_max plls[PLLS_MAX] = {
54 { 108, 140, 18, 26,
55 6, 16, 3, 16,
56 4, 128, 0, 31,
57 930000, 1400000, 165000, 48000,
58 4, 2 }, //I8xx
59
60 { 75, 120, 10, 20,
61 5, 9, 4, 7,
62 5, 80, 1, 8,
63 1400000, 2800000, 200000, 96000,
64 10, 5 } //I9xx
65 };
66
67 int
68 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
69 {
70 u32 tmp;
71 if (!pdev || !dinfo)
72 return 1;
73
74 switch (pdev->device) {
75 case PCI_DEVICE_ID_INTEL_830M:
76 dinfo->name = "Intel(R) 830M";
77 dinfo->chipset = INTEL_830M;
78 dinfo->mobile = 1;
79 dinfo->pll_index = PLLS_I8xx;
80 return 0;
81 case PCI_DEVICE_ID_INTEL_845G:
82 dinfo->name = "Intel(R) 845G";
83 dinfo->chipset = INTEL_845G;
84 dinfo->mobile = 0;
85 dinfo->pll_index = PLLS_I8xx;
86 return 0;
87 case PCI_DEVICE_ID_INTEL_85XGM:
88 tmp = 0;
89 dinfo->mobile = 1;
90 dinfo->pll_index = PLLS_I8xx;
91 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
92 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
93 INTEL_85X_VARIANT_MASK) {
94 case INTEL_VAR_855GME:
95 dinfo->name = "Intel(R) 855GME";
96 dinfo->chipset = INTEL_855GME;
97 return 0;
98 case INTEL_VAR_855GM:
99 dinfo->name = "Intel(R) 855GM";
100 dinfo->chipset = INTEL_855GM;
101 return 0;
102 case INTEL_VAR_852GME:
103 dinfo->name = "Intel(R) 852GME";
104 dinfo->chipset = INTEL_852GME;
105 return 0;
106 case INTEL_VAR_852GM:
107 dinfo->name = "Intel(R) 852GM";
108 dinfo->chipset = INTEL_852GM;
109 return 0;
110 default:
111 dinfo->name = "Intel(R) 852GM/855GM";
112 dinfo->chipset = INTEL_85XGM;
113 return 0;
114 }
115 break;
116 case PCI_DEVICE_ID_INTEL_865G:
117 dinfo->name = "Intel(R) 865G";
118 dinfo->chipset = INTEL_865G;
119 dinfo->mobile = 0;
120 dinfo->pll_index = PLLS_I8xx;
121 return 0;
122 case PCI_DEVICE_ID_INTEL_915G:
123 dinfo->name = "Intel(R) 915G";
124 dinfo->chipset = INTEL_915G;
125 dinfo->mobile = 0;
126 dinfo->pll_index = PLLS_I9xx;
127 return 0;
128 case PCI_DEVICE_ID_INTEL_915GM:
129 dinfo->name = "Intel(R) 915GM";
130 dinfo->chipset = INTEL_915GM;
131 dinfo->mobile = 1;
132 dinfo->pll_index = PLLS_I9xx;
133 return 0;
134 case PCI_DEVICE_ID_INTEL_945G:
135 dinfo->name = "Intel(R) 945G";
136 dinfo->chipset = INTEL_945G;
137 dinfo->mobile = 0;
138 dinfo->pll_index = PLLS_I9xx;
139 return 0;
140 case PCI_DEVICE_ID_INTEL_945GM:
141 dinfo->name = "Intel(R) 945GM";
142 dinfo->chipset = INTEL_945GM;
143 dinfo->mobile = 1;
144 dinfo->pll_index = PLLS_I9xx;
145 return 0;
146 default:
147 return 1;
148 }
149 }
150
151 int
152 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
153 int *stolen_size)
154 {
155 struct pci_dev *bridge_dev;
156 u16 tmp;
157 int stolen_overhead;
158
159 if (!pdev || !aperture_size || !stolen_size)
160 return 1;
161
162 /* Find the bridge device. It is always 0:0.0 */
163 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
164 ERR_MSG("cannot find bridge device\n");
165 return 1;
166 }
167
168 /* Get the fb aperture size and "stolen" memory amount. */
169 tmp = 0;
170 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
171 switch (pdev->device) {
172 case PCI_DEVICE_ID_INTEL_915G:
173 case PCI_DEVICE_ID_INTEL_915GM:
174 case PCI_DEVICE_ID_INTEL_945G:
175 case PCI_DEVICE_ID_INTEL_945GM:
176 /* 915 and 945 chipsets support a 256MB aperture.
177 Aperture size is determined by inspected the
178 base address of the aperture. */
179 if (pci_resource_start(pdev, 2) & 0x08000000)
180 *aperture_size = MB(128);
181 else
182 *aperture_size = MB(256);
183 break;
184 default:
185 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
186 *aperture_size = MB(64);
187 else
188 *aperture_size = MB(128);
189 break;
190 }
191
192 /* Stolen memory size is reduced by the GTT and the popup.
193 GTT is 1K per MB of aperture size, and popup is 4K. */
194 stolen_overhead = (*aperture_size / MB(1)) + 4;
195 switch(pdev->device) {
196 case PCI_DEVICE_ID_INTEL_830M:
197 case PCI_DEVICE_ID_INTEL_845G:
198 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
199 case INTEL_830_GMCH_GMS_STOLEN_512:
200 *stolen_size = KB(512) - KB(stolen_overhead);
201 return 0;
202 case INTEL_830_GMCH_GMS_STOLEN_1024:
203 *stolen_size = MB(1) - KB(stolen_overhead);
204 return 0;
205 case INTEL_830_GMCH_GMS_STOLEN_8192:
206 *stolen_size = MB(8) - KB(stolen_overhead);
207 return 0;
208 case INTEL_830_GMCH_GMS_LOCAL:
209 ERR_MSG("only local memory found\n");
210 return 1;
211 case INTEL_830_GMCH_GMS_DISABLED:
212 ERR_MSG("video memory is disabled\n");
213 return 1;
214 default:
215 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
216 tmp & INTEL_830_GMCH_GMS_MASK);
217 return 1;
218 }
219 break;
220 default:
221 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
222 case INTEL_855_GMCH_GMS_STOLEN_1M:
223 *stolen_size = MB(1) - KB(stolen_overhead);
224 return 0;
225 case INTEL_855_GMCH_GMS_STOLEN_4M:
226 *stolen_size = MB(4) - KB(stolen_overhead);
227 return 0;
228 case INTEL_855_GMCH_GMS_STOLEN_8M:
229 *stolen_size = MB(8) - KB(stolen_overhead);
230 return 0;
231 case INTEL_855_GMCH_GMS_STOLEN_16M:
232 *stolen_size = MB(16) - KB(stolen_overhead);
233 return 0;
234 case INTEL_855_GMCH_GMS_STOLEN_32M:
235 *stolen_size = MB(32) - KB(stolen_overhead);
236 return 0;
237 case INTEL_915G_GMCH_GMS_STOLEN_48M:
238 *stolen_size = MB(48) - KB(stolen_overhead);
239 return 0;
240 case INTEL_915G_GMCH_GMS_STOLEN_64M:
241 *stolen_size = MB(64) - KB(stolen_overhead);
242 return 0;
243 case INTEL_855_GMCH_GMS_DISABLED:
244 ERR_MSG("video memory is disabled\n");
245 return 0;
246 default:
247 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
248 tmp & INTEL_855_GMCH_GMS_MASK);
249 return 1;
250 }
251 }
252 }
253
254 int
255 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
256 {
257 int dvo = 0;
258
259 if (INREG(LVDS) & PORT_ENABLE)
260 dvo |= LVDS_PORT;
261 if (INREG(DVOA) & PORT_ENABLE)
262 dvo |= DVOA_PORT;
263 if (INREG(DVOB) & PORT_ENABLE)
264 dvo |= DVOB_PORT;
265 if (INREG(DVOC) & PORT_ENABLE)
266 dvo |= DVOC_PORT;
267
268 return dvo;
269 }
270
271 const char *
272 intelfbhw_dvo_to_string(int dvo)
273 {
274 if (dvo & DVOA_PORT)
275 return "DVO port A";
276 else if (dvo & DVOB_PORT)
277 return "DVO port B";
278 else if (dvo & DVOC_PORT)
279 return "DVO port C";
280 else if (dvo & LVDS_PORT)
281 return "LVDS port";
282 else
283 return NULL;
284 }
285
286
287 int
288 intelfbhw_validate_mode(struct intelfb_info *dinfo,
289 struct fb_var_screeninfo *var)
290 {
291 int bytes_per_pixel;
292 int tmp;
293
294 #if VERBOSE > 0
295 DBG_MSG("intelfbhw_validate_mode\n");
296 #endif
297
298 bytes_per_pixel = var->bits_per_pixel / 8;
299 if (bytes_per_pixel == 3)
300 bytes_per_pixel = 4;
301
302 /* Check if enough video memory. */
303 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
304 if (tmp > dinfo->fb.size) {
305 WRN_MSG("Not enough video ram for mode "
306 "(%d KByte vs %d KByte).\n",
307 BtoKB(tmp), BtoKB(dinfo->fb.size));
308 return 1;
309 }
310
311 /* Check if x/y limits are OK. */
312 if (var->xres - 1 > HACTIVE_MASK) {
313 WRN_MSG("X resolution too large (%d vs %d).\n",
314 var->xres, HACTIVE_MASK + 1);
315 return 1;
316 }
317 if (var->yres - 1 > VACTIVE_MASK) {
318 WRN_MSG("Y resolution too large (%d vs %d).\n",
319 var->yres, VACTIVE_MASK + 1);
320 return 1;
321 }
322
323 /* Check for interlaced/doublescan modes. */
324 if (var->vmode & FB_VMODE_INTERLACED) {
325 WRN_MSG("Mode is interlaced.\n");
326 return 1;
327 }
328 if (var->vmode & FB_VMODE_DOUBLE) {
329 WRN_MSG("Mode is double-scan.\n");
330 return 1;
331 }
332
333 /* Check if clock is OK. */
334 tmp = 1000000000 / var->pixclock;
335 if (tmp < MIN_CLOCK) {
336 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
337 (tmp + 500) / 1000, MIN_CLOCK / 1000);
338 return 1;
339 }
340 if (tmp > MAX_CLOCK) {
341 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
342 (tmp + 500) / 1000, MAX_CLOCK / 1000);
343 return 1;
344 }
345
346 return 0;
347 }
348
349 int
350 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
351 {
352 struct intelfb_info *dinfo = GET_DINFO(info);
353 u32 offset, xoffset, yoffset;
354
355 #if VERBOSE > 0
356 DBG_MSG("intelfbhw_pan_display\n");
357 #endif
358
359 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
360 yoffset = var->yoffset;
361
362 if ((xoffset + var->xres > var->xres_virtual) ||
363 (yoffset + var->yres > var->yres_virtual))
364 return -EINVAL;
365
366 offset = (yoffset * dinfo->pitch) +
367 (xoffset * var->bits_per_pixel) / 8;
368
369 offset += dinfo->fb.offset << 12;
370
371 OUTREG(DSPABASE, offset);
372
373 return 0;
374 }
375
376 /* Blank the screen. */
377 void
378 intelfbhw_do_blank(int blank, struct fb_info *info)
379 {
380 struct intelfb_info *dinfo = GET_DINFO(info);
381 u32 tmp;
382
383 #if VERBOSE > 0
384 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
385 #endif
386
387 /* Turn plane A on or off */
388 tmp = INREG(DSPACNTR);
389 if (blank)
390 tmp &= ~DISPPLANE_PLANE_ENABLE;
391 else
392 tmp |= DISPPLANE_PLANE_ENABLE;
393 OUTREG(DSPACNTR, tmp);
394 /* Flush */
395 tmp = INREG(DSPABASE);
396 OUTREG(DSPABASE, tmp);
397
398 /* Turn off/on the HW cursor */
399 #if VERBOSE > 0
400 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
401 #endif
402 if (dinfo->cursor_on) {
403 if (blank) {
404 intelfbhw_cursor_hide(dinfo);
405 } else {
406 intelfbhw_cursor_show(dinfo);
407 }
408 dinfo->cursor_on = 1;
409 }
410 dinfo->cursor_blanked = blank;
411
412 /* Set DPMS level */
413 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
414 switch (blank) {
415 case FB_BLANK_UNBLANK:
416 case FB_BLANK_NORMAL:
417 tmp |= ADPA_DPMS_D0;
418 break;
419 case FB_BLANK_VSYNC_SUSPEND:
420 tmp |= ADPA_DPMS_D1;
421 break;
422 case FB_BLANK_HSYNC_SUSPEND:
423 tmp |= ADPA_DPMS_D2;
424 break;
425 case FB_BLANK_POWERDOWN:
426 tmp |= ADPA_DPMS_D3;
427 break;
428 }
429 OUTREG(ADPA, tmp);
430
431 return;
432 }
433
434
435 void
436 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
437 unsigned red, unsigned green, unsigned blue,
438 unsigned transp)
439 {
440 #if VERBOSE > 0
441 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
442 regno, red, green, blue);
443 #endif
444
445 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
446 PALETTE_A : PALETTE_B;
447
448 OUTREG(palette_reg + (regno << 2),
449 (red << PALETTE_8_RED_SHIFT) |
450 (green << PALETTE_8_GREEN_SHIFT) |
451 (blue << PALETTE_8_BLUE_SHIFT));
452 }
453
454
455 int
456 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
457 int flag)
458 {
459 int i;
460
461 #if VERBOSE > 0
462 DBG_MSG("intelfbhw_read_hw_state\n");
463 #endif
464
465 if (!hw || !dinfo)
466 return -1;
467
468 /* Read in as much of the HW state as possible. */
469 hw->vga0_divisor = INREG(VGA0_DIVISOR);
470 hw->vga1_divisor = INREG(VGA1_DIVISOR);
471 hw->vga_pd = INREG(VGAPD);
472 hw->dpll_a = INREG(DPLL_A);
473 hw->dpll_b = INREG(DPLL_B);
474 hw->fpa0 = INREG(FPA0);
475 hw->fpa1 = INREG(FPA1);
476 hw->fpb0 = INREG(FPB0);
477 hw->fpb1 = INREG(FPB1);
478
479 if (flag == 1)
480 return flag;
481
482 #if 0
483 /* This seems to be a problem with the 852GM/855GM */
484 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
485 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
486 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
487 }
488 #endif
489
490 if (flag == 2)
491 return flag;
492
493 hw->htotal_a = INREG(HTOTAL_A);
494 hw->hblank_a = INREG(HBLANK_A);
495 hw->hsync_a = INREG(HSYNC_A);
496 hw->vtotal_a = INREG(VTOTAL_A);
497 hw->vblank_a = INREG(VBLANK_A);
498 hw->vsync_a = INREG(VSYNC_A);
499 hw->src_size_a = INREG(SRC_SIZE_A);
500 hw->bclrpat_a = INREG(BCLRPAT_A);
501 hw->htotal_b = INREG(HTOTAL_B);
502 hw->hblank_b = INREG(HBLANK_B);
503 hw->hsync_b = INREG(HSYNC_B);
504 hw->vtotal_b = INREG(VTOTAL_B);
505 hw->vblank_b = INREG(VBLANK_B);
506 hw->vsync_b = INREG(VSYNC_B);
507 hw->src_size_b = INREG(SRC_SIZE_B);
508 hw->bclrpat_b = INREG(BCLRPAT_B);
509
510 if (flag == 3)
511 return flag;
512
513 hw->adpa = INREG(ADPA);
514 hw->dvoa = INREG(DVOA);
515 hw->dvob = INREG(DVOB);
516 hw->dvoc = INREG(DVOC);
517 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
518 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
519 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
520 hw->lvds = INREG(LVDS);
521
522 if (flag == 4)
523 return flag;
524
525 hw->pipe_a_conf = INREG(PIPEACONF);
526 hw->pipe_b_conf = INREG(PIPEBCONF);
527 hw->disp_arb = INREG(DISPARB);
528
529 if (flag == 5)
530 return flag;
531
532 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
533 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
534 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
535 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
536
537 if (flag == 6)
538 return flag;
539
540 for (i = 0; i < 4; i++) {
541 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
542 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
543 }
544
545 if (flag == 7)
546 return flag;
547
548 hw->cursor_size = INREG(CURSOR_SIZE);
549
550 if (flag == 8)
551 return flag;
552
553 hw->disp_a_ctrl = INREG(DSPACNTR);
554 hw->disp_b_ctrl = INREG(DSPBCNTR);
555 hw->disp_a_base = INREG(DSPABASE);
556 hw->disp_b_base = INREG(DSPBBASE);
557 hw->disp_a_stride = INREG(DSPASTRIDE);
558 hw->disp_b_stride = INREG(DSPBSTRIDE);
559
560 if (flag == 9)
561 return flag;
562
563 hw->vgacntrl = INREG(VGACNTRL);
564
565 if (flag == 10)
566 return flag;
567
568 hw->add_id = INREG(ADD_ID);
569
570 if (flag == 11)
571 return flag;
572
573 for (i = 0; i < 7; i++) {
574 hw->swf0x[i] = INREG(SWF00 + (i << 2));
575 hw->swf1x[i] = INREG(SWF10 + (i << 2));
576 if (i < 3)
577 hw->swf3x[i] = INREG(SWF30 + (i << 2));
578 }
579
580 for (i = 0; i < 8; i++)
581 hw->fence[i] = INREG(FENCE + (i << 2));
582
583 hw->instpm = INREG(INSTPM);
584 hw->mem_mode = INREG(MEM_MODE);
585 hw->fw_blc_0 = INREG(FW_BLC_0);
586 hw->fw_blc_1 = INREG(FW_BLC_1);
587
588 return 0;
589 }
590
591
592 static int calc_vclock3(int index, int m, int n, int p)
593 {
594 if (p == 0 || n == 0)
595 return 0;
596 return plls[index].ref_clk * m / n / p;
597 }
598
599 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
600 {
601 struct pll_min_max *pll = &plls[index];
602 u32 m, vco, p;
603
604 m = (5 * (m1 + 2)) + (m2 + 2);
605 n += 2;
606 vco = pll->ref_clk * m / n;
607
608 if (index == PLLS_I8xx) {
609 p = ((p1 + 2) * (1 << (p2 + 1)));
610 } else {
611 p = ((p1) * (p2 ? 5 : 10));
612 }
613 return vco / p;
614 }
615
616 static void
617 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
618 {
619 int p1, p2;
620
621 if (IS_I9XX(dinfo)) {
622 if (dpll & DPLL_P1_FORCE_DIV2)
623 p1 = 1;
624 else
625 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
626
627 p1 = ffs(p1);
628
629 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
630 } else {
631 if (dpll & DPLL_P1_FORCE_DIV2)
632 p1 = 0;
633 else
634 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
635 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
636 }
637
638 *o_p1 = p1;
639 *o_p2 = p2;
640 }
641
642
643 void
644 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
645 {
646 #if REGDUMP
647 int i, m1, m2, n, p1, p2;
648 int index = dinfo->pll_index;
649 DBG_MSG("intelfbhw_print_hw_state\n");
650
651 if (!hw || !dinfo)
652 return;
653 /* Read in as much of the HW state as possible. */
654 printk("hw state dump start\n");
655 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
656 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
657 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
658 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
659 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
660 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
661
662 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
663
664 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
665 m1, m2, n, p1, p2);
666 printk(" VGA0: clock is %d\n",
667 calc_vclock(index, m1, m2, n, p1, p2, 0));
668
669 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
670 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
671 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
672
673 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
674 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
675 m1, m2, n, p1, p2);
676 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
677
678 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
679 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
680 printk(" FPA0: 0x%08x\n", hw->fpa0);
681 printk(" FPA1: 0x%08x\n", hw->fpa1);
682 printk(" FPB0: 0x%08x\n", hw->fpb0);
683 printk(" FPB1: 0x%08x\n", hw->fpb1);
684
685 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
686 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
687 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
688
689 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
690
691 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
692 m1, m2, n, p1, p2);
693 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
694
695 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
696 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
697 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
698
699 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
700
701 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
702 m1, m2, n, p1, p2);
703 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
704
705 #if 0
706 printk(" PALETTE_A:\n");
707 for (i = 0; i < PALETTE_8_ENTRIES)
708 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
709 printk(" PALETTE_B:\n");
710 for (i = 0; i < PALETTE_8_ENTRIES)
711 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
712 #endif
713
714 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
715 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
716 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
717 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
718 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
719 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
720 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
721 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
722 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
723 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
724 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
725 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
726 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
727 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
728 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
729 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
730
731 printk(" ADPA: 0x%08x\n", hw->adpa);
732 printk(" DVOA: 0x%08x\n", hw->dvoa);
733 printk(" DVOB: 0x%08x\n", hw->dvob);
734 printk(" DVOC: 0x%08x\n", hw->dvoc);
735 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
736 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
737 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
738 printk(" LVDS: 0x%08x\n", hw->lvds);
739
740 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
741 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
742 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
743
744 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
745 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
746 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
747 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
748
749 printk(" CURSOR_A_PALETTE: ");
750 for (i = 0; i < 4; i++) {
751 printk("0x%08x", hw->cursor_a_palette[i]);
752 if (i < 3)
753 printk(", ");
754 }
755 printk("\n");
756 printk(" CURSOR_B_PALETTE: ");
757 for (i = 0; i < 4; i++) {
758 printk("0x%08x", hw->cursor_b_palette[i]);
759 if (i < 3)
760 printk(", ");
761 }
762 printk("\n");
763
764 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
765
766 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
767 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
768 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
769 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
770 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
771 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
772
773 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
774 printk(" ADD_ID: 0x%08x\n", hw->add_id);
775
776 for (i = 0; i < 7; i++) {
777 printk(" SWF0%d 0x%08x\n", i,
778 hw->swf0x[i]);
779 }
780 for (i = 0; i < 7; i++) {
781 printk(" SWF1%d 0x%08x\n", i,
782 hw->swf1x[i]);
783 }
784 for (i = 0; i < 3; i++) {
785 printk(" SWF3%d 0x%08x\n", i,
786 hw->swf3x[i]);
787 }
788 for (i = 0; i < 8; i++)
789 printk(" FENCE%d 0x%08x\n", i,
790 hw->fence[i]);
791
792 printk(" INSTPM 0x%08x\n", hw->instpm);
793 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
794 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
795 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
796
797 printk("hw state dump end\n");
798 #endif
799 }
800
801
802
803 /* Split the M parameter into M1 and M2. */
804 static int
805 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
806 {
807 int m1, m2;
808 int testm;
809 struct pll_min_max *pll = &plls[index];
810
811 /* no point optimising too much - brute force m */
812 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
813 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
814 testm = (5 * (m1 + 2)) + (m2 + 2);
815 if (testm == m) {
816 *retm1 = (unsigned int)m1;
817 *retm2 = (unsigned int)m2;
818 return 0;
819 }
820 }
821 }
822 return 1;
823 }
824
825 /* Split the P parameter into P1 and P2. */
826 static int
827 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
828 {
829 int p1, p2;
830 struct pll_min_max *pll = &plls[index];
831
832 if (index == PLLS_I9xx) {
833 p2 = (p % 10) ? 1 : 0;
834
835 p1 = p / (p2 ? 5 : 10);
836
837 *retp1 = (unsigned int)p1;
838 *retp2 = (unsigned int)p2;
839 return 0;
840 }
841
842 if (p % 4 == 0)
843 p2 = 1;
844 else
845 p2 = 0;
846 p1 = (p / (1 << (p2 + 1))) - 2;
847 if (p % 4 == 0 && p1 < pll->min_p1) {
848 p2 = 0;
849 p1 = (p / (1 << (p2 + 1))) - 2;
850 }
851 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
852 (p1 + 2) * (1 << (p2 + 1)) != p) {
853 return 1;
854 } else {
855 *retp1 = (unsigned int)p1;
856 *retp2 = (unsigned int)p2;
857 return 0;
858 }
859 }
860
861 static int
862 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
863 u32 *retp2, u32 *retclock)
864 {
865 u32 m1, m2, n, p1, p2, n1, testm;
866 u32 f_vco, p, p_best = 0, m, f_out = 0;
867 u32 err_max, err_target, err_best = 10000000;
868 u32 n_best = 0, m_best = 0, f_best, f_err;
869 u32 p_min, p_max, p_inc, div_max;
870 struct pll_min_max *pll = &plls[index];
871
872 /* Accept 0.5% difference, but aim for 0.1% */
873 err_max = 5 * clock / 1000;
874 err_target = clock / 1000;
875
876 DBG_MSG("Clock is %d\n", clock);
877
878 div_max = pll->max_vco / clock;
879
880 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
881 p_min = p_inc;
882 p_max = ROUND_DOWN_TO(div_max, p_inc);
883 if (p_min < pll->min_p)
884 p_min = pll->min_p;
885 if (p_max > pll->max_p)
886 p_max = pll->max_p;
887
888 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
889
890 p = p_min;
891 do {
892 if (splitp(index, p, &p1, &p2)) {
893 WRN_MSG("cannot split p = %d\n", p);
894 p += p_inc;
895 continue;
896 }
897 n = pll->min_n;
898 f_vco = clock * p;
899
900 do {
901 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
902 if (m < pll->min_m)
903 m = pll->min_m + 1;
904 if (m > pll->max_m)
905 m = pll->max_m - 1;
906 for (testm = m - 1; testm <= m; testm++) {
907 f_out = calc_vclock3(index, m, n, p);
908 if (splitm(index, testm, &m1, &m2)) {
909 WRN_MSG("cannot split m = %d\n", m);
910 n++;
911 continue;
912 }
913 if (clock > f_out)
914 f_err = clock - f_out;
915 else/* slightly bias the error for bigger clocks */
916 f_err = f_out - clock + 1;
917
918 if (f_err < err_best) {
919 m_best = testm;
920 n_best = n;
921 p_best = p;
922 f_best = f_out;
923 err_best = f_err;
924 }
925 }
926 n++;
927 } while ((n <= pll->max_n) && (f_out >= clock));
928 p += p_inc;
929 } while ((p <= p_max));
930
931 if (!m_best) {
932 WRN_MSG("cannot find parameters for clock %d\n", clock);
933 return 1;
934 }
935 m = m_best;
936 n = n_best;
937 p = p_best;
938 splitm(index, m, &m1, &m2);
939 splitp(index, p, &p1, &p2);
940 n1 = n - 2;
941
942 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
943 "f: %d (%d), VCO: %d\n",
944 m, m1, m2, n, n1, p, p1, p2,
945 calc_vclock3(index, m, n, p),
946 calc_vclock(index, m1, m2, n1, p1, p2, 0),
947 calc_vclock3(index, m, n, p) * p);
948 *retm1 = m1;
949 *retm2 = m2;
950 *retn = n1;
951 *retp1 = p1;
952 *retp2 = p2;
953 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
954
955 return 0;
956 }
957
958 static __inline__ int
959 check_overflow(u32 value, u32 limit, const char *description)
960 {
961 if (value > limit) {
962 WRN_MSG("%s value %d exceeds limit %d\n",
963 description, value, limit);
964 return 1;
965 }
966 return 0;
967 }
968
969 /* It is assumed that hw is filled in with the initial state information. */
970 int
971 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
972 struct fb_var_screeninfo *var)
973 {
974 int pipe = PIPE_A;
975 u32 *dpll, *fp0, *fp1;
976 u32 m1, m2, n, p1, p2, clock_target, clock;
977 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
978 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
979 u32 vsync_pol, hsync_pol;
980 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
981 u32 stride_alignment;
982
983 DBG_MSG("intelfbhw_mode_to_hw\n");
984
985 /* Disable VGA */
986 hw->vgacntrl |= VGA_DISABLE;
987
988 /* Check whether pipe A or pipe B is enabled. */
989 if (hw->pipe_a_conf & PIPECONF_ENABLE)
990 pipe = PIPE_A;
991 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
992 pipe = PIPE_B;
993
994 /* Set which pipe's registers will be set. */
995 if (pipe == PIPE_B) {
996 dpll = &hw->dpll_b;
997 fp0 = &hw->fpb0;
998 fp1 = &hw->fpb1;
999 hs = &hw->hsync_b;
1000 hb = &hw->hblank_b;
1001 ht = &hw->htotal_b;
1002 vs = &hw->vsync_b;
1003 vb = &hw->vblank_b;
1004 vt = &hw->vtotal_b;
1005 ss = &hw->src_size_b;
1006 pipe_conf = &hw->pipe_b_conf;
1007 } else {
1008 dpll = &hw->dpll_a;
1009 fp0 = &hw->fpa0;
1010 fp1 = &hw->fpa1;
1011 hs = &hw->hsync_a;
1012 hb = &hw->hblank_a;
1013 ht = &hw->htotal_a;
1014 vs = &hw->vsync_a;
1015 vb = &hw->vblank_a;
1016 vt = &hw->vtotal_a;
1017 ss = &hw->src_size_a;
1018 pipe_conf = &hw->pipe_a_conf;
1019 }
1020
1021 /* Use ADPA register for sync control. */
1022 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1023
1024 /* sync polarity */
1025 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1026 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1027 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1028 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1029 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1030 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1031 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1032 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1033
1034 /* Connect correct pipe to the analog port DAC */
1035 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1036 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1037
1038 /* Set DPMS state to D0 (on) */
1039 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1040 hw->adpa |= ADPA_DPMS_D0;
1041
1042 hw->adpa |= ADPA_DAC_ENABLE;
1043
1044 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1045 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1046 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1047
1048 /* Desired clock in kHz */
1049 clock_target = 1000000000 / var->pixclock;
1050
1051 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1052 &n, &p1, &p2, &clock)) {
1053 WRN_MSG("calc_pll_params failed\n");
1054 return 1;
1055 }
1056
1057 /* Check for overflow. */
1058 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1059 return 1;
1060 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1061 return 1;
1062 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1063 return 1;
1064 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1065 return 1;
1066 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1067 return 1;
1068
1069 *dpll &= ~DPLL_P1_FORCE_DIV2;
1070 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1071 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1072
1073 if (IS_I9XX(dinfo)) {
1074 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1075 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1076 } else {
1077 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1078 }
1079
1080 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1081 (m1 << FP_M1_DIVISOR_SHIFT) |
1082 (m2 << FP_M2_DIVISOR_SHIFT);
1083 *fp1 = *fp0;
1084
1085 hw->dvob &= ~PORT_ENABLE;
1086 hw->dvoc &= ~PORT_ENABLE;
1087
1088 /* Use display plane A. */
1089 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1090 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1091 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1092 switch (intelfb_var_to_depth(var)) {
1093 case 8:
1094 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1095 break;
1096 case 15:
1097 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1098 break;
1099 case 16:
1100 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1101 break;
1102 case 24:
1103 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1104 break;
1105 }
1106 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1107 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1108
1109 /* Set CRTC registers. */
1110 hactive = var->xres;
1111 hsync_start = hactive + var->right_margin;
1112 hsync_end = hsync_start + var->hsync_len;
1113 htotal = hsync_end + var->left_margin;
1114 hblank_start = hactive;
1115 hblank_end = htotal;
1116
1117 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1118 hactive, hsync_start, hsync_end, htotal, hblank_start,
1119 hblank_end);
1120
1121 vactive = var->yres;
1122 vsync_start = vactive + var->lower_margin;
1123 vsync_end = vsync_start + var->vsync_len;
1124 vtotal = vsync_end + var->upper_margin;
1125 vblank_start = vactive;
1126 vblank_end = vtotal;
1127 vblank_end = vsync_end + 1;
1128
1129 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1130 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1131 vblank_end);
1132
1133 /* Adjust for register values, and check for overflow. */
1134 hactive--;
1135 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1136 return 1;
1137 hsync_start--;
1138 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1139 return 1;
1140 hsync_end--;
1141 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1142 return 1;
1143 htotal--;
1144 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1145 return 1;
1146 hblank_start--;
1147 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1148 return 1;
1149 hblank_end--;
1150 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1151 return 1;
1152
1153 vactive--;
1154 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1155 return 1;
1156 vsync_start--;
1157 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1158 return 1;
1159 vsync_end--;
1160 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1161 return 1;
1162 vtotal--;
1163 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1164 return 1;
1165 vblank_start--;
1166 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1167 return 1;
1168 vblank_end--;
1169 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1170 return 1;
1171
1172 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1173 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1174 (hblank_end << HSYNCEND_SHIFT);
1175 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1176
1177 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1178 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1179 (vblank_end << VSYNCEND_SHIFT);
1180 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1181 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1182 (vactive << SRC_SIZE_VERT_SHIFT);
1183
1184 hw->disp_a_stride = dinfo->pitch;
1185 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1186
1187 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1188 var->xoffset * var->bits_per_pixel / 8;
1189
1190 hw->disp_a_base += dinfo->fb.offset << 12;
1191
1192 /* Check stride alignment. */
1193 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1194 STRIDE_ALIGNMENT;
1195 if (hw->disp_a_stride % stride_alignment != 0) {
1196 WRN_MSG("display stride %d has bad alignment %d\n",
1197 hw->disp_a_stride, stride_alignment);
1198 return 1;
1199 }
1200
1201 /* Set the palette to 8-bit mode. */
1202 *pipe_conf &= ~PIPECONF_GAMMA;
1203 return 0;
1204 }
1205
1206 /* Program a (non-VGA) video mode. */
1207 int
1208 intelfbhw_program_mode(struct intelfb_info *dinfo,
1209 const struct intelfb_hwstate *hw, int blank)
1210 {
1211 int pipe = PIPE_A;
1212 u32 tmp;
1213 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1214 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1215 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1216 u32 hsync_reg, htotal_reg, hblank_reg;
1217 u32 vsync_reg, vtotal_reg, vblank_reg;
1218 u32 src_size_reg;
1219 u32 count, tmp_val[3];
1220
1221 /* Assume single pipe, display plane A, analog CRT. */
1222
1223 #if VERBOSE > 0
1224 DBG_MSG("intelfbhw_program_mode\n");
1225 #endif
1226
1227 /* Disable VGA */
1228 tmp = INREG(VGACNTRL);
1229 tmp |= VGA_DISABLE;
1230 OUTREG(VGACNTRL, tmp);
1231
1232 /* Check whether pipe A or pipe B is enabled. */
1233 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1234 pipe = PIPE_A;
1235 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1236 pipe = PIPE_B;
1237
1238 dinfo->pipe = pipe;
1239
1240 if (pipe == PIPE_B) {
1241 dpll = &hw->dpll_b;
1242 fp0 = &hw->fpb0;
1243 fp1 = &hw->fpb1;
1244 pipe_conf = &hw->pipe_b_conf;
1245 hs = &hw->hsync_b;
1246 hb = &hw->hblank_b;
1247 ht = &hw->htotal_b;
1248 vs = &hw->vsync_b;
1249 vb = &hw->vblank_b;
1250 vt = &hw->vtotal_b;
1251 ss = &hw->src_size_b;
1252 dpll_reg = DPLL_B;
1253 fp0_reg = FPB0;
1254 fp1_reg = FPB1;
1255 pipe_conf_reg = PIPEBCONF;
1256 hsync_reg = HSYNC_B;
1257 htotal_reg = HTOTAL_B;
1258 hblank_reg = HBLANK_B;
1259 vsync_reg = VSYNC_B;
1260 vtotal_reg = VTOTAL_B;
1261 vblank_reg = VBLANK_B;
1262 src_size_reg = SRC_SIZE_B;
1263 } else {
1264 dpll = &hw->dpll_a;
1265 fp0 = &hw->fpa0;
1266 fp1 = &hw->fpa1;
1267 pipe_conf = &hw->pipe_a_conf;
1268 hs = &hw->hsync_a;
1269 hb = &hw->hblank_a;
1270 ht = &hw->htotal_a;
1271 vs = &hw->vsync_a;
1272 vb = &hw->vblank_a;
1273 vt = &hw->vtotal_a;
1274 ss = &hw->src_size_a;
1275 dpll_reg = DPLL_A;
1276 fp0_reg = FPA0;
1277 fp1_reg = FPA1;
1278 pipe_conf_reg = PIPEACONF;
1279 hsync_reg = HSYNC_A;
1280 htotal_reg = HTOTAL_A;
1281 hblank_reg = HBLANK_A;
1282 vsync_reg = VSYNC_A;
1283 vtotal_reg = VTOTAL_A;
1284 vblank_reg = VBLANK_A;
1285 src_size_reg = SRC_SIZE_A;
1286 }
1287
1288 /* turn off pipe */
1289 tmp = INREG(pipe_conf_reg);
1290 tmp &= ~PIPECONF_ENABLE;
1291 OUTREG(pipe_conf_reg, tmp);
1292
1293 count = 0;
1294 do {
1295 tmp_val[count%3] = INREG(0x70000);
1296 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1297 break;
1298 count++;
1299 udelay(1);
1300 if (count % 200 == 0) {
1301 tmp = INREG(pipe_conf_reg);
1302 tmp &= ~PIPECONF_ENABLE;
1303 OUTREG(pipe_conf_reg, tmp);
1304 }
1305 } while(count < 2000);
1306
1307 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1308
1309 /* Disable planes A and B. */
1310 tmp = INREG(DSPACNTR);
1311 tmp &= ~DISPPLANE_PLANE_ENABLE;
1312 OUTREG(DSPACNTR, tmp);
1313 tmp = INREG(DSPBCNTR);
1314 tmp &= ~DISPPLANE_PLANE_ENABLE;
1315 OUTREG(DSPBCNTR, tmp);
1316
1317 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1318 mdelay(20);
1319
1320 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1321 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1322 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1323
1324 /* Disable Sync */
1325 tmp = INREG(ADPA);
1326 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1327 tmp |= ADPA_DPMS_D3;
1328 OUTREG(ADPA, tmp);
1329
1330 /* do some funky magic - xyzzy */
1331 OUTREG(0x61204, 0xabcd0000);
1332
1333 /* turn off PLL */
1334 tmp = INREG(dpll_reg);
1335 dpll_reg &= ~DPLL_VCO_ENABLE;
1336 OUTREG(dpll_reg, tmp);
1337
1338 /* Set PLL parameters */
1339 OUTREG(fp0_reg, *fp0);
1340 OUTREG(fp1_reg, *fp1);
1341
1342 /* Enable PLL */
1343 OUTREG(dpll_reg, *dpll);
1344
1345 /* Set DVOs B/C */
1346 OUTREG(DVOB, hw->dvob);
1347 OUTREG(DVOC, hw->dvoc);
1348
1349 /* undo funky magic */
1350 OUTREG(0x61204, 0x00000000);
1351
1352 /* Set ADPA */
1353 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1354 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1355
1356 /* Set pipe parameters */
1357 OUTREG(hsync_reg, *hs);
1358 OUTREG(hblank_reg, *hb);
1359 OUTREG(htotal_reg, *ht);
1360 OUTREG(vsync_reg, *vs);
1361 OUTREG(vblank_reg, *vb);
1362 OUTREG(vtotal_reg, *vt);
1363 OUTREG(src_size_reg, *ss);
1364
1365 /* Enable pipe */
1366 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1367
1368 /* Enable sync */
1369 tmp = INREG(ADPA);
1370 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1371 tmp |= ADPA_DPMS_D0;
1372 OUTREG(ADPA, tmp);
1373
1374 /* setup display plane */
1375 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1376 /*
1377 * i830M errata: the display plane must be enabled
1378 * to allow writes to the other bits in the plane
1379 * control register.
1380 */
1381 tmp = INREG(DSPACNTR);
1382 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1383 tmp |= DISPPLANE_PLANE_ENABLE;
1384 OUTREG(DSPACNTR, tmp);
1385 OUTREG(DSPACNTR,
1386 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1387 mdelay(1);
1388 }
1389 }
1390
1391 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1392 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1393 OUTREG(DSPABASE, hw->disp_a_base);
1394
1395 /* Enable plane */
1396 if (!blank) {
1397 tmp = INREG(DSPACNTR);
1398 tmp |= DISPPLANE_PLANE_ENABLE;
1399 OUTREG(DSPACNTR, tmp);
1400 OUTREG(DSPABASE, hw->disp_a_base);
1401 }
1402
1403 return 0;
1404 }
1405
1406 /* forward declarations */
1407 static void refresh_ring(struct intelfb_info *dinfo);
1408 static void reset_state(struct intelfb_info *dinfo);
1409 static void do_flush(struct intelfb_info *dinfo);
1410
1411 static int
1412 wait_ring(struct intelfb_info *dinfo, int n)
1413 {
1414 int i = 0;
1415 unsigned long end;
1416 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1417
1418 #if VERBOSE > 0
1419 DBG_MSG("wait_ring: %d\n", n);
1420 #endif
1421
1422 end = jiffies + (HZ * 3);
1423 while (dinfo->ring_space < n) {
1424 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1425 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1426 dinfo->ring_space = dinfo->ring_head
1427 - (dinfo->ring_tail + RING_MIN_FREE);
1428 else
1429 dinfo->ring_space = (dinfo->ring.size +
1430 dinfo->ring_head)
1431 - (dinfo->ring_tail + RING_MIN_FREE);
1432 if (dinfo->ring_head != last_head) {
1433 end = jiffies + (HZ * 3);
1434 last_head = dinfo->ring_head;
1435 }
1436 i++;
1437 if (time_before(end, jiffies)) {
1438 if (!i) {
1439 /* Try again */
1440 reset_state(dinfo);
1441 refresh_ring(dinfo);
1442 do_flush(dinfo);
1443 end = jiffies + (HZ * 3);
1444 i = 1;
1445 } else {
1446 WRN_MSG("ring buffer : space: %d wanted %d\n",
1447 dinfo->ring_space, n);
1448 WRN_MSG("lockup - turning off hardware "
1449 "acceleration\n");
1450 dinfo->ring_lockup = 1;
1451 break;
1452 }
1453 }
1454 udelay(1);
1455 }
1456 return i;
1457 }
1458
1459 static void
1460 do_flush(struct intelfb_info *dinfo) {
1461 START_RING(2);
1462 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1463 OUT_RING(MI_NOOP);
1464 ADVANCE_RING();
1465 }
1466
1467 void
1468 intelfbhw_do_sync(struct intelfb_info *dinfo)
1469 {
1470 #if VERBOSE > 0
1471 DBG_MSG("intelfbhw_do_sync\n");
1472 #endif
1473
1474 if (!dinfo->accel)
1475 return;
1476
1477 /*
1478 * Send a flush, then wait until the ring is empty. This is what
1479 * the XFree86 driver does, and actually it doesn't seem a lot worse
1480 * than the recommended method (both have problems).
1481 */
1482 do_flush(dinfo);
1483 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1484 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1485 }
1486
1487 static void
1488 refresh_ring(struct intelfb_info *dinfo)
1489 {
1490 #if VERBOSE > 0
1491 DBG_MSG("refresh_ring\n");
1492 #endif
1493
1494 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1495 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1496 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1497 dinfo->ring_space = dinfo->ring_head
1498 - (dinfo->ring_tail + RING_MIN_FREE);
1499 else
1500 dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
1501 - (dinfo->ring_tail + RING_MIN_FREE);
1502 }
1503
1504 static void
1505 reset_state(struct intelfb_info *dinfo)
1506 {
1507 int i;
1508 u32 tmp;
1509
1510 #if VERBOSE > 0
1511 DBG_MSG("reset_state\n");
1512 #endif
1513
1514 for (i = 0; i < FENCE_NUM; i++)
1515 OUTREG(FENCE + (i << 2), 0);
1516
1517 /* Flush the ring buffer if it's enabled. */
1518 tmp = INREG(PRI_RING_LENGTH);
1519 if (tmp & RING_ENABLE) {
1520 #if VERBOSE > 0
1521 DBG_MSG("reset_state: ring was enabled\n");
1522 #endif
1523 refresh_ring(dinfo);
1524 intelfbhw_do_sync(dinfo);
1525 DO_RING_IDLE();
1526 }
1527
1528 OUTREG(PRI_RING_LENGTH, 0);
1529 OUTREG(PRI_RING_HEAD, 0);
1530 OUTREG(PRI_RING_TAIL, 0);
1531 OUTREG(PRI_RING_START, 0);
1532 }
1533
1534 /* Stop the 2D engine, and turn off the ring buffer. */
1535 void
1536 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1537 {
1538 #if VERBOSE > 0
1539 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1540 dinfo->ring_active);
1541 #endif
1542
1543 if (!dinfo->accel)
1544 return;
1545
1546 dinfo->ring_active = 0;
1547 reset_state(dinfo);
1548 }
1549
1550 /*
1551 * Enable the ring buffer, and initialise the 2D engine.
1552 * It is assumed that the graphics engine has been stopped by previously
1553 * calling intelfb_2d_stop().
1554 */
1555 void
1556 intelfbhw_2d_start(struct intelfb_info *dinfo)
1557 {
1558 #if VERBOSE > 0
1559 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1560 dinfo->accel, dinfo->ring_active);
1561 #endif
1562
1563 if (!dinfo->accel)
1564 return;
1565
1566 /* Initialise the primary ring buffer. */
1567 OUTREG(PRI_RING_LENGTH, 0);
1568 OUTREG(PRI_RING_TAIL, 0);
1569 OUTREG(PRI_RING_HEAD, 0);
1570
1571 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1572 OUTREG(PRI_RING_LENGTH,
1573 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1574 RING_NO_REPORT | RING_ENABLE);
1575 refresh_ring(dinfo);
1576 dinfo->ring_active = 1;
1577 }
1578
1579 /* 2D fillrect (solid fill or invert) */
1580 void
1581 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1582 u32 color, u32 pitch, u32 bpp, u32 rop)
1583 {
1584 u32 br00, br09, br13, br14, br16;
1585
1586 #if VERBOSE > 0
1587 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1588 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1589 #endif
1590
1591 br00 = COLOR_BLT_CMD;
1592 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1593 br13 = (rop << ROP_SHIFT) | pitch;
1594 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1595 br16 = color;
1596
1597 switch (bpp) {
1598 case 8:
1599 br13 |= COLOR_DEPTH_8;
1600 break;
1601 case 16:
1602 br13 |= COLOR_DEPTH_16;
1603 break;
1604 case 32:
1605 br13 |= COLOR_DEPTH_32;
1606 br00 |= WRITE_ALPHA | WRITE_RGB;
1607 break;
1608 }
1609
1610 START_RING(6);
1611 OUT_RING(br00);
1612 OUT_RING(br13);
1613 OUT_RING(br14);
1614 OUT_RING(br09);
1615 OUT_RING(br16);
1616 OUT_RING(MI_NOOP);
1617 ADVANCE_RING();
1618
1619 #if VERBOSE > 0
1620 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1621 dinfo->ring_tail, dinfo->ring_space);
1622 #endif
1623 }
1624
1625 void
1626 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1627 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1628 {
1629 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1630
1631 #if VERBOSE > 0
1632 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1633 curx, cury, dstx, dsty, w, h, pitch, bpp);
1634 #endif
1635
1636 br00 = XY_SRC_COPY_BLT_CMD;
1637 br09 = dinfo->fb_start;
1638 br11 = (pitch << PITCH_SHIFT);
1639 br12 = dinfo->fb_start;
1640 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1641 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1642 br23 = ((dstx + w) << WIDTH_SHIFT) |
1643 ((dsty + h) << HEIGHT_SHIFT);
1644 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1645
1646 switch (bpp) {
1647 case 8:
1648 br13 |= COLOR_DEPTH_8;
1649 break;
1650 case 16:
1651 br13 |= COLOR_DEPTH_16;
1652 break;
1653 case 32:
1654 br13 |= COLOR_DEPTH_32;
1655 br00 |= WRITE_ALPHA | WRITE_RGB;
1656 break;
1657 }
1658
1659 START_RING(8);
1660 OUT_RING(br00);
1661 OUT_RING(br13);
1662 OUT_RING(br22);
1663 OUT_RING(br23);
1664 OUT_RING(br09);
1665 OUT_RING(br26);
1666 OUT_RING(br11);
1667 OUT_RING(br12);
1668 ADVANCE_RING();
1669 }
1670
1671 int
1672 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1673 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1674 {
1675 int nbytes, ndwords, pad, tmp;
1676 u32 br00, br09, br13, br18, br19, br22, br23;
1677 int dat, ix, iy, iw;
1678 int i, j;
1679
1680 #if VERBOSE > 0
1681 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1682 #endif
1683
1684 /* size in bytes of a padded scanline */
1685 nbytes = ROUND_UP_TO(w, 16) / 8;
1686
1687 /* Total bytes of padded scanline data to write out. */
1688 nbytes = nbytes * h;
1689
1690 /*
1691 * Check if the glyph data exceeds the immediate mode limit.
1692 * It would take a large font (1K pixels) to hit this limit.
1693 */
1694 if (nbytes > MAX_MONO_IMM_SIZE)
1695 return 0;
1696
1697 /* Src data is packaged a dword (32-bit) at a time. */
1698 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1699
1700 /*
1701 * Ring has to be padded to a quad word. But because the command starts
1702 with 7 bytes, pad only if there is an even number of ndwords
1703 */
1704 pad = !(ndwords % 2);
1705
1706 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1707 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1708 br09 = dinfo->fb_start;
1709 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1710 br18 = bg;
1711 br19 = fg;
1712 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1713 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1714
1715 switch (bpp) {
1716 case 8:
1717 br13 |= COLOR_DEPTH_8;
1718 break;
1719 case 16:
1720 br13 |= COLOR_DEPTH_16;
1721 break;
1722 case 32:
1723 br13 |= COLOR_DEPTH_32;
1724 br00 |= WRITE_ALPHA | WRITE_RGB;
1725 break;
1726 }
1727
1728 START_RING(8 + ndwords);
1729 OUT_RING(br00);
1730 OUT_RING(br13);
1731 OUT_RING(br22);
1732 OUT_RING(br23);
1733 OUT_RING(br09);
1734 OUT_RING(br18);
1735 OUT_RING(br19);
1736 ix = iy = 0;
1737 iw = ROUND_UP_TO(w, 8) / 8;
1738 while (ndwords--) {
1739 dat = 0;
1740 for (j = 0; j < 2; ++j) {
1741 for (i = 0; i < 2; ++i) {
1742 if (ix != iw || i == 0)
1743 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1744 }
1745 if (ix == iw && iy != (h-1)) {
1746 ix = 0;
1747 ++iy;
1748 }
1749 }
1750 OUT_RING(dat);
1751 }
1752 if (pad)
1753 OUT_RING(MI_NOOP);
1754 ADVANCE_RING();
1755
1756 return 1;
1757 }
1758
1759 /* HW cursor functions. */
1760 void
1761 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1762 {
1763 u32 tmp;
1764
1765 #if VERBOSE > 0
1766 DBG_MSG("intelfbhw_cursor_init\n");
1767 #endif
1768
1769 if (dinfo->mobile || IS_I9XX(dinfo)) {
1770 if (!dinfo->cursor.physical)
1771 return;
1772 tmp = INREG(CURSOR_A_CONTROL);
1773 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1774 CURSOR_MEM_TYPE_LOCAL |
1775 (1 << CURSOR_PIPE_SELECT_SHIFT));
1776 tmp |= CURSOR_MODE_DISABLE;
1777 OUTREG(CURSOR_A_CONTROL, tmp);
1778 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1779 } else {
1780 tmp = INREG(CURSOR_CONTROL);
1781 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1782 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1783 tmp = CURSOR_FORMAT_3C;
1784 OUTREG(CURSOR_CONTROL, tmp);
1785 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1786 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1787 (64 << CURSOR_SIZE_V_SHIFT);
1788 OUTREG(CURSOR_SIZE, tmp);
1789 }
1790 }
1791
1792 void
1793 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1794 {
1795 u32 tmp;
1796
1797 #if VERBOSE > 0
1798 DBG_MSG("intelfbhw_cursor_hide\n");
1799 #endif
1800
1801 dinfo->cursor_on = 0;
1802 if (dinfo->mobile || IS_I9XX(dinfo)) {
1803 if (!dinfo->cursor.physical)
1804 return;
1805 tmp = INREG(CURSOR_A_CONTROL);
1806 tmp &= ~CURSOR_MODE_MASK;
1807 tmp |= CURSOR_MODE_DISABLE;
1808 OUTREG(CURSOR_A_CONTROL, tmp);
1809 /* Flush changes */
1810 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1811 } else {
1812 tmp = INREG(CURSOR_CONTROL);
1813 tmp &= ~CURSOR_ENABLE;
1814 OUTREG(CURSOR_CONTROL, tmp);
1815 }
1816 }
1817
1818 void
1819 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1820 {
1821 u32 tmp;
1822
1823 #if VERBOSE > 0
1824 DBG_MSG("intelfbhw_cursor_show\n");
1825 #endif
1826
1827 dinfo->cursor_on = 1;
1828
1829 if (dinfo->cursor_blanked)
1830 return;
1831
1832 if (dinfo->mobile || IS_I9XX(dinfo)) {
1833 if (!dinfo->cursor.physical)
1834 return;
1835 tmp = INREG(CURSOR_A_CONTROL);
1836 tmp &= ~CURSOR_MODE_MASK;
1837 tmp |= CURSOR_MODE_64_4C_AX;
1838 OUTREG(CURSOR_A_CONTROL, tmp);
1839 /* Flush changes */
1840 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1841 } else {
1842 tmp = INREG(CURSOR_CONTROL);
1843 tmp |= CURSOR_ENABLE;
1844 OUTREG(CURSOR_CONTROL, tmp);
1845 }
1846 }
1847
1848 void
1849 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1850 {
1851 u32 tmp;
1852
1853 #if VERBOSE > 0
1854 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1855 #endif
1856
1857 /*
1858 * Sets the position. The coordinates are assumed to already
1859 * have any offset adjusted. Assume that the cursor is never
1860 * completely off-screen, and that x, y are always >= 0.
1861 */
1862
1863 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1864 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1865 OUTREG(CURSOR_A_POSITION, tmp);
1866
1867 if (IS_I9XX(dinfo)) {
1868 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1869 }
1870 }
1871
1872 void
1873 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1874 {
1875 #if VERBOSE > 0
1876 DBG_MSG("intelfbhw_cursor_setcolor\n");
1877 #endif
1878
1879 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1880 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1881 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1882 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1883 }
1884
1885 void
1886 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1887 u8 *data)
1888 {
1889 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1890 int i, j, w = width / 8;
1891 int mod = width % 8, t_mask, d_mask;
1892
1893 #if VERBOSE > 0
1894 DBG_MSG("intelfbhw_cursor_load\n");
1895 #endif
1896
1897 if (!dinfo->cursor.virtual)
1898 return;
1899
1900 t_mask = 0xff >> mod;
1901 d_mask = ~(0xff >> mod);
1902 for (i = height; i--; ) {
1903 for (j = 0; j < w; j++) {
1904 writeb(0x00, addr + j);
1905 writeb(*(data++), addr + j+8);
1906 }
1907 if (mod) {
1908 writeb(t_mask, addr + j);
1909 writeb(*(data++) & d_mask, addr + j+8);
1910 }
1911 addr += 16;
1912 }
1913 }
1914
1915 void
1916 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1917 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1918 int i, j;
1919
1920 #if VERBOSE > 0
1921 DBG_MSG("intelfbhw_cursor_reset\n");
1922 #endif
1923
1924 if (!dinfo->cursor.virtual)
1925 return;
1926
1927 for (i = 64; i--; ) {
1928 for (j = 0; j < 8; j++) {
1929 writeb(0xff, addr + j+0);
1930 writeb(0x00, addr + j+8);
1931 }
1932 addr += 16;
1933 }
1934 }
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