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[mirror_ubuntu-artful-kernel.git] / drivers / video / intelfb / intelfbhw.c
1 /*
2 * intelfb
3 *
4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5 *
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
7 * 2004 Sylvain Meyer
8 *
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
15 *
16 * Author: David Dawes
17 *
18 */
19
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/string.h>
26 #include <linux/mm.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/fb.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/pci.h>
33 #include <linux/vmalloc.h>
34 #include <linux/pagemap.h>
35 #include <linux/interrupt.h>
36
37 #include <asm/io.h>
38
39 #include "intelfb.h"
40 #include "intelfbhw.h"
41
42 struct pll_min_max {
43 int min_m, max_m, min_m1, max_m1;
44 int min_m2, max_m2, min_n, max_n;
45 int min_p, max_p, min_p1, max_p1;
46 int min_vco, max_vco, p_transition_clk, ref_clk;
47 int p_inc_lo, p_inc_hi;
48 };
49
50 #define PLLS_I8xx 0
51 #define PLLS_I9xx 1
52 #define PLLS_MAX 2
53
54 static struct pll_min_max plls[PLLS_MAX] = {
55 { 108, 140, 18, 26,
56 6, 16, 3, 16,
57 4, 128, 0, 31,
58 930000, 1400000, 165000, 48000,
59 4, 2 }, //I8xx
60
61 { 75, 120, 10, 20,
62 5, 9, 4, 7,
63 5, 80, 1, 8,
64 1400000, 2800000, 200000, 96000,
65 10, 5 } //I9xx
66 };
67
68 int
69 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
70 {
71 u32 tmp;
72 if (!pdev || !dinfo)
73 return 1;
74
75 switch (pdev->device) {
76 case PCI_DEVICE_ID_INTEL_830M:
77 dinfo->name = "Intel(R) 830M";
78 dinfo->chipset = INTEL_830M;
79 dinfo->mobile = 1;
80 dinfo->pll_index = PLLS_I8xx;
81 return 0;
82 case PCI_DEVICE_ID_INTEL_845G:
83 dinfo->name = "Intel(R) 845G";
84 dinfo->chipset = INTEL_845G;
85 dinfo->mobile = 0;
86 dinfo->pll_index = PLLS_I8xx;
87 return 0;
88 case PCI_DEVICE_ID_INTEL_85XGM:
89 tmp = 0;
90 dinfo->mobile = 1;
91 dinfo->pll_index = PLLS_I8xx;
92 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
93 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
94 INTEL_85X_VARIANT_MASK) {
95 case INTEL_VAR_855GME:
96 dinfo->name = "Intel(R) 855GME";
97 dinfo->chipset = INTEL_855GME;
98 return 0;
99 case INTEL_VAR_855GM:
100 dinfo->name = "Intel(R) 855GM";
101 dinfo->chipset = INTEL_855GM;
102 return 0;
103 case INTEL_VAR_852GME:
104 dinfo->name = "Intel(R) 852GME";
105 dinfo->chipset = INTEL_852GME;
106 return 0;
107 case INTEL_VAR_852GM:
108 dinfo->name = "Intel(R) 852GM";
109 dinfo->chipset = INTEL_852GM;
110 return 0;
111 default:
112 dinfo->name = "Intel(R) 852GM/855GM";
113 dinfo->chipset = INTEL_85XGM;
114 return 0;
115 }
116 break;
117 case PCI_DEVICE_ID_INTEL_865G:
118 dinfo->name = "Intel(R) 865G";
119 dinfo->chipset = INTEL_865G;
120 dinfo->mobile = 0;
121 dinfo->pll_index = PLLS_I8xx;
122 return 0;
123 case PCI_DEVICE_ID_INTEL_915G:
124 dinfo->name = "Intel(R) 915G";
125 dinfo->chipset = INTEL_915G;
126 dinfo->mobile = 0;
127 dinfo->pll_index = PLLS_I9xx;
128 return 0;
129 case PCI_DEVICE_ID_INTEL_915GM:
130 dinfo->name = "Intel(R) 915GM";
131 dinfo->chipset = INTEL_915GM;
132 dinfo->mobile = 1;
133 dinfo->pll_index = PLLS_I9xx;
134 return 0;
135 case PCI_DEVICE_ID_INTEL_945G:
136 dinfo->name = "Intel(R) 945G";
137 dinfo->chipset = INTEL_945G;
138 dinfo->mobile = 0;
139 dinfo->pll_index = PLLS_I9xx;
140 return 0;
141 case PCI_DEVICE_ID_INTEL_945GM:
142 dinfo->name = "Intel(R) 945GM";
143 dinfo->chipset = INTEL_945GM;
144 dinfo->mobile = 1;
145 dinfo->pll_index = PLLS_I9xx;
146 return 0;
147 default:
148 return 1;
149 }
150 }
151
152 int
153 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
154 int *stolen_size)
155 {
156 struct pci_dev *bridge_dev;
157 u16 tmp;
158 int stolen_overhead;
159
160 if (!pdev || !aperture_size || !stolen_size)
161 return 1;
162
163 /* Find the bridge device. It is always 0:0.0 */
164 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
165 ERR_MSG("cannot find bridge device\n");
166 return 1;
167 }
168
169 /* Get the fb aperture size and "stolen" memory amount. */
170 tmp = 0;
171 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
172 switch (pdev->device) {
173 case PCI_DEVICE_ID_INTEL_915G:
174 case PCI_DEVICE_ID_INTEL_915GM:
175 case PCI_DEVICE_ID_INTEL_945G:
176 case PCI_DEVICE_ID_INTEL_945GM:
177 /* 915 and 945 chipsets support a 256MB aperture.
178 Aperture size is determined by inspected the
179 base address of the aperture. */
180 if (pci_resource_start(pdev, 2) & 0x08000000)
181 *aperture_size = MB(128);
182 else
183 *aperture_size = MB(256);
184 break;
185 default:
186 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
187 *aperture_size = MB(64);
188 else
189 *aperture_size = MB(128);
190 break;
191 }
192
193 /* Stolen memory size is reduced by the GTT and the popup.
194 GTT is 1K per MB of aperture size, and popup is 4K. */
195 stolen_overhead = (*aperture_size / MB(1)) + 4;
196 switch(pdev->device) {
197 case PCI_DEVICE_ID_INTEL_830M:
198 case PCI_DEVICE_ID_INTEL_845G:
199 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
200 case INTEL_830_GMCH_GMS_STOLEN_512:
201 *stolen_size = KB(512) - KB(stolen_overhead);
202 return 0;
203 case INTEL_830_GMCH_GMS_STOLEN_1024:
204 *stolen_size = MB(1) - KB(stolen_overhead);
205 return 0;
206 case INTEL_830_GMCH_GMS_STOLEN_8192:
207 *stolen_size = MB(8) - KB(stolen_overhead);
208 return 0;
209 case INTEL_830_GMCH_GMS_LOCAL:
210 ERR_MSG("only local memory found\n");
211 return 1;
212 case INTEL_830_GMCH_GMS_DISABLED:
213 ERR_MSG("video memory is disabled\n");
214 return 1;
215 default:
216 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
217 tmp & INTEL_830_GMCH_GMS_MASK);
218 return 1;
219 }
220 break;
221 default:
222 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
223 case INTEL_855_GMCH_GMS_STOLEN_1M:
224 *stolen_size = MB(1) - KB(stolen_overhead);
225 return 0;
226 case INTEL_855_GMCH_GMS_STOLEN_4M:
227 *stolen_size = MB(4) - KB(stolen_overhead);
228 return 0;
229 case INTEL_855_GMCH_GMS_STOLEN_8M:
230 *stolen_size = MB(8) - KB(stolen_overhead);
231 return 0;
232 case INTEL_855_GMCH_GMS_STOLEN_16M:
233 *stolen_size = MB(16) - KB(stolen_overhead);
234 return 0;
235 case INTEL_855_GMCH_GMS_STOLEN_32M:
236 *stolen_size = MB(32) - KB(stolen_overhead);
237 return 0;
238 case INTEL_915G_GMCH_GMS_STOLEN_48M:
239 *stolen_size = MB(48) - KB(stolen_overhead);
240 return 0;
241 case INTEL_915G_GMCH_GMS_STOLEN_64M:
242 *stolen_size = MB(64) - KB(stolen_overhead);
243 return 0;
244 case INTEL_855_GMCH_GMS_DISABLED:
245 ERR_MSG("video memory is disabled\n");
246 return 0;
247 default:
248 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
249 tmp & INTEL_855_GMCH_GMS_MASK);
250 return 1;
251 }
252 }
253 }
254
255 int
256 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
257 {
258 int dvo = 0;
259
260 if (INREG(LVDS) & PORT_ENABLE)
261 dvo |= LVDS_PORT;
262 if (INREG(DVOA) & PORT_ENABLE)
263 dvo |= DVOA_PORT;
264 if (INREG(DVOB) & PORT_ENABLE)
265 dvo |= DVOB_PORT;
266 if (INREG(DVOC) & PORT_ENABLE)
267 dvo |= DVOC_PORT;
268
269 return dvo;
270 }
271
272 const char *
273 intelfbhw_dvo_to_string(int dvo)
274 {
275 if (dvo & DVOA_PORT)
276 return "DVO port A";
277 else if (dvo & DVOB_PORT)
278 return "DVO port B";
279 else if (dvo & DVOC_PORT)
280 return "DVO port C";
281 else if (dvo & LVDS_PORT)
282 return "LVDS port";
283 else
284 return NULL;
285 }
286
287
288 int
289 intelfbhw_validate_mode(struct intelfb_info *dinfo,
290 struct fb_var_screeninfo *var)
291 {
292 int bytes_per_pixel;
293 int tmp;
294
295 #if VERBOSE > 0
296 DBG_MSG("intelfbhw_validate_mode\n");
297 #endif
298
299 bytes_per_pixel = var->bits_per_pixel / 8;
300 if (bytes_per_pixel == 3)
301 bytes_per_pixel = 4;
302
303 /* Check if enough video memory. */
304 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
305 if (tmp > dinfo->fb.size) {
306 WRN_MSG("Not enough video ram for mode "
307 "(%d KByte vs %d KByte).\n",
308 BtoKB(tmp), BtoKB(dinfo->fb.size));
309 return 1;
310 }
311
312 /* Check if x/y limits are OK. */
313 if (var->xres - 1 > HACTIVE_MASK) {
314 WRN_MSG("X resolution too large (%d vs %d).\n",
315 var->xres, HACTIVE_MASK + 1);
316 return 1;
317 }
318 if (var->yres - 1 > VACTIVE_MASK) {
319 WRN_MSG("Y resolution too large (%d vs %d).\n",
320 var->yres, VACTIVE_MASK + 1);
321 return 1;
322 }
323
324 /* Check for interlaced/doublescan modes. */
325 if (var->vmode & FB_VMODE_INTERLACED) {
326 WRN_MSG("Mode is interlaced.\n");
327 return 1;
328 }
329 if (var->vmode & FB_VMODE_DOUBLE) {
330 WRN_MSG("Mode is double-scan.\n");
331 return 1;
332 }
333
334 /* Check if clock is OK. */
335 tmp = 1000000000 / var->pixclock;
336 if (tmp < MIN_CLOCK) {
337 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
338 (tmp + 500) / 1000, MIN_CLOCK / 1000);
339 return 1;
340 }
341 if (tmp > MAX_CLOCK) {
342 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
343 (tmp + 500) / 1000, MAX_CLOCK / 1000);
344 return 1;
345 }
346
347 return 0;
348 }
349
350 int
351 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
352 {
353 struct intelfb_info *dinfo = GET_DINFO(info);
354 u32 offset, xoffset, yoffset;
355
356 #if VERBOSE > 0
357 DBG_MSG("intelfbhw_pan_display\n");
358 #endif
359
360 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
361 yoffset = var->yoffset;
362
363 if ((xoffset + var->xres > var->xres_virtual) ||
364 (yoffset + var->yres > var->yres_virtual))
365 return -EINVAL;
366
367 offset = (yoffset * dinfo->pitch) +
368 (xoffset * var->bits_per_pixel) / 8;
369
370 offset += dinfo->fb.offset << 12;
371
372 dinfo->vsync.pan_offset = offset;
373 if ((var->activate & FB_ACTIVATE_VBL) && !intelfbhw_enable_irq(dinfo, 0)) {
374 dinfo->vsync.pan_display = 1;
375 } else {
376 dinfo->vsync.pan_display = 0;
377 OUTREG(DSPABASE, offset);
378 }
379
380 return 0;
381 }
382
383 /* Blank the screen. */
384 void
385 intelfbhw_do_blank(int blank, struct fb_info *info)
386 {
387 struct intelfb_info *dinfo = GET_DINFO(info);
388 u32 tmp;
389
390 #if VERBOSE > 0
391 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
392 #endif
393
394 /* Turn plane A on or off */
395 tmp = INREG(DSPACNTR);
396 if (blank)
397 tmp &= ~DISPPLANE_PLANE_ENABLE;
398 else
399 tmp |= DISPPLANE_PLANE_ENABLE;
400 OUTREG(DSPACNTR, tmp);
401 /* Flush */
402 tmp = INREG(DSPABASE);
403 OUTREG(DSPABASE, tmp);
404
405 /* Turn off/on the HW cursor */
406 #if VERBOSE > 0
407 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
408 #endif
409 if (dinfo->cursor_on) {
410 if (blank) {
411 intelfbhw_cursor_hide(dinfo);
412 } else {
413 intelfbhw_cursor_show(dinfo);
414 }
415 dinfo->cursor_on = 1;
416 }
417 dinfo->cursor_blanked = blank;
418
419 /* Set DPMS level */
420 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
421 switch (blank) {
422 case FB_BLANK_UNBLANK:
423 case FB_BLANK_NORMAL:
424 tmp |= ADPA_DPMS_D0;
425 break;
426 case FB_BLANK_VSYNC_SUSPEND:
427 tmp |= ADPA_DPMS_D1;
428 break;
429 case FB_BLANK_HSYNC_SUSPEND:
430 tmp |= ADPA_DPMS_D2;
431 break;
432 case FB_BLANK_POWERDOWN:
433 tmp |= ADPA_DPMS_D3;
434 break;
435 }
436 OUTREG(ADPA, tmp);
437
438 return;
439 }
440
441
442 void
443 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
444 unsigned red, unsigned green, unsigned blue,
445 unsigned transp)
446 {
447 #if VERBOSE > 0
448 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
449 regno, red, green, blue);
450 #endif
451
452 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
453 PALETTE_A : PALETTE_B;
454
455 OUTREG(palette_reg + (regno << 2),
456 (red << PALETTE_8_RED_SHIFT) |
457 (green << PALETTE_8_GREEN_SHIFT) |
458 (blue << PALETTE_8_BLUE_SHIFT));
459 }
460
461
462 int
463 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
464 int flag)
465 {
466 int i;
467
468 #if VERBOSE > 0
469 DBG_MSG("intelfbhw_read_hw_state\n");
470 #endif
471
472 if (!hw || !dinfo)
473 return -1;
474
475 /* Read in as much of the HW state as possible. */
476 hw->vga0_divisor = INREG(VGA0_DIVISOR);
477 hw->vga1_divisor = INREG(VGA1_DIVISOR);
478 hw->vga_pd = INREG(VGAPD);
479 hw->dpll_a = INREG(DPLL_A);
480 hw->dpll_b = INREG(DPLL_B);
481 hw->fpa0 = INREG(FPA0);
482 hw->fpa1 = INREG(FPA1);
483 hw->fpb0 = INREG(FPB0);
484 hw->fpb1 = INREG(FPB1);
485
486 if (flag == 1)
487 return flag;
488
489 #if 0
490 /* This seems to be a problem with the 852GM/855GM */
491 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
492 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
493 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
494 }
495 #endif
496
497 if (flag == 2)
498 return flag;
499
500 hw->htotal_a = INREG(HTOTAL_A);
501 hw->hblank_a = INREG(HBLANK_A);
502 hw->hsync_a = INREG(HSYNC_A);
503 hw->vtotal_a = INREG(VTOTAL_A);
504 hw->vblank_a = INREG(VBLANK_A);
505 hw->vsync_a = INREG(VSYNC_A);
506 hw->src_size_a = INREG(SRC_SIZE_A);
507 hw->bclrpat_a = INREG(BCLRPAT_A);
508 hw->htotal_b = INREG(HTOTAL_B);
509 hw->hblank_b = INREG(HBLANK_B);
510 hw->hsync_b = INREG(HSYNC_B);
511 hw->vtotal_b = INREG(VTOTAL_B);
512 hw->vblank_b = INREG(VBLANK_B);
513 hw->vsync_b = INREG(VSYNC_B);
514 hw->src_size_b = INREG(SRC_SIZE_B);
515 hw->bclrpat_b = INREG(BCLRPAT_B);
516
517 if (flag == 3)
518 return flag;
519
520 hw->adpa = INREG(ADPA);
521 hw->dvoa = INREG(DVOA);
522 hw->dvob = INREG(DVOB);
523 hw->dvoc = INREG(DVOC);
524 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
525 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
526 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
527 hw->lvds = INREG(LVDS);
528
529 if (flag == 4)
530 return flag;
531
532 hw->pipe_a_conf = INREG(PIPEACONF);
533 hw->pipe_b_conf = INREG(PIPEBCONF);
534 hw->disp_arb = INREG(DISPARB);
535
536 if (flag == 5)
537 return flag;
538
539 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
540 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
541 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
542 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
543
544 if (flag == 6)
545 return flag;
546
547 for (i = 0; i < 4; i++) {
548 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
549 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
550 }
551
552 if (flag == 7)
553 return flag;
554
555 hw->cursor_size = INREG(CURSOR_SIZE);
556
557 if (flag == 8)
558 return flag;
559
560 hw->disp_a_ctrl = INREG(DSPACNTR);
561 hw->disp_b_ctrl = INREG(DSPBCNTR);
562 hw->disp_a_base = INREG(DSPABASE);
563 hw->disp_b_base = INREG(DSPBBASE);
564 hw->disp_a_stride = INREG(DSPASTRIDE);
565 hw->disp_b_stride = INREG(DSPBSTRIDE);
566
567 if (flag == 9)
568 return flag;
569
570 hw->vgacntrl = INREG(VGACNTRL);
571
572 if (flag == 10)
573 return flag;
574
575 hw->add_id = INREG(ADD_ID);
576
577 if (flag == 11)
578 return flag;
579
580 for (i = 0; i < 7; i++) {
581 hw->swf0x[i] = INREG(SWF00 + (i << 2));
582 hw->swf1x[i] = INREG(SWF10 + (i << 2));
583 if (i < 3)
584 hw->swf3x[i] = INREG(SWF30 + (i << 2));
585 }
586
587 for (i = 0; i < 8; i++)
588 hw->fence[i] = INREG(FENCE + (i << 2));
589
590 hw->instpm = INREG(INSTPM);
591 hw->mem_mode = INREG(MEM_MODE);
592 hw->fw_blc_0 = INREG(FW_BLC_0);
593 hw->fw_blc_1 = INREG(FW_BLC_1);
594
595 hw->hwstam = INREG16(HWSTAM);
596 hw->ier = INREG16(IER);
597 hw->iir = INREG16(IIR);
598 hw->imr = INREG16(IMR);
599
600 return 0;
601 }
602
603
604 static int calc_vclock3(int index, int m, int n, int p)
605 {
606 if (p == 0 || n == 0)
607 return 0;
608 return plls[index].ref_clk * m / n / p;
609 }
610
611 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
612 {
613 struct pll_min_max *pll = &plls[index];
614 u32 m, vco, p;
615
616 m = (5 * (m1 + 2)) + (m2 + 2);
617 n += 2;
618 vco = pll->ref_clk * m / n;
619
620 if (index == PLLS_I8xx) {
621 p = ((p1 + 2) * (1 << (p2 + 1)));
622 } else {
623 p = ((p1) * (p2 ? 5 : 10));
624 }
625 return vco / p;
626 }
627
628 #if REGDUMP
629 static void
630 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
631 {
632 int p1, p2;
633
634 if (IS_I9XX(dinfo)) {
635 if (dpll & DPLL_P1_FORCE_DIV2)
636 p1 = 1;
637 else
638 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
639
640 p1 = ffs(p1);
641
642 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
643 } else {
644 if (dpll & DPLL_P1_FORCE_DIV2)
645 p1 = 0;
646 else
647 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
648 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
649 }
650
651 *o_p1 = p1;
652 *o_p2 = p2;
653 }
654 #endif
655
656
657 void
658 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
659 {
660 #if REGDUMP
661 int i, m1, m2, n, p1, p2;
662 int index = dinfo->pll_index;
663 DBG_MSG("intelfbhw_print_hw_state\n");
664
665 if (!hw || !dinfo)
666 return;
667 /* Read in as much of the HW state as possible. */
668 printk("hw state dump start\n");
669 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
670 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
671 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
672 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
673 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
674 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
675
676 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
677
678 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
679 m1, m2, n, p1, p2);
680 printk(" VGA0: clock is %d\n",
681 calc_vclock(index, m1, m2, n, p1, p2, 0));
682
683 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
684 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
685 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
686
687 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
688 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
689 m1, m2, n, p1, p2);
690 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
691
692 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
693 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
694 printk(" FPA0: 0x%08x\n", hw->fpa0);
695 printk(" FPA1: 0x%08x\n", hw->fpa1);
696 printk(" FPB0: 0x%08x\n", hw->fpb0);
697 printk(" FPB1: 0x%08x\n", hw->fpb1);
698
699 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
700 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
701 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
702
703 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
704
705 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
706 m1, m2, n, p1, p2);
707 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
708
709 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
710 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
711 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
712
713 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
714
715 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
716 m1, m2, n, p1, p2);
717 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
718
719 #if 0
720 printk(" PALETTE_A:\n");
721 for (i = 0; i < PALETTE_8_ENTRIES)
722 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
723 printk(" PALETTE_B:\n");
724 for (i = 0; i < PALETTE_8_ENTRIES)
725 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
726 #endif
727
728 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
729 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
730 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
731 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
732 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
733 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
734 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
735 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
736 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
737 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
738 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
739 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
740 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
741 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
742 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
743 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
744
745 printk(" ADPA: 0x%08x\n", hw->adpa);
746 printk(" DVOA: 0x%08x\n", hw->dvoa);
747 printk(" DVOB: 0x%08x\n", hw->dvob);
748 printk(" DVOC: 0x%08x\n", hw->dvoc);
749 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
750 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
751 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
752 printk(" LVDS: 0x%08x\n", hw->lvds);
753
754 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
755 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
756 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
757
758 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
759 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
760 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
761 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
762
763 printk(" CURSOR_A_PALETTE: ");
764 for (i = 0; i < 4; i++) {
765 printk("0x%08x", hw->cursor_a_palette[i]);
766 if (i < 3)
767 printk(", ");
768 }
769 printk("\n");
770 printk(" CURSOR_B_PALETTE: ");
771 for (i = 0; i < 4; i++) {
772 printk("0x%08x", hw->cursor_b_palette[i]);
773 if (i < 3)
774 printk(", ");
775 }
776 printk("\n");
777
778 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
779
780 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
781 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
782 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
783 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
784 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
785 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
786
787 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
788 printk(" ADD_ID: 0x%08x\n", hw->add_id);
789
790 for (i = 0; i < 7; i++) {
791 printk(" SWF0%d 0x%08x\n", i,
792 hw->swf0x[i]);
793 }
794 for (i = 0; i < 7; i++) {
795 printk(" SWF1%d 0x%08x\n", i,
796 hw->swf1x[i]);
797 }
798 for (i = 0; i < 3; i++) {
799 printk(" SWF3%d 0x%08x\n", i,
800 hw->swf3x[i]);
801 }
802 for (i = 0; i < 8; i++)
803 printk(" FENCE%d 0x%08x\n", i,
804 hw->fence[i]);
805
806 printk(" INSTPM 0x%08x\n", hw->instpm);
807 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
808 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
809 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
810
811 printk(" HWSTAM 0x%04x\n", hw->hwstam);
812 printk(" IER 0x%04x\n", hw->ier);
813 printk(" IIR 0x%04x\n", hw->iir);
814 printk(" IMR 0x%04x\n", hw->imr);
815 printk("hw state dump end\n");
816 #endif
817 }
818
819
820
821 /* Split the M parameter into M1 and M2. */
822 static int
823 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
824 {
825 int m1, m2;
826 int testm;
827 struct pll_min_max *pll = &plls[index];
828
829 /* no point optimising too much - brute force m */
830 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
831 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
832 testm = (5 * (m1 + 2)) + (m2 + 2);
833 if (testm == m) {
834 *retm1 = (unsigned int)m1;
835 *retm2 = (unsigned int)m2;
836 return 0;
837 }
838 }
839 }
840 return 1;
841 }
842
843 /* Split the P parameter into P1 and P2. */
844 static int
845 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
846 {
847 int p1, p2;
848 struct pll_min_max *pll = &plls[index];
849
850 if (index == PLLS_I9xx) {
851 p2 = (p % 10) ? 1 : 0;
852
853 p1 = p / (p2 ? 5 : 10);
854
855 *retp1 = (unsigned int)p1;
856 *retp2 = (unsigned int)p2;
857 return 0;
858 }
859
860 if (p % 4 == 0)
861 p2 = 1;
862 else
863 p2 = 0;
864 p1 = (p / (1 << (p2 + 1))) - 2;
865 if (p % 4 == 0 && p1 < pll->min_p1) {
866 p2 = 0;
867 p1 = (p / (1 << (p2 + 1))) - 2;
868 }
869 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
870 (p1 + 2) * (1 << (p2 + 1)) != p) {
871 return 1;
872 } else {
873 *retp1 = (unsigned int)p1;
874 *retp2 = (unsigned int)p2;
875 return 0;
876 }
877 }
878
879 static int
880 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
881 u32 *retp2, u32 *retclock)
882 {
883 u32 m1, m2, n, p1, p2, n1, testm;
884 u32 f_vco, p, p_best = 0, m, f_out = 0;
885 u32 err_max, err_target, err_best = 10000000;
886 u32 n_best = 0, m_best = 0, f_best, f_err;
887 u32 p_min, p_max, p_inc, div_max;
888 struct pll_min_max *pll = &plls[index];
889
890 /* Accept 0.5% difference, but aim for 0.1% */
891 err_max = 5 * clock / 1000;
892 err_target = clock / 1000;
893
894 DBG_MSG("Clock is %d\n", clock);
895
896 div_max = pll->max_vco / clock;
897
898 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
899 p_min = p_inc;
900 p_max = ROUND_DOWN_TO(div_max, p_inc);
901 if (p_min < pll->min_p)
902 p_min = pll->min_p;
903 if (p_max > pll->max_p)
904 p_max = pll->max_p;
905
906 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
907
908 p = p_min;
909 do {
910 if (splitp(index, p, &p1, &p2)) {
911 WRN_MSG("cannot split p = %d\n", p);
912 p += p_inc;
913 continue;
914 }
915 n = pll->min_n;
916 f_vco = clock * p;
917
918 do {
919 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
920 if (m < pll->min_m)
921 m = pll->min_m + 1;
922 if (m > pll->max_m)
923 m = pll->max_m - 1;
924 for (testm = m - 1; testm <= m; testm++) {
925 f_out = calc_vclock3(index, m, n, p);
926 if (splitm(index, testm, &m1, &m2)) {
927 WRN_MSG("cannot split m = %d\n", m);
928 n++;
929 continue;
930 }
931 if (clock > f_out)
932 f_err = clock - f_out;
933 else/* slightly bias the error for bigger clocks */
934 f_err = f_out - clock + 1;
935
936 if (f_err < err_best) {
937 m_best = testm;
938 n_best = n;
939 p_best = p;
940 f_best = f_out;
941 err_best = f_err;
942 }
943 }
944 n++;
945 } while ((n <= pll->max_n) && (f_out >= clock));
946 p += p_inc;
947 } while ((p <= p_max));
948
949 if (!m_best) {
950 WRN_MSG("cannot find parameters for clock %d\n", clock);
951 return 1;
952 }
953 m = m_best;
954 n = n_best;
955 p = p_best;
956 splitm(index, m, &m1, &m2);
957 splitp(index, p, &p1, &p2);
958 n1 = n - 2;
959
960 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
961 "f: %d (%d), VCO: %d\n",
962 m, m1, m2, n, n1, p, p1, p2,
963 calc_vclock3(index, m, n, p),
964 calc_vclock(index, m1, m2, n1, p1, p2, 0),
965 calc_vclock3(index, m, n, p) * p);
966 *retm1 = m1;
967 *retm2 = m2;
968 *retn = n1;
969 *retp1 = p1;
970 *retp2 = p2;
971 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
972
973 return 0;
974 }
975
976 static __inline__ int
977 check_overflow(u32 value, u32 limit, const char *description)
978 {
979 if (value > limit) {
980 WRN_MSG("%s value %d exceeds limit %d\n",
981 description, value, limit);
982 return 1;
983 }
984 return 0;
985 }
986
987 /* It is assumed that hw is filled in with the initial state information. */
988 int
989 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
990 struct fb_var_screeninfo *var)
991 {
992 int pipe = PIPE_A;
993 u32 *dpll, *fp0, *fp1;
994 u32 m1, m2, n, p1, p2, clock_target, clock;
995 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
996 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
997 u32 vsync_pol, hsync_pol;
998 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
999 u32 stride_alignment;
1000
1001 DBG_MSG("intelfbhw_mode_to_hw\n");
1002
1003 /* Disable VGA */
1004 hw->vgacntrl |= VGA_DISABLE;
1005
1006 /* Check whether pipe A or pipe B is enabled. */
1007 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1008 pipe = PIPE_A;
1009 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1010 pipe = PIPE_B;
1011
1012 /* Set which pipe's registers will be set. */
1013 if (pipe == PIPE_B) {
1014 dpll = &hw->dpll_b;
1015 fp0 = &hw->fpb0;
1016 fp1 = &hw->fpb1;
1017 hs = &hw->hsync_b;
1018 hb = &hw->hblank_b;
1019 ht = &hw->htotal_b;
1020 vs = &hw->vsync_b;
1021 vb = &hw->vblank_b;
1022 vt = &hw->vtotal_b;
1023 ss = &hw->src_size_b;
1024 pipe_conf = &hw->pipe_b_conf;
1025 } else {
1026 dpll = &hw->dpll_a;
1027 fp0 = &hw->fpa0;
1028 fp1 = &hw->fpa1;
1029 hs = &hw->hsync_a;
1030 hb = &hw->hblank_a;
1031 ht = &hw->htotal_a;
1032 vs = &hw->vsync_a;
1033 vb = &hw->vblank_a;
1034 vt = &hw->vtotal_a;
1035 ss = &hw->src_size_a;
1036 pipe_conf = &hw->pipe_a_conf;
1037 }
1038
1039 /* Use ADPA register for sync control. */
1040 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1041
1042 /* sync polarity */
1043 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1044 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1045 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1046 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1047 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1048 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1049 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1050 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1051
1052 /* Connect correct pipe to the analog port DAC */
1053 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1054 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1055
1056 /* Set DPMS state to D0 (on) */
1057 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1058 hw->adpa |= ADPA_DPMS_D0;
1059
1060 hw->adpa |= ADPA_DAC_ENABLE;
1061
1062 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1063 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1064 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1065
1066 /* Desired clock in kHz */
1067 clock_target = 1000000000 / var->pixclock;
1068
1069 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1070 &n, &p1, &p2, &clock)) {
1071 WRN_MSG("calc_pll_params failed\n");
1072 return 1;
1073 }
1074
1075 /* Check for overflow. */
1076 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1077 return 1;
1078 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1079 return 1;
1080 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1081 return 1;
1082 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1083 return 1;
1084 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1085 return 1;
1086
1087 *dpll &= ~DPLL_P1_FORCE_DIV2;
1088 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1089 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1090
1091 if (IS_I9XX(dinfo)) {
1092 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1093 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1094 } else {
1095 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1096 }
1097
1098 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1099 (m1 << FP_M1_DIVISOR_SHIFT) |
1100 (m2 << FP_M2_DIVISOR_SHIFT);
1101 *fp1 = *fp0;
1102
1103 hw->dvob &= ~PORT_ENABLE;
1104 hw->dvoc &= ~PORT_ENABLE;
1105
1106 /* Use display plane A. */
1107 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1108 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1109 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1110 switch (intelfb_var_to_depth(var)) {
1111 case 8:
1112 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1113 break;
1114 case 15:
1115 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1116 break;
1117 case 16:
1118 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1119 break;
1120 case 24:
1121 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1122 break;
1123 }
1124 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1125 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1126
1127 /* Set CRTC registers. */
1128 hactive = var->xres;
1129 hsync_start = hactive + var->right_margin;
1130 hsync_end = hsync_start + var->hsync_len;
1131 htotal = hsync_end + var->left_margin;
1132 hblank_start = hactive;
1133 hblank_end = htotal;
1134
1135 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1136 hactive, hsync_start, hsync_end, htotal, hblank_start,
1137 hblank_end);
1138
1139 vactive = var->yres;
1140 vsync_start = vactive + var->lower_margin;
1141 vsync_end = vsync_start + var->vsync_len;
1142 vtotal = vsync_end + var->upper_margin;
1143 vblank_start = vactive;
1144 vblank_end = vtotal;
1145 vblank_end = vsync_end + 1;
1146
1147 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1148 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1149 vblank_end);
1150
1151 /* Adjust for register values, and check for overflow. */
1152 hactive--;
1153 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1154 return 1;
1155 hsync_start--;
1156 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1157 return 1;
1158 hsync_end--;
1159 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1160 return 1;
1161 htotal--;
1162 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1163 return 1;
1164 hblank_start--;
1165 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1166 return 1;
1167 hblank_end--;
1168 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1169 return 1;
1170
1171 vactive--;
1172 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1173 return 1;
1174 vsync_start--;
1175 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1176 return 1;
1177 vsync_end--;
1178 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1179 return 1;
1180 vtotal--;
1181 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1182 return 1;
1183 vblank_start--;
1184 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1185 return 1;
1186 vblank_end--;
1187 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1188 return 1;
1189
1190 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1191 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1192 (hblank_end << HSYNCEND_SHIFT);
1193 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1194
1195 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1196 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1197 (vblank_end << VSYNCEND_SHIFT);
1198 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1199 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1200 (vactive << SRC_SIZE_VERT_SHIFT);
1201
1202 hw->disp_a_stride = dinfo->pitch;
1203 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1204
1205 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1206 var->xoffset * var->bits_per_pixel / 8;
1207
1208 hw->disp_a_base += dinfo->fb.offset << 12;
1209
1210 /* Check stride alignment. */
1211 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1212 STRIDE_ALIGNMENT;
1213 if (hw->disp_a_stride % stride_alignment != 0) {
1214 WRN_MSG("display stride %d has bad alignment %d\n",
1215 hw->disp_a_stride, stride_alignment);
1216 return 1;
1217 }
1218
1219 /* Set the palette to 8-bit mode. */
1220 *pipe_conf &= ~PIPECONF_GAMMA;
1221 return 0;
1222 }
1223
1224 /* Program a (non-VGA) video mode. */
1225 int
1226 intelfbhw_program_mode(struct intelfb_info *dinfo,
1227 const struct intelfb_hwstate *hw, int blank)
1228 {
1229 int pipe = PIPE_A;
1230 u32 tmp;
1231 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1232 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1233 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1234 u32 hsync_reg, htotal_reg, hblank_reg;
1235 u32 vsync_reg, vtotal_reg, vblank_reg;
1236 u32 src_size_reg;
1237 u32 count, tmp_val[3];
1238
1239 /* Assume single pipe, display plane A, analog CRT. */
1240
1241 #if VERBOSE > 0
1242 DBG_MSG("intelfbhw_program_mode\n");
1243 #endif
1244
1245 /* Disable VGA */
1246 tmp = INREG(VGACNTRL);
1247 tmp |= VGA_DISABLE;
1248 OUTREG(VGACNTRL, tmp);
1249
1250 /* Check whether pipe A or pipe B is enabled. */
1251 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1252 pipe = PIPE_A;
1253 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1254 pipe = PIPE_B;
1255
1256 dinfo->pipe = pipe;
1257
1258 if (pipe == PIPE_B) {
1259 dpll = &hw->dpll_b;
1260 fp0 = &hw->fpb0;
1261 fp1 = &hw->fpb1;
1262 pipe_conf = &hw->pipe_b_conf;
1263 hs = &hw->hsync_b;
1264 hb = &hw->hblank_b;
1265 ht = &hw->htotal_b;
1266 vs = &hw->vsync_b;
1267 vb = &hw->vblank_b;
1268 vt = &hw->vtotal_b;
1269 ss = &hw->src_size_b;
1270 dpll_reg = DPLL_B;
1271 fp0_reg = FPB0;
1272 fp1_reg = FPB1;
1273 pipe_conf_reg = PIPEBCONF;
1274 hsync_reg = HSYNC_B;
1275 htotal_reg = HTOTAL_B;
1276 hblank_reg = HBLANK_B;
1277 vsync_reg = VSYNC_B;
1278 vtotal_reg = VTOTAL_B;
1279 vblank_reg = VBLANK_B;
1280 src_size_reg = SRC_SIZE_B;
1281 } else {
1282 dpll = &hw->dpll_a;
1283 fp0 = &hw->fpa0;
1284 fp1 = &hw->fpa1;
1285 pipe_conf = &hw->pipe_a_conf;
1286 hs = &hw->hsync_a;
1287 hb = &hw->hblank_a;
1288 ht = &hw->htotal_a;
1289 vs = &hw->vsync_a;
1290 vb = &hw->vblank_a;
1291 vt = &hw->vtotal_a;
1292 ss = &hw->src_size_a;
1293 dpll_reg = DPLL_A;
1294 fp0_reg = FPA0;
1295 fp1_reg = FPA1;
1296 pipe_conf_reg = PIPEACONF;
1297 hsync_reg = HSYNC_A;
1298 htotal_reg = HTOTAL_A;
1299 hblank_reg = HBLANK_A;
1300 vsync_reg = VSYNC_A;
1301 vtotal_reg = VTOTAL_A;
1302 vblank_reg = VBLANK_A;
1303 src_size_reg = SRC_SIZE_A;
1304 }
1305
1306 /* turn off pipe */
1307 tmp = INREG(pipe_conf_reg);
1308 tmp &= ~PIPECONF_ENABLE;
1309 OUTREG(pipe_conf_reg, tmp);
1310
1311 count = 0;
1312 do {
1313 tmp_val[count%3] = INREG(0x70000);
1314 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1315 break;
1316 count++;
1317 udelay(1);
1318 if (count % 200 == 0) {
1319 tmp = INREG(pipe_conf_reg);
1320 tmp &= ~PIPECONF_ENABLE;
1321 OUTREG(pipe_conf_reg, tmp);
1322 }
1323 } while(count < 2000);
1324
1325 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1326
1327 /* Disable planes A and B. */
1328 tmp = INREG(DSPACNTR);
1329 tmp &= ~DISPPLANE_PLANE_ENABLE;
1330 OUTREG(DSPACNTR, tmp);
1331 tmp = INREG(DSPBCNTR);
1332 tmp &= ~DISPPLANE_PLANE_ENABLE;
1333 OUTREG(DSPBCNTR, tmp);
1334
1335 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1336 mdelay(20);
1337
1338 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1339 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1340 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1341
1342 /* Disable Sync */
1343 tmp = INREG(ADPA);
1344 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1345 tmp |= ADPA_DPMS_D3;
1346 OUTREG(ADPA, tmp);
1347
1348 /* do some funky magic - xyzzy */
1349 OUTREG(0x61204, 0xabcd0000);
1350
1351 /* turn off PLL */
1352 tmp = INREG(dpll_reg);
1353 dpll_reg &= ~DPLL_VCO_ENABLE;
1354 OUTREG(dpll_reg, tmp);
1355
1356 /* Set PLL parameters */
1357 OUTREG(fp0_reg, *fp0);
1358 OUTREG(fp1_reg, *fp1);
1359
1360 /* Enable PLL */
1361 OUTREG(dpll_reg, *dpll);
1362
1363 /* Set DVOs B/C */
1364 OUTREG(DVOB, hw->dvob);
1365 OUTREG(DVOC, hw->dvoc);
1366
1367 /* undo funky magic */
1368 OUTREG(0x61204, 0x00000000);
1369
1370 /* Set ADPA */
1371 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1372 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1373
1374 /* Set pipe parameters */
1375 OUTREG(hsync_reg, *hs);
1376 OUTREG(hblank_reg, *hb);
1377 OUTREG(htotal_reg, *ht);
1378 OUTREG(vsync_reg, *vs);
1379 OUTREG(vblank_reg, *vb);
1380 OUTREG(vtotal_reg, *vt);
1381 OUTREG(src_size_reg, *ss);
1382
1383 /* Enable pipe */
1384 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1385
1386 /* Enable sync */
1387 tmp = INREG(ADPA);
1388 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1389 tmp |= ADPA_DPMS_D0;
1390 OUTREG(ADPA, tmp);
1391
1392 /* setup display plane */
1393 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1394 /*
1395 * i830M errata: the display plane must be enabled
1396 * to allow writes to the other bits in the plane
1397 * control register.
1398 */
1399 tmp = INREG(DSPACNTR);
1400 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1401 tmp |= DISPPLANE_PLANE_ENABLE;
1402 OUTREG(DSPACNTR, tmp);
1403 OUTREG(DSPACNTR,
1404 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1405 mdelay(1);
1406 }
1407 }
1408
1409 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1410 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1411 OUTREG(DSPABASE, hw->disp_a_base);
1412
1413 /* Enable plane */
1414 if (!blank) {
1415 tmp = INREG(DSPACNTR);
1416 tmp |= DISPPLANE_PLANE_ENABLE;
1417 OUTREG(DSPACNTR, tmp);
1418 OUTREG(DSPABASE, hw->disp_a_base);
1419 }
1420
1421 return 0;
1422 }
1423
1424 /* forward declarations */
1425 static void refresh_ring(struct intelfb_info *dinfo);
1426 static void reset_state(struct intelfb_info *dinfo);
1427 static void do_flush(struct intelfb_info *dinfo);
1428
1429 static int
1430 wait_ring(struct intelfb_info *dinfo, int n)
1431 {
1432 int i = 0;
1433 unsigned long end;
1434 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1435
1436 #if VERBOSE > 0
1437 DBG_MSG("wait_ring: %d\n", n);
1438 #endif
1439
1440 end = jiffies + (HZ * 3);
1441 while (dinfo->ring_space < n) {
1442 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1443 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1444 dinfo->ring_space = dinfo->ring_head
1445 - (dinfo->ring_tail + RING_MIN_FREE);
1446 else
1447 dinfo->ring_space = (dinfo->ring.size +
1448 dinfo->ring_head)
1449 - (dinfo->ring_tail + RING_MIN_FREE);
1450 if (dinfo->ring_head != last_head) {
1451 end = jiffies + (HZ * 3);
1452 last_head = dinfo->ring_head;
1453 }
1454 i++;
1455 if (time_before(end, jiffies)) {
1456 if (!i) {
1457 /* Try again */
1458 reset_state(dinfo);
1459 refresh_ring(dinfo);
1460 do_flush(dinfo);
1461 end = jiffies + (HZ * 3);
1462 i = 1;
1463 } else {
1464 WRN_MSG("ring buffer : space: %d wanted %d\n",
1465 dinfo->ring_space, n);
1466 WRN_MSG("lockup - turning off hardware "
1467 "acceleration\n");
1468 dinfo->ring_lockup = 1;
1469 break;
1470 }
1471 }
1472 udelay(1);
1473 }
1474 return i;
1475 }
1476
1477 static void
1478 do_flush(struct intelfb_info *dinfo) {
1479 START_RING(2);
1480 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1481 OUT_RING(MI_NOOP);
1482 ADVANCE_RING();
1483 }
1484
1485 void
1486 intelfbhw_do_sync(struct intelfb_info *dinfo)
1487 {
1488 #if VERBOSE > 0
1489 DBG_MSG("intelfbhw_do_sync\n");
1490 #endif
1491
1492 if (!dinfo->accel)
1493 return;
1494
1495 /*
1496 * Send a flush, then wait until the ring is empty. This is what
1497 * the XFree86 driver does, and actually it doesn't seem a lot worse
1498 * than the recommended method (both have problems).
1499 */
1500 do_flush(dinfo);
1501 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1502 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1503 }
1504
1505 static void
1506 refresh_ring(struct intelfb_info *dinfo)
1507 {
1508 #if VERBOSE > 0
1509 DBG_MSG("refresh_ring\n");
1510 #endif
1511
1512 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1513 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1514 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1515 dinfo->ring_space = dinfo->ring_head
1516 - (dinfo->ring_tail + RING_MIN_FREE);
1517 else
1518 dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
1519 - (dinfo->ring_tail + RING_MIN_FREE);
1520 }
1521
1522 static void
1523 reset_state(struct intelfb_info *dinfo)
1524 {
1525 int i;
1526 u32 tmp;
1527
1528 #if VERBOSE > 0
1529 DBG_MSG("reset_state\n");
1530 #endif
1531
1532 for (i = 0; i < FENCE_NUM; i++)
1533 OUTREG(FENCE + (i << 2), 0);
1534
1535 /* Flush the ring buffer if it's enabled. */
1536 tmp = INREG(PRI_RING_LENGTH);
1537 if (tmp & RING_ENABLE) {
1538 #if VERBOSE > 0
1539 DBG_MSG("reset_state: ring was enabled\n");
1540 #endif
1541 refresh_ring(dinfo);
1542 intelfbhw_do_sync(dinfo);
1543 DO_RING_IDLE();
1544 }
1545
1546 OUTREG(PRI_RING_LENGTH, 0);
1547 OUTREG(PRI_RING_HEAD, 0);
1548 OUTREG(PRI_RING_TAIL, 0);
1549 OUTREG(PRI_RING_START, 0);
1550 }
1551
1552 /* Stop the 2D engine, and turn off the ring buffer. */
1553 void
1554 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1555 {
1556 #if VERBOSE > 0
1557 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1558 dinfo->ring_active);
1559 #endif
1560
1561 if (!dinfo->accel)
1562 return;
1563
1564 dinfo->ring_active = 0;
1565 reset_state(dinfo);
1566 }
1567
1568 /*
1569 * Enable the ring buffer, and initialise the 2D engine.
1570 * It is assumed that the graphics engine has been stopped by previously
1571 * calling intelfb_2d_stop().
1572 */
1573 void
1574 intelfbhw_2d_start(struct intelfb_info *dinfo)
1575 {
1576 #if VERBOSE > 0
1577 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1578 dinfo->accel, dinfo->ring_active);
1579 #endif
1580
1581 if (!dinfo->accel)
1582 return;
1583
1584 /* Initialise the primary ring buffer. */
1585 OUTREG(PRI_RING_LENGTH, 0);
1586 OUTREG(PRI_RING_TAIL, 0);
1587 OUTREG(PRI_RING_HEAD, 0);
1588
1589 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1590 OUTREG(PRI_RING_LENGTH,
1591 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1592 RING_NO_REPORT | RING_ENABLE);
1593 refresh_ring(dinfo);
1594 dinfo->ring_active = 1;
1595 }
1596
1597 /* 2D fillrect (solid fill or invert) */
1598 void
1599 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1600 u32 color, u32 pitch, u32 bpp, u32 rop)
1601 {
1602 u32 br00, br09, br13, br14, br16;
1603
1604 #if VERBOSE > 0
1605 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1606 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1607 #endif
1608
1609 br00 = COLOR_BLT_CMD;
1610 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1611 br13 = (rop << ROP_SHIFT) | pitch;
1612 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1613 br16 = color;
1614
1615 switch (bpp) {
1616 case 8:
1617 br13 |= COLOR_DEPTH_8;
1618 break;
1619 case 16:
1620 br13 |= COLOR_DEPTH_16;
1621 break;
1622 case 32:
1623 br13 |= COLOR_DEPTH_32;
1624 br00 |= WRITE_ALPHA | WRITE_RGB;
1625 break;
1626 }
1627
1628 START_RING(6);
1629 OUT_RING(br00);
1630 OUT_RING(br13);
1631 OUT_RING(br14);
1632 OUT_RING(br09);
1633 OUT_RING(br16);
1634 OUT_RING(MI_NOOP);
1635 ADVANCE_RING();
1636
1637 #if VERBOSE > 0
1638 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1639 dinfo->ring_tail, dinfo->ring_space);
1640 #endif
1641 }
1642
1643 void
1644 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1645 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1646 {
1647 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1648
1649 #if VERBOSE > 0
1650 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1651 curx, cury, dstx, dsty, w, h, pitch, bpp);
1652 #endif
1653
1654 br00 = XY_SRC_COPY_BLT_CMD;
1655 br09 = dinfo->fb_start;
1656 br11 = (pitch << PITCH_SHIFT);
1657 br12 = dinfo->fb_start;
1658 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1659 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1660 br23 = ((dstx + w) << WIDTH_SHIFT) |
1661 ((dsty + h) << HEIGHT_SHIFT);
1662 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1663
1664 switch (bpp) {
1665 case 8:
1666 br13 |= COLOR_DEPTH_8;
1667 break;
1668 case 16:
1669 br13 |= COLOR_DEPTH_16;
1670 break;
1671 case 32:
1672 br13 |= COLOR_DEPTH_32;
1673 br00 |= WRITE_ALPHA | WRITE_RGB;
1674 break;
1675 }
1676
1677 START_RING(8);
1678 OUT_RING(br00);
1679 OUT_RING(br13);
1680 OUT_RING(br22);
1681 OUT_RING(br23);
1682 OUT_RING(br09);
1683 OUT_RING(br26);
1684 OUT_RING(br11);
1685 OUT_RING(br12);
1686 ADVANCE_RING();
1687 }
1688
1689 int
1690 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1691 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1692 {
1693 int nbytes, ndwords, pad, tmp;
1694 u32 br00, br09, br13, br18, br19, br22, br23;
1695 int dat, ix, iy, iw;
1696 int i, j;
1697
1698 #if VERBOSE > 0
1699 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1700 #endif
1701
1702 /* size in bytes of a padded scanline */
1703 nbytes = ROUND_UP_TO(w, 16) / 8;
1704
1705 /* Total bytes of padded scanline data to write out. */
1706 nbytes = nbytes * h;
1707
1708 /*
1709 * Check if the glyph data exceeds the immediate mode limit.
1710 * It would take a large font (1K pixels) to hit this limit.
1711 */
1712 if (nbytes > MAX_MONO_IMM_SIZE)
1713 return 0;
1714
1715 /* Src data is packaged a dword (32-bit) at a time. */
1716 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1717
1718 /*
1719 * Ring has to be padded to a quad word. But because the command starts
1720 with 7 bytes, pad only if there is an even number of ndwords
1721 */
1722 pad = !(ndwords % 2);
1723
1724 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1725 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1726 br09 = dinfo->fb_start;
1727 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1728 br18 = bg;
1729 br19 = fg;
1730 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1731 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1732
1733 switch (bpp) {
1734 case 8:
1735 br13 |= COLOR_DEPTH_8;
1736 break;
1737 case 16:
1738 br13 |= COLOR_DEPTH_16;
1739 break;
1740 case 32:
1741 br13 |= COLOR_DEPTH_32;
1742 br00 |= WRITE_ALPHA | WRITE_RGB;
1743 break;
1744 }
1745
1746 START_RING(8 + ndwords);
1747 OUT_RING(br00);
1748 OUT_RING(br13);
1749 OUT_RING(br22);
1750 OUT_RING(br23);
1751 OUT_RING(br09);
1752 OUT_RING(br18);
1753 OUT_RING(br19);
1754 ix = iy = 0;
1755 iw = ROUND_UP_TO(w, 8) / 8;
1756 while (ndwords--) {
1757 dat = 0;
1758 for (j = 0; j < 2; ++j) {
1759 for (i = 0; i < 2; ++i) {
1760 if (ix != iw || i == 0)
1761 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1762 }
1763 if (ix == iw && iy != (h-1)) {
1764 ix = 0;
1765 ++iy;
1766 }
1767 }
1768 OUT_RING(dat);
1769 }
1770 if (pad)
1771 OUT_RING(MI_NOOP);
1772 ADVANCE_RING();
1773
1774 return 1;
1775 }
1776
1777 /* HW cursor functions. */
1778 void
1779 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1780 {
1781 u32 tmp;
1782
1783 #if VERBOSE > 0
1784 DBG_MSG("intelfbhw_cursor_init\n");
1785 #endif
1786
1787 if (dinfo->mobile || IS_I9XX(dinfo)) {
1788 if (!dinfo->cursor.physical)
1789 return;
1790 tmp = INREG(CURSOR_A_CONTROL);
1791 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1792 CURSOR_MEM_TYPE_LOCAL |
1793 (1 << CURSOR_PIPE_SELECT_SHIFT));
1794 tmp |= CURSOR_MODE_DISABLE;
1795 OUTREG(CURSOR_A_CONTROL, tmp);
1796 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1797 } else {
1798 tmp = INREG(CURSOR_CONTROL);
1799 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1800 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1801 tmp = CURSOR_FORMAT_3C;
1802 OUTREG(CURSOR_CONTROL, tmp);
1803 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1804 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1805 (64 << CURSOR_SIZE_V_SHIFT);
1806 OUTREG(CURSOR_SIZE, tmp);
1807 }
1808 }
1809
1810 void
1811 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1812 {
1813 u32 tmp;
1814
1815 #if VERBOSE > 0
1816 DBG_MSG("intelfbhw_cursor_hide\n");
1817 #endif
1818
1819 dinfo->cursor_on = 0;
1820 if (dinfo->mobile || IS_I9XX(dinfo)) {
1821 if (!dinfo->cursor.physical)
1822 return;
1823 tmp = INREG(CURSOR_A_CONTROL);
1824 tmp &= ~CURSOR_MODE_MASK;
1825 tmp |= CURSOR_MODE_DISABLE;
1826 OUTREG(CURSOR_A_CONTROL, tmp);
1827 /* Flush changes */
1828 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1829 } else {
1830 tmp = INREG(CURSOR_CONTROL);
1831 tmp &= ~CURSOR_ENABLE;
1832 OUTREG(CURSOR_CONTROL, tmp);
1833 }
1834 }
1835
1836 void
1837 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1838 {
1839 u32 tmp;
1840
1841 #if VERBOSE > 0
1842 DBG_MSG("intelfbhw_cursor_show\n");
1843 #endif
1844
1845 dinfo->cursor_on = 1;
1846
1847 if (dinfo->cursor_blanked)
1848 return;
1849
1850 if (dinfo->mobile || IS_I9XX(dinfo)) {
1851 if (!dinfo->cursor.physical)
1852 return;
1853 tmp = INREG(CURSOR_A_CONTROL);
1854 tmp &= ~CURSOR_MODE_MASK;
1855 tmp |= CURSOR_MODE_64_4C_AX;
1856 OUTREG(CURSOR_A_CONTROL, tmp);
1857 /* Flush changes */
1858 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1859 } else {
1860 tmp = INREG(CURSOR_CONTROL);
1861 tmp |= CURSOR_ENABLE;
1862 OUTREG(CURSOR_CONTROL, tmp);
1863 }
1864 }
1865
1866 void
1867 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1868 {
1869 u32 tmp;
1870
1871 #if VERBOSE > 0
1872 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1873 #endif
1874
1875 /*
1876 * Sets the position. The coordinates are assumed to already
1877 * have any offset adjusted. Assume that the cursor is never
1878 * completely off-screen, and that x, y are always >= 0.
1879 */
1880
1881 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1882 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1883 OUTREG(CURSOR_A_POSITION, tmp);
1884
1885 if (IS_I9XX(dinfo)) {
1886 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1887 }
1888 }
1889
1890 void
1891 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1892 {
1893 #if VERBOSE > 0
1894 DBG_MSG("intelfbhw_cursor_setcolor\n");
1895 #endif
1896
1897 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1898 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1899 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1900 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1901 }
1902
1903 void
1904 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1905 u8 *data)
1906 {
1907 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1908 int i, j, w = width / 8;
1909 int mod = width % 8, t_mask, d_mask;
1910
1911 #if VERBOSE > 0
1912 DBG_MSG("intelfbhw_cursor_load\n");
1913 #endif
1914
1915 if (!dinfo->cursor.virtual)
1916 return;
1917
1918 t_mask = 0xff >> mod;
1919 d_mask = ~(0xff >> mod);
1920 for (i = height; i--; ) {
1921 for (j = 0; j < w; j++) {
1922 writeb(0x00, addr + j);
1923 writeb(*(data++), addr + j+8);
1924 }
1925 if (mod) {
1926 writeb(t_mask, addr + j);
1927 writeb(*(data++) & d_mask, addr + j+8);
1928 }
1929 addr += 16;
1930 }
1931 }
1932
1933 void
1934 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1935 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1936 int i, j;
1937
1938 #if VERBOSE > 0
1939 DBG_MSG("intelfbhw_cursor_reset\n");
1940 #endif
1941
1942 if (!dinfo->cursor.virtual)
1943 return;
1944
1945 for (i = 64; i--; ) {
1946 for (j = 0; j < 8; j++) {
1947 writeb(0xff, addr + j+0);
1948 writeb(0x00, addr + j+8);
1949 }
1950 addr += 16;
1951 }
1952 }
1953
1954 static irqreturn_t
1955 intelfbhw_irq(int irq, void *dev_id, struct pt_regs *fp) {
1956 int handled = 0;
1957 u16 tmp;
1958 struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
1959
1960 spin_lock(&dinfo->int_lock);
1961
1962 tmp = INREG16(IIR);
1963 tmp &= VSYNC_PIPE_A_INTERRUPT;
1964
1965 if (tmp == 0) {
1966 spin_unlock(&dinfo->int_lock);
1967 return IRQ_RETVAL(handled);
1968 }
1969
1970 OUTREG16(IIR, tmp);
1971
1972 if (tmp & VSYNC_PIPE_A_INTERRUPT) {
1973 dinfo->vsync.count++;
1974 if (dinfo->vsync.pan_display) {
1975 dinfo->vsync.pan_display = 0;
1976 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
1977 }
1978 wake_up_interruptible(&dinfo->vsync.wait);
1979 handled = 1;
1980 }
1981
1982 spin_unlock(&dinfo->int_lock);
1983
1984 return IRQ_RETVAL(handled);
1985 }
1986
1987 int
1988 intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
1989
1990 if (!test_and_set_bit(0, &dinfo->irq_flags)) {
1991 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, SA_SHIRQ, "intelfb", dinfo)) {
1992 clear_bit(0, &dinfo->irq_flags);
1993 return -EINVAL;
1994 }
1995
1996 spin_lock_irq(&dinfo->int_lock);
1997 OUTREG16(HWSTAM, 0xfffe);
1998 OUTREG16(IMR, 0x0);
1999 OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
2000 spin_unlock_irq(&dinfo->int_lock);
2001 } else if (reenable) {
2002 u16 ier;
2003
2004 spin_lock_irq(&dinfo->int_lock);
2005 ier = INREG16(IER);
2006 if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
2007 DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
2008 OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
2009 }
2010 spin_unlock_irq(&dinfo->int_lock);
2011 }
2012 return 0;
2013 }
2014
2015 void
2016 intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2017 u16 tmp;
2018
2019 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2020 if (dinfo->vsync.pan_display) {
2021 dinfo->vsync.pan_display = 0;
2022 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2023 }
2024 spin_lock_irq(&dinfo->int_lock);
2025 OUTREG16(HWSTAM, 0xffff);
2026 OUTREG16(IMR, 0xffff);
2027 OUTREG16(IER, 0x0);
2028
2029 tmp = INREG16(IIR);
2030 OUTREG16(IIR, tmp);
2031 spin_unlock_irq(&dinfo->int_lock);
2032
2033 free_irq(dinfo->pdev->irq, dinfo);
2034 }
2035 }
2036
2037 int
2038 intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe) {
2039 struct intelfb_vsync *vsync;
2040 unsigned int count;
2041 int ret;
2042
2043 switch (pipe) {
2044 case 0:
2045 vsync = &dinfo->vsync;
2046 break;
2047 default:
2048 return -ENODEV;
2049 }
2050
2051 ret = intelfbhw_enable_irq(dinfo, 0);
2052 if (ret) {
2053 return ret;
2054 }
2055
2056 count = vsync->count;
2057 ret = wait_event_interruptible_timeout(vsync->wait, count != vsync->count, HZ/10);
2058 if (ret < 0) {
2059 return ret;
2060 }
2061 if (ret == 0) {
2062 intelfbhw_enable_irq(dinfo, 1);
2063 DBG_MSG("wait_for_vsync timed out!\n");
2064 return -ETIMEDOUT;
2065 }
2066
2067 return 0;
2068 }
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