]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/video/intelfb/intelfbhw.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[mirror_ubuntu-artful-kernel.git] / drivers / video / intelfb / intelfbhw.c
1 /*
2 * intelfb
3 *
4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
5 *
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
7 * 2004 Sylvain Meyer
8 *
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
15 *
16 * Author: David Dawes
17 *
18 */
19
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25 #include <linux/string.h>
26 #include <linux/mm.h>
27 #include <linux/tty.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/fb.h>
31 #include <linux/ioport.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/vmalloc.h>
35 #include <linux/pagemap.h>
36
37 #include <asm/io.h>
38
39 #include "intelfb.h"
40 #include "intelfbhw.h"
41
42 struct pll_min_max {
43 int min_m, max_m, min_m1, max_m1;
44 int min_m2, max_m2, min_n, max_n;
45 int min_p, max_p, min_p1, max_p1;
46 int min_vco, max_vco, p_transition_clk, ref_clk;
47 int p_inc_lo, p_inc_hi;
48 };
49
50 #define PLLS_I8xx 0
51 #define PLLS_I9xx 1
52 #define PLLS_MAX 2
53
54 static struct pll_min_max plls[PLLS_MAX] = {
55 { 108, 140, 18, 26,
56 6, 16, 3, 16,
57 4, 128, 0, 31,
58 930000, 1400000, 165000, 48000,
59 4, 2 }, //I8xx
60
61 { 75, 120, 10, 20,
62 5, 9, 4, 7,
63 5, 80, 1, 8,
64 1400000, 2800000, 200000, 96000,
65 10, 5 } //I9xx
66 };
67
68 int
69 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
70 {
71 u32 tmp;
72 if (!pdev || !dinfo)
73 return 1;
74
75 switch (pdev->device) {
76 case PCI_DEVICE_ID_INTEL_830M:
77 dinfo->name = "Intel(R) 830M";
78 dinfo->chipset = INTEL_830M;
79 dinfo->mobile = 1;
80 dinfo->pll_index = PLLS_I8xx;
81 return 0;
82 case PCI_DEVICE_ID_INTEL_845G:
83 dinfo->name = "Intel(R) 845G";
84 dinfo->chipset = INTEL_845G;
85 dinfo->mobile = 0;
86 dinfo->pll_index = PLLS_I8xx;
87 return 0;
88 case PCI_DEVICE_ID_INTEL_85XGM:
89 tmp = 0;
90 dinfo->mobile = 1;
91 dinfo->pll_index = PLLS_I8xx;
92 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
93 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
94 INTEL_85X_VARIANT_MASK) {
95 case INTEL_VAR_855GME:
96 dinfo->name = "Intel(R) 855GME";
97 dinfo->chipset = INTEL_855GME;
98 return 0;
99 case INTEL_VAR_855GM:
100 dinfo->name = "Intel(R) 855GM";
101 dinfo->chipset = INTEL_855GM;
102 return 0;
103 case INTEL_VAR_852GME:
104 dinfo->name = "Intel(R) 852GME";
105 dinfo->chipset = INTEL_852GME;
106 return 0;
107 case INTEL_VAR_852GM:
108 dinfo->name = "Intel(R) 852GM";
109 dinfo->chipset = INTEL_852GM;
110 return 0;
111 default:
112 dinfo->name = "Intel(R) 852GM/855GM";
113 dinfo->chipset = INTEL_85XGM;
114 return 0;
115 }
116 break;
117 case PCI_DEVICE_ID_INTEL_865G:
118 dinfo->name = "Intel(R) 865G";
119 dinfo->chipset = INTEL_865G;
120 dinfo->mobile = 0;
121 dinfo->pll_index = PLLS_I8xx;
122 return 0;
123 case PCI_DEVICE_ID_INTEL_915G:
124 dinfo->name = "Intel(R) 915G";
125 dinfo->chipset = INTEL_915G;
126 dinfo->mobile = 0;
127 dinfo->pll_index = PLLS_I9xx;
128 return 0;
129 case PCI_DEVICE_ID_INTEL_915GM:
130 dinfo->name = "Intel(R) 915GM";
131 dinfo->chipset = INTEL_915GM;
132 dinfo->mobile = 1;
133 dinfo->pll_index = PLLS_I9xx;
134 return 0;
135 case PCI_DEVICE_ID_INTEL_945G:
136 dinfo->name = "Intel(R) 945G";
137 dinfo->chipset = INTEL_945G;
138 dinfo->mobile = 0;
139 dinfo->pll_index = PLLS_I9xx;
140 return 0;
141 case PCI_DEVICE_ID_INTEL_945GM:
142 dinfo->name = "Intel(R) 945GM";
143 dinfo->chipset = INTEL_945GM;
144 dinfo->mobile = 1;
145 dinfo->pll_index = PLLS_I9xx;
146 return 0;
147 default:
148 return 1;
149 }
150 }
151
152 int
153 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
154 int *stolen_size)
155 {
156 struct pci_dev *bridge_dev;
157 u16 tmp;
158 int stolen_overhead;
159
160 if (!pdev || !aperture_size || !stolen_size)
161 return 1;
162
163 /* Find the bridge device. It is always 0:0.0 */
164 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
165 ERR_MSG("cannot find bridge device\n");
166 return 1;
167 }
168
169 /* Get the fb aperture size and "stolen" memory amount. */
170 tmp = 0;
171 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
172 switch (pdev->device) {
173 case PCI_DEVICE_ID_INTEL_915G:
174 case PCI_DEVICE_ID_INTEL_915GM:
175 case PCI_DEVICE_ID_INTEL_945G:
176 case PCI_DEVICE_ID_INTEL_945GM:
177 /* 915 and 945 chipsets support a 256MB aperture.
178 Aperture size is determined by inspected the
179 base address of the aperture. */
180 if (pci_resource_start(pdev, 2) & 0x08000000)
181 *aperture_size = MB(128);
182 else
183 *aperture_size = MB(256);
184 break;
185 default:
186 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
187 *aperture_size = MB(64);
188 else
189 *aperture_size = MB(128);
190 break;
191 }
192
193 /* Stolen memory size is reduced by the GTT and the popup.
194 GTT is 1K per MB of aperture size, and popup is 4K. */
195 stolen_overhead = (*aperture_size / MB(1)) + 4;
196 switch(pdev->device) {
197 case PCI_DEVICE_ID_INTEL_830M:
198 case PCI_DEVICE_ID_INTEL_845G:
199 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
200 case INTEL_830_GMCH_GMS_STOLEN_512:
201 *stolen_size = KB(512) - KB(stolen_overhead);
202 return 0;
203 case INTEL_830_GMCH_GMS_STOLEN_1024:
204 *stolen_size = MB(1) - KB(stolen_overhead);
205 return 0;
206 case INTEL_830_GMCH_GMS_STOLEN_8192:
207 *stolen_size = MB(8) - KB(stolen_overhead);
208 return 0;
209 case INTEL_830_GMCH_GMS_LOCAL:
210 ERR_MSG("only local memory found\n");
211 return 1;
212 case INTEL_830_GMCH_GMS_DISABLED:
213 ERR_MSG("video memory is disabled\n");
214 return 1;
215 default:
216 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
217 tmp & INTEL_830_GMCH_GMS_MASK);
218 return 1;
219 }
220 break;
221 default:
222 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
223 case INTEL_855_GMCH_GMS_STOLEN_1M:
224 *stolen_size = MB(1) - KB(stolen_overhead);
225 return 0;
226 case INTEL_855_GMCH_GMS_STOLEN_4M:
227 *stolen_size = MB(4) - KB(stolen_overhead);
228 return 0;
229 case INTEL_855_GMCH_GMS_STOLEN_8M:
230 *stolen_size = MB(8) - KB(stolen_overhead);
231 return 0;
232 case INTEL_855_GMCH_GMS_STOLEN_16M:
233 *stolen_size = MB(16) - KB(stolen_overhead);
234 return 0;
235 case INTEL_855_GMCH_GMS_STOLEN_32M:
236 *stolen_size = MB(32) - KB(stolen_overhead);
237 return 0;
238 case INTEL_915G_GMCH_GMS_STOLEN_48M:
239 *stolen_size = MB(48) - KB(stolen_overhead);
240 return 0;
241 case INTEL_915G_GMCH_GMS_STOLEN_64M:
242 *stolen_size = MB(64) - KB(stolen_overhead);
243 return 0;
244 case INTEL_855_GMCH_GMS_DISABLED:
245 ERR_MSG("video memory is disabled\n");
246 return 0;
247 default:
248 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
249 tmp & INTEL_855_GMCH_GMS_MASK);
250 return 1;
251 }
252 }
253 }
254
255 int
256 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
257 {
258 int dvo = 0;
259
260 if (INREG(LVDS) & PORT_ENABLE)
261 dvo |= LVDS_PORT;
262 if (INREG(DVOA) & PORT_ENABLE)
263 dvo |= DVOA_PORT;
264 if (INREG(DVOB) & PORT_ENABLE)
265 dvo |= DVOB_PORT;
266 if (INREG(DVOC) & PORT_ENABLE)
267 dvo |= DVOC_PORT;
268
269 return dvo;
270 }
271
272 const char *
273 intelfbhw_dvo_to_string(int dvo)
274 {
275 if (dvo & DVOA_PORT)
276 return "DVO port A";
277 else if (dvo & DVOB_PORT)
278 return "DVO port B";
279 else if (dvo & DVOC_PORT)
280 return "DVO port C";
281 else if (dvo & LVDS_PORT)
282 return "LVDS port";
283 else
284 return NULL;
285 }
286
287
288 int
289 intelfbhw_validate_mode(struct intelfb_info *dinfo,
290 struct fb_var_screeninfo *var)
291 {
292 int bytes_per_pixel;
293 int tmp;
294
295 #if VERBOSE > 0
296 DBG_MSG("intelfbhw_validate_mode\n");
297 #endif
298
299 bytes_per_pixel = var->bits_per_pixel / 8;
300 if (bytes_per_pixel == 3)
301 bytes_per_pixel = 4;
302
303 /* Check if enough video memory. */
304 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
305 if (tmp > dinfo->fb.size) {
306 WRN_MSG("Not enough video ram for mode "
307 "(%d KByte vs %d KByte).\n",
308 BtoKB(tmp), BtoKB(dinfo->fb.size));
309 return 1;
310 }
311
312 /* Check if x/y limits are OK. */
313 if (var->xres - 1 > HACTIVE_MASK) {
314 WRN_MSG("X resolution too large (%d vs %d).\n",
315 var->xres, HACTIVE_MASK + 1);
316 return 1;
317 }
318 if (var->yres - 1 > VACTIVE_MASK) {
319 WRN_MSG("Y resolution too large (%d vs %d).\n",
320 var->yres, VACTIVE_MASK + 1);
321 return 1;
322 }
323
324 /* Check for interlaced/doublescan modes. */
325 if (var->vmode & FB_VMODE_INTERLACED) {
326 WRN_MSG("Mode is interlaced.\n");
327 return 1;
328 }
329 if (var->vmode & FB_VMODE_DOUBLE) {
330 WRN_MSG("Mode is double-scan.\n");
331 return 1;
332 }
333
334 /* Check if clock is OK. */
335 tmp = 1000000000 / var->pixclock;
336 if (tmp < MIN_CLOCK) {
337 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
338 (tmp + 500) / 1000, MIN_CLOCK / 1000);
339 return 1;
340 }
341 if (tmp > MAX_CLOCK) {
342 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
343 (tmp + 500) / 1000, MAX_CLOCK / 1000);
344 return 1;
345 }
346
347 return 0;
348 }
349
350 int
351 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
352 {
353 struct intelfb_info *dinfo = GET_DINFO(info);
354 u32 offset, xoffset, yoffset;
355
356 #if VERBOSE > 0
357 DBG_MSG("intelfbhw_pan_display\n");
358 #endif
359
360 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
361 yoffset = var->yoffset;
362
363 if ((xoffset + var->xres > var->xres_virtual) ||
364 (yoffset + var->yres > var->yres_virtual))
365 return -EINVAL;
366
367 offset = (yoffset * dinfo->pitch) +
368 (xoffset * var->bits_per_pixel) / 8;
369
370 offset += dinfo->fb.offset << 12;
371
372 OUTREG(DSPABASE, offset);
373
374 return 0;
375 }
376
377 /* Blank the screen. */
378 void
379 intelfbhw_do_blank(int blank, struct fb_info *info)
380 {
381 struct intelfb_info *dinfo = GET_DINFO(info);
382 u32 tmp;
383
384 #if VERBOSE > 0
385 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
386 #endif
387
388 /* Turn plane A on or off */
389 tmp = INREG(DSPACNTR);
390 if (blank)
391 tmp &= ~DISPPLANE_PLANE_ENABLE;
392 else
393 tmp |= DISPPLANE_PLANE_ENABLE;
394 OUTREG(DSPACNTR, tmp);
395 /* Flush */
396 tmp = INREG(DSPABASE);
397 OUTREG(DSPABASE, tmp);
398
399 /* Turn off/on the HW cursor */
400 #if VERBOSE > 0
401 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
402 #endif
403 if (dinfo->cursor_on) {
404 if (blank) {
405 intelfbhw_cursor_hide(dinfo);
406 } else {
407 intelfbhw_cursor_show(dinfo);
408 }
409 dinfo->cursor_on = 1;
410 }
411 dinfo->cursor_blanked = blank;
412
413 /* Set DPMS level */
414 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
415 switch (blank) {
416 case FB_BLANK_UNBLANK:
417 case FB_BLANK_NORMAL:
418 tmp |= ADPA_DPMS_D0;
419 break;
420 case FB_BLANK_VSYNC_SUSPEND:
421 tmp |= ADPA_DPMS_D1;
422 break;
423 case FB_BLANK_HSYNC_SUSPEND:
424 tmp |= ADPA_DPMS_D2;
425 break;
426 case FB_BLANK_POWERDOWN:
427 tmp |= ADPA_DPMS_D3;
428 break;
429 }
430 OUTREG(ADPA, tmp);
431
432 return;
433 }
434
435
436 void
437 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
438 unsigned red, unsigned green, unsigned blue,
439 unsigned transp)
440 {
441 #if VERBOSE > 0
442 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
443 regno, red, green, blue);
444 #endif
445
446 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
447 PALETTE_A : PALETTE_B;
448
449 OUTREG(palette_reg + (regno << 2),
450 (red << PALETTE_8_RED_SHIFT) |
451 (green << PALETTE_8_GREEN_SHIFT) |
452 (blue << PALETTE_8_BLUE_SHIFT));
453 }
454
455
456 int
457 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
458 int flag)
459 {
460 int i;
461
462 #if VERBOSE > 0
463 DBG_MSG("intelfbhw_read_hw_state\n");
464 #endif
465
466 if (!hw || !dinfo)
467 return -1;
468
469 /* Read in as much of the HW state as possible. */
470 hw->vga0_divisor = INREG(VGA0_DIVISOR);
471 hw->vga1_divisor = INREG(VGA1_DIVISOR);
472 hw->vga_pd = INREG(VGAPD);
473 hw->dpll_a = INREG(DPLL_A);
474 hw->dpll_b = INREG(DPLL_B);
475 hw->fpa0 = INREG(FPA0);
476 hw->fpa1 = INREG(FPA1);
477 hw->fpb0 = INREG(FPB0);
478 hw->fpb1 = INREG(FPB1);
479
480 if (flag == 1)
481 return flag;
482
483 #if 0
484 /* This seems to be a problem with the 852GM/855GM */
485 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
486 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
487 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
488 }
489 #endif
490
491 if (flag == 2)
492 return flag;
493
494 hw->htotal_a = INREG(HTOTAL_A);
495 hw->hblank_a = INREG(HBLANK_A);
496 hw->hsync_a = INREG(HSYNC_A);
497 hw->vtotal_a = INREG(VTOTAL_A);
498 hw->vblank_a = INREG(VBLANK_A);
499 hw->vsync_a = INREG(VSYNC_A);
500 hw->src_size_a = INREG(SRC_SIZE_A);
501 hw->bclrpat_a = INREG(BCLRPAT_A);
502 hw->htotal_b = INREG(HTOTAL_B);
503 hw->hblank_b = INREG(HBLANK_B);
504 hw->hsync_b = INREG(HSYNC_B);
505 hw->vtotal_b = INREG(VTOTAL_B);
506 hw->vblank_b = INREG(VBLANK_B);
507 hw->vsync_b = INREG(VSYNC_B);
508 hw->src_size_b = INREG(SRC_SIZE_B);
509 hw->bclrpat_b = INREG(BCLRPAT_B);
510
511 if (flag == 3)
512 return flag;
513
514 hw->adpa = INREG(ADPA);
515 hw->dvoa = INREG(DVOA);
516 hw->dvob = INREG(DVOB);
517 hw->dvoc = INREG(DVOC);
518 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
519 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
520 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
521 hw->lvds = INREG(LVDS);
522
523 if (flag == 4)
524 return flag;
525
526 hw->pipe_a_conf = INREG(PIPEACONF);
527 hw->pipe_b_conf = INREG(PIPEBCONF);
528 hw->disp_arb = INREG(DISPARB);
529
530 if (flag == 5)
531 return flag;
532
533 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
534 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
535 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
536 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
537
538 if (flag == 6)
539 return flag;
540
541 for (i = 0; i < 4; i++) {
542 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
543 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
544 }
545
546 if (flag == 7)
547 return flag;
548
549 hw->cursor_size = INREG(CURSOR_SIZE);
550
551 if (flag == 8)
552 return flag;
553
554 hw->disp_a_ctrl = INREG(DSPACNTR);
555 hw->disp_b_ctrl = INREG(DSPBCNTR);
556 hw->disp_a_base = INREG(DSPABASE);
557 hw->disp_b_base = INREG(DSPBBASE);
558 hw->disp_a_stride = INREG(DSPASTRIDE);
559 hw->disp_b_stride = INREG(DSPBSTRIDE);
560
561 if (flag == 9)
562 return flag;
563
564 hw->vgacntrl = INREG(VGACNTRL);
565
566 if (flag == 10)
567 return flag;
568
569 hw->add_id = INREG(ADD_ID);
570
571 if (flag == 11)
572 return flag;
573
574 for (i = 0; i < 7; i++) {
575 hw->swf0x[i] = INREG(SWF00 + (i << 2));
576 hw->swf1x[i] = INREG(SWF10 + (i << 2));
577 if (i < 3)
578 hw->swf3x[i] = INREG(SWF30 + (i << 2));
579 }
580
581 for (i = 0; i < 8; i++)
582 hw->fence[i] = INREG(FENCE + (i << 2));
583
584 hw->instpm = INREG(INSTPM);
585 hw->mem_mode = INREG(MEM_MODE);
586 hw->fw_blc_0 = INREG(FW_BLC_0);
587 hw->fw_blc_1 = INREG(FW_BLC_1);
588
589 return 0;
590 }
591
592
593 static int calc_vclock3(int index, int m, int n, int p)
594 {
595 if (p == 0 || n == 0)
596 return 0;
597 return plls[index].ref_clk * m / n / p;
598 }
599
600 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
601 {
602 struct pll_min_max *pll = &plls[index];
603 u32 m, vco, p;
604
605 m = (5 * (m1 + 2)) + (m2 + 2);
606 n += 2;
607 vco = pll->ref_clk * m / n;
608
609 if (index == PLLS_I8xx) {
610 p = ((p1 + 2) * (1 << (p2 + 1)));
611 } else {
612 p = ((p1) * (p2 ? 5 : 10));
613 }
614 return vco / p;
615 }
616
617 static void
618 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
619 {
620 int p1, p2;
621
622 if (IS_I9XX(dinfo)) {
623 if (dpll & DPLL_P1_FORCE_DIV2)
624 p1 = 1;
625 else
626 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
627
628 p1 = ffs(p1);
629
630 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
631 } else {
632 if (dpll & DPLL_P1_FORCE_DIV2)
633 p1 = 0;
634 else
635 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
636 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
637 }
638
639 *o_p1 = p1;
640 *o_p2 = p2;
641 }
642
643
644 void
645 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
646 {
647 #if REGDUMP
648 int i, m1, m2, n, p1, p2;
649 int index = dinfo->pll_index;
650 DBG_MSG("intelfbhw_print_hw_state\n");
651
652 if (!hw || !dinfo)
653 return;
654 /* Read in as much of the HW state as possible. */
655 printk("hw state dump start\n");
656 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
657 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
658 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
659 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
660 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
661 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
662
663 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
664
665 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
666 m1, m2, n, p1, p2);
667 printk(" VGA0: clock is %d\n",
668 calc_vclock(index, m1, m2, n, p1, p2, 0));
669
670 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
671 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
672 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
673
674 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
675 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
676 m1, m2, n, p1, p2);
677 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
678
679 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
680 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
681 printk(" FPA0: 0x%08x\n", hw->fpa0);
682 printk(" FPA1: 0x%08x\n", hw->fpa1);
683 printk(" FPB0: 0x%08x\n", hw->fpb0);
684 printk(" FPB1: 0x%08x\n", hw->fpb1);
685
686 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
687 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
688 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
689
690 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
691
692 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
693 m1, m2, n, p1, p2);
694 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
695
696 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
697 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
698 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
699
700 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
701
702 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
703 m1, m2, n, p1, p2);
704 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
705
706 #if 0
707 printk(" PALETTE_A:\n");
708 for (i = 0; i < PALETTE_8_ENTRIES)
709 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
710 printk(" PALETTE_B:\n");
711 for (i = 0; i < PALETTE_8_ENTRIES)
712 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
713 #endif
714
715 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
716 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
717 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
718 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
719 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
720 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
721 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
722 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
723 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
724 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
725 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
726 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
727 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
728 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
729 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
730 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
731
732 printk(" ADPA: 0x%08x\n", hw->adpa);
733 printk(" DVOA: 0x%08x\n", hw->dvoa);
734 printk(" DVOB: 0x%08x\n", hw->dvob);
735 printk(" DVOC: 0x%08x\n", hw->dvoc);
736 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
737 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
738 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
739 printk(" LVDS: 0x%08x\n", hw->lvds);
740
741 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
742 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
743 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
744
745 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
746 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
747 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
748 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
749
750 printk(" CURSOR_A_PALETTE: ");
751 for (i = 0; i < 4; i++) {
752 printk("0x%08x", hw->cursor_a_palette[i]);
753 if (i < 3)
754 printk(", ");
755 }
756 printk("\n");
757 printk(" CURSOR_B_PALETTE: ");
758 for (i = 0; i < 4; i++) {
759 printk("0x%08x", hw->cursor_b_palette[i]);
760 if (i < 3)
761 printk(", ");
762 }
763 printk("\n");
764
765 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
766
767 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
768 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
769 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
770 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
771 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
772 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
773
774 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
775 printk(" ADD_ID: 0x%08x\n", hw->add_id);
776
777 for (i = 0; i < 7; i++) {
778 printk(" SWF0%d 0x%08x\n", i,
779 hw->swf0x[i]);
780 }
781 for (i = 0; i < 7; i++) {
782 printk(" SWF1%d 0x%08x\n", i,
783 hw->swf1x[i]);
784 }
785 for (i = 0; i < 3; i++) {
786 printk(" SWF3%d 0x%08x\n", i,
787 hw->swf3x[i]);
788 }
789 for (i = 0; i < 8; i++)
790 printk(" FENCE%d 0x%08x\n", i,
791 hw->fence[i]);
792
793 printk(" INSTPM 0x%08x\n", hw->instpm);
794 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
795 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
796 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
797
798 printk("hw state dump end\n");
799 #endif
800 }
801
802
803
804 /* Split the M parameter into M1 and M2. */
805 static int
806 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
807 {
808 int m1, m2;
809 int testm;
810 struct pll_min_max *pll = &plls[index];
811
812 /* no point optimising too much - brute force m */
813 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
814 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
815 testm = (5 * (m1 + 2)) + (m2 + 2);
816 if (testm == m) {
817 *retm1 = (unsigned int)m1;
818 *retm2 = (unsigned int)m2;
819 return 0;
820 }
821 }
822 }
823 return 1;
824 }
825
826 /* Split the P parameter into P1 and P2. */
827 static int
828 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
829 {
830 int p1, p2;
831 struct pll_min_max *pll = &plls[index];
832
833 if (index == PLLS_I9xx) {
834 p2 = (p % 10) ? 1 : 0;
835
836 p1 = p / (p2 ? 5 : 10);
837
838 *retp1 = (unsigned int)p1;
839 *retp2 = (unsigned int)p2;
840 return 0;
841 }
842
843 if (p % 4 == 0)
844 p2 = 1;
845 else
846 p2 = 0;
847 p1 = (p / (1 << (p2 + 1))) - 2;
848 if (p % 4 == 0 && p1 < pll->min_p1) {
849 p2 = 0;
850 p1 = (p / (1 << (p2 + 1))) - 2;
851 }
852 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
853 (p1 + 2) * (1 << (p2 + 1)) != p) {
854 return 1;
855 } else {
856 *retp1 = (unsigned int)p1;
857 *retp2 = (unsigned int)p2;
858 return 0;
859 }
860 }
861
862 static int
863 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
864 u32 *retp2, u32 *retclock)
865 {
866 u32 m1, m2, n, p1, p2, n1, testm;
867 u32 f_vco, p, p_best = 0, m, f_out = 0;
868 u32 err_max, err_target, err_best = 10000000;
869 u32 n_best = 0, m_best = 0, f_best, f_err;
870 u32 p_min, p_max, p_inc, div_max;
871 struct pll_min_max *pll = &plls[index];
872
873 /* Accept 0.5% difference, but aim for 0.1% */
874 err_max = 5 * clock / 1000;
875 err_target = clock / 1000;
876
877 DBG_MSG("Clock is %d\n", clock);
878
879 div_max = pll->max_vco / clock;
880
881 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
882 p_min = p_inc;
883 p_max = ROUND_DOWN_TO(div_max, p_inc);
884 if (p_min < pll->min_p)
885 p_min = pll->min_p;
886 if (p_max > pll->max_p)
887 p_max = pll->max_p;
888
889 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
890
891 p = p_min;
892 do {
893 if (splitp(index, p, &p1, &p2)) {
894 WRN_MSG("cannot split p = %d\n", p);
895 p += p_inc;
896 continue;
897 }
898 n = pll->min_n;
899 f_vco = clock * p;
900
901 do {
902 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
903 if (m < pll->min_m)
904 m = pll->min_m + 1;
905 if (m > pll->max_m)
906 m = pll->max_m - 1;
907 for (testm = m - 1; testm <= m; testm++) {
908 f_out = calc_vclock3(index, m, n, p);
909 if (splitm(index, testm, &m1, &m2)) {
910 WRN_MSG("cannot split m = %d\n", m);
911 n++;
912 continue;
913 }
914 if (clock > f_out)
915 f_err = clock - f_out;
916 else/* slightly bias the error for bigger clocks */
917 f_err = f_out - clock + 1;
918
919 if (f_err < err_best) {
920 m_best = testm;
921 n_best = n;
922 p_best = p;
923 f_best = f_out;
924 err_best = f_err;
925 }
926 }
927 n++;
928 } while ((n <= pll->max_n) && (f_out >= clock));
929 p += p_inc;
930 } while ((p <= p_max));
931
932 if (!m_best) {
933 WRN_MSG("cannot find parameters for clock %d\n", clock);
934 return 1;
935 }
936 m = m_best;
937 n = n_best;
938 p = p_best;
939 splitm(index, m, &m1, &m2);
940 splitp(index, p, &p1, &p2);
941 n1 = n - 2;
942
943 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
944 "f: %d (%d), VCO: %d\n",
945 m, m1, m2, n, n1, p, p1, p2,
946 calc_vclock3(index, m, n, p),
947 calc_vclock(index, m1, m2, n1, p1, p2, 0),
948 calc_vclock3(index, m, n, p) * p);
949 *retm1 = m1;
950 *retm2 = m2;
951 *retn = n1;
952 *retp1 = p1;
953 *retp2 = p2;
954 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
955
956 return 0;
957 }
958
959 static __inline__ int
960 check_overflow(u32 value, u32 limit, const char *description)
961 {
962 if (value > limit) {
963 WRN_MSG("%s value %d exceeds limit %d\n",
964 description, value, limit);
965 return 1;
966 }
967 return 0;
968 }
969
970 /* It is assumed that hw is filled in with the initial state information. */
971 int
972 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
973 struct fb_var_screeninfo *var)
974 {
975 int pipe = PIPE_A;
976 u32 *dpll, *fp0, *fp1;
977 u32 m1, m2, n, p1, p2, clock_target, clock;
978 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
979 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
980 u32 vsync_pol, hsync_pol;
981 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
982 u32 stride_alignment;
983
984 DBG_MSG("intelfbhw_mode_to_hw\n");
985
986 /* Disable VGA */
987 hw->vgacntrl |= VGA_DISABLE;
988
989 /* Check whether pipe A or pipe B is enabled. */
990 if (hw->pipe_a_conf & PIPECONF_ENABLE)
991 pipe = PIPE_A;
992 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
993 pipe = PIPE_B;
994
995 /* Set which pipe's registers will be set. */
996 if (pipe == PIPE_B) {
997 dpll = &hw->dpll_b;
998 fp0 = &hw->fpb0;
999 fp1 = &hw->fpb1;
1000 hs = &hw->hsync_b;
1001 hb = &hw->hblank_b;
1002 ht = &hw->htotal_b;
1003 vs = &hw->vsync_b;
1004 vb = &hw->vblank_b;
1005 vt = &hw->vtotal_b;
1006 ss = &hw->src_size_b;
1007 pipe_conf = &hw->pipe_b_conf;
1008 } else {
1009 dpll = &hw->dpll_a;
1010 fp0 = &hw->fpa0;
1011 fp1 = &hw->fpa1;
1012 hs = &hw->hsync_a;
1013 hb = &hw->hblank_a;
1014 ht = &hw->htotal_a;
1015 vs = &hw->vsync_a;
1016 vb = &hw->vblank_a;
1017 vt = &hw->vtotal_a;
1018 ss = &hw->src_size_a;
1019 pipe_conf = &hw->pipe_a_conf;
1020 }
1021
1022 /* Use ADPA register for sync control. */
1023 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1024
1025 /* sync polarity */
1026 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1027 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1028 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1029 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1030 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1031 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1032 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1033 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1034
1035 /* Connect correct pipe to the analog port DAC */
1036 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1037 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1038
1039 /* Set DPMS state to D0 (on) */
1040 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1041 hw->adpa |= ADPA_DPMS_D0;
1042
1043 hw->adpa |= ADPA_DAC_ENABLE;
1044
1045 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1046 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1047 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1048
1049 /* Desired clock in kHz */
1050 clock_target = 1000000000 / var->pixclock;
1051
1052 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1053 &n, &p1, &p2, &clock)) {
1054 WRN_MSG("calc_pll_params failed\n");
1055 return 1;
1056 }
1057
1058 /* Check for overflow. */
1059 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1060 return 1;
1061 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1062 return 1;
1063 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1064 return 1;
1065 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1066 return 1;
1067 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1068 return 1;
1069
1070 *dpll &= ~DPLL_P1_FORCE_DIV2;
1071 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1072 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1073
1074 if (IS_I9XX(dinfo)) {
1075 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1076 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1077 } else {
1078 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1079 }
1080
1081 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1082 (m1 << FP_M1_DIVISOR_SHIFT) |
1083 (m2 << FP_M2_DIVISOR_SHIFT);
1084 *fp1 = *fp0;
1085
1086 hw->dvob &= ~PORT_ENABLE;
1087 hw->dvoc &= ~PORT_ENABLE;
1088
1089 /* Use display plane A. */
1090 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1091 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1092 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1093 switch (intelfb_var_to_depth(var)) {
1094 case 8:
1095 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1096 break;
1097 case 15:
1098 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1099 break;
1100 case 16:
1101 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1102 break;
1103 case 24:
1104 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1105 break;
1106 }
1107 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1108 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1109
1110 /* Set CRTC registers. */
1111 hactive = var->xres;
1112 hsync_start = hactive + var->right_margin;
1113 hsync_end = hsync_start + var->hsync_len;
1114 htotal = hsync_end + var->left_margin;
1115 hblank_start = hactive;
1116 hblank_end = htotal;
1117
1118 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1119 hactive, hsync_start, hsync_end, htotal, hblank_start,
1120 hblank_end);
1121
1122 vactive = var->yres;
1123 vsync_start = vactive + var->lower_margin;
1124 vsync_end = vsync_start + var->vsync_len;
1125 vtotal = vsync_end + var->upper_margin;
1126 vblank_start = vactive;
1127 vblank_end = vtotal;
1128 vblank_end = vsync_end + 1;
1129
1130 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1131 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1132 vblank_end);
1133
1134 /* Adjust for register values, and check for overflow. */
1135 hactive--;
1136 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1137 return 1;
1138 hsync_start--;
1139 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1140 return 1;
1141 hsync_end--;
1142 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1143 return 1;
1144 htotal--;
1145 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1146 return 1;
1147 hblank_start--;
1148 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1149 return 1;
1150 hblank_end--;
1151 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1152 return 1;
1153
1154 vactive--;
1155 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1156 return 1;
1157 vsync_start--;
1158 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1159 return 1;
1160 vsync_end--;
1161 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1162 return 1;
1163 vtotal--;
1164 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1165 return 1;
1166 vblank_start--;
1167 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1168 return 1;
1169 vblank_end--;
1170 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1171 return 1;
1172
1173 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1174 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1175 (hblank_end << HSYNCEND_SHIFT);
1176 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1177
1178 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1179 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1180 (vblank_end << VSYNCEND_SHIFT);
1181 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1182 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1183 (vactive << SRC_SIZE_VERT_SHIFT);
1184
1185 hw->disp_a_stride = dinfo->pitch;
1186 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1187
1188 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1189 var->xoffset * var->bits_per_pixel / 8;
1190
1191 hw->disp_a_base += dinfo->fb.offset << 12;
1192
1193 /* Check stride alignment. */
1194 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1195 STRIDE_ALIGNMENT;
1196 if (hw->disp_a_stride % stride_alignment != 0) {
1197 WRN_MSG("display stride %d has bad alignment %d\n",
1198 hw->disp_a_stride, stride_alignment);
1199 return 1;
1200 }
1201
1202 /* Set the palette to 8-bit mode. */
1203 *pipe_conf &= ~PIPECONF_GAMMA;
1204 return 0;
1205 }
1206
1207 /* Program a (non-VGA) video mode. */
1208 int
1209 intelfbhw_program_mode(struct intelfb_info *dinfo,
1210 const struct intelfb_hwstate *hw, int blank)
1211 {
1212 int pipe = PIPE_A;
1213 u32 tmp;
1214 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1215 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1216 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1217 u32 hsync_reg, htotal_reg, hblank_reg;
1218 u32 vsync_reg, vtotal_reg, vblank_reg;
1219 u32 src_size_reg;
1220 u32 count, tmp_val[3];
1221
1222 /* Assume single pipe, display plane A, analog CRT. */
1223
1224 #if VERBOSE > 0
1225 DBG_MSG("intelfbhw_program_mode\n");
1226 #endif
1227
1228 /* Disable VGA */
1229 tmp = INREG(VGACNTRL);
1230 tmp |= VGA_DISABLE;
1231 OUTREG(VGACNTRL, tmp);
1232
1233 /* Check whether pipe A or pipe B is enabled. */
1234 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1235 pipe = PIPE_A;
1236 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1237 pipe = PIPE_B;
1238
1239 dinfo->pipe = pipe;
1240
1241 if (pipe == PIPE_B) {
1242 dpll = &hw->dpll_b;
1243 fp0 = &hw->fpb0;
1244 fp1 = &hw->fpb1;
1245 pipe_conf = &hw->pipe_b_conf;
1246 hs = &hw->hsync_b;
1247 hb = &hw->hblank_b;
1248 ht = &hw->htotal_b;
1249 vs = &hw->vsync_b;
1250 vb = &hw->vblank_b;
1251 vt = &hw->vtotal_b;
1252 ss = &hw->src_size_b;
1253 dpll_reg = DPLL_B;
1254 fp0_reg = FPB0;
1255 fp1_reg = FPB1;
1256 pipe_conf_reg = PIPEBCONF;
1257 hsync_reg = HSYNC_B;
1258 htotal_reg = HTOTAL_B;
1259 hblank_reg = HBLANK_B;
1260 vsync_reg = VSYNC_B;
1261 vtotal_reg = VTOTAL_B;
1262 vblank_reg = VBLANK_B;
1263 src_size_reg = SRC_SIZE_B;
1264 } else {
1265 dpll = &hw->dpll_a;
1266 fp0 = &hw->fpa0;
1267 fp1 = &hw->fpa1;
1268 pipe_conf = &hw->pipe_a_conf;
1269 hs = &hw->hsync_a;
1270 hb = &hw->hblank_a;
1271 ht = &hw->htotal_a;
1272 vs = &hw->vsync_a;
1273 vb = &hw->vblank_a;
1274 vt = &hw->vtotal_a;
1275 ss = &hw->src_size_a;
1276 dpll_reg = DPLL_A;
1277 fp0_reg = FPA0;
1278 fp1_reg = FPA1;
1279 pipe_conf_reg = PIPEACONF;
1280 hsync_reg = HSYNC_A;
1281 htotal_reg = HTOTAL_A;
1282 hblank_reg = HBLANK_A;
1283 vsync_reg = VSYNC_A;
1284 vtotal_reg = VTOTAL_A;
1285 vblank_reg = VBLANK_A;
1286 src_size_reg = SRC_SIZE_A;
1287 }
1288
1289 /* turn off pipe */
1290 tmp = INREG(pipe_conf_reg);
1291 tmp &= ~PIPECONF_ENABLE;
1292 OUTREG(pipe_conf_reg, tmp);
1293
1294 count = 0;
1295 do {
1296 tmp_val[count%3] = INREG(0x70000);
1297 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1298 break;
1299 count++;
1300 udelay(1);
1301 if (count % 200 == 0) {
1302 tmp = INREG(pipe_conf_reg);
1303 tmp &= ~PIPECONF_ENABLE;
1304 OUTREG(pipe_conf_reg, tmp);
1305 }
1306 } while(count < 2000);
1307
1308 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1309
1310 /* Disable planes A and B. */
1311 tmp = INREG(DSPACNTR);
1312 tmp &= ~DISPPLANE_PLANE_ENABLE;
1313 OUTREG(DSPACNTR, tmp);
1314 tmp = INREG(DSPBCNTR);
1315 tmp &= ~DISPPLANE_PLANE_ENABLE;
1316 OUTREG(DSPBCNTR, tmp);
1317
1318 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1319 mdelay(20);
1320
1321 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1322 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1323 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1324
1325 /* Disable Sync */
1326 tmp = INREG(ADPA);
1327 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1328 tmp |= ADPA_DPMS_D3;
1329 OUTREG(ADPA, tmp);
1330
1331 /* do some funky magic - xyzzy */
1332 OUTREG(0x61204, 0xabcd0000);
1333
1334 /* turn off PLL */
1335 tmp = INREG(dpll_reg);
1336 dpll_reg &= ~DPLL_VCO_ENABLE;
1337 OUTREG(dpll_reg, tmp);
1338
1339 /* Set PLL parameters */
1340 OUTREG(fp0_reg, *fp0);
1341 OUTREG(fp1_reg, *fp1);
1342
1343 /* Enable PLL */
1344 OUTREG(dpll_reg, *dpll);
1345
1346 /* Set DVOs B/C */
1347 OUTREG(DVOB, hw->dvob);
1348 OUTREG(DVOC, hw->dvoc);
1349
1350 /* undo funky magic */
1351 OUTREG(0x61204, 0x00000000);
1352
1353 /* Set ADPA */
1354 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1355 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1356
1357 /* Set pipe parameters */
1358 OUTREG(hsync_reg, *hs);
1359 OUTREG(hblank_reg, *hb);
1360 OUTREG(htotal_reg, *ht);
1361 OUTREG(vsync_reg, *vs);
1362 OUTREG(vblank_reg, *vb);
1363 OUTREG(vtotal_reg, *vt);
1364 OUTREG(src_size_reg, *ss);
1365
1366 /* Enable pipe */
1367 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1368
1369 /* Enable sync */
1370 tmp = INREG(ADPA);
1371 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1372 tmp |= ADPA_DPMS_D0;
1373 OUTREG(ADPA, tmp);
1374
1375 /* setup display plane */
1376 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1377 /*
1378 * i830M errata: the display plane must be enabled
1379 * to allow writes to the other bits in the plane
1380 * control register.
1381 */
1382 tmp = INREG(DSPACNTR);
1383 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1384 tmp |= DISPPLANE_PLANE_ENABLE;
1385 OUTREG(DSPACNTR, tmp);
1386 OUTREG(DSPACNTR,
1387 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1388 mdelay(1);
1389 }
1390 }
1391
1392 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1393 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1394 OUTREG(DSPABASE, hw->disp_a_base);
1395
1396 /* Enable plane */
1397 if (!blank) {
1398 tmp = INREG(DSPACNTR);
1399 tmp |= DISPPLANE_PLANE_ENABLE;
1400 OUTREG(DSPACNTR, tmp);
1401 OUTREG(DSPABASE, hw->disp_a_base);
1402 }
1403
1404 return 0;
1405 }
1406
1407 /* forward declarations */
1408 static void refresh_ring(struct intelfb_info *dinfo);
1409 static void reset_state(struct intelfb_info *dinfo);
1410 static void do_flush(struct intelfb_info *dinfo);
1411
1412 static int
1413 wait_ring(struct intelfb_info *dinfo, int n)
1414 {
1415 int i = 0;
1416 unsigned long end;
1417 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1418
1419 #if VERBOSE > 0
1420 DBG_MSG("wait_ring: %d\n", n);
1421 #endif
1422
1423 end = jiffies + (HZ * 3);
1424 while (dinfo->ring_space < n) {
1425 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1426 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1427 dinfo->ring_space = dinfo->ring_head
1428 - (dinfo->ring_tail + RING_MIN_FREE);
1429 else
1430 dinfo->ring_space = (dinfo->ring.size +
1431 dinfo->ring_head)
1432 - (dinfo->ring_tail + RING_MIN_FREE);
1433 if (dinfo->ring_head != last_head) {
1434 end = jiffies + (HZ * 3);
1435 last_head = dinfo->ring_head;
1436 }
1437 i++;
1438 if (time_before(end, jiffies)) {
1439 if (!i) {
1440 /* Try again */
1441 reset_state(dinfo);
1442 refresh_ring(dinfo);
1443 do_flush(dinfo);
1444 end = jiffies + (HZ * 3);
1445 i = 1;
1446 } else {
1447 WRN_MSG("ring buffer : space: %d wanted %d\n",
1448 dinfo->ring_space, n);
1449 WRN_MSG("lockup - turning off hardware "
1450 "acceleration\n");
1451 dinfo->ring_lockup = 1;
1452 break;
1453 }
1454 }
1455 udelay(1);
1456 }
1457 return i;
1458 }
1459
1460 static void
1461 do_flush(struct intelfb_info *dinfo) {
1462 START_RING(2);
1463 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1464 OUT_RING(MI_NOOP);
1465 ADVANCE_RING();
1466 }
1467
1468 void
1469 intelfbhw_do_sync(struct intelfb_info *dinfo)
1470 {
1471 #if VERBOSE > 0
1472 DBG_MSG("intelfbhw_do_sync\n");
1473 #endif
1474
1475 if (!dinfo->accel)
1476 return;
1477
1478 /*
1479 * Send a flush, then wait until the ring is empty. This is what
1480 * the XFree86 driver does, and actually it doesn't seem a lot worse
1481 * than the recommended method (both have problems).
1482 */
1483 do_flush(dinfo);
1484 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1485 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1486 }
1487
1488 static void
1489 refresh_ring(struct intelfb_info *dinfo)
1490 {
1491 #if VERBOSE > 0
1492 DBG_MSG("refresh_ring\n");
1493 #endif
1494
1495 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1496 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1497 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1498 dinfo->ring_space = dinfo->ring_head
1499 - (dinfo->ring_tail + RING_MIN_FREE);
1500 else
1501 dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
1502 - (dinfo->ring_tail + RING_MIN_FREE);
1503 }
1504
1505 static void
1506 reset_state(struct intelfb_info *dinfo)
1507 {
1508 int i;
1509 u32 tmp;
1510
1511 #if VERBOSE > 0
1512 DBG_MSG("reset_state\n");
1513 #endif
1514
1515 for (i = 0; i < FENCE_NUM; i++)
1516 OUTREG(FENCE + (i << 2), 0);
1517
1518 /* Flush the ring buffer if it's enabled. */
1519 tmp = INREG(PRI_RING_LENGTH);
1520 if (tmp & RING_ENABLE) {
1521 #if VERBOSE > 0
1522 DBG_MSG("reset_state: ring was enabled\n");
1523 #endif
1524 refresh_ring(dinfo);
1525 intelfbhw_do_sync(dinfo);
1526 DO_RING_IDLE();
1527 }
1528
1529 OUTREG(PRI_RING_LENGTH, 0);
1530 OUTREG(PRI_RING_HEAD, 0);
1531 OUTREG(PRI_RING_TAIL, 0);
1532 OUTREG(PRI_RING_START, 0);
1533 }
1534
1535 /* Stop the 2D engine, and turn off the ring buffer. */
1536 void
1537 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1538 {
1539 #if VERBOSE > 0
1540 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1541 dinfo->ring_active);
1542 #endif
1543
1544 if (!dinfo->accel)
1545 return;
1546
1547 dinfo->ring_active = 0;
1548 reset_state(dinfo);
1549 }
1550
1551 /*
1552 * Enable the ring buffer, and initialise the 2D engine.
1553 * It is assumed that the graphics engine has been stopped by previously
1554 * calling intelfb_2d_stop().
1555 */
1556 void
1557 intelfbhw_2d_start(struct intelfb_info *dinfo)
1558 {
1559 #if VERBOSE > 0
1560 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1561 dinfo->accel, dinfo->ring_active);
1562 #endif
1563
1564 if (!dinfo->accel)
1565 return;
1566
1567 /* Initialise the primary ring buffer. */
1568 OUTREG(PRI_RING_LENGTH, 0);
1569 OUTREG(PRI_RING_TAIL, 0);
1570 OUTREG(PRI_RING_HEAD, 0);
1571
1572 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1573 OUTREG(PRI_RING_LENGTH,
1574 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1575 RING_NO_REPORT | RING_ENABLE);
1576 refresh_ring(dinfo);
1577 dinfo->ring_active = 1;
1578 }
1579
1580 /* 2D fillrect (solid fill or invert) */
1581 void
1582 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1583 u32 color, u32 pitch, u32 bpp, u32 rop)
1584 {
1585 u32 br00, br09, br13, br14, br16;
1586
1587 #if VERBOSE > 0
1588 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1589 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1590 #endif
1591
1592 br00 = COLOR_BLT_CMD;
1593 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1594 br13 = (rop << ROP_SHIFT) | pitch;
1595 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1596 br16 = color;
1597
1598 switch (bpp) {
1599 case 8:
1600 br13 |= COLOR_DEPTH_8;
1601 break;
1602 case 16:
1603 br13 |= COLOR_DEPTH_16;
1604 break;
1605 case 32:
1606 br13 |= COLOR_DEPTH_32;
1607 br00 |= WRITE_ALPHA | WRITE_RGB;
1608 break;
1609 }
1610
1611 START_RING(6);
1612 OUT_RING(br00);
1613 OUT_RING(br13);
1614 OUT_RING(br14);
1615 OUT_RING(br09);
1616 OUT_RING(br16);
1617 OUT_RING(MI_NOOP);
1618 ADVANCE_RING();
1619
1620 #if VERBOSE > 0
1621 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1622 dinfo->ring_tail, dinfo->ring_space);
1623 #endif
1624 }
1625
1626 void
1627 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1628 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1629 {
1630 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1631
1632 #if VERBOSE > 0
1633 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1634 curx, cury, dstx, dsty, w, h, pitch, bpp);
1635 #endif
1636
1637 br00 = XY_SRC_COPY_BLT_CMD;
1638 br09 = dinfo->fb_start;
1639 br11 = (pitch << PITCH_SHIFT);
1640 br12 = dinfo->fb_start;
1641 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1642 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1643 br23 = ((dstx + w) << WIDTH_SHIFT) |
1644 ((dsty + h) << HEIGHT_SHIFT);
1645 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1646
1647 switch (bpp) {
1648 case 8:
1649 br13 |= COLOR_DEPTH_8;
1650 break;
1651 case 16:
1652 br13 |= COLOR_DEPTH_16;
1653 break;
1654 case 32:
1655 br13 |= COLOR_DEPTH_32;
1656 br00 |= WRITE_ALPHA | WRITE_RGB;
1657 break;
1658 }
1659
1660 START_RING(8);
1661 OUT_RING(br00);
1662 OUT_RING(br13);
1663 OUT_RING(br22);
1664 OUT_RING(br23);
1665 OUT_RING(br09);
1666 OUT_RING(br26);
1667 OUT_RING(br11);
1668 OUT_RING(br12);
1669 ADVANCE_RING();
1670 }
1671
1672 int
1673 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1674 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1675 {
1676 int nbytes, ndwords, pad, tmp;
1677 u32 br00, br09, br13, br18, br19, br22, br23;
1678 int dat, ix, iy, iw;
1679 int i, j;
1680
1681 #if VERBOSE > 0
1682 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1683 #endif
1684
1685 /* size in bytes of a padded scanline */
1686 nbytes = ROUND_UP_TO(w, 16) / 8;
1687
1688 /* Total bytes of padded scanline data to write out. */
1689 nbytes = nbytes * h;
1690
1691 /*
1692 * Check if the glyph data exceeds the immediate mode limit.
1693 * It would take a large font (1K pixels) to hit this limit.
1694 */
1695 if (nbytes > MAX_MONO_IMM_SIZE)
1696 return 0;
1697
1698 /* Src data is packaged a dword (32-bit) at a time. */
1699 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1700
1701 /*
1702 * Ring has to be padded to a quad word. But because the command starts
1703 with 7 bytes, pad only if there is an even number of ndwords
1704 */
1705 pad = !(ndwords % 2);
1706
1707 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1708 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1709 br09 = dinfo->fb_start;
1710 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1711 br18 = bg;
1712 br19 = fg;
1713 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1714 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1715
1716 switch (bpp) {
1717 case 8:
1718 br13 |= COLOR_DEPTH_8;
1719 break;
1720 case 16:
1721 br13 |= COLOR_DEPTH_16;
1722 break;
1723 case 32:
1724 br13 |= COLOR_DEPTH_32;
1725 br00 |= WRITE_ALPHA | WRITE_RGB;
1726 break;
1727 }
1728
1729 START_RING(8 + ndwords);
1730 OUT_RING(br00);
1731 OUT_RING(br13);
1732 OUT_RING(br22);
1733 OUT_RING(br23);
1734 OUT_RING(br09);
1735 OUT_RING(br18);
1736 OUT_RING(br19);
1737 ix = iy = 0;
1738 iw = ROUND_UP_TO(w, 8) / 8;
1739 while (ndwords--) {
1740 dat = 0;
1741 for (j = 0; j < 2; ++j) {
1742 for (i = 0; i < 2; ++i) {
1743 if (ix != iw || i == 0)
1744 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1745 }
1746 if (ix == iw && iy != (h-1)) {
1747 ix = 0;
1748 ++iy;
1749 }
1750 }
1751 OUT_RING(dat);
1752 }
1753 if (pad)
1754 OUT_RING(MI_NOOP);
1755 ADVANCE_RING();
1756
1757 return 1;
1758 }
1759
1760 /* HW cursor functions. */
1761 void
1762 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1763 {
1764 u32 tmp;
1765
1766 #if VERBOSE > 0
1767 DBG_MSG("intelfbhw_cursor_init\n");
1768 #endif
1769
1770 if (dinfo->mobile || IS_I9XX(dinfo)) {
1771 if (!dinfo->cursor.physical)
1772 return;
1773 tmp = INREG(CURSOR_A_CONTROL);
1774 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1775 CURSOR_MEM_TYPE_LOCAL |
1776 (1 << CURSOR_PIPE_SELECT_SHIFT));
1777 tmp |= CURSOR_MODE_DISABLE;
1778 OUTREG(CURSOR_A_CONTROL, tmp);
1779 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1780 } else {
1781 tmp = INREG(CURSOR_CONTROL);
1782 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1783 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1784 tmp = CURSOR_FORMAT_3C;
1785 OUTREG(CURSOR_CONTROL, tmp);
1786 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1787 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1788 (64 << CURSOR_SIZE_V_SHIFT);
1789 OUTREG(CURSOR_SIZE, tmp);
1790 }
1791 }
1792
1793 void
1794 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1795 {
1796 u32 tmp;
1797
1798 #if VERBOSE > 0
1799 DBG_MSG("intelfbhw_cursor_hide\n");
1800 #endif
1801
1802 dinfo->cursor_on = 0;
1803 if (dinfo->mobile || IS_I9XX(dinfo)) {
1804 if (!dinfo->cursor.physical)
1805 return;
1806 tmp = INREG(CURSOR_A_CONTROL);
1807 tmp &= ~CURSOR_MODE_MASK;
1808 tmp |= CURSOR_MODE_DISABLE;
1809 OUTREG(CURSOR_A_CONTROL, tmp);
1810 /* Flush changes */
1811 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1812 } else {
1813 tmp = INREG(CURSOR_CONTROL);
1814 tmp &= ~CURSOR_ENABLE;
1815 OUTREG(CURSOR_CONTROL, tmp);
1816 }
1817 }
1818
1819 void
1820 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1821 {
1822 u32 tmp;
1823
1824 #if VERBOSE > 0
1825 DBG_MSG("intelfbhw_cursor_show\n");
1826 #endif
1827
1828 dinfo->cursor_on = 1;
1829
1830 if (dinfo->cursor_blanked)
1831 return;
1832
1833 if (dinfo->mobile || IS_I9XX(dinfo)) {
1834 if (!dinfo->cursor.physical)
1835 return;
1836 tmp = INREG(CURSOR_A_CONTROL);
1837 tmp &= ~CURSOR_MODE_MASK;
1838 tmp |= CURSOR_MODE_64_4C_AX;
1839 OUTREG(CURSOR_A_CONTROL, tmp);
1840 /* Flush changes */
1841 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1842 } else {
1843 tmp = INREG(CURSOR_CONTROL);
1844 tmp |= CURSOR_ENABLE;
1845 OUTREG(CURSOR_CONTROL, tmp);
1846 }
1847 }
1848
1849 void
1850 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1851 {
1852 u32 tmp;
1853
1854 #if VERBOSE > 0
1855 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1856 #endif
1857
1858 /*
1859 * Sets the position. The coordinates are assumed to already
1860 * have any offset adjusted. Assume that the cursor is never
1861 * completely off-screen, and that x, y are always >= 0.
1862 */
1863
1864 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1865 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1866 OUTREG(CURSOR_A_POSITION, tmp);
1867
1868 if (IS_I9XX(dinfo)) {
1869 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1870 }
1871 }
1872
1873 void
1874 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1875 {
1876 #if VERBOSE > 0
1877 DBG_MSG("intelfbhw_cursor_setcolor\n");
1878 #endif
1879
1880 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1881 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1882 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1883 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1884 }
1885
1886 void
1887 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1888 u8 *data)
1889 {
1890 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1891 int i, j, w = width / 8;
1892 int mod = width % 8, t_mask, d_mask;
1893
1894 #if VERBOSE > 0
1895 DBG_MSG("intelfbhw_cursor_load\n");
1896 #endif
1897
1898 if (!dinfo->cursor.virtual)
1899 return;
1900
1901 t_mask = 0xff >> mod;
1902 d_mask = ~(0xff >> mod);
1903 for (i = height; i--; ) {
1904 for (j = 0; j < w; j++) {
1905 writeb(0x00, addr + j);
1906 writeb(*(data++), addr + j+8);
1907 }
1908 if (mod) {
1909 writeb(t_mask, addr + j);
1910 writeb(*(data++) & d_mask, addr + j+8);
1911 }
1912 addr += 16;
1913 }
1914 }
1915
1916 void
1917 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1918 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1919 int i, j;
1920
1921 #if VERBOSE > 0
1922 DBG_MSG("intelfbhw_cursor_reset\n");
1923 #endif
1924
1925 if (!dinfo->cursor.virtual)
1926 return;
1927
1928 for (i = 64; i--; ) {
1929 for (j = 0; j < 8; j++) {
1930 writeb(0xff, addr + j+0);
1931 writeb(0x00, addr + j+8);
1932 }
1933 addr += 16;
1934 }
1935 }
Ubuntu Artful kernel mirror