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[mirror_ubuntu-bionic-kernel.git] / drivers / video / matrox / matroxfb_Ti3026.c
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.65 2002/08/14
10 *
11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12 *
13 * Contributors: "menion?" <menion@mindless.com>
14 * Betatesting, fixes, ideas
15 *
16 * "Kurt Garloff" <garloff@suse.de>
17 * Betatesting, fixes, ideas, videomodes, videomodes timmings
18 *
19 * "Tom Rini" <trini@kernel.crashing.org>
20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21 *
22 * "Bibek Sahu" <scorpio@dodds.net>
23 * Access device through readb|w|l and write b|w|l
24 * Extensive debugging stuff
25 *
26 * "Daniel Haun" <haund@usa.net>
27 * Testing, hardware cursor fixes
28 *
29 * "Scott Wood" <sawst46+@pitt.edu>
30 * Fixes
31 *
32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33 * Betatesting
34 *
35 * "Kelly French" <targon@hazmat.com>
36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37 * Betatesting, bug reporting
38 *
39 * "Pablo Bianucci" <pbian@pccp.com.ar>
40 * Fixes, ideas, betatesting
41 *
42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43 * Fixes, enhandcements, ideas, betatesting
44 *
45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46 * PPC betatesting, PPC support, backward compatibility
47 *
48 * "Paul Womar" <Paul@pwomar.demon.co.uk>
49 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
50 * PPC betatesting
51 *
52 * "Thomas Pornin" <pornin@bolet.ens.fr>
53 * Alpha betatesting
54 *
55 * "Pieter van Leuven" <pvl@iae.nl>
56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57 * G100 testing
58 *
59 * "H. Peter Arvin" <hpa@transmeta.com>
60 * Ideas
61 *
62 * "Cort Dougan" <cort@cs.nmt.edu>
63 * CHRP fixes and PReP cleanup
64 *
65 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
66 * G400 support
67 *
68 * (following author is not in any relation with this code, but his code
69 * is included in this driver)
70 *
71 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
72 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
73 *
74 * (following author is not in any relation with this code, but his ideas
75 * were used when writting this driver)
76 *
77 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
78 *
79 */
80
81 #include <linux/config.h>
82
83 #include "matroxfb_Ti3026.h"
84 #include "matroxfb_misc.h"
85 #include "matroxfb_accel.h"
86 #include <linux/matroxfb.h>
87
88 #ifdef CONFIG_FB_MATROX_MILLENIUM
89 #define outTi3026 matroxfb_DAC_out
90 #define inTi3026 matroxfb_DAC_in
91
92 #define TVP3026_INDEX 0x00
93 #define TVP3026_PALWRADD 0x00
94 #define TVP3026_PALDATA 0x01
95 #define TVP3026_PIXRDMSK 0x02
96 #define TVP3026_PALRDADD 0x03
97 #define TVP3026_CURCOLWRADD 0x04
98 #define TVP3026_CLOVERSCAN 0x00
99 #define TVP3026_CLCOLOR0 0x01
100 #define TVP3026_CLCOLOR1 0x02
101 #define TVP3026_CLCOLOR2 0x03
102 #define TVP3026_CURCOLDATA 0x05
103 #define TVP3026_CURCOLRDADD 0x07
104 #define TVP3026_CURCTRL 0x09
105 #define TVP3026_X_DATAREG 0x0A
106 #define TVP3026_CURRAMDATA 0x0B
107 #define TVP3026_CURPOSXL 0x0C
108 #define TVP3026_CURPOSXH 0x0D
109 #define TVP3026_CURPOSYL 0x0E
110 #define TVP3026_CURPOSYH 0x0F
111
112 #define TVP3026_XSILICONREV 0x01
113 #define TVP3026_XCURCTRL 0x06
114 #define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
115 #define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
116 #define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
117 #define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
118 #define TVP3026_XCURCTRL_BLANK2048 0x00
119 #define TVP3026_XCURCTRL_BLANK4096 0x10
120 #define TVP3026_XCURCTRL_INTERLACED 0x20
121 #define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
122 #define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
123 #define TVP3026_XCURCTRL_INDIRECT 0x00
124 #define TVP3026_XCURCTRL_DIRECT 0x80
125 #define TVP3026_XLATCHCTRL 0x0F
126 #define TVP3026_XLATCHCTRL_1_1 0x06
127 #define TVP3026_XLATCHCTRL_2_1 0x07
128 #define TVP3026_XLATCHCTRL_4_1 0x06
129 #define TVP3026_XLATCHCTRL_8_1 0x06
130 #define TVP3026_XLATCHCTRL_16_1 0x06
131 #define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
132 #define TVP3026A_XLATCHCTRL_8_3 0x07
133 #define TVP3026B_XLATCHCTRL_4_3 0x08
134 #define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
135 #define TVP3026_XTRUECOLORCTRL 0x18
136 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
137 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
138 #define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
139 #define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
140 #define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
141 #define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
142 #define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
143 #define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
144 #define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
145 #define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
146 #define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
147 #define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
148 #define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
149 #define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
150 #define TVP3026_XMUXCTRL 0x19
151 #define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
152 #define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
153 #define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
154 #define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
155 #define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
156 #define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
157 #define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
158 #define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
159 #define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
160 #define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
161 #define TVP3026_XCLKCTRL 0x1A
162 #define TVP3026_XCLKCTRL_DIV1 0x00
163 #define TVP3026_XCLKCTRL_DIV2 0x10
164 #define TVP3026_XCLKCTRL_DIV4 0x20
165 #define TVP3026_XCLKCTRL_DIV8 0x30
166 #define TVP3026_XCLKCTRL_DIV16 0x40
167 #define TVP3026_XCLKCTRL_DIV32 0x50
168 #define TVP3026_XCLKCTRL_DIV64 0x60
169 #define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
170 #define TVP3026_XCLKCTRL_SRC_CLK0 0x00
171 #define TVP3026_XCLKCTRL_SRC_CLK1 0x01
172 #define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
173 #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
174 #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
175 #define TVP3026_XCLKCTRL_SRC_PLL 0x05
176 #define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
177 #define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
178 #define TVP3026_XPALETTEPAGE 0x1C
179 #define TVP3026_XGENCTRL 0x1D
180 #define TVP3026_XGENCTRL_HSYNC_POS 0x00
181 #define TVP3026_XGENCTRL_HSYNC_NEG 0x01
182 #define TVP3026_XGENCTRL_VSYNC_POS 0x00
183 #define TVP3026_XGENCTRL_VSYNC_NEG 0x02
184 #define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
185 #define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
186 #define TVP3026_XGENCTRL_BLACK_0IRE 0x00
187 #define TVP3026_XGENCTRL_BLACK_75IRE 0x10
188 #define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
189 #define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
190 #define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
191 #define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
192 #define TVP3026_XMISCCTRL 0x1E
193 #define TVP3026_XMISCCTRL_DAC_PUP 0x00
194 #define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
195 #define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
196 #define TVP3026_XMISCCTRL_DAC_6BIT 0x04
197 #define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
198 #define TVP3026_XMISCCTRL_PSEL_DIS 0x00
199 #define TVP3026_XMISCCTRL_PSEL_EN 0x10
200 #define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
201 #define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
202 #define TVP3026_XGENIOCTRL 0x2A
203 #define TVP3026_XGENIODATA 0x2B
204 #define TVP3026_XPLLADDR 0x2C
205 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
206 #define TVP3026_XPLLDATA_N 0x00
207 #define TVP3026_XPLLDATA_M 0x01
208 #define TVP3026_XPLLDATA_P 0x02
209 #define TVP3026_XPLLDATA_STAT 0x03
210 #define TVP3026_XPIXPLLDATA 0x2D
211 #define TVP3026_XMEMPLLDATA 0x2E
212 #define TVP3026_XLOOPPLLDATA 0x2F
213 #define TVP3026_XCOLKEYOVRMIN 0x30
214 #define TVP3026_XCOLKEYOVRMAX 0x31
215 #define TVP3026_XCOLKEYREDMIN 0x32
216 #define TVP3026_XCOLKEYREDMAX 0x33
217 #define TVP3026_XCOLKEYGREENMIN 0x34
218 #define TVP3026_XCOLKEYGREENMAX 0x35
219 #define TVP3026_XCOLKEYBLUEMIN 0x36
220 #define TVP3026_XCOLKEYBLUEMAX 0x37
221 #define TVP3026_XCOLKEYCTRL 0x38
222 #define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
223 #define TVP3026_XCOLKEYCTRL_RED_EN 0x02
224 #define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
225 #define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
226 #define TVP3026_XCOLKEYCTRL_NEGATE 0x10
227 #define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
228 #define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
229 #define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
230 #define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
231 #define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
232 #define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
233 #define TVP3026_XMEMPLLCTRL 0x39
234 #define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
235 #define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
236 #define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
237 #define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
238 #define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
239 #define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
240 #define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
241 #define TVP3026_XSENSETEST 0x3A
242 #define TVP3026_XTESTMODEDATA 0x3B
243 #define TVP3026_XCRCREML 0x3C
244 #define TVP3026_XCRCREMH 0x3D
245 #define TVP3026_XCRCBITSEL 0x3E
246 #define TVP3026_XID 0x3F
247
248 static const unsigned char DACseq[] =
249 { TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
250 TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
251 TVP3026_XPALETTEPAGE,
252 TVP3026_XGENCTRL,
253 TVP3026_XMISCCTRL,
254 TVP3026_XGENIOCTRL,
255 TVP3026_XGENIODATA,
256 TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
257 TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
258 TVP3026_XCOLKEYCTRL,
259 TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
260
261 #define POS3026_XLATCHCTRL 0
262 #define POS3026_XTRUECOLORCTRL 1
263 #define POS3026_XMUXCTRL 2
264 #define POS3026_XCLKCTRL 3
265 #define POS3026_XGENCTRL 5
266 #define POS3026_XMISCCTRL 6
267 #define POS3026_XMEMPLLCTRL 18
268 #define POS3026_XCURCTRL 20
269
270 static const unsigned char MGADACbpp32[] =
271 { TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
272 0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
273 0x00,
274 TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
275 TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
276 0x00,
277 0x1E,
278 0xFF, 0xFF, 0xFF, 0xFF,
279 0xFF, 0xFF, 0xFF, 0xFF,
280 TVP3026_XCOLKEYCTRL_ZOOM1,
281 0x00, 0x00, TVP3026_XCURCTRL_DIS };
282
283 static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
284 unsigned int fvco;
285 unsigned int lin, lfeed, lpost;
286
287 DBG(__FUNCTION__)
288
289 fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
290 fvco >>= (*post = lpost);
291 *in = 64 - lin;
292 *feed = 64 - lfeed;
293 return fvco;
294 }
295
296 static int Ti3026_setpclk(WPMINFO int clk) {
297 unsigned int f_pll;
298 unsigned int pixfeed, pixin, pixpost;
299 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
300
301 DBG(__FUNCTION__)
302
303 f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
304
305 hw->DACclk[0] = pixin | 0xC0;
306 hw->DACclk[1] = pixfeed;
307 hw->DACclk[2] = pixpost | 0xB0;
308
309 {
310 unsigned int loopfeed, loopin, looppost, loopdiv, z;
311 unsigned int Bpp;
312
313 Bpp = ACCESS_FBINFO(curr.final_bppShift);
314
315 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
316 loopfeed = 3; /* set lm to any possible value */
317 loopin = 3 * 32 / Bpp;
318 } else {
319 loopfeed = 4;
320 loopin = 4 * 32 / Bpp;
321 }
322 z = (110000 * loopin) / (f_pll * loopfeed);
323 loopdiv = 0; /* div 2 */
324 if (z < 2)
325 looppost = 0;
326 else if (z < 4)
327 looppost = 1;
328 else if (z < 8)
329 looppost = 2;
330 else {
331 looppost = 3;
332 loopdiv = z/16;
333 }
334 if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
335 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
336 hw->DACclk[4] = (65 - loopfeed) | 0x80;
337 if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
338 if (isInterleave(MINFO))
339 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
340 else {
341 hw->DACclk[4] &= ~0xC0;
342 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
343 }
344 } else {
345 if (isInterleave(MINFO))
346 ; /* default... */
347 else {
348 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
349 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
350 }
351 }
352 hw->DACclk[5] = looppost | 0xF8;
353 if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
354 hw->DACclk[5] ^= 0x40;
355 } else {
356 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
357 hw->DACclk[4] = 65 - loopfeed;
358 hw->DACclk[5] = looppost | 0xF0;
359 }
360 hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
361 }
362 return 0;
363 }
364
365 static int Ti3026_init(WPMINFO struct my_timming* m) {
366 u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
367 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
368
369 DBG(__FUNCTION__)
370
371 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
372 switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) {
373 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
374 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
375 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
376 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
377 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
378 break;
379 case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
380 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
381 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
382 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
383 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
384 break;
385 case 16:
386 /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
387 hw->DACreg[POS3026_XTRUECOLORCTRL] = (ACCESS_FBINFO(fbcon).var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
388 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
389 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
390 break;
391 case 24:
392 /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
393 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
394 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
395 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
396 break;
397 case 32:
398 /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used everytime) */
399 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
400 break;
401 default:
402 return 1; /* TODO: failed */
403 }
404 if (matroxfb_vgaHWinit(PMINFO m)) return 1;
405
406 /* set SYNC */
407 hw->MiscOutReg = 0xCB;
408 if (m->sync & FB_SYNC_HOR_HIGH_ACT)
409 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
410 if (m->sync & FB_SYNC_VERT_HIGH_ACT)
411 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
412 if (m->sync & FB_SYNC_ON_GREEN)
413 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
414
415 /* set DELAY */
416 if (ACCESS_FBINFO(video.len) < 0x400000)
417 hw->CRTCEXT[3] |= 0x08;
418 else if (ACCESS_FBINFO(video.len) > 0x400000)
419 hw->CRTCEXT[3] |= 0x10;
420
421 /* set HWCURSOR */
422 if (m->interlaced) {
423 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
424 }
425 if (m->HTotal >= 1536)
426 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
427
428 /* set interleaving */
429 hw->MXoptionReg &= ~0x00001000;
430 if (isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
431
432 /* set DAC */
433 Ti3026_setpclk(PMINFO m->pixclock);
434 return 0;
435 }
436
437 static void ti3026_setMCLK(WPMINFO int fout){
438 unsigned int f_pll;
439 unsigned int pclk_m, pclk_n, pclk_p;
440 unsigned int mclk_m, mclk_n, mclk_p;
441 unsigned int rfhcnt, mclk_ctl;
442 int tmout;
443
444 DBG(__FUNCTION__)
445
446 f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
447
448 /* save pclk */
449 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
450 pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
451 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
452 pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
453 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
454 pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
455
456 /* stop pclk */
457 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
458 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
459
460 /* set pclk to new mclk */
461 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
462 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
463 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
464 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
465
466 /* wait for PLL to lock */
467 for (tmout = 500000; tmout; tmout--) {
468 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
469 break;
470 udelay(10);
471 };
472 if (!tmout)
473 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
474
475 /* output pclk on mclk pin */
476 mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
477 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
478 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
479
480 /* stop MCLK */
481 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
482 outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
483
484 /* set mclk to new freq */
485 outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
486 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
487 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
488 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
489
490 /* wait for PLL to lock */
491 for (tmout = 500000; tmout; tmout--) {
492 if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
493 break;
494 udelay(10);
495 }
496 if (!tmout)
497 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
498
499 f_pll = f_pll * 333 / (10000 << mclk_p);
500 if (isMilleniumII(MINFO)) {
501 rfhcnt = (f_pll - 128) / 256;
502 if (rfhcnt > 15)
503 rfhcnt = 15;
504 } else {
505 rfhcnt = (f_pll - 64) / 128;
506 if (rfhcnt > 15)
507 rfhcnt = 0;
508 }
509 ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
510 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg);
511
512 /* output MCLK to MCLK pin */
513 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
514 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
515
516 /* stop PCLK */
517 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
518 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
519
520 /* restore pclk */
521 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
522 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
523 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
524 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
525
526 /* wait for PLL to lock */
527 for (tmout = 500000; tmout; tmout--) {
528 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
529 break;
530 udelay(10);
531 }
532 if (!tmout)
533 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
534 }
535
536 static void ti3026_ramdac_init(WPMINFO2) {
537
538 DBG(__FUNCTION__)
539
540 ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
541 ACCESS_FBINFO(features.pll.ref_freq) = 114545;
542 ACCESS_FBINFO(features.pll.feed_div_min) = 2;
543 ACCESS_FBINFO(features.pll.feed_div_max) = 24;
544 ACCESS_FBINFO(features.pll.in_div_min) = 2;
545 ACCESS_FBINFO(features.pll.in_div_max) = 63;
546 ACCESS_FBINFO(features.pll.post_shift_max) = 3;
547 if (ACCESS_FBINFO(devflags.noinit))
548 return;
549 ti3026_setMCLK(PMINFO 60000);
550 }
551
552 static void Ti3026_restore(WPMINFO2) {
553 int i;
554 unsigned char progdac[6];
555 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
556 CRITFLAGS
557
558 DBG(__FUNCTION__)
559
560 #ifdef DEBUG
561 dprintk(KERN_INFO "EXTVGA regs: ");
562 for (i = 0; i < 6; i++)
563 dprintk("%02X:", hw->CRTCEXT[i]);
564 dprintk("\n");
565 #endif
566
567 CRITBEGIN
568
569 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
570
571 CRITEND
572
573 matroxfb_vgaHWrestore(PMINFO2);
574
575 CRITBEGIN
576
577 ACCESS_FBINFO(crtc1.panpos) = -1;
578 for (i = 0; i < 6; i++)
579 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
580
581 for (i = 0; i < 21; i++) {
582 outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
583 }
584
585 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
586 progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
587 progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
588 outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
589 progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
590 progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
591 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
592 progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
593 progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
594
595 CRITEND
596 if (memcmp(hw->DACclk, progdac, 6)) {
597 /* agrhh... setting up PLL is very slow on Millennium... */
598 /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
599 /* Maybe even we should call schedule() ? */
600
601 CRITBEGIN
602 outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
603 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
604 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
605 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
606
607 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
608 for (i = 0; i < 3; i++)
609 outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
610 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
611 if (hw->MiscOutReg & 0x08) {
612 int tmout;
613 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
614 for (tmout = 500000; tmout; --tmout) {
615 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
616 break;
617 udelay(10);
618 }
619
620 CRITEND
621
622 if (!tmout)
623 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
624 else
625 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
626 CRITBEGIN
627 }
628 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
629 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
630 for (i = 3; i < 6; i++)
631 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
632 CRITEND
633 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
634 int tmout;
635
636 CRITBEGIN
637 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
638 for (tmout = 500000; tmout; --tmout) {
639 if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
640 break;
641 udelay(10);
642 }
643 CRITEND
644 if (!tmout)
645 printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
646 else
647 dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
648 }
649 }
650
651 #ifdef DEBUG
652 dprintk(KERN_DEBUG "3026DACregs ");
653 for (i = 0; i < 21; i++) {
654 dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
655 if ((i & 0x7) == 0x7) dprintk("\n" KERN_DEBUG "continuing... ");
656 }
657 dprintk("\n" KERN_DEBUG "DACclk ");
658 for (i = 0; i < 6; i++)
659 dprintk("C%02X=%02X ", i, hw->DACclk[i]);
660 dprintk("\n");
661 #endif
662 }
663
664 static void Ti3026_reset(WPMINFO2) {
665
666 DBG(__FUNCTION__)
667
668 ti3026_ramdac_init(PMINFO2);
669 }
670
671 static struct matrox_altout ti3026_output = {
672 .name = "Primary output",
673 };
674
675 static int Ti3026_preinit(WPMINFO2) {
676 static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
677 1024, 1152, 1280, 1600, 1664, 1920,
678 2048, 0};
679 static const int vxres_mill1[] = { 640, 768, 800, 960,
680 1024, 1152, 1280, 1600, 1920,
681 2048, 0};
682 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
683
684 DBG(__FUNCTION__)
685
686 ACCESS_FBINFO(millenium) = 1;
687 ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
688 ACCESS_FBINFO(capable.cfb4) = 1;
689 ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
690 ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
691
692 ACCESS_FBINFO(outputs[0]).data = MINFO;
693 ACCESS_FBINFO(outputs[0]).output = &ti3026_output;
694 ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src;
695 ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
696
697 if (ACCESS_FBINFO(devflags.noinit))
698 return 0;
699 /* preserve VGA I/O, BIOS and PPC */
700 hw->MXoptionReg &= 0xC0000100;
701 hw->MXoptionReg |= 0x002C0000;
702 if (ACCESS_FBINFO(devflags.novga))
703 hw->MXoptionReg &= ~0x00000100;
704 if (ACCESS_FBINFO(devflags.nobios))
705 hw->MXoptionReg &= ~0x40000000;
706 if (ACCESS_FBINFO(devflags.nopciretry))
707 hw->MXoptionReg |= 0x20000000;
708 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
709
710 ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
711
712 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
713 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
714 outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
715
716 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
717 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
718 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
719
720 mga_outb(M_MISC_REG, 0x67);
721
722 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
723
724 mga_outl(M_RESET, 1);
725 udelay(250);
726 mga_outl(M_RESET, 0);
727 udelay(250);
728 mga_outl(M_MACCESS, 0x00008000);
729 udelay(10);
730 return 0;
731 }
732
733 struct matrox_switch matrox_millennium = {
734 Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore
735 };
736 EXPORT_SYMBOL(matrox_millennium);
737 #endif
738 MODULE_LICENSE("GPL");
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