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[mirror_ubuntu-artful-kernel.git] / drivers / video / omap / dispc.c
1 /*
2 * OMAP2 display controller support
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/kernel.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mm.h>
24 #include <linux/vmalloc.h>
25 #include <linux/clk.h>
26 #include <linux/io.h>
27 #include <linux/platform_device.h>
28
29 #include <plat/sram.h>
30 #include <plat/board.h>
31
32 #include "omapfb.h"
33 #include "dispc.h"
34
35 #define MODULE_NAME "dispc"
36
37 #define DSS_BASE 0x48050000
38 #define DSS_SYSCONFIG 0x0010
39
40 #define DISPC_BASE 0x48050400
41
42 /* DISPC common */
43 #define DISPC_REVISION 0x0000
44 #define DISPC_SYSCONFIG 0x0010
45 #define DISPC_SYSSTATUS 0x0014
46 #define DISPC_IRQSTATUS 0x0018
47 #define DISPC_IRQENABLE 0x001C
48 #define DISPC_CONTROL 0x0040
49 #define DISPC_CONFIG 0x0044
50 #define DISPC_CAPABLE 0x0048
51 #define DISPC_DEFAULT_COLOR0 0x004C
52 #define DISPC_DEFAULT_COLOR1 0x0050
53 #define DISPC_TRANS_COLOR0 0x0054
54 #define DISPC_TRANS_COLOR1 0x0058
55 #define DISPC_LINE_STATUS 0x005C
56 #define DISPC_LINE_NUMBER 0x0060
57 #define DISPC_TIMING_H 0x0064
58 #define DISPC_TIMING_V 0x0068
59 #define DISPC_POL_FREQ 0x006C
60 #define DISPC_DIVISOR 0x0070
61 #define DISPC_SIZE_DIG 0x0078
62 #define DISPC_SIZE_LCD 0x007C
63
64 #define DISPC_DATA_CYCLE1 0x01D4
65 #define DISPC_DATA_CYCLE2 0x01D8
66 #define DISPC_DATA_CYCLE3 0x01DC
67
68 /* DISPC GFX plane */
69 #define DISPC_GFX_BA0 0x0080
70 #define DISPC_GFX_BA1 0x0084
71 #define DISPC_GFX_POSITION 0x0088
72 #define DISPC_GFX_SIZE 0x008C
73 #define DISPC_GFX_ATTRIBUTES 0x00A0
74 #define DISPC_GFX_FIFO_THRESHOLD 0x00A4
75 #define DISPC_GFX_FIFO_SIZE_STATUS 0x00A8
76 #define DISPC_GFX_ROW_INC 0x00AC
77 #define DISPC_GFX_PIXEL_INC 0x00B0
78 #define DISPC_GFX_WINDOW_SKIP 0x00B4
79 #define DISPC_GFX_TABLE_BA 0x00B8
80
81 /* DISPC Video plane 1/2 */
82 #define DISPC_VID1_BASE 0x00BC
83 #define DISPC_VID2_BASE 0x014C
84
85 /* Offsets into DISPC_VID1/2_BASE */
86 #define DISPC_VID_BA0 0x0000
87 #define DISPC_VID_BA1 0x0004
88 #define DISPC_VID_POSITION 0x0008
89 #define DISPC_VID_SIZE 0x000C
90 #define DISPC_VID_ATTRIBUTES 0x0010
91 #define DISPC_VID_FIFO_THRESHOLD 0x0014
92 #define DISPC_VID_FIFO_SIZE_STATUS 0x0018
93 #define DISPC_VID_ROW_INC 0x001C
94 #define DISPC_VID_PIXEL_INC 0x0020
95 #define DISPC_VID_FIR 0x0024
96 #define DISPC_VID_PICTURE_SIZE 0x0028
97 #define DISPC_VID_ACCU0 0x002C
98 #define DISPC_VID_ACCU1 0x0030
99
100 /* 8 elements in 8 byte increments */
101 #define DISPC_VID_FIR_COEF_H0 0x0034
102 /* 8 elements in 8 byte increments */
103 #define DISPC_VID_FIR_COEF_HV0 0x0038
104 /* 5 elements in 4 byte increments */
105 #define DISPC_VID_CONV_COEF0 0x0074
106
107 #define DISPC_IRQ_FRAMEMASK 0x0001
108 #define DISPC_IRQ_VSYNC 0x0002
109 #define DISPC_IRQ_EVSYNC_EVEN 0x0004
110 #define DISPC_IRQ_EVSYNC_ODD 0x0008
111 #define DISPC_IRQ_ACBIAS_COUNT_STAT 0x0010
112 #define DISPC_IRQ_PROG_LINE_NUM 0x0020
113 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW 0x0040
114 #define DISPC_IRQ_GFX_END_WIN 0x0080
115 #define DISPC_IRQ_PAL_GAMMA_MASK 0x0100
116 #define DISPC_IRQ_OCP_ERR 0x0200
117 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW 0x0400
118 #define DISPC_IRQ_VID1_END_WIN 0x0800
119 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW 0x1000
120 #define DISPC_IRQ_VID2_END_WIN 0x2000
121 #define DISPC_IRQ_SYNC_LOST 0x4000
122
123 #define DISPC_IRQ_MASK_ALL 0x7fff
124
125 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
126 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
127 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
128 DISPC_IRQ_SYNC_LOST)
129
130 #define RFBI_CONTROL 0x48050040
131
132 #define MAX_PALETTE_SIZE (256 * 16)
133
134 #define FLD_MASK(pos, len) (((1 << len) - 1) << pos)
135
136 #define MOD_REG_FLD(reg, mask, val) \
137 dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val));
138
139 #define OMAP2_SRAM_START 0x40200000
140 /* Maximum size, in reality this is smaller if SRAM is partially locked. */
141 #define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
142
143 /* We support the SDRAM / SRAM types. See OMAPFB_PLANE_MEMTYPE_* in omapfb.h */
144 #define DISPC_MEMTYPE_NUM 2
145
146 #define RESMAP_SIZE(_page_cnt) \
147 ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
148 #define RESMAP_PTR(_res_map, _page_nr) \
149 (((_res_map)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
150 #define RESMAP_MASK(_page_nr) \
151 (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
152
153 struct resmap {
154 unsigned long start;
155 unsigned page_cnt;
156 unsigned long *map;
157 };
158
159 #define MAX_IRQ_HANDLERS 4
160
161 static struct {
162 void __iomem *base;
163
164 struct omapfb_mem_desc mem_desc;
165 struct resmap *res_map[DISPC_MEMTYPE_NUM];
166 atomic_t map_count[OMAPFB_PLANE_NUM];
167
168 dma_addr_t palette_paddr;
169 void *palette_vaddr;
170
171 int ext_mode;
172
173 struct {
174 u32 irq_mask;
175 void (*callback)(void *);
176 void *data;
177 } irq_handlers[MAX_IRQ_HANDLERS];
178 struct completion frame_done;
179
180 int fir_hinc[OMAPFB_PLANE_NUM];
181 int fir_vinc[OMAPFB_PLANE_NUM];
182
183 struct clk *dss_ick, *dss1_fck;
184 struct clk *dss_54m_fck;
185
186 enum omapfb_update_mode update_mode;
187 struct omapfb_device *fbdev;
188
189 struct omapfb_color_key color_key;
190 } dispc;
191
192 static struct platform_device omapdss_device = {
193 .name = "omapdss",
194 .id = -1,
195 };
196
197 static void enable_lcd_clocks(int enable);
198
199 static void inline dispc_write_reg(int idx, u32 val)
200 {
201 __raw_writel(val, dispc.base + idx);
202 }
203
204 static u32 inline dispc_read_reg(int idx)
205 {
206 u32 l = __raw_readl(dispc.base + idx);
207 return l;
208 }
209
210 /* Select RFBI or bypass mode */
211 static void enable_rfbi_mode(int enable)
212 {
213 void __iomem *rfbi_control;
214 u32 l;
215
216 l = dispc_read_reg(DISPC_CONTROL);
217 /* Enable RFBI, GPIO0/1 */
218 l &= ~((1 << 11) | (1 << 15) | (1 << 16));
219 l |= enable ? (1 << 11) : 0;
220 /* RFBI En: GPIO0/1=10 RFBI Dis: GPIO0/1=11 */
221 l |= 1 << 15;
222 l |= enable ? 0 : (1 << 16);
223 dispc_write_reg(DISPC_CONTROL, l);
224
225 /* Set bypass mode in RFBI module */
226 rfbi_control = ioremap(RFBI_CONTROL, SZ_1K);
227 if (!rfbi_control) {
228 pr_err("Unable to ioremap rfbi_control\n");
229 return;
230 }
231 l = __raw_readl(rfbi_control);
232 l |= enable ? 0 : (1 << 1);
233 __raw_writel(l, rfbi_control);
234 iounmap(rfbi_control);
235 }
236
237 static void set_lcd_data_lines(int data_lines)
238 {
239 u32 l;
240 int code = 0;
241
242 switch (data_lines) {
243 case 12:
244 code = 0;
245 break;
246 case 16:
247 code = 1;
248 break;
249 case 18:
250 code = 2;
251 break;
252 case 24:
253 code = 3;
254 break;
255 default:
256 BUG();
257 }
258
259 l = dispc_read_reg(DISPC_CONTROL);
260 l &= ~(0x03 << 8);
261 l |= code << 8;
262 dispc_write_reg(DISPC_CONTROL, l);
263 }
264
265 static void set_load_mode(int mode)
266 {
267 BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY |
268 DISPC_LOAD_CLUT_ONCE_FRAME));
269 MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);
270 }
271
272 void omap_dispc_set_lcd_size(int x, int y)
273 {
274 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
275 enable_lcd_clocks(1);
276 MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),
277 ((y - 1) << 16) | (x - 1));
278 enable_lcd_clocks(0);
279 }
280 EXPORT_SYMBOL(omap_dispc_set_lcd_size);
281
282 void omap_dispc_set_digit_size(int x, int y)
283 {
284 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
285 enable_lcd_clocks(1);
286 MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),
287 ((y - 1) << 16) | (x - 1));
288 enable_lcd_clocks(0);
289 }
290 EXPORT_SYMBOL(omap_dispc_set_digit_size);
291
292 static void setup_plane_fifo(int plane, int ext_mode)
293 {
294 const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
295 DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD,
296 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD };
297 const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
298 DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS,
299 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS };
300 int low, high;
301 u32 l;
302
303 BUG_ON(plane > 2);
304
305 l = dispc_read_reg(fsz_reg[plane]);
306 l &= FLD_MASK(0, 11);
307 if (ext_mode) {
308 low = l * 3 / 4;
309 high = l;
310 } else {
311 low = l / 4;
312 high = l * 3 / 4;
313 }
314 MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),
315 (high << 16) | low);
316 }
317
318 void omap_dispc_enable_lcd_out(int enable)
319 {
320 enable_lcd_clocks(1);
321 MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);
322 enable_lcd_clocks(0);
323 }
324 EXPORT_SYMBOL(omap_dispc_enable_lcd_out);
325
326 void omap_dispc_enable_digit_out(int enable)
327 {
328 enable_lcd_clocks(1);
329 MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);
330 enable_lcd_clocks(0);
331 }
332 EXPORT_SYMBOL(omap_dispc_enable_digit_out);
333
334 static inline int _setup_plane(int plane, int channel_out,
335 u32 paddr, int screen_width,
336 int pos_x, int pos_y, int width, int height,
337 int color_mode)
338 {
339 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
340 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
341 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
342 const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0,
343 DISPC_VID2_BASE + DISPC_VID_BA0 };
344 const u32 ps_reg[] = { DISPC_GFX_POSITION,
345 DISPC_VID1_BASE + DISPC_VID_POSITION,
346 DISPC_VID2_BASE + DISPC_VID_POSITION };
347 const u32 sz_reg[] = { DISPC_GFX_SIZE,
348 DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE,
349 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE };
350 const u32 ri_reg[] = { DISPC_GFX_ROW_INC,
351 DISPC_VID1_BASE + DISPC_VID_ROW_INC,
352 DISPC_VID2_BASE + DISPC_VID_ROW_INC };
353 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
354 DISPC_VID2_BASE + DISPC_VID_SIZE };
355
356 int chout_shift, burst_shift;
357 int chout_val;
358 int color_code;
359 int bpp;
360 int cconv_en;
361 int set_vsize;
362 u32 l;
363
364 #ifdef VERBOSE
365 dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d"
366 " pos_x %d pos_y %d width %d height %d color_mode %d\n",
367 plane, channel_out, paddr, screen_width, pos_x, pos_y,
368 width, height, color_mode);
369 #endif
370
371 set_vsize = 0;
372 switch (plane) {
373 case OMAPFB_PLANE_GFX:
374 burst_shift = 6;
375 chout_shift = 8;
376 break;
377 case OMAPFB_PLANE_VID1:
378 case OMAPFB_PLANE_VID2:
379 burst_shift = 14;
380 chout_shift = 16;
381 set_vsize = 1;
382 break;
383 default:
384 return -EINVAL;
385 }
386
387 switch (channel_out) {
388 case OMAPFB_CHANNEL_OUT_LCD:
389 chout_val = 0;
390 break;
391 case OMAPFB_CHANNEL_OUT_DIGIT:
392 chout_val = 1;
393 break;
394 default:
395 return -EINVAL;
396 }
397
398 cconv_en = 0;
399 switch (color_mode) {
400 case OMAPFB_COLOR_RGB565:
401 color_code = DISPC_RGB_16_BPP;
402 bpp = 16;
403 break;
404 case OMAPFB_COLOR_YUV422:
405 if (plane == 0)
406 return -EINVAL;
407 color_code = DISPC_UYVY_422;
408 cconv_en = 1;
409 bpp = 16;
410 break;
411 case OMAPFB_COLOR_YUY422:
412 if (plane == 0)
413 return -EINVAL;
414 color_code = DISPC_YUV2_422;
415 cconv_en = 1;
416 bpp = 16;
417 break;
418 default:
419 return -EINVAL;
420 }
421
422 l = dispc_read_reg(at_reg[plane]);
423
424 l &= ~(0x0f << 1);
425 l |= color_code << 1;
426 l &= ~(1 << 9);
427 l |= cconv_en << 9;
428
429 l &= ~(0x03 << burst_shift);
430 l |= DISPC_BURST_8x32 << burst_shift;
431
432 l &= ~(1 << chout_shift);
433 l |= chout_val << chout_shift;
434
435 dispc_write_reg(at_reg[plane], l);
436
437 dispc_write_reg(ba_reg[plane], paddr);
438 MOD_REG_FLD(ps_reg[plane],
439 FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x);
440
441 MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),
442 ((height - 1) << 16) | (width - 1));
443
444 if (set_vsize) {
445 /* Set video size if set_scale hasn't set it */
446 if (!dispc.fir_vinc[plane])
447 MOD_REG_FLD(vs_reg[plane],
448 FLD_MASK(16, 11), (height - 1) << 16);
449 if (!dispc.fir_hinc[plane])
450 MOD_REG_FLD(vs_reg[plane],
451 FLD_MASK(0, 11), width - 1);
452 }
453
454 dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
455
456 return height * screen_width * bpp / 8;
457 }
458
459 static int omap_dispc_setup_plane(int plane, int channel_out,
460 unsigned long offset,
461 int screen_width,
462 int pos_x, int pos_y, int width, int height,
463 int color_mode)
464 {
465 u32 paddr;
466 int r;
467
468 if ((unsigned)plane > dispc.mem_desc.region_cnt)
469 return -EINVAL;
470 paddr = dispc.mem_desc.region[plane].paddr + offset;
471 enable_lcd_clocks(1);
472 r = _setup_plane(plane, channel_out, paddr,
473 screen_width,
474 pos_x, pos_y, width, height, color_mode);
475 enable_lcd_clocks(0);
476 return r;
477 }
478
479 static void write_firh_reg(int plane, int reg, u32 value)
480 {
481 u32 base;
482
483 if (plane == 1)
484 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0;
485 else
486 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0;
487 dispc_write_reg(base + reg * 8, value);
488 }
489
490 static void write_firhv_reg(int plane, int reg, u32 value)
491 {
492 u32 base;
493
494 if (plane == 1)
495 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0;
496 else
497 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0;
498 dispc_write_reg(base + reg * 8, value);
499 }
500
501 static void set_upsampling_coef_table(int plane)
502 {
503 const u32 coef[][2] = {
504 { 0x00800000, 0x00800000 },
505 { 0x0D7CF800, 0x037B02FF },
506 { 0x1E70F5FF, 0x0C6F05FE },
507 { 0x335FF5FE, 0x205907FB },
508 { 0xF74949F7, 0x00404000 },
509 { 0xF55F33FB, 0x075920FE },
510 { 0xF5701EFE, 0x056F0CFF },
511 { 0xF87C0DFF, 0x027B0300 },
512 };
513 int i;
514
515 for (i = 0; i < 8; i++) {
516 write_firh_reg(plane, i, coef[i][0]);
517 write_firhv_reg(plane, i, coef[i][1]);
518 }
519 }
520
521 static int omap_dispc_set_scale(int plane,
522 int orig_width, int orig_height,
523 int out_width, int out_height)
524 {
525 const u32 at_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
526 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
527 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
528 DISPC_VID2_BASE + DISPC_VID_SIZE };
529 const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR,
530 DISPC_VID2_BASE + DISPC_VID_FIR };
531
532 u32 l;
533 int fir_hinc;
534 int fir_vinc;
535
536 if ((unsigned)plane > OMAPFB_PLANE_NUM)
537 return -ENODEV;
538
539 if (plane == OMAPFB_PLANE_GFX &&
540 (out_width != orig_width || out_height != orig_height))
541 return -EINVAL;
542
543 enable_lcd_clocks(1);
544 if (orig_width < out_width) {
545 /*
546 * Upsampling.
547 * Currently you can only scale both dimensions in one way.
548 */
549 if (orig_height > out_height ||
550 orig_width * 8 < out_width ||
551 orig_height * 8 < out_height) {
552 enable_lcd_clocks(0);
553 return -EINVAL;
554 }
555 set_upsampling_coef_table(plane);
556 } else if (orig_width > out_width) {
557 /* Downsampling not yet supported
558 */
559
560 enable_lcd_clocks(0);
561 return -EINVAL;
562 }
563 if (!orig_width || orig_width == out_width)
564 fir_hinc = 0;
565 else
566 fir_hinc = 1024 * orig_width / out_width;
567 if (!orig_height || orig_height == out_height)
568 fir_vinc = 0;
569 else
570 fir_vinc = 1024 * orig_height / out_height;
571 dispc.fir_hinc[plane] = fir_hinc;
572 dispc.fir_vinc[plane] = fir_vinc;
573
574 MOD_REG_FLD(fir_reg[plane],
575 FLD_MASK(16, 12) | FLD_MASK(0, 12),
576 ((fir_vinc & 4095) << 16) |
577 (fir_hinc & 4095));
578
579 dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
580 "orig_height %d fir_hinc %d fir_vinc %d\n",
581 out_width, out_height, orig_width, orig_height,
582 fir_hinc, fir_vinc);
583
584 MOD_REG_FLD(vs_reg[plane],
585 FLD_MASK(16, 11) | FLD_MASK(0, 11),
586 ((out_height - 1) << 16) | (out_width - 1));
587
588 l = dispc_read_reg(at_reg[plane]);
589 l &= ~(0x03 << 5);
590 l |= fir_hinc ? (1 << 5) : 0;
591 l |= fir_vinc ? (1 << 6) : 0;
592 dispc_write_reg(at_reg[plane], l);
593
594 enable_lcd_clocks(0);
595 return 0;
596 }
597
598 static int omap_dispc_enable_plane(int plane, int enable)
599 {
600 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
601 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
602 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
603 if ((unsigned int)plane > dispc.mem_desc.region_cnt)
604 return -EINVAL;
605
606 enable_lcd_clocks(1);
607 MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
608 enable_lcd_clocks(0);
609
610 return 0;
611 }
612
613 static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
614 {
615 u32 df_reg, tr_reg;
616 int shift, val;
617
618 switch (ck->channel_out) {
619 case OMAPFB_CHANNEL_OUT_LCD:
620 df_reg = DISPC_DEFAULT_COLOR0;
621 tr_reg = DISPC_TRANS_COLOR0;
622 shift = 10;
623 break;
624 case OMAPFB_CHANNEL_OUT_DIGIT:
625 df_reg = DISPC_DEFAULT_COLOR1;
626 tr_reg = DISPC_TRANS_COLOR1;
627 shift = 12;
628 break;
629 default:
630 return -EINVAL;
631 }
632 switch (ck->key_type) {
633 case OMAPFB_COLOR_KEY_DISABLED:
634 val = 0;
635 break;
636 case OMAPFB_COLOR_KEY_GFX_DST:
637 val = 1;
638 break;
639 case OMAPFB_COLOR_KEY_VID_SRC:
640 val = 3;
641 break;
642 default:
643 return -EINVAL;
644 }
645 enable_lcd_clocks(1);
646 MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);
647
648 if (val != 0)
649 dispc_write_reg(tr_reg, ck->trans_key);
650 dispc_write_reg(df_reg, ck->background);
651 enable_lcd_clocks(0);
652
653 dispc.color_key = *ck;
654
655 return 0;
656 }
657
658 static int omap_dispc_get_color_key(struct omapfb_color_key *ck)
659 {
660 *ck = dispc.color_key;
661 return 0;
662 }
663
664 static void load_palette(void)
665 {
666 }
667
668 static int omap_dispc_set_update_mode(enum omapfb_update_mode mode)
669 {
670 int r = 0;
671
672 if (mode != dispc.update_mode) {
673 switch (mode) {
674 case OMAPFB_AUTO_UPDATE:
675 case OMAPFB_MANUAL_UPDATE:
676 enable_lcd_clocks(1);
677 omap_dispc_enable_lcd_out(1);
678 dispc.update_mode = mode;
679 break;
680 case OMAPFB_UPDATE_DISABLED:
681 init_completion(&dispc.frame_done);
682 omap_dispc_enable_lcd_out(0);
683 if (!wait_for_completion_timeout(&dispc.frame_done,
684 msecs_to_jiffies(500))) {
685 dev_err(dispc.fbdev->dev,
686 "timeout waiting for FRAME DONE\n");
687 }
688 dispc.update_mode = mode;
689 enable_lcd_clocks(0);
690 break;
691 default:
692 r = -EINVAL;
693 }
694 }
695
696 return r;
697 }
698
699 static void omap_dispc_get_caps(int plane, struct omapfb_caps *caps)
700 {
701 caps->ctrl |= OMAPFB_CAPS_PLANE_RELOCATE_MEM;
702 if (plane > 0)
703 caps->ctrl |= OMAPFB_CAPS_PLANE_SCALE;
704 caps->plane_color |= (1 << OMAPFB_COLOR_RGB565) |
705 (1 << OMAPFB_COLOR_YUV422) |
706 (1 << OMAPFB_COLOR_YUY422);
707 if (plane == 0)
708 caps->plane_color |= (1 << OMAPFB_COLOR_CLUT_8BPP) |
709 (1 << OMAPFB_COLOR_CLUT_4BPP) |
710 (1 << OMAPFB_COLOR_CLUT_2BPP) |
711 (1 << OMAPFB_COLOR_CLUT_1BPP) |
712 (1 << OMAPFB_COLOR_RGB444);
713 }
714
715 static enum omapfb_update_mode omap_dispc_get_update_mode(void)
716 {
717 return dispc.update_mode;
718 }
719
720 static void setup_color_conv_coef(void)
721 {
722 u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11);
723 int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0;
724 int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0;
725 int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES;
726 int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES;
727 const struct color_conv_coef {
728 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
729 int full_range;
730 } ctbl_bt601_5 = {
731 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
732 };
733 const struct color_conv_coef *ct;
734 #define CVAL(x, y) (((x & 2047) << 16) | (y & 2047))
735
736 ct = &ctbl_bt601_5;
737
738 MOD_REG_FLD(cf1_reg, mask, CVAL(ct->rcr, ct->ry));
739 MOD_REG_FLD(cf1_reg + 4, mask, CVAL(ct->gy, ct->rcb));
740 MOD_REG_FLD(cf1_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
741 MOD_REG_FLD(cf1_reg + 12, mask, CVAL(ct->bcr, ct->by));
742 MOD_REG_FLD(cf1_reg + 16, mask, CVAL(0, ct->bcb));
743
744 MOD_REG_FLD(cf2_reg, mask, CVAL(ct->rcr, ct->ry));
745 MOD_REG_FLD(cf2_reg + 4, mask, CVAL(ct->gy, ct->rcb));
746 MOD_REG_FLD(cf2_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
747 MOD_REG_FLD(cf2_reg + 12, mask, CVAL(ct->bcr, ct->by));
748 MOD_REG_FLD(cf2_reg + 16, mask, CVAL(0, ct->bcb));
749 #undef CVAL
750
751 MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);
752 MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
753 }
754
755 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
756 {
757 unsigned long fck, lck;
758
759 *lck_div = 1;
760 pck = max(1, pck);
761 fck = clk_get_rate(dispc.dss1_fck);
762 lck = fck;
763 *pck_div = (lck + pck - 1) / pck;
764 if (is_tft)
765 *pck_div = max(2, *pck_div);
766 else
767 *pck_div = max(3, *pck_div);
768 if (*pck_div > 255) {
769 *pck_div = 255;
770 lck = pck * *pck_div;
771 *lck_div = fck / lck;
772 BUG_ON(*lck_div < 1);
773 if (*lck_div > 255) {
774 *lck_div = 255;
775 dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n",
776 pck / 1000);
777 }
778 }
779 }
780
781 static void set_lcd_tft_mode(int enable)
782 {
783 u32 mask;
784
785 mask = 1 << 3;
786 MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);
787 }
788
789 static void set_lcd_timings(void)
790 {
791 u32 l;
792 int lck_div, pck_div;
793 struct lcd_panel *panel = dispc.fbdev->panel;
794 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
795 unsigned long fck;
796
797 l = dispc_read_reg(DISPC_TIMING_H);
798 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
799 l |= ( max(1, (min(64, panel->hsw))) - 1 ) << 0;
800 l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8;
801 l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20;
802 dispc_write_reg(DISPC_TIMING_H, l);
803
804 l = dispc_read_reg(DISPC_TIMING_V);
805 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
806 l |= ( max(1, (min(64, panel->vsw))) - 1 ) << 0;
807 l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8;
808 l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20;
809 dispc_write_reg(DISPC_TIMING_V, l);
810
811 l = dispc_read_reg(DISPC_POL_FREQ);
812 l &= ~FLD_MASK(12, 6);
813 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12;
814 l |= panel->acb & 0xff;
815 dispc_write_reg(DISPC_POL_FREQ, l);
816
817 calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
818
819 l = dispc_read_reg(DISPC_DIVISOR);
820 l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
821 l |= (lck_div << 16) | (pck_div << 0);
822 dispc_write_reg(DISPC_DIVISOR, l);
823
824 /* update panel info with the exact clock */
825 fck = clk_get_rate(dispc.dss1_fck);
826 panel->pixel_clock = fck / lck_div / pck_div / 1000;
827 }
828
829 static void recalc_irq_mask(void)
830 {
831 int i;
832 unsigned long irq_mask = DISPC_IRQ_MASK_ERROR;
833
834 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
835 if (!dispc.irq_handlers[i].callback)
836 continue;
837
838 irq_mask |= dispc.irq_handlers[i].irq_mask;
839 }
840
841 enable_lcd_clocks(1);
842 MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
843 enable_lcd_clocks(0);
844 }
845
846 int omap_dispc_request_irq(unsigned long irq_mask, void (*callback)(void *data),
847 void *data)
848 {
849 int i;
850
851 BUG_ON(callback == NULL);
852
853 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
854 if (dispc.irq_handlers[i].callback)
855 continue;
856
857 dispc.irq_handlers[i].irq_mask = irq_mask;
858 dispc.irq_handlers[i].callback = callback;
859 dispc.irq_handlers[i].data = data;
860 recalc_irq_mask();
861
862 return 0;
863 }
864
865 return -EBUSY;
866 }
867 EXPORT_SYMBOL(omap_dispc_request_irq);
868
869 void omap_dispc_free_irq(unsigned long irq_mask, void (*callback)(void *data),
870 void *data)
871 {
872 int i;
873
874 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
875 if (dispc.irq_handlers[i].callback == callback &&
876 dispc.irq_handlers[i].data == data) {
877 dispc.irq_handlers[i].irq_mask = 0;
878 dispc.irq_handlers[i].callback = NULL;
879 dispc.irq_handlers[i].data = NULL;
880 recalc_irq_mask();
881 return;
882 }
883 }
884
885 BUG();
886 }
887 EXPORT_SYMBOL(omap_dispc_free_irq);
888
889 static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
890 {
891 u32 stat;
892 int i = 0;
893
894 enable_lcd_clocks(1);
895
896 stat = dispc_read_reg(DISPC_IRQSTATUS);
897 if (stat & DISPC_IRQ_FRAMEMASK)
898 complete(&dispc.frame_done);
899
900 if (stat & DISPC_IRQ_MASK_ERROR) {
901 if (printk_ratelimit()) {
902 dev_err(dispc.fbdev->dev, "irq error status %04x\n",
903 stat & 0x7fff);
904 }
905 }
906
907 for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
908 if (unlikely(dispc.irq_handlers[i].callback &&
909 (stat & dispc.irq_handlers[i].irq_mask)))
910 dispc.irq_handlers[i].callback(
911 dispc.irq_handlers[i].data);
912 }
913
914 dispc_write_reg(DISPC_IRQSTATUS, stat);
915
916 enable_lcd_clocks(0);
917
918 return IRQ_HANDLED;
919 }
920
921 static int get_dss_clocks(void)
922 {
923 dispc.dss_ick = clk_get(&omapdss_device.dev, "ick");
924 if (IS_ERR(dispc.dss_ick)) {
925 dev_err(dispc.fbdev->dev, "can't get ick\n");
926 return PTR_ERR(dispc.dss_ick);
927 }
928
929 dispc.dss1_fck = clk_get(&omapdss_device.dev, "dss1_fck");
930 if (IS_ERR(dispc.dss1_fck)) {
931 dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
932 clk_put(dispc.dss_ick);
933 return PTR_ERR(dispc.dss1_fck);
934 }
935
936 dispc.dss_54m_fck = clk_get(&omapdss_device.dev, "tv_fck");
937 if (IS_ERR(dispc.dss_54m_fck)) {
938 dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
939 clk_put(dispc.dss_ick);
940 clk_put(dispc.dss1_fck);
941 return PTR_ERR(dispc.dss_54m_fck);
942 }
943
944 return 0;
945 }
946
947 static void put_dss_clocks(void)
948 {
949 clk_put(dispc.dss_54m_fck);
950 clk_put(dispc.dss1_fck);
951 clk_put(dispc.dss_ick);
952 }
953
954 static void enable_lcd_clocks(int enable)
955 {
956 if (enable) {
957 clk_enable(dispc.dss_ick);
958 clk_enable(dispc.dss1_fck);
959 } else {
960 clk_disable(dispc.dss1_fck);
961 clk_disable(dispc.dss_ick);
962 }
963 }
964
965 static void enable_digit_clocks(int enable)
966 {
967 if (enable)
968 clk_enable(dispc.dss_54m_fck);
969 else
970 clk_disable(dispc.dss_54m_fck);
971 }
972
973 static void omap_dispc_suspend(void)
974 {
975 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
976 init_completion(&dispc.frame_done);
977 omap_dispc_enable_lcd_out(0);
978 if (!wait_for_completion_timeout(&dispc.frame_done,
979 msecs_to_jiffies(500))) {
980 dev_err(dispc.fbdev->dev,
981 "timeout waiting for FRAME DONE\n");
982 }
983 enable_lcd_clocks(0);
984 }
985 }
986
987 static void omap_dispc_resume(void)
988 {
989 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
990 enable_lcd_clocks(1);
991 if (!dispc.ext_mode) {
992 set_lcd_timings();
993 load_palette();
994 }
995 omap_dispc_enable_lcd_out(1);
996 }
997 }
998
999
1000 static int omap_dispc_update_window(struct fb_info *fbi,
1001 struct omapfb_update_window *win,
1002 void (*complete_callback)(void *arg),
1003 void *complete_callback_data)
1004 {
1005 return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0;
1006 }
1007
1008 static int mmap_kern(struct omapfb_mem_region *region)
1009 {
1010 struct vm_struct *kvma;
1011 struct vm_area_struct vma;
1012 pgprot_t pgprot;
1013 unsigned long vaddr;
1014
1015 kvma = get_vm_area(region->size, VM_IOREMAP);
1016 if (kvma == NULL) {
1017 dev_err(dispc.fbdev->dev, "can't get kernel vm area\n");
1018 return -ENOMEM;
1019 }
1020 vma.vm_mm = &init_mm;
1021
1022 vaddr = (unsigned long)kvma->addr;
1023
1024 pgprot = pgprot_writecombine(pgprot_kernel);
1025 vma.vm_start = vaddr;
1026 vma.vm_end = vaddr + region->size;
1027 if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT,
1028 region->size, pgprot) < 0) {
1029 dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n");
1030 return -EAGAIN;
1031 }
1032 region->vaddr = (void *)vaddr;
1033
1034 return 0;
1035 }
1036
1037 static void mmap_user_open(struct vm_area_struct *vma)
1038 {
1039 int plane = (int)vma->vm_private_data;
1040
1041 atomic_inc(&dispc.map_count[plane]);
1042 }
1043
1044 static void mmap_user_close(struct vm_area_struct *vma)
1045 {
1046 int plane = (int)vma->vm_private_data;
1047
1048 atomic_dec(&dispc.map_count[plane]);
1049 }
1050
1051 static const struct vm_operations_struct mmap_user_ops = {
1052 .open = mmap_user_open,
1053 .close = mmap_user_close,
1054 };
1055
1056 static int omap_dispc_mmap_user(struct fb_info *info,
1057 struct vm_area_struct *vma)
1058 {
1059 struct omapfb_plane_struct *plane = info->par;
1060 unsigned long off;
1061 unsigned long start;
1062 u32 len;
1063
1064 if (vma->vm_end - vma->vm_start == 0)
1065 return 0;
1066 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1067 return -EINVAL;
1068 off = vma->vm_pgoff << PAGE_SHIFT;
1069
1070 start = info->fix.smem_start;
1071 len = info->fix.smem_len;
1072 if (off >= len)
1073 return -EINVAL;
1074 if ((vma->vm_end - vma->vm_start + off) > len)
1075 return -EINVAL;
1076 off += start;
1077 vma->vm_pgoff = off >> PAGE_SHIFT;
1078 vma->vm_flags |= VM_IO | VM_RESERVED;
1079 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1080 vma->vm_ops = &mmap_user_ops;
1081 vma->vm_private_data = (void *)plane->idx;
1082 if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1083 vma->vm_end - vma->vm_start, vma->vm_page_prot))
1084 return -EAGAIN;
1085 /* vm_ops.open won't be called for mmap itself. */
1086 atomic_inc(&dispc.map_count[plane->idx]);
1087 return 0;
1088 }
1089
1090 static void unmap_kern(struct omapfb_mem_region *region)
1091 {
1092 vunmap(region->vaddr);
1093 }
1094
1095 static int alloc_palette_ram(void)
1096 {
1097 dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1098 MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL);
1099 if (dispc.palette_vaddr == NULL) {
1100 dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n");
1101 return -ENOMEM;
1102 }
1103
1104 return 0;
1105 }
1106
1107 static void free_palette_ram(void)
1108 {
1109 dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE,
1110 dispc.palette_vaddr, dispc.palette_paddr);
1111 }
1112
1113 static int alloc_fbmem(struct omapfb_mem_region *region)
1114 {
1115 region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1116 region->size, &region->paddr, GFP_KERNEL);
1117
1118 if (region->vaddr == NULL) {
1119 dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n");
1120 return -ENOMEM;
1121 }
1122
1123 return 0;
1124 }
1125
1126 static void free_fbmem(struct omapfb_mem_region *region)
1127 {
1128 dma_free_writecombine(dispc.fbdev->dev, region->size,
1129 region->vaddr, region->paddr);
1130 }
1131
1132 static struct resmap *init_resmap(unsigned long start, size_t size)
1133 {
1134 unsigned page_cnt;
1135 struct resmap *res_map;
1136
1137 page_cnt = PAGE_ALIGN(size) / PAGE_SIZE;
1138 res_map =
1139 kzalloc(sizeof(struct resmap) + RESMAP_SIZE(page_cnt), GFP_KERNEL);
1140 if (res_map == NULL)
1141 return NULL;
1142 res_map->start = start;
1143 res_map->page_cnt = page_cnt;
1144 res_map->map = (unsigned long *)(res_map + 1);
1145 return res_map;
1146 }
1147
1148 static void cleanup_resmap(struct resmap *res_map)
1149 {
1150 kfree(res_map);
1151 }
1152
1153 static inline int resmap_mem_type(unsigned long start)
1154 {
1155 if (start >= OMAP2_SRAM_START &&
1156 start < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
1157 return OMAPFB_MEMTYPE_SRAM;
1158 else
1159 return OMAPFB_MEMTYPE_SDRAM;
1160 }
1161
1162 static inline int resmap_page_reserved(struct resmap *res_map, unsigned page_nr)
1163 {
1164 return *RESMAP_PTR(res_map, page_nr) & RESMAP_MASK(page_nr) ? 1 : 0;
1165 }
1166
1167 static inline void resmap_reserve_page(struct resmap *res_map, unsigned page_nr)
1168 {
1169 BUG_ON(resmap_page_reserved(res_map, page_nr));
1170 *RESMAP_PTR(res_map, page_nr) |= RESMAP_MASK(page_nr);
1171 }
1172
1173 static inline void resmap_free_page(struct resmap *res_map, unsigned page_nr)
1174 {
1175 BUG_ON(!resmap_page_reserved(res_map, page_nr));
1176 *RESMAP_PTR(res_map, page_nr) &= ~RESMAP_MASK(page_nr);
1177 }
1178
1179 static void resmap_reserve_region(unsigned long start, size_t size)
1180 {
1181
1182 struct resmap *res_map;
1183 unsigned start_page;
1184 unsigned end_page;
1185 int mtype;
1186 unsigned i;
1187
1188 mtype = resmap_mem_type(start);
1189 res_map = dispc.res_map[mtype];
1190 dev_dbg(dispc.fbdev->dev, "reserve mem type %d start %08lx size %d\n",
1191 mtype, start, size);
1192 start_page = (start - res_map->start) / PAGE_SIZE;
1193 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1194 for (i = start_page; i < end_page; i++)
1195 resmap_reserve_page(res_map, i);
1196 }
1197
1198 static void resmap_free_region(unsigned long start, size_t size)
1199 {
1200 struct resmap *res_map;
1201 unsigned start_page;
1202 unsigned end_page;
1203 unsigned i;
1204 int mtype;
1205
1206 mtype = resmap_mem_type(start);
1207 res_map = dispc.res_map[mtype];
1208 dev_dbg(dispc.fbdev->dev, "free mem type %d start %08lx size %d\n",
1209 mtype, start, size);
1210 start_page = (start - res_map->start) / PAGE_SIZE;
1211 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1212 for (i = start_page; i < end_page; i++)
1213 resmap_free_page(res_map, i);
1214 }
1215
1216 static unsigned long resmap_alloc_region(int mtype, size_t size)
1217 {
1218 unsigned i;
1219 unsigned total;
1220 unsigned start_page;
1221 unsigned long start;
1222 struct resmap *res_map = dispc.res_map[mtype];
1223
1224 BUG_ON(mtype >= DISPC_MEMTYPE_NUM || res_map == NULL || !size);
1225
1226 size = PAGE_ALIGN(size) / PAGE_SIZE;
1227 start_page = 0;
1228 total = 0;
1229 for (i = 0; i < res_map->page_cnt; i++) {
1230 if (resmap_page_reserved(res_map, i)) {
1231 start_page = i + 1;
1232 total = 0;
1233 } else if (++total == size)
1234 break;
1235 }
1236 if (total < size)
1237 return 0;
1238
1239 start = res_map->start + start_page * PAGE_SIZE;
1240 resmap_reserve_region(start, size * PAGE_SIZE);
1241
1242 return start;
1243 }
1244
1245 /* Note that this will only work for user mappings, we don't deal with
1246 * kernel mappings here, so fbcon will keep using the old region.
1247 */
1248 static int omap_dispc_setup_mem(int plane, size_t size, int mem_type,
1249 unsigned long *paddr)
1250 {
1251 struct omapfb_mem_region *rg;
1252 unsigned long new_addr = 0;
1253
1254 if ((unsigned)plane > dispc.mem_desc.region_cnt)
1255 return -EINVAL;
1256 if (mem_type >= DISPC_MEMTYPE_NUM)
1257 return -EINVAL;
1258 if (dispc.res_map[mem_type] == NULL)
1259 return -ENOMEM;
1260 rg = &dispc.mem_desc.region[plane];
1261 if (size == rg->size && mem_type == rg->type)
1262 return 0;
1263 if (atomic_read(&dispc.map_count[plane]))
1264 return -EBUSY;
1265 if (rg->size != 0)
1266 resmap_free_region(rg->paddr, rg->size);
1267 if (size != 0) {
1268 new_addr = resmap_alloc_region(mem_type, size);
1269 if (!new_addr) {
1270 /* Reallocate old region. */
1271 resmap_reserve_region(rg->paddr, rg->size);
1272 return -ENOMEM;
1273 }
1274 }
1275 rg->paddr = new_addr;
1276 rg->size = size;
1277 rg->type = mem_type;
1278
1279 *paddr = new_addr;
1280
1281 return 0;
1282 }
1283
1284 static int setup_fbmem(struct omapfb_mem_desc *req_md)
1285 {
1286 struct omapfb_mem_region *rg;
1287 int i;
1288 int r;
1289 unsigned long mem_start[DISPC_MEMTYPE_NUM];
1290 unsigned long mem_end[DISPC_MEMTYPE_NUM];
1291
1292 if (!req_md->region_cnt) {
1293 dev_err(dispc.fbdev->dev, "no memory regions defined\n");
1294 return -ENOENT;
1295 }
1296
1297 rg = &req_md->region[0];
1298 memset(mem_start, 0xff, sizeof(mem_start));
1299 memset(mem_end, 0, sizeof(mem_end));
1300
1301 for (i = 0; i < req_md->region_cnt; i++, rg++) {
1302 int mtype;
1303 if (rg->paddr) {
1304 rg->alloc = 0;
1305 if (rg->vaddr == NULL) {
1306 rg->map = 1;
1307 if ((r = mmap_kern(rg)) < 0)
1308 return r;
1309 }
1310 } else {
1311 if (rg->type != OMAPFB_MEMTYPE_SDRAM) {
1312 dev_err(dispc.fbdev->dev,
1313 "unsupported memory type\n");
1314 return -EINVAL;
1315 }
1316 rg->alloc = rg->map = 1;
1317 if ((r = alloc_fbmem(rg)) < 0)
1318 return r;
1319 }
1320 mtype = rg->type;
1321
1322 if (rg->paddr < mem_start[mtype])
1323 mem_start[mtype] = rg->paddr;
1324 if (rg->paddr + rg->size > mem_end[mtype])
1325 mem_end[mtype] = rg->paddr + rg->size;
1326 }
1327
1328 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1329 unsigned long start;
1330 size_t size;
1331 if (mem_end[i] == 0)
1332 continue;
1333 start = mem_start[i];
1334 size = mem_end[i] - start;
1335 dispc.res_map[i] = init_resmap(start, size);
1336 r = -ENOMEM;
1337 if (dispc.res_map[i] == NULL)
1338 goto fail;
1339 /* Initial state is that everything is reserved. This
1340 * includes possible holes as well, which will never be
1341 * freed.
1342 */
1343 resmap_reserve_region(start, size);
1344 }
1345
1346 dispc.mem_desc = *req_md;
1347
1348 return 0;
1349 fail:
1350 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1351 if (dispc.res_map[i] != NULL)
1352 cleanup_resmap(dispc.res_map[i]);
1353 }
1354 return r;
1355 }
1356
1357 static void cleanup_fbmem(void)
1358 {
1359 struct omapfb_mem_region *rg;
1360 int i;
1361
1362 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1363 if (dispc.res_map[i] != NULL)
1364 cleanup_resmap(dispc.res_map[i]);
1365 }
1366 rg = &dispc.mem_desc.region[0];
1367 for (i = 0; i < dispc.mem_desc.region_cnt; i++, rg++) {
1368 if (rg->alloc)
1369 free_fbmem(rg);
1370 else {
1371 if (rg->map)
1372 unmap_kern(rg);
1373 }
1374 }
1375 }
1376
1377 static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1378 struct omapfb_mem_desc *req_vram)
1379 {
1380 int r;
1381 u32 l;
1382 struct lcd_panel *panel = fbdev->panel;
1383 void __iomem *ram_fw_base;
1384 int tmo = 10000;
1385 int skip_init = 0;
1386 int i;
1387
1388 r = platform_device_register(&omapdss_device);
1389 if (r) {
1390 dev_err(fbdev->dev, "can't register omapdss device\n");
1391 return r;
1392 }
1393
1394 memset(&dispc, 0, sizeof(dispc));
1395
1396 dispc.base = ioremap(DISPC_BASE, SZ_1K);
1397 if (!dispc.base) {
1398 dev_err(fbdev->dev, "can't ioremap DISPC\n");
1399 return -ENOMEM;
1400 }
1401
1402 dispc.fbdev = fbdev;
1403 dispc.ext_mode = ext_mode;
1404
1405 init_completion(&dispc.frame_done);
1406
1407 if ((r = get_dss_clocks()) < 0)
1408 goto fail0;
1409
1410 enable_lcd_clocks(1);
1411
1412 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
1413 l = dispc_read_reg(DISPC_CONTROL);
1414 /* LCD enabled ? */
1415 if (l & 1) {
1416 pr_info("omapfb: skipping hardware initialization\n");
1417 skip_init = 1;
1418 }
1419 #endif
1420
1421 if (!skip_init) {
1422 /* Reset monitoring works only w/ the 54M clk */
1423 enable_digit_clocks(1);
1424
1425 /* Soft reset */
1426 MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);
1427
1428 while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) {
1429 if (!--tmo) {
1430 dev_err(dispc.fbdev->dev, "soft reset failed\n");
1431 r = -ENODEV;
1432 enable_digit_clocks(0);
1433 goto fail1;
1434 }
1435 }
1436
1437 enable_digit_clocks(0);
1438 }
1439
1440 /* Enable smart standby/idle, autoidle and wakeup */
1441 l = dispc_read_reg(DISPC_SYSCONFIG);
1442 l &= ~((3 << 12) | (3 << 3));
1443 l |= (2 << 12) | (2 << 3) | (1 << 2) | (1 << 0);
1444 dispc_write_reg(DISPC_SYSCONFIG, l);
1445 omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
1446
1447 /* Set functional clock autogating */
1448 l = dispc_read_reg(DISPC_CONFIG);
1449 l |= 1 << 9;
1450 dispc_write_reg(DISPC_CONFIG, l);
1451
1452 l = dispc_read_reg(DISPC_IRQSTATUS);
1453 dispc_write_reg(DISPC_IRQSTATUS, l);
1454
1455 recalc_irq_mask();
1456
1457 if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
1458 0, MODULE_NAME, fbdev)) < 0) {
1459 dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n");
1460 goto fail1;
1461 }
1462
1463 /* L3 firewall setting: enable access to OCM RAM */
1464 ram_fw_base = ioremap(0x68005000, SZ_1K);
1465 if (!ram_fw_base) {
1466 dev_err(dispc.fbdev->dev, "Cannot ioremap to enable OCM RAM\n");
1467 goto fail1;
1468 }
1469 __raw_writel(0x402000b0, ram_fw_base + 0xa0);
1470 iounmap(ram_fw_base);
1471
1472 if ((r = alloc_palette_ram()) < 0)
1473 goto fail2;
1474
1475 if ((r = setup_fbmem(req_vram)) < 0)
1476 goto fail3;
1477
1478 if (!skip_init) {
1479 for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1480 memset(dispc.mem_desc.region[i].vaddr, 0,
1481 dispc.mem_desc.region[i].size);
1482 }
1483
1484 /* Set logic clock to fck, pixel clock to fck/2 for now */
1485 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);
1486 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);
1487
1488 setup_plane_fifo(0, ext_mode);
1489 setup_plane_fifo(1, ext_mode);
1490 setup_plane_fifo(2, ext_mode);
1491
1492 setup_color_conv_coef();
1493
1494 set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT);
1495 set_load_mode(DISPC_LOAD_FRAME_ONLY);
1496
1497 if (!ext_mode) {
1498 set_lcd_data_lines(panel->data_lines);
1499 omap_dispc_set_lcd_size(panel->x_res, panel->y_res);
1500 set_lcd_timings();
1501 } else
1502 set_lcd_data_lines(panel->bpp);
1503 enable_rfbi_mode(ext_mode);
1504 }
1505
1506 l = dispc_read_reg(DISPC_REVISION);
1507 pr_info("omapfb: DISPC version %d.%d initialized\n",
1508 l >> 4 & 0x0f, l & 0x0f);
1509 enable_lcd_clocks(0);
1510
1511 return 0;
1512 fail3:
1513 free_palette_ram();
1514 fail2:
1515 free_irq(INT_24XX_DSS_IRQ, fbdev);
1516 fail1:
1517 enable_lcd_clocks(0);
1518 put_dss_clocks();
1519 fail0:
1520 iounmap(dispc.base);
1521 return r;
1522 }
1523
1524 static void omap_dispc_cleanup(void)
1525 {
1526 int i;
1527
1528 omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED);
1529 /* This will also disable clocks that are on */
1530 for (i = 0; i < dispc.mem_desc.region_cnt; i++)
1531 omap_dispc_enable_plane(i, 0);
1532 cleanup_fbmem();
1533 free_palette_ram();
1534 free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1535 put_dss_clocks();
1536 iounmap(dispc.base);
1537 platform_device_unregister(&omapdss_device);
1538 }
1539
1540 const struct lcd_ctrl omap2_int_ctrl = {
1541 .name = "internal",
1542 .init = omap_dispc_init,
1543 .cleanup = omap_dispc_cleanup,
1544 .get_caps = omap_dispc_get_caps,
1545 .set_update_mode = omap_dispc_set_update_mode,
1546 .get_update_mode = omap_dispc_get_update_mode,
1547 .update_window = omap_dispc_update_window,
1548 .suspend = omap_dispc_suspend,
1549 .resume = omap_dispc_resume,
1550 .setup_plane = omap_dispc_setup_plane,
1551 .setup_mem = omap_dispc_setup_mem,
1552 .set_scale = omap_dispc_set_scale,
1553 .enable_plane = omap_dispc_enable_plane,
1554 .set_color_key = omap_dispc_set_color_key,
1555 .get_color_key = omap_dispc_get_color_key,
1556 .mmap = omap_dispc_mmap_user,
1557 };
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