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[mirror_ubuntu-eoan-kernel.git] / drivers / video / omap2 / dss / dispc.c
1 /*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
39
40 #include <plat/sram.h>
41 #include <plat/clock.h>
42
43 #include <video/omapdss.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47 #include "dispc.h"
48
49 /* DISPC */
50 #define DISPC_SZ_REGS SZ_4K
51
52 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
53 DISPC_IRQ_OCP_ERR | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
58
59 #define DISPC_MAX_NR_ISRS 8
60
61 struct omap_dispc_isr_data {
62 omap_dispc_isr_t isr;
63 void *arg;
64 u32 mask;
65 };
66
67 struct dispc_h_coef {
68 s8 hc4;
69 s8 hc3;
70 u8 hc2;
71 s8 hc1;
72 s8 hc0;
73 };
74
75 struct dispc_v_coef {
76 s8 vc22;
77 s8 vc2;
78 u8 vc1;
79 s8 vc0;
80 s8 vc00;
81 };
82
83 enum omap_burst_size {
84 BURST_SIZE_X2 = 0,
85 BURST_SIZE_X4 = 1,
86 BURST_SIZE_X8 = 2,
87 };
88
89 #define REG_GET(idx, start, end) \
90 FLD_GET(dispc_read_reg(idx), start, end)
91
92 #define REG_FLD_MOD(idx, val, start, end) \
93 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
94
95 struct dispc_irq_stats {
96 unsigned long last_reset;
97 unsigned irq_count;
98 unsigned irqs[32];
99 };
100
101 static struct {
102 struct platform_device *pdev;
103 void __iomem *base;
104
105 int ctx_loss_cnt;
106
107 int irq;
108 struct clk *dss_clk;
109
110 u32 fifo_size[MAX_DSS_OVERLAYS];
111
112 spinlock_t irq_lock;
113 u32 irq_error_mask;
114 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
115 u32 error_irqs;
116 struct work_struct error_work;
117
118 bool ctx_valid;
119 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
120
121 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
122 spinlock_t irq_stats_lock;
123 struct dispc_irq_stats irq_stats;
124 #endif
125 } dispc;
126
127 enum omap_color_component {
128 /* used for all color formats for OMAP3 and earlier
129 * and for RGB and Y color component on OMAP4
130 */
131 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
132 /* used for UV component for
133 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
134 * color formats on OMAP4
135 */
136 DISPC_COLOR_COMPONENT_UV = 1 << 1,
137 };
138
139 static void _omap_dispc_set_irqs(void);
140
141 static inline void dispc_write_reg(const u16 idx, u32 val)
142 {
143 __raw_writel(val, dispc.base + idx);
144 }
145
146 static inline u32 dispc_read_reg(const u16 idx)
147 {
148 return __raw_readl(dispc.base + idx);
149 }
150
151 static int dispc_get_ctx_loss_count(void)
152 {
153 struct device *dev = &dispc.pdev->dev;
154 struct omap_display_platform_data *pdata = dev->platform_data;
155 struct omap_dss_board_info *board_data = pdata->board_data;
156 int cnt;
157
158 if (!board_data->get_context_loss_count)
159 return -ENOENT;
160
161 cnt = board_data->get_context_loss_count(dev);
162
163 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
164
165 return cnt;
166 }
167
168 #define SR(reg) \
169 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
170 #define RR(reg) \
171 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
172
173 static void dispc_save_context(void)
174 {
175 int i, j;
176
177 DSSDBG("dispc_save_context\n");
178
179 SR(IRQENABLE);
180 SR(CONTROL);
181 SR(CONFIG);
182 SR(LINE_NUMBER);
183 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
184 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
185 SR(GLOBAL_ALPHA);
186 if (dss_has_feature(FEAT_MGR_LCD2)) {
187 SR(CONTROL2);
188 SR(CONFIG2);
189 }
190
191 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
192 SR(DEFAULT_COLOR(i));
193 SR(TRANS_COLOR(i));
194 SR(SIZE_MGR(i));
195 if (i == OMAP_DSS_CHANNEL_DIGIT)
196 continue;
197 SR(TIMING_H(i));
198 SR(TIMING_V(i));
199 SR(POL_FREQ(i));
200 SR(DIVISORo(i));
201
202 SR(DATA_CYCLE1(i));
203 SR(DATA_CYCLE2(i));
204 SR(DATA_CYCLE3(i));
205
206 if (dss_has_feature(FEAT_CPR)) {
207 SR(CPR_COEF_R(i));
208 SR(CPR_COEF_G(i));
209 SR(CPR_COEF_B(i));
210 }
211 }
212
213 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
214 SR(OVL_BA0(i));
215 SR(OVL_BA1(i));
216 SR(OVL_POSITION(i));
217 SR(OVL_SIZE(i));
218 SR(OVL_ATTRIBUTES(i));
219 SR(OVL_FIFO_THRESHOLD(i));
220 SR(OVL_ROW_INC(i));
221 SR(OVL_PIXEL_INC(i));
222 if (dss_has_feature(FEAT_PRELOAD))
223 SR(OVL_PRELOAD(i));
224 if (i == OMAP_DSS_GFX) {
225 SR(OVL_WINDOW_SKIP(i));
226 SR(OVL_TABLE_BA(i));
227 continue;
228 }
229 SR(OVL_FIR(i));
230 SR(OVL_PICTURE_SIZE(i));
231 SR(OVL_ACCU0(i));
232 SR(OVL_ACCU1(i));
233
234 for (j = 0; j < 8; j++)
235 SR(OVL_FIR_COEF_H(i, j));
236
237 for (j = 0; j < 8; j++)
238 SR(OVL_FIR_COEF_HV(i, j));
239
240 for (j = 0; j < 5; j++)
241 SR(OVL_CONV_COEF(i, j));
242
243 if (dss_has_feature(FEAT_FIR_COEF_V)) {
244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V(i, j));
246 }
247
248 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
249 SR(OVL_BA0_UV(i));
250 SR(OVL_BA1_UV(i));
251 SR(OVL_FIR2(i));
252 SR(OVL_ACCU2_0(i));
253 SR(OVL_ACCU2_1(i));
254
255 for (j = 0; j < 8; j++)
256 SR(OVL_FIR_COEF_H2(i, j));
257
258 for (j = 0; j < 8; j++)
259 SR(OVL_FIR_COEF_HV2(i, j));
260
261 for (j = 0; j < 8; j++)
262 SR(OVL_FIR_COEF_V2(i, j));
263 }
264 if (dss_has_feature(FEAT_ATTR2))
265 SR(OVL_ATTRIBUTES2(i));
266 }
267
268 if (dss_has_feature(FEAT_CORE_CLK_DIV))
269 SR(DIVISOR);
270
271 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
272 dispc.ctx_valid = true;
273
274 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
275 }
276
277 static void dispc_restore_context(void)
278 {
279 int i, j, ctx;
280
281 DSSDBG("dispc_restore_context\n");
282
283 if (!dispc.ctx_valid)
284 return;
285
286 ctx = dispc_get_ctx_loss_count();
287
288 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
289 return;
290
291 DSSDBG("ctx_loss_count: saved %d, current %d\n",
292 dispc.ctx_loss_cnt, ctx);
293
294 /*RR(IRQENABLE);*/
295 /*RR(CONTROL);*/
296 RR(CONFIG);
297 RR(LINE_NUMBER);
298 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
299 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
300 RR(GLOBAL_ALPHA);
301 if (dss_has_feature(FEAT_MGR_LCD2))
302 RR(CONFIG2);
303
304 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
305 RR(DEFAULT_COLOR(i));
306 RR(TRANS_COLOR(i));
307 RR(SIZE_MGR(i));
308 if (i == OMAP_DSS_CHANNEL_DIGIT)
309 continue;
310 RR(TIMING_H(i));
311 RR(TIMING_V(i));
312 RR(POL_FREQ(i));
313 RR(DIVISORo(i));
314
315 RR(DATA_CYCLE1(i));
316 RR(DATA_CYCLE2(i));
317 RR(DATA_CYCLE3(i));
318
319 if (dss_has_feature(FEAT_CPR)) {
320 RR(CPR_COEF_R(i));
321 RR(CPR_COEF_G(i));
322 RR(CPR_COEF_B(i));
323 }
324 }
325
326 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
327 RR(OVL_BA0(i));
328 RR(OVL_BA1(i));
329 RR(OVL_POSITION(i));
330 RR(OVL_SIZE(i));
331 RR(OVL_ATTRIBUTES(i));
332 RR(OVL_FIFO_THRESHOLD(i));
333 RR(OVL_ROW_INC(i));
334 RR(OVL_PIXEL_INC(i));
335 if (dss_has_feature(FEAT_PRELOAD))
336 RR(OVL_PRELOAD(i));
337 if (i == OMAP_DSS_GFX) {
338 RR(OVL_WINDOW_SKIP(i));
339 RR(OVL_TABLE_BA(i));
340 continue;
341 }
342 RR(OVL_FIR(i));
343 RR(OVL_PICTURE_SIZE(i));
344 RR(OVL_ACCU0(i));
345 RR(OVL_ACCU1(i));
346
347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_H(i, j));
349
350 for (j = 0; j < 8; j++)
351 RR(OVL_FIR_COEF_HV(i, j));
352
353 for (j = 0; j < 5; j++)
354 RR(OVL_CONV_COEF(i, j));
355
356 if (dss_has_feature(FEAT_FIR_COEF_V)) {
357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V(i, j));
359 }
360
361 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
362 RR(OVL_BA0_UV(i));
363 RR(OVL_BA1_UV(i));
364 RR(OVL_FIR2(i));
365 RR(OVL_ACCU2_0(i));
366 RR(OVL_ACCU2_1(i));
367
368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_H2(i, j));
370
371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_HV2(i, j));
373
374 for (j = 0; j < 8; j++)
375 RR(OVL_FIR_COEF_V2(i, j));
376 }
377 if (dss_has_feature(FEAT_ATTR2))
378 RR(OVL_ATTRIBUTES2(i));
379 }
380
381 if (dss_has_feature(FEAT_CORE_CLK_DIV))
382 RR(DIVISOR);
383
384 /* enable last, because LCD & DIGIT enable are here */
385 RR(CONTROL);
386 if (dss_has_feature(FEAT_MGR_LCD2))
387 RR(CONTROL2);
388 /* clear spurious SYNC_LOST_DIGIT interrupts */
389 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
390
391 /*
392 * enable last so IRQs won't trigger before
393 * the context is fully restored
394 */
395 RR(IRQENABLE);
396
397 DSSDBG("context restored\n");
398 }
399
400 #undef SR
401 #undef RR
402
403 int dispc_runtime_get(void)
404 {
405 int r;
406
407 DSSDBG("dispc_runtime_get\n");
408
409 r = pm_runtime_get_sync(&dispc.pdev->dev);
410 WARN_ON(r < 0);
411 return r < 0 ? r : 0;
412 }
413
414 void dispc_runtime_put(void)
415 {
416 int r;
417
418 DSSDBG("dispc_runtime_put\n");
419
420 r = pm_runtime_put(&dispc.pdev->dev);
421 WARN_ON(r < 0);
422 }
423
424 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
425 {
426 if (channel == OMAP_DSS_CHANNEL_LCD ||
427 channel == OMAP_DSS_CHANNEL_LCD2)
428 return true;
429 else
430 return false;
431 }
432
433 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
434 {
435 struct omap_overlay_manager *mgr =
436 omap_dss_get_overlay_manager(channel);
437
438 return mgr ? mgr->device : NULL;
439 }
440
441 bool dispc_mgr_go_busy(enum omap_channel channel)
442 {
443 int bit;
444
445 if (dispc_mgr_is_lcd(channel))
446 bit = 5; /* GOLCD */
447 else
448 bit = 6; /* GODIGIT */
449
450 if (channel == OMAP_DSS_CHANNEL_LCD2)
451 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
452 else
453 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
454 }
455
456 void dispc_mgr_go(enum omap_channel channel)
457 {
458 int bit;
459 bool enable_bit, go_bit;
460
461 if (dispc_mgr_is_lcd(channel))
462 bit = 0; /* LCDENABLE */
463 else
464 bit = 1; /* DIGITALENABLE */
465
466 /* if the channel is not enabled, we don't need GO */
467 if (channel == OMAP_DSS_CHANNEL_LCD2)
468 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
469 else
470 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
471
472 if (!enable_bit)
473 return;
474
475 if (dispc_mgr_is_lcd(channel))
476 bit = 5; /* GOLCD */
477 else
478 bit = 6; /* GODIGIT */
479
480 if (channel == OMAP_DSS_CHANNEL_LCD2)
481 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
482 else
483 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
484
485 if (go_bit) {
486 DSSERR("GO bit not down for channel %d\n", channel);
487 return;
488 }
489
490 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
491 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
492
493 if (channel == OMAP_DSS_CHANNEL_LCD2)
494 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
495 else
496 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
497 }
498
499 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
500 {
501 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
502 }
503
504 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
505 {
506 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
507 }
508
509 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
510 {
511 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
512 }
513
514 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
515 {
516 BUG_ON(plane == OMAP_DSS_GFX);
517
518 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
519 }
520
521 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
522 u32 value)
523 {
524 BUG_ON(plane == OMAP_DSS_GFX);
525
526 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
527 }
528
529 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
530 {
531 BUG_ON(plane == OMAP_DSS_GFX);
532
533 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
534 }
535
536 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
537 int vscaleup, int five_taps,
538 enum omap_color_component color_comp)
539 {
540 /* Coefficients for horizontal up-sampling */
541 static const struct dispc_h_coef coef_hup[8] = {
542 { 0, 0, 128, 0, 0 },
543 { -1, 13, 124, -8, 0 },
544 { -2, 30, 112, -11, -1 },
545 { -5, 51, 95, -11, -2 },
546 { 0, -9, 73, 73, -9 },
547 { -2, -11, 95, 51, -5 },
548 { -1, -11, 112, 30, -2 },
549 { 0, -8, 124, 13, -1 },
550 };
551
552 /* Coefficients for vertical up-sampling */
553 static const struct dispc_v_coef coef_vup_3tap[8] = {
554 { 0, 0, 128, 0, 0 },
555 { 0, 3, 123, 2, 0 },
556 { 0, 12, 111, 5, 0 },
557 { 0, 32, 89, 7, 0 },
558 { 0, 0, 64, 64, 0 },
559 { 0, 7, 89, 32, 0 },
560 { 0, 5, 111, 12, 0 },
561 { 0, 2, 123, 3, 0 },
562 };
563
564 static const struct dispc_v_coef coef_vup_5tap[8] = {
565 { 0, 0, 128, 0, 0 },
566 { -1, 13, 124, -8, 0 },
567 { -2, 30, 112, -11, -1 },
568 { -5, 51, 95, -11, -2 },
569 { 0, -9, 73, 73, -9 },
570 { -2, -11, 95, 51, -5 },
571 { -1, -11, 112, 30, -2 },
572 { 0, -8, 124, 13, -1 },
573 };
574
575 /* Coefficients for horizontal down-sampling */
576 static const struct dispc_h_coef coef_hdown[8] = {
577 { 0, 36, 56, 36, 0 },
578 { 4, 40, 55, 31, -2 },
579 { 8, 44, 54, 27, -5 },
580 { 12, 48, 53, 22, -7 },
581 { -9, 17, 52, 51, 17 },
582 { -7, 22, 53, 48, 12 },
583 { -5, 27, 54, 44, 8 },
584 { -2, 31, 55, 40, 4 },
585 };
586
587 /* Coefficients for vertical down-sampling */
588 static const struct dispc_v_coef coef_vdown_3tap[8] = {
589 { 0, 36, 56, 36, 0 },
590 { 0, 40, 57, 31, 0 },
591 { 0, 45, 56, 27, 0 },
592 { 0, 50, 55, 23, 0 },
593 { 0, 18, 55, 55, 0 },
594 { 0, 23, 55, 50, 0 },
595 { 0, 27, 56, 45, 0 },
596 { 0, 31, 57, 40, 0 },
597 };
598
599 static const struct dispc_v_coef coef_vdown_5tap[8] = {
600 { 0, 36, 56, 36, 0 },
601 { 4, 40, 55, 31, -2 },
602 { 8, 44, 54, 27, -5 },
603 { 12, 48, 53, 22, -7 },
604 { -9, 17, 52, 51, 17 },
605 { -7, 22, 53, 48, 12 },
606 { -5, 27, 54, 44, 8 },
607 { -2, 31, 55, 40, 4 },
608 };
609
610 const struct dispc_h_coef *h_coef;
611 const struct dispc_v_coef *v_coef;
612 int i;
613
614 if (hscaleup)
615 h_coef = coef_hup;
616 else
617 h_coef = coef_hdown;
618
619 if (vscaleup)
620 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
621 else
622 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
623
624 for (i = 0; i < 8; i++) {
625 u32 h, hv;
626
627 h = FLD_VAL(h_coef[i].hc0, 7, 0)
628 | FLD_VAL(h_coef[i].hc1, 15, 8)
629 | FLD_VAL(h_coef[i].hc2, 23, 16)
630 | FLD_VAL(h_coef[i].hc3, 31, 24);
631 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
632 | FLD_VAL(v_coef[i].vc0, 15, 8)
633 | FLD_VAL(v_coef[i].vc1, 23, 16)
634 | FLD_VAL(v_coef[i].vc2, 31, 24);
635
636 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
637 dispc_ovl_write_firh_reg(plane, i, h);
638 dispc_ovl_write_firhv_reg(plane, i, hv);
639 } else {
640 dispc_ovl_write_firh2_reg(plane, i, h);
641 dispc_ovl_write_firhv2_reg(plane, i, hv);
642 }
643
644 }
645
646 if (five_taps) {
647 for (i = 0; i < 8; i++) {
648 u32 v;
649 v = FLD_VAL(v_coef[i].vc00, 7, 0)
650 | FLD_VAL(v_coef[i].vc22, 15, 8);
651 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
652 dispc_ovl_write_firv_reg(plane, i, v);
653 else
654 dispc_ovl_write_firv2_reg(plane, i, v);
655 }
656 }
657 }
658
659 static void _dispc_setup_color_conv_coef(void)
660 {
661 int i;
662 const struct color_conv_coef {
663 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
664 int full_range;
665 } ctbl_bt601_5 = {
666 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
667 };
668
669 const struct color_conv_coef *ct;
670
671 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
672
673 ct = &ctbl_bt601_5;
674
675 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
676 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
677 CVAL(ct->rcr, ct->ry));
678 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
679 CVAL(ct->gy, ct->rcb));
680 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
681 CVAL(ct->gcb, ct->gcr));
682 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
683 CVAL(ct->bcr, ct->by));
684 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
685 CVAL(0, ct->bcb));
686
687 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
688 11, 11);
689 }
690
691 #undef CVAL
692 }
693
694
695 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
696 {
697 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
698 }
699
700 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
701 {
702 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
703 }
704
705 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
706 {
707 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
708 }
709
710 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
711 {
712 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
713 }
714
715 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
716 {
717 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
718
719 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
720 }
721
722 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
723 {
724 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
725
726 if (plane == OMAP_DSS_GFX)
727 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
728 else
729 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
730 }
731
732 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
733 {
734 u32 val;
735
736 BUG_ON(plane == OMAP_DSS_GFX);
737
738 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
739
740 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
741 }
742
743 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
744 {
745 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
746
747 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
748 return;
749
750 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
751 }
752
753 static void dispc_ovl_enable_zorder_planes(void)
754 {
755 int i;
756
757 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
758 return;
759
760 for (i = 0; i < dss_feat_get_num_ovls(); i++)
761 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
762 }
763
764 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
765 {
766 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
767
768 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
769 return;
770
771 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
772 }
773
774 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
775 {
776 static const unsigned shifts[] = { 0, 8, 16, 24, };
777 int shift;
778 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
779
780 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
781 return;
782
783 shift = shifts[plane];
784 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
785 }
786
787 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
788 {
789 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
790 }
791
792 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
793 {
794 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
795 }
796
797 static void dispc_ovl_set_color_mode(enum omap_plane plane,
798 enum omap_color_mode color_mode)
799 {
800 u32 m = 0;
801 if (plane != OMAP_DSS_GFX) {
802 switch (color_mode) {
803 case OMAP_DSS_COLOR_NV12:
804 m = 0x0; break;
805 case OMAP_DSS_COLOR_RGB12U:
806 m = 0x1; break;
807 case OMAP_DSS_COLOR_RGBA16:
808 m = 0x2; break;
809 case OMAP_DSS_COLOR_RGBX16:
810 m = 0x4; break;
811 case OMAP_DSS_COLOR_ARGB16:
812 m = 0x5; break;
813 case OMAP_DSS_COLOR_RGB16:
814 m = 0x6; break;
815 case OMAP_DSS_COLOR_ARGB16_1555:
816 m = 0x7; break;
817 case OMAP_DSS_COLOR_RGB24U:
818 m = 0x8; break;
819 case OMAP_DSS_COLOR_RGB24P:
820 m = 0x9; break;
821 case OMAP_DSS_COLOR_YUV2:
822 m = 0xa; break;
823 case OMAP_DSS_COLOR_UYVY:
824 m = 0xb; break;
825 case OMAP_DSS_COLOR_ARGB32:
826 m = 0xc; break;
827 case OMAP_DSS_COLOR_RGBA32:
828 m = 0xd; break;
829 case OMAP_DSS_COLOR_RGBX32:
830 m = 0xe; break;
831 case OMAP_DSS_COLOR_XRGB16_1555:
832 m = 0xf; break;
833 default:
834 BUG(); break;
835 }
836 } else {
837 switch (color_mode) {
838 case OMAP_DSS_COLOR_CLUT1:
839 m = 0x0; break;
840 case OMAP_DSS_COLOR_CLUT2:
841 m = 0x1; break;
842 case OMAP_DSS_COLOR_CLUT4:
843 m = 0x2; break;
844 case OMAP_DSS_COLOR_CLUT8:
845 m = 0x3; break;
846 case OMAP_DSS_COLOR_RGB12U:
847 m = 0x4; break;
848 case OMAP_DSS_COLOR_ARGB16:
849 m = 0x5; break;
850 case OMAP_DSS_COLOR_RGB16:
851 m = 0x6; break;
852 case OMAP_DSS_COLOR_ARGB16_1555:
853 m = 0x7; break;
854 case OMAP_DSS_COLOR_RGB24U:
855 m = 0x8; break;
856 case OMAP_DSS_COLOR_RGB24P:
857 m = 0x9; break;
858 case OMAP_DSS_COLOR_YUV2:
859 m = 0xa; break;
860 case OMAP_DSS_COLOR_UYVY:
861 m = 0xb; break;
862 case OMAP_DSS_COLOR_ARGB32:
863 m = 0xc; break;
864 case OMAP_DSS_COLOR_RGBA32:
865 m = 0xd; break;
866 case OMAP_DSS_COLOR_RGBX32:
867 m = 0xe; break;
868 case OMAP_DSS_COLOR_XRGB16_1555:
869 m = 0xf; break;
870 default:
871 BUG(); break;
872 }
873 }
874
875 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
876 }
877
878 static void dispc_ovl_set_channel_out(enum omap_plane plane,
879 enum omap_channel channel)
880 {
881 int shift;
882 u32 val;
883 int chan = 0, chan2 = 0;
884
885 switch (plane) {
886 case OMAP_DSS_GFX:
887 shift = 8;
888 break;
889 case OMAP_DSS_VIDEO1:
890 case OMAP_DSS_VIDEO2:
891 case OMAP_DSS_VIDEO3:
892 shift = 16;
893 break;
894 default:
895 BUG();
896 return;
897 }
898
899 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
900 if (dss_has_feature(FEAT_MGR_LCD2)) {
901 switch (channel) {
902 case OMAP_DSS_CHANNEL_LCD:
903 chan = 0;
904 chan2 = 0;
905 break;
906 case OMAP_DSS_CHANNEL_DIGIT:
907 chan = 1;
908 chan2 = 0;
909 break;
910 case OMAP_DSS_CHANNEL_LCD2:
911 chan = 0;
912 chan2 = 1;
913 break;
914 default:
915 BUG();
916 }
917
918 val = FLD_MOD(val, chan, shift, shift);
919 val = FLD_MOD(val, chan2, 31, 30);
920 } else {
921 val = FLD_MOD(val, channel, shift, shift);
922 }
923 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
924 }
925
926 static void dispc_ovl_set_burst_size(enum omap_plane plane,
927 enum omap_burst_size burst_size)
928 {
929 static const unsigned shifts[] = { 6, 14, 14, 14, };
930 int shift;
931
932 shift = shifts[plane];
933 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
934 }
935
936 static void dispc_configure_burst_sizes(void)
937 {
938 int i;
939 const int burst_size = BURST_SIZE_X8;
940
941 /* Configure burst size always to maximum size */
942 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
943 dispc_ovl_set_burst_size(i, burst_size);
944 }
945
946 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
947 {
948 unsigned unit = dss_feat_get_burst_size_unit();
949 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
950 return unit * 8;
951 }
952
953 void dispc_enable_gamma_table(bool enable)
954 {
955 /*
956 * This is partially implemented to support only disabling of
957 * the gamma table.
958 */
959 if (enable) {
960 DSSWARN("Gamma table enabling for TV not yet supported");
961 return;
962 }
963
964 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
965 }
966
967 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
968 {
969 u16 reg;
970
971 if (channel == OMAP_DSS_CHANNEL_LCD)
972 reg = DISPC_CONFIG;
973 else if (channel == OMAP_DSS_CHANNEL_LCD2)
974 reg = DISPC_CONFIG2;
975 else
976 return;
977
978 REG_FLD_MOD(reg, enable, 15, 15);
979 }
980
981 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
982 struct omap_dss_cpr_coefs *coefs)
983 {
984 u32 coef_r, coef_g, coef_b;
985
986 if (!dispc_mgr_is_lcd(channel))
987 return;
988
989 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
990 FLD_VAL(coefs->rb, 9, 0);
991 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
992 FLD_VAL(coefs->gb, 9, 0);
993 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
994 FLD_VAL(coefs->bb, 9, 0);
995
996 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
997 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
998 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
999 }
1000
1001 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1002 {
1003 u32 val;
1004
1005 BUG_ON(plane == OMAP_DSS_GFX);
1006
1007 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1008 val = FLD_MOD(val, enable, 9, 9);
1009 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1010 }
1011
1012 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1013 {
1014 static const unsigned shifts[] = { 5, 10, 10, 10 };
1015 int shift;
1016
1017 shift = shifts[plane];
1018 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1019 }
1020
1021 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1022 {
1023 u32 val;
1024 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1025 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1026 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1027 }
1028
1029 void dispc_set_digit_size(u16 width, u16 height)
1030 {
1031 u32 val;
1032 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1033 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1034 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1035 }
1036
1037 static void dispc_read_plane_fifo_sizes(void)
1038 {
1039 u32 size;
1040 int plane;
1041 u8 start, end;
1042 u32 unit;
1043
1044 unit = dss_feat_get_buffer_size_unit();
1045
1046 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1047
1048 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1049 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1050 size *= unit;
1051 dispc.fifo_size[plane] = size;
1052 }
1053 }
1054
1055 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1056 {
1057 return dispc.fifo_size[plane];
1058 }
1059
1060 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1061 u32 high)
1062 {
1063 u8 hi_start, hi_end, lo_start, lo_end;
1064 u32 unit;
1065
1066 unit = dss_feat_get_buffer_size_unit();
1067
1068 WARN_ON(low % unit != 0);
1069 WARN_ON(high % unit != 0);
1070
1071 low /= unit;
1072 high /= unit;
1073
1074 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1075 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1076
1077 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1078 plane,
1079 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1080 lo_start, lo_end),
1081 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1082 hi_start, hi_end),
1083 low, high);
1084
1085 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1086 FLD_VAL(high, hi_start, hi_end) |
1087 FLD_VAL(low, lo_start, lo_end));
1088 }
1089
1090 void dispc_enable_fifomerge(bool enable)
1091 {
1092 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1093 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1094 }
1095
1096 static void dispc_ovl_set_fir(enum omap_plane plane,
1097 int hinc, int vinc,
1098 enum omap_color_component color_comp)
1099 {
1100 u32 val;
1101
1102 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1103 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1104
1105 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1106 &hinc_start, &hinc_end);
1107 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1108 &vinc_start, &vinc_end);
1109 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1110 FLD_VAL(hinc, hinc_start, hinc_end);
1111
1112 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1113 } else {
1114 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1115 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1116 }
1117 }
1118
1119 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1120 {
1121 u32 val;
1122 u8 hor_start, hor_end, vert_start, vert_end;
1123
1124 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1125 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1126
1127 val = FLD_VAL(vaccu, vert_start, vert_end) |
1128 FLD_VAL(haccu, hor_start, hor_end);
1129
1130 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1131 }
1132
1133 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1134 {
1135 u32 val;
1136 u8 hor_start, hor_end, vert_start, vert_end;
1137
1138 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1139 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1140
1141 val = FLD_VAL(vaccu, vert_start, vert_end) |
1142 FLD_VAL(haccu, hor_start, hor_end);
1143
1144 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1145 }
1146
1147 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1148 int vaccu)
1149 {
1150 u32 val;
1151
1152 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1153 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1154 }
1155
1156 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1157 int vaccu)
1158 {
1159 u32 val;
1160
1161 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1162 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1163 }
1164
1165 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1166 u16 orig_width, u16 orig_height,
1167 u16 out_width, u16 out_height,
1168 bool five_taps, u8 rotation,
1169 enum omap_color_component color_comp)
1170 {
1171 int fir_hinc, fir_vinc;
1172 int hscaleup, vscaleup;
1173
1174 hscaleup = orig_width <= out_width;
1175 vscaleup = orig_height <= out_height;
1176
1177 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1178 color_comp);
1179
1180 fir_hinc = 1024 * orig_width / out_width;
1181 fir_vinc = 1024 * orig_height / out_height;
1182
1183 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1184 }
1185
1186 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1187 u16 orig_width, u16 orig_height,
1188 u16 out_width, u16 out_height,
1189 bool ilace, bool five_taps,
1190 bool fieldmode, enum omap_color_mode color_mode,
1191 u8 rotation)
1192 {
1193 int accu0 = 0;
1194 int accu1 = 0;
1195 u32 l;
1196
1197 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1198 out_width, out_height, five_taps,
1199 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1200 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1201
1202 /* RESIZEENABLE and VERTICALTAPS */
1203 l &= ~((0x3 << 5) | (0x1 << 21));
1204 l |= (orig_width != out_width) ? (1 << 5) : 0;
1205 l |= (orig_height != out_height) ? (1 << 6) : 0;
1206 l |= five_taps ? (1 << 21) : 0;
1207
1208 /* VRESIZECONF and HRESIZECONF */
1209 if (dss_has_feature(FEAT_RESIZECONF)) {
1210 l &= ~(0x3 << 7);
1211 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1212 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1213 }
1214
1215 /* LINEBUFFERSPLIT */
1216 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1217 l &= ~(0x1 << 22);
1218 l |= five_taps ? (1 << 22) : 0;
1219 }
1220
1221 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1222
1223 /*
1224 * field 0 = even field = bottom field
1225 * field 1 = odd field = top field
1226 */
1227 if (ilace && !fieldmode) {
1228 accu1 = 0;
1229 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1230 if (accu0 >= 1024/2) {
1231 accu1 = 1024/2;
1232 accu0 -= accu1;
1233 }
1234 }
1235
1236 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1237 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1238 }
1239
1240 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1241 u16 orig_width, u16 orig_height,
1242 u16 out_width, u16 out_height,
1243 bool ilace, bool five_taps,
1244 bool fieldmode, enum omap_color_mode color_mode,
1245 u8 rotation)
1246 {
1247 int scale_x = out_width != orig_width;
1248 int scale_y = out_height != orig_height;
1249
1250 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1251 return;
1252 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1253 color_mode != OMAP_DSS_COLOR_UYVY &&
1254 color_mode != OMAP_DSS_COLOR_NV12)) {
1255 /* reset chroma resampling for RGB formats */
1256 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1257 return;
1258 }
1259 switch (color_mode) {
1260 case OMAP_DSS_COLOR_NV12:
1261 /* UV is subsampled by 2 vertically*/
1262 orig_height >>= 1;
1263 /* UV is subsampled by 2 horz.*/
1264 orig_width >>= 1;
1265 break;
1266 case OMAP_DSS_COLOR_YUV2:
1267 case OMAP_DSS_COLOR_UYVY:
1268 /*For YUV422 with 90/270 rotation,
1269 *we don't upsample chroma
1270 */
1271 if (rotation == OMAP_DSS_ROT_0 ||
1272 rotation == OMAP_DSS_ROT_180)
1273 /* UV is subsampled by 2 hrz*/
1274 orig_width >>= 1;
1275 /* must use FIR for YUV422 if rotated */
1276 if (rotation != OMAP_DSS_ROT_0)
1277 scale_x = scale_y = true;
1278 break;
1279 default:
1280 BUG();
1281 }
1282
1283 if (out_width != orig_width)
1284 scale_x = true;
1285 if (out_height != orig_height)
1286 scale_y = true;
1287
1288 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1289 out_width, out_height, five_taps,
1290 rotation, DISPC_COLOR_COMPONENT_UV);
1291
1292 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1293 (scale_x || scale_y) ? 1 : 0, 8, 8);
1294 /* set H scaling */
1295 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1296 /* set V scaling */
1297 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1298
1299 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1300 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1301 }
1302
1303 static void dispc_ovl_set_scaling(enum omap_plane plane,
1304 u16 orig_width, u16 orig_height,
1305 u16 out_width, u16 out_height,
1306 bool ilace, bool five_taps,
1307 bool fieldmode, enum omap_color_mode color_mode,
1308 u8 rotation)
1309 {
1310 BUG_ON(plane == OMAP_DSS_GFX);
1311
1312 dispc_ovl_set_scaling_common(plane,
1313 orig_width, orig_height,
1314 out_width, out_height,
1315 ilace, five_taps,
1316 fieldmode, color_mode,
1317 rotation);
1318
1319 dispc_ovl_set_scaling_uv(plane,
1320 orig_width, orig_height,
1321 out_width, out_height,
1322 ilace, five_taps,
1323 fieldmode, color_mode,
1324 rotation);
1325 }
1326
1327 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1328 bool mirroring, enum omap_color_mode color_mode)
1329 {
1330 bool row_repeat = false;
1331 int vidrot = 0;
1332
1333 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1334 color_mode == OMAP_DSS_COLOR_UYVY) {
1335
1336 if (mirroring) {
1337 switch (rotation) {
1338 case OMAP_DSS_ROT_0:
1339 vidrot = 2;
1340 break;
1341 case OMAP_DSS_ROT_90:
1342 vidrot = 1;
1343 break;
1344 case OMAP_DSS_ROT_180:
1345 vidrot = 0;
1346 break;
1347 case OMAP_DSS_ROT_270:
1348 vidrot = 3;
1349 break;
1350 }
1351 } else {
1352 switch (rotation) {
1353 case OMAP_DSS_ROT_0:
1354 vidrot = 0;
1355 break;
1356 case OMAP_DSS_ROT_90:
1357 vidrot = 1;
1358 break;
1359 case OMAP_DSS_ROT_180:
1360 vidrot = 2;
1361 break;
1362 case OMAP_DSS_ROT_270:
1363 vidrot = 3;
1364 break;
1365 }
1366 }
1367
1368 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1369 row_repeat = true;
1370 else
1371 row_repeat = false;
1372 }
1373
1374 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1375 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1376 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1377 row_repeat ? 1 : 0, 18, 18);
1378 }
1379
1380 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1381 {
1382 switch (color_mode) {
1383 case OMAP_DSS_COLOR_CLUT1:
1384 return 1;
1385 case OMAP_DSS_COLOR_CLUT2:
1386 return 2;
1387 case OMAP_DSS_COLOR_CLUT4:
1388 return 4;
1389 case OMAP_DSS_COLOR_CLUT8:
1390 case OMAP_DSS_COLOR_NV12:
1391 return 8;
1392 case OMAP_DSS_COLOR_RGB12U:
1393 case OMAP_DSS_COLOR_RGB16:
1394 case OMAP_DSS_COLOR_ARGB16:
1395 case OMAP_DSS_COLOR_YUV2:
1396 case OMAP_DSS_COLOR_UYVY:
1397 case OMAP_DSS_COLOR_RGBA16:
1398 case OMAP_DSS_COLOR_RGBX16:
1399 case OMAP_DSS_COLOR_ARGB16_1555:
1400 case OMAP_DSS_COLOR_XRGB16_1555:
1401 return 16;
1402 case OMAP_DSS_COLOR_RGB24P:
1403 return 24;
1404 case OMAP_DSS_COLOR_RGB24U:
1405 case OMAP_DSS_COLOR_ARGB32:
1406 case OMAP_DSS_COLOR_RGBA32:
1407 case OMAP_DSS_COLOR_RGBX32:
1408 return 32;
1409 default:
1410 BUG();
1411 }
1412 }
1413
1414 static s32 pixinc(int pixels, u8 ps)
1415 {
1416 if (pixels == 1)
1417 return 1;
1418 else if (pixels > 1)
1419 return 1 + (pixels - 1) * ps;
1420 else if (pixels < 0)
1421 return 1 - (-pixels + 1) * ps;
1422 else
1423 BUG();
1424 }
1425
1426 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1427 u16 screen_width,
1428 u16 width, u16 height,
1429 enum omap_color_mode color_mode, bool fieldmode,
1430 unsigned int field_offset,
1431 unsigned *offset0, unsigned *offset1,
1432 s32 *row_inc, s32 *pix_inc)
1433 {
1434 u8 ps;
1435
1436 /* FIXME CLUT formats */
1437 switch (color_mode) {
1438 case OMAP_DSS_COLOR_CLUT1:
1439 case OMAP_DSS_COLOR_CLUT2:
1440 case OMAP_DSS_COLOR_CLUT4:
1441 case OMAP_DSS_COLOR_CLUT8:
1442 BUG();
1443 return;
1444 case OMAP_DSS_COLOR_YUV2:
1445 case OMAP_DSS_COLOR_UYVY:
1446 ps = 4;
1447 break;
1448 default:
1449 ps = color_mode_to_bpp(color_mode) / 8;
1450 break;
1451 }
1452
1453 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1454 width, height);
1455
1456 /*
1457 * field 0 = even field = bottom field
1458 * field 1 = odd field = top field
1459 */
1460 switch (rotation + mirror * 4) {
1461 case OMAP_DSS_ROT_0:
1462 case OMAP_DSS_ROT_180:
1463 /*
1464 * If the pixel format is YUV or UYVY divide the width
1465 * of the image by 2 for 0 and 180 degree rotation.
1466 */
1467 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1468 color_mode == OMAP_DSS_COLOR_UYVY)
1469 width = width >> 1;
1470 case OMAP_DSS_ROT_90:
1471 case OMAP_DSS_ROT_270:
1472 *offset1 = 0;
1473 if (field_offset)
1474 *offset0 = field_offset * screen_width * ps;
1475 else
1476 *offset0 = 0;
1477
1478 *row_inc = pixinc(1 + (screen_width - width) +
1479 (fieldmode ? screen_width : 0),
1480 ps);
1481 *pix_inc = pixinc(1, ps);
1482 break;
1483
1484 case OMAP_DSS_ROT_0 + 4:
1485 case OMAP_DSS_ROT_180 + 4:
1486 /* If the pixel format is YUV or UYVY divide the width
1487 * of the image by 2 for 0 degree and 180 degree
1488 */
1489 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1490 color_mode == OMAP_DSS_COLOR_UYVY)
1491 width = width >> 1;
1492 case OMAP_DSS_ROT_90 + 4:
1493 case OMAP_DSS_ROT_270 + 4:
1494 *offset1 = 0;
1495 if (field_offset)
1496 *offset0 = field_offset * screen_width * ps;
1497 else
1498 *offset0 = 0;
1499 *row_inc = pixinc(1 - (screen_width + width) -
1500 (fieldmode ? screen_width : 0),
1501 ps);
1502 *pix_inc = pixinc(1, ps);
1503 break;
1504
1505 default:
1506 BUG();
1507 }
1508 }
1509
1510 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1511 u16 screen_width,
1512 u16 width, u16 height,
1513 enum omap_color_mode color_mode, bool fieldmode,
1514 unsigned int field_offset,
1515 unsigned *offset0, unsigned *offset1,
1516 s32 *row_inc, s32 *pix_inc)
1517 {
1518 u8 ps;
1519 u16 fbw, fbh;
1520
1521 /* FIXME CLUT formats */
1522 switch (color_mode) {
1523 case OMAP_DSS_COLOR_CLUT1:
1524 case OMAP_DSS_COLOR_CLUT2:
1525 case OMAP_DSS_COLOR_CLUT4:
1526 case OMAP_DSS_COLOR_CLUT8:
1527 BUG();
1528 return;
1529 default:
1530 ps = color_mode_to_bpp(color_mode) / 8;
1531 break;
1532 }
1533
1534 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1535 width, height);
1536
1537 /* width & height are overlay sizes, convert to fb sizes */
1538
1539 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1540 fbw = width;
1541 fbh = height;
1542 } else {
1543 fbw = height;
1544 fbh = width;
1545 }
1546
1547 /*
1548 * field 0 = even field = bottom field
1549 * field 1 = odd field = top field
1550 */
1551 switch (rotation + mirror * 4) {
1552 case OMAP_DSS_ROT_0:
1553 *offset1 = 0;
1554 if (field_offset)
1555 *offset0 = *offset1 + field_offset * screen_width * ps;
1556 else
1557 *offset0 = *offset1;
1558 *row_inc = pixinc(1 + (screen_width - fbw) +
1559 (fieldmode ? screen_width : 0),
1560 ps);
1561 *pix_inc = pixinc(1, ps);
1562 break;
1563 case OMAP_DSS_ROT_90:
1564 *offset1 = screen_width * (fbh - 1) * ps;
1565 if (field_offset)
1566 *offset0 = *offset1 + field_offset * ps;
1567 else
1568 *offset0 = *offset1;
1569 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1570 (fieldmode ? 1 : 0), ps);
1571 *pix_inc = pixinc(-screen_width, ps);
1572 break;
1573 case OMAP_DSS_ROT_180:
1574 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1575 if (field_offset)
1576 *offset0 = *offset1 - field_offset * screen_width * ps;
1577 else
1578 *offset0 = *offset1;
1579 *row_inc = pixinc(-1 -
1580 (screen_width - fbw) -
1581 (fieldmode ? screen_width : 0),
1582 ps);
1583 *pix_inc = pixinc(-1, ps);
1584 break;
1585 case OMAP_DSS_ROT_270:
1586 *offset1 = (fbw - 1) * ps;
1587 if (field_offset)
1588 *offset0 = *offset1 - field_offset * ps;
1589 else
1590 *offset0 = *offset1;
1591 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1592 (fieldmode ? 1 : 0), ps);
1593 *pix_inc = pixinc(screen_width, ps);
1594 break;
1595
1596 /* mirroring */
1597 case OMAP_DSS_ROT_0 + 4:
1598 *offset1 = (fbw - 1) * ps;
1599 if (field_offset)
1600 *offset0 = *offset1 + field_offset * screen_width * ps;
1601 else
1602 *offset0 = *offset1;
1603 *row_inc = pixinc(screen_width * 2 - 1 +
1604 (fieldmode ? screen_width : 0),
1605 ps);
1606 *pix_inc = pixinc(-1, ps);
1607 break;
1608
1609 case OMAP_DSS_ROT_90 + 4:
1610 *offset1 = 0;
1611 if (field_offset)
1612 *offset0 = *offset1 + field_offset * ps;
1613 else
1614 *offset0 = *offset1;
1615 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1616 (fieldmode ? 1 : 0),
1617 ps);
1618 *pix_inc = pixinc(screen_width, ps);
1619 break;
1620
1621 case OMAP_DSS_ROT_180 + 4:
1622 *offset1 = screen_width * (fbh - 1) * ps;
1623 if (field_offset)
1624 *offset0 = *offset1 - field_offset * screen_width * ps;
1625 else
1626 *offset0 = *offset1;
1627 *row_inc = pixinc(1 - screen_width * 2 -
1628 (fieldmode ? screen_width : 0),
1629 ps);
1630 *pix_inc = pixinc(1, ps);
1631 break;
1632
1633 case OMAP_DSS_ROT_270 + 4:
1634 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1635 if (field_offset)
1636 *offset0 = *offset1 - field_offset * ps;
1637 else
1638 *offset0 = *offset1;
1639 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1640 (fieldmode ? 1 : 0),
1641 ps);
1642 *pix_inc = pixinc(-screen_width, ps);
1643 break;
1644
1645 default:
1646 BUG();
1647 }
1648 }
1649
1650 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1651 u16 height, u16 out_width, u16 out_height,
1652 enum omap_color_mode color_mode)
1653 {
1654 u32 fclk = 0;
1655 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1656
1657 if (height > out_height) {
1658 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1659 unsigned int ppl = dssdev->panel.timings.x_res;
1660
1661 tmp = pclk * height * out_width;
1662 do_div(tmp, 2 * out_height * ppl);
1663 fclk = tmp;
1664
1665 if (height > 2 * out_height) {
1666 if (ppl == out_width)
1667 return 0;
1668
1669 tmp = pclk * (height - 2 * out_height) * out_width;
1670 do_div(tmp, 2 * out_height * (ppl - out_width));
1671 fclk = max(fclk, (u32) tmp);
1672 }
1673 }
1674
1675 if (width > out_width) {
1676 tmp = pclk * width;
1677 do_div(tmp, out_width);
1678 fclk = max(fclk, (u32) tmp);
1679
1680 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1681 fclk <<= 1;
1682 }
1683
1684 return fclk;
1685 }
1686
1687 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1688 u16 height, u16 out_width, u16 out_height)
1689 {
1690 unsigned int hf, vf;
1691
1692 /*
1693 * FIXME how to determine the 'A' factor
1694 * for the no downscaling case ?
1695 */
1696
1697 if (width > 3 * out_width)
1698 hf = 4;
1699 else if (width > 2 * out_width)
1700 hf = 3;
1701 else if (width > out_width)
1702 hf = 2;
1703 else
1704 hf = 1;
1705
1706 if (height > out_height)
1707 vf = 2;
1708 else
1709 vf = 1;
1710
1711 return dispc_mgr_pclk_rate(channel) * vf * hf;
1712 }
1713
1714 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1715 enum omap_channel channel, u16 width, u16 height,
1716 u16 out_width, u16 out_height,
1717 enum omap_color_mode color_mode, bool *five_taps)
1718 {
1719 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1720 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1721 unsigned long fclk = 0;
1722
1723 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
1724 if (width != out_width || height != out_height)
1725 return -EINVAL;
1726 else
1727 return 0;
1728 }
1729
1730 if (out_width < width / maxdownscale ||
1731 out_width > width * 8)
1732 return -EINVAL;
1733
1734 if (out_height < height / maxdownscale ||
1735 out_height > height * 8)
1736 return -EINVAL;
1737
1738 /* Must use 5-tap filter? */
1739 *five_taps = height > out_height * 2;
1740
1741 if (!*five_taps) {
1742 fclk = calc_fclk(channel, width, height, out_width,
1743 out_height);
1744
1745 /* Try 5-tap filter if 3-tap fclk is too high */
1746 if (cpu_is_omap34xx() && height > out_height &&
1747 fclk > dispc_fclk_rate())
1748 *five_taps = true;
1749 }
1750
1751 if (width > (2048 >> *five_taps)) {
1752 DSSERR("failed to set up scaling, fclk too low\n");
1753 return -EINVAL;
1754 }
1755
1756 if (*five_taps)
1757 fclk = calc_fclk_five_taps(channel, width, height,
1758 out_width, out_height, color_mode);
1759
1760 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1761 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1762
1763 if (!fclk || fclk > dispc_fclk_rate()) {
1764 DSSERR("failed to set up scaling, "
1765 "required fclk rate = %lu Hz, "
1766 "current fclk rate = %lu Hz\n",
1767 fclk, dispc_fclk_rate());
1768 return -EINVAL;
1769 }
1770
1771 return 0;
1772 }
1773
1774 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1775 bool ilace, enum omap_channel channel, bool replication,
1776 u32 fifo_low, u32 fifo_high)
1777 {
1778 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1779 bool five_taps = false;
1780 bool fieldmode = 0;
1781 int r, cconv = 0;
1782 unsigned offset0, offset1;
1783 s32 row_inc;
1784 s32 pix_inc;
1785 u16 frame_height = oi->height;
1786 unsigned int field_offset = 0;
1787
1788 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1789 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1790 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1791 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1792 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1793 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1794
1795 if (oi->paddr == 0)
1796 return -EINVAL;
1797
1798 if (ilace && oi->height == oi->out_height)
1799 fieldmode = 1;
1800
1801 if (ilace) {
1802 if (fieldmode)
1803 oi->height /= 2;
1804 oi->pos_y /= 2;
1805 oi->out_height /= 2;
1806
1807 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1808 "out_height %d\n",
1809 oi->height, oi->pos_y, oi->out_height);
1810 }
1811
1812 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1813 return -EINVAL;
1814
1815 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1816 oi->out_width, oi->out_height, oi->color_mode,
1817 &five_taps);
1818 if (r)
1819 return r;
1820
1821 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1822 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1823 oi->color_mode == OMAP_DSS_COLOR_NV12)
1824 cconv = 1;
1825
1826 if (ilace && !fieldmode) {
1827 /*
1828 * when downscaling the bottom field may have to start several
1829 * source lines below the top field. Unfortunately ACCUI
1830 * registers will only hold the fractional part of the offset
1831 * so the integer part must be added to the base address of the
1832 * bottom field.
1833 */
1834 if (!oi->height || oi->height == oi->out_height)
1835 field_offset = 0;
1836 else
1837 field_offset = oi->height / oi->out_height / 2;
1838 }
1839
1840 /* Fields are independent but interleaved in memory. */
1841 if (fieldmode)
1842 field_offset = 1;
1843
1844 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1845 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1846 oi->screen_width, oi->width, frame_height,
1847 oi->color_mode, fieldmode, field_offset,
1848 &offset0, &offset1, &row_inc, &pix_inc);
1849 else
1850 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1851 oi->screen_width, oi->width, frame_height,
1852 oi->color_mode, fieldmode, field_offset,
1853 &offset0, &offset1, &row_inc, &pix_inc);
1854
1855 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1856 offset0, offset1, row_inc, pix_inc);
1857
1858 dispc_ovl_set_color_mode(plane, oi->color_mode);
1859
1860 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1861 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1862
1863 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1864 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1865 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1866 }
1867
1868
1869 dispc_ovl_set_row_inc(plane, row_inc);
1870 dispc_ovl_set_pix_inc(plane, pix_inc);
1871
1872 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1873 oi->height, oi->out_width, oi->out_height);
1874
1875 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1876
1877 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1878
1879 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1880 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1881 oi->out_width, oi->out_height,
1882 ilace, five_taps, fieldmode,
1883 oi->color_mode, oi->rotation);
1884 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1885 dispc_ovl_set_vid_color_conv(plane, cconv);
1886 }
1887
1888 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1889 oi->color_mode);
1890
1891 dispc_ovl_set_zorder(plane, oi->zorder);
1892 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1893 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1894
1895 dispc_ovl_set_channel_out(plane, channel);
1896
1897 dispc_ovl_enable_replication(plane, replication);
1898 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1899
1900 return 0;
1901 }
1902
1903 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1904 {
1905 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1906
1907 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1908
1909 return 0;
1910 }
1911
1912 static void dispc_disable_isr(void *data, u32 mask)
1913 {
1914 struct completion *compl = data;
1915 complete(compl);
1916 }
1917
1918 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1919 {
1920 if (channel == OMAP_DSS_CHANNEL_LCD2)
1921 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1922 else
1923 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1924 }
1925
1926 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1927 {
1928 struct completion frame_done_completion;
1929 bool is_on;
1930 int r;
1931 u32 irq;
1932
1933 /* When we disable LCD output, we need to wait until frame is done.
1934 * Otherwise the DSS is still working, and turning off the clocks
1935 * prevents DSS from going to OFF mode */
1936 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1937 REG_GET(DISPC_CONTROL2, 0, 0) :
1938 REG_GET(DISPC_CONTROL, 0, 0);
1939
1940 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1941 DISPC_IRQ_FRAMEDONE;
1942
1943 if (!enable && is_on) {
1944 init_completion(&frame_done_completion);
1945
1946 r = omap_dispc_register_isr(dispc_disable_isr,
1947 &frame_done_completion, irq);
1948
1949 if (r)
1950 DSSERR("failed to register FRAMEDONE isr\n");
1951 }
1952
1953 _enable_lcd_out(channel, enable);
1954
1955 if (!enable && is_on) {
1956 if (!wait_for_completion_timeout(&frame_done_completion,
1957 msecs_to_jiffies(100)))
1958 DSSERR("timeout waiting for FRAME DONE\n");
1959
1960 r = omap_dispc_unregister_isr(dispc_disable_isr,
1961 &frame_done_completion, irq);
1962
1963 if (r)
1964 DSSERR("failed to unregister FRAMEDONE isr\n");
1965 }
1966 }
1967
1968 static void _enable_digit_out(bool enable)
1969 {
1970 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1971 }
1972
1973 static void dispc_mgr_enable_digit_out(bool enable)
1974 {
1975 struct completion frame_done_completion;
1976 enum dss_hdmi_venc_clk_source_select src;
1977 int r, i;
1978 u32 irq_mask;
1979 int num_irqs;
1980
1981 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1982 return;
1983
1984 src = dss_get_hdmi_venc_clk_source();
1985
1986 if (enable) {
1987 unsigned long flags;
1988 /* When we enable digit output, we'll get an extra digit
1989 * sync lost interrupt, that we need to ignore */
1990 spin_lock_irqsave(&dispc.irq_lock, flags);
1991 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1992 _omap_dispc_set_irqs();
1993 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1994 }
1995
1996 /* When we disable digit output, we need to wait until fields are done.
1997 * Otherwise the DSS is still working, and turning off the clocks
1998 * prevents DSS from going to OFF mode. And when enabling, we need to
1999 * wait for the extra sync losts */
2000 init_completion(&frame_done_completion);
2001
2002 if (src == DSS_HDMI_M_PCLK && enable == false) {
2003 irq_mask = DISPC_IRQ_FRAMEDONETV;
2004 num_irqs = 1;
2005 } else {
2006 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2007 /* XXX I understand from TRM that we should only wait for the
2008 * current field to complete. But it seems we have to wait for
2009 * both fields */
2010 num_irqs = 2;
2011 }
2012
2013 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2014 irq_mask);
2015 if (r)
2016 DSSERR("failed to register %x isr\n", irq_mask);
2017
2018 _enable_digit_out(enable);
2019
2020 for (i = 0; i < num_irqs; ++i) {
2021 if (!wait_for_completion_timeout(&frame_done_completion,
2022 msecs_to_jiffies(100)))
2023 DSSERR("timeout waiting for digit out to %s\n",
2024 enable ? "start" : "stop");
2025 }
2026
2027 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2028 irq_mask);
2029 if (r)
2030 DSSERR("failed to unregister %x isr\n", irq_mask);
2031
2032 if (enable) {
2033 unsigned long flags;
2034 spin_lock_irqsave(&dispc.irq_lock, flags);
2035 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2036 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2037 _omap_dispc_set_irqs();
2038 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2039 }
2040 }
2041
2042 bool dispc_mgr_is_enabled(enum omap_channel channel)
2043 {
2044 if (channel == OMAP_DSS_CHANNEL_LCD)
2045 return !!REG_GET(DISPC_CONTROL, 0, 0);
2046 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2047 return !!REG_GET(DISPC_CONTROL, 1, 1);
2048 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2049 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2050 else
2051 BUG();
2052 }
2053
2054 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2055 {
2056 if (dispc_mgr_is_lcd(channel))
2057 dispc_mgr_enable_lcd_out(channel, enable);
2058 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2059 dispc_mgr_enable_digit_out(enable);
2060 else
2061 BUG();
2062 }
2063
2064 void dispc_lcd_enable_signal_polarity(bool act_high)
2065 {
2066 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2067 return;
2068
2069 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2070 }
2071
2072 void dispc_lcd_enable_signal(bool enable)
2073 {
2074 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2075 return;
2076
2077 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2078 }
2079
2080 void dispc_pck_free_enable(bool enable)
2081 {
2082 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2083 return;
2084
2085 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2086 }
2087
2088 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2089 {
2090 if (channel == OMAP_DSS_CHANNEL_LCD2)
2091 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2092 else
2093 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2094 }
2095
2096
2097 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2098 enum omap_lcd_display_type type)
2099 {
2100 int mode;
2101
2102 switch (type) {
2103 case OMAP_DSS_LCD_DISPLAY_STN:
2104 mode = 0;
2105 break;
2106
2107 case OMAP_DSS_LCD_DISPLAY_TFT:
2108 mode = 1;
2109 break;
2110
2111 default:
2112 BUG();
2113 return;
2114 }
2115
2116 if (channel == OMAP_DSS_CHANNEL_LCD2)
2117 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2118 else
2119 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2120 }
2121
2122 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2123 {
2124 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2125 }
2126
2127
2128 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2129 {
2130 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2131 }
2132
2133 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2134 {
2135 u32 l;
2136
2137 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2138 channel != OMAP_DSS_CHANNEL_LCD &&
2139 channel != OMAP_DSS_CHANNEL_LCD2);
2140
2141 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2142
2143 return l;
2144 }
2145
2146 void dispc_mgr_set_trans_key(enum omap_channel ch,
2147 enum omap_dss_trans_key_type type,
2148 u32 trans_key)
2149 {
2150 if (ch == OMAP_DSS_CHANNEL_LCD)
2151 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2152 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2153 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2154 else /* OMAP_DSS_CHANNEL_LCD2 */
2155 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2156
2157 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2158 }
2159
2160 void dispc_mgr_get_trans_key(enum omap_channel ch,
2161 enum omap_dss_trans_key_type *type,
2162 u32 *trans_key)
2163 {
2164 if (type) {
2165 if (ch == OMAP_DSS_CHANNEL_LCD)
2166 *type = REG_GET(DISPC_CONFIG, 11, 11);
2167 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2168 *type = REG_GET(DISPC_CONFIG, 13, 13);
2169 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2170 *type = REG_GET(DISPC_CONFIG2, 11, 11);
2171 else
2172 BUG();
2173 }
2174
2175 if (trans_key)
2176 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2177 }
2178
2179 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2180 {
2181 if (ch == OMAP_DSS_CHANNEL_LCD)
2182 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2183 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2184 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2185 else /* OMAP_DSS_CHANNEL_LCD2 */
2186 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2187 }
2188
2189 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
2190 {
2191 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2192 return;
2193
2194 if (ch == OMAP_DSS_CHANNEL_LCD)
2195 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2196 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2197 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2198 }
2199
2200 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
2201 {
2202 bool enabled;
2203
2204 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2205 return false;
2206
2207 if (ch == OMAP_DSS_CHANNEL_LCD)
2208 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2209 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2210 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2211 else
2212 BUG();
2213
2214 return enabled;
2215 }
2216
2217 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2218 {
2219 bool enabled;
2220
2221 if (ch == OMAP_DSS_CHANNEL_LCD)
2222 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2223 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2224 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2225 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2226 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2227 else
2228 BUG();
2229
2230 return enabled;
2231 }
2232
2233
2234 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2235 {
2236 int code;
2237
2238 switch (data_lines) {
2239 case 12:
2240 code = 0;
2241 break;
2242 case 16:
2243 code = 1;
2244 break;
2245 case 18:
2246 code = 2;
2247 break;
2248 case 24:
2249 code = 3;
2250 break;
2251 default:
2252 BUG();
2253 return;
2254 }
2255
2256 if (channel == OMAP_DSS_CHANNEL_LCD2)
2257 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2258 else
2259 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2260 }
2261
2262 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2263 {
2264 u32 l;
2265 int gpout0, gpout1;
2266
2267 switch (mode) {
2268 case DSS_IO_PAD_MODE_RESET:
2269 gpout0 = 0;
2270 gpout1 = 0;
2271 break;
2272 case DSS_IO_PAD_MODE_RFBI:
2273 gpout0 = 1;
2274 gpout1 = 0;
2275 break;
2276 case DSS_IO_PAD_MODE_BYPASS:
2277 gpout0 = 1;
2278 gpout1 = 1;
2279 break;
2280 default:
2281 BUG();
2282 return;
2283 }
2284
2285 l = dispc_read_reg(DISPC_CONTROL);
2286 l = FLD_MOD(l, gpout0, 15, 15);
2287 l = FLD_MOD(l, gpout1, 16, 16);
2288 dispc_write_reg(DISPC_CONTROL, l);
2289 }
2290
2291 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2292 {
2293 if (channel == OMAP_DSS_CHANNEL_LCD2)
2294 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2295 else
2296 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2297 }
2298
2299 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2300 int vsw, int vfp, int vbp)
2301 {
2302 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2303 if (hsw < 1 || hsw > 64 ||
2304 hfp < 1 || hfp > 256 ||
2305 hbp < 1 || hbp > 256 ||
2306 vsw < 1 || vsw > 64 ||
2307 vfp < 0 || vfp > 255 ||
2308 vbp < 0 || vbp > 255)
2309 return false;
2310 } else {
2311 if (hsw < 1 || hsw > 256 ||
2312 hfp < 1 || hfp > 4096 ||
2313 hbp < 1 || hbp > 4096 ||
2314 vsw < 1 || vsw > 256 ||
2315 vfp < 0 || vfp > 4095 ||
2316 vbp < 0 || vbp > 4095)
2317 return false;
2318 }
2319
2320 return true;
2321 }
2322
2323 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2324 {
2325 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2326 timings->hbp, timings->vsw,
2327 timings->vfp, timings->vbp);
2328 }
2329
2330 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2331 int hfp, int hbp, int vsw, int vfp, int vbp)
2332 {
2333 u32 timing_h, timing_v;
2334
2335 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2336 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2337 FLD_VAL(hbp-1, 27, 20);
2338
2339 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2340 FLD_VAL(vbp, 27, 20);
2341 } else {
2342 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2343 FLD_VAL(hbp-1, 31, 20);
2344
2345 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2346 FLD_VAL(vbp, 31, 20);
2347 }
2348
2349 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2350 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2351 }
2352
2353 /* change name to mode? */
2354 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2355 struct omap_video_timings *timings)
2356 {
2357 unsigned xtot, ytot;
2358 unsigned long ht, vt;
2359
2360 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2361 timings->hbp, timings->vsw,
2362 timings->vfp, timings->vbp))
2363 BUG();
2364
2365 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2366 timings->hbp, timings->vsw, timings->vfp,
2367 timings->vbp);
2368
2369 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2370
2371 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2372 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2373
2374 ht = (timings->pixel_clock * 1000) / xtot;
2375 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2376
2377 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2378 timings->y_res);
2379 DSSDBG("pck %u\n", timings->pixel_clock);
2380 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2381 timings->hsw, timings->hfp, timings->hbp,
2382 timings->vsw, timings->vfp, timings->vbp);
2383
2384 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2385 }
2386
2387 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2388 u16 pck_div)
2389 {
2390 BUG_ON(lck_div < 1);
2391 BUG_ON(pck_div < 1);
2392
2393 dispc_write_reg(DISPC_DIVISORo(channel),
2394 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2395 }
2396
2397 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2398 int *pck_div)
2399 {
2400 u32 l;
2401 l = dispc_read_reg(DISPC_DIVISORo(channel));
2402 *lck_div = FLD_GET(l, 23, 16);
2403 *pck_div = FLD_GET(l, 7, 0);
2404 }
2405
2406 unsigned long dispc_fclk_rate(void)
2407 {
2408 struct platform_device *dsidev;
2409 unsigned long r = 0;
2410
2411 switch (dss_get_dispc_clk_source()) {
2412 case OMAP_DSS_CLK_SRC_FCK:
2413 r = clk_get_rate(dispc.dss_clk);
2414 break;
2415 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2416 dsidev = dsi_get_dsidev_from_id(0);
2417 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2418 break;
2419 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2420 dsidev = dsi_get_dsidev_from_id(1);
2421 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2422 break;
2423 default:
2424 BUG();
2425 }
2426
2427 return r;
2428 }
2429
2430 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2431 {
2432 struct platform_device *dsidev;
2433 int lcd;
2434 unsigned long r;
2435 u32 l;
2436
2437 l = dispc_read_reg(DISPC_DIVISORo(channel));
2438
2439 lcd = FLD_GET(l, 23, 16);
2440
2441 switch (dss_get_lcd_clk_source(channel)) {
2442 case OMAP_DSS_CLK_SRC_FCK:
2443 r = clk_get_rate(dispc.dss_clk);
2444 break;
2445 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2446 dsidev = dsi_get_dsidev_from_id(0);
2447 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2448 break;
2449 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2450 dsidev = dsi_get_dsidev_from_id(1);
2451 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2452 break;
2453 default:
2454 BUG();
2455 }
2456
2457 return r / lcd;
2458 }
2459
2460 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2461 {
2462 unsigned long r;
2463
2464 if (dispc_mgr_is_lcd(channel)) {
2465 int pcd;
2466 u32 l;
2467
2468 l = dispc_read_reg(DISPC_DIVISORo(channel));
2469
2470 pcd = FLD_GET(l, 7, 0);
2471
2472 r = dispc_mgr_lclk_rate(channel);
2473
2474 return r / pcd;
2475 } else {
2476 struct omap_dss_device *dssdev =
2477 dispc_mgr_get_device(channel);
2478
2479 switch (dssdev->type) {
2480 case OMAP_DISPLAY_TYPE_VENC:
2481 return venc_get_pixel_clock();
2482 case OMAP_DISPLAY_TYPE_HDMI:
2483 return hdmi_get_pixel_clock();
2484 default:
2485 BUG();
2486 }
2487 }
2488 }
2489
2490 void dispc_dump_clocks(struct seq_file *s)
2491 {
2492 int lcd, pcd;
2493 u32 l;
2494 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2495 enum omap_dss_clk_source lcd_clk_src;
2496
2497 if (dispc_runtime_get())
2498 return;
2499
2500 seq_printf(s, "- DISPC -\n");
2501
2502 seq_printf(s, "dispc fclk source = %s (%s)\n",
2503 dss_get_generic_clk_source_name(dispc_clk_src),
2504 dss_feat_get_clk_source_name(dispc_clk_src));
2505
2506 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2507
2508 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2509 seq_printf(s, "- DISPC-CORE-CLK -\n");
2510 l = dispc_read_reg(DISPC_DIVISOR);
2511 lcd = FLD_GET(l, 23, 16);
2512
2513 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2514 (dispc_fclk_rate()/lcd), lcd);
2515 }
2516 seq_printf(s, "- LCD1 -\n");
2517
2518 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2519
2520 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2521 dss_get_generic_clk_source_name(lcd_clk_src),
2522 dss_feat_get_clk_source_name(lcd_clk_src));
2523
2524 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2525
2526 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2527 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2528 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2529 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2530 if (dss_has_feature(FEAT_MGR_LCD2)) {
2531 seq_printf(s, "- LCD2 -\n");
2532
2533 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2534
2535 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2536 dss_get_generic_clk_source_name(lcd_clk_src),
2537 dss_feat_get_clk_source_name(lcd_clk_src));
2538
2539 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2540
2541 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2542 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2543 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2544 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2545 }
2546
2547 dispc_runtime_put();
2548 }
2549
2550 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2551 void dispc_dump_irqs(struct seq_file *s)
2552 {
2553 unsigned long flags;
2554 struct dispc_irq_stats stats;
2555
2556 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2557
2558 stats = dispc.irq_stats;
2559 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2560 dispc.irq_stats.last_reset = jiffies;
2561
2562 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2563
2564 seq_printf(s, "period %u ms\n",
2565 jiffies_to_msecs(jiffies - stats.last_reset));
2566
2567 seq_printf(s, "irqs %d\n", stats.irq_count);
2568 #define PIS(x) \
2569 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2570
2571 PIS(FRAMEDONE);
2572 PIS(VSYNC);
2573 PIS(EVSYNC_EVEN);
2574 PIS(EVSYNC_ODD);
2575 PIS(ACBIAS_COUNT_STAT);
2576 PIS(PROG_LINE_NUM);
2577 PIS(GFX_FIFO_UNDERFLOW);
2578 PIS(GFX_END_WIN);
2579 PIS(PAL_GAMMA_MASK);
2580 PIS(OCP_ERR);
2581 PIS(VID1_FIFO_UNDERFLOW);
2582 PIS(VID1_END_WIN);
2583 PIS(VID2_FIFO_UNDERFLOW);
2584 PIS(VID2_END_WIN);
2585 if (dss_feat_get_num_ovls() > 3) {
2586 PIS(VID3_FIFO_UNDERFLOW);
2587 PIS(VID3_END_WIN);
2588 }
2589 PIS(SYNC_LOST);
2590 PIS(SYNC_LOST_DIGIT);
2591 PIS(WAKEUP);
2592 if (dss_has_feature(FEAT_MGR_LCD2)) {
2593 PIS(FRAMEDONE2);
2594 PIS(VSYNC2);
2595 PIS(ACBIAS_COUNT_STAT2);
2596 PIS(SYNC_LOST2);
2597 }
2598 #undef PIS
2599 }
2600 #endif
2601
2602 void dispc_dump_regs(struct seq_file *s)
2603 {
2604 int i, j;
2605 const char *mgr_names[] = {
2606 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2607 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2608 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2609 };
2610 const char *ovl_names[] = {
2611 [OMAP_DSS_GFX] = "GFX",
2612 [OMAP_DSS_VIDEO1] = "VID1",
2613 [OMAP_DSS_VIDEO2] = "VID2",
2614 [OMAP_DSS_VIDEO3] = "VID3",
2615 };
2616 const char **p_names;
2617
2618 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2619
2620 if (dispc_runtime_get())
2621 return;
2622
2623 /* DISPC common registers */
2624 DUMPREG(DISPC_REVISION);
2625 DUMPREG(DISPC_SYSCONFIG);
2626 DUMPREG(DISPC_SYSSTATUS);
2627 DUMPREG(DISPC_IRQSTATUS);
2628 DUMPREG(DISPC_IRQENABLE);
2629 DUMPREG(DISPC_CONTROL);
2630 DUMPREG(DISPC_CONFIG);
2631 DUMPREG(DISPC_CAPABLE);
2632 DUMPREG(DISPC_LINE_STATUS);
2633 DUMPREG(DISPC_LINE_NUMBER);
2634 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2635 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2636 DUMPREG(DISPC_GLOBAL_ALPHA);
2637 if (dss_has_feature(FEAT_MGR_LCD2)) {
2638 DUMPREG(DISPC_CONTROL2);
2639 DUMPREG(DISPC_CONFIG2);
2640 }
2641
2642 #undef DUMPREG
2643
2644 #define DISPC_REG(i, name) name(i)
2645 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2646 48 - strlen(#r) - strlen(p_names[i]), " ", \
2647 dispc_read_reg(DISPC_REG(i, r)))
2648
2649 p_names = mgr_names;
2650
2651 /* DISPC channel specific registers */
2652 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2653 DUMPREG(i, DISPC_DEFAULT_COLOR);
2654 DUMPREG(i, DISPC_TRANS_COLOR);
2655 DUMPREG(i, DISPC_SIZE_MGR);
2656
2657 if (i == OMAP_DSS_CHANNEL_DIGIT)
2658 continue;
2659
2660 DUMPREG(i, DISPC_DEFAULT_COLOR);
2661 DUMPREG(i, DISPC_TRANS_COLOR);
2662 DUMPREG(i, DISPC_TIMING_H);
2663 DUMPREG(i, DISPC_TIMING_V);
2664 DUMPREG(i, DISPC_POL_FREQ);
2665 DUMPREG(i, DISPC_DIVISORo);
2666 DUMPREG(i, DISPC_SIZE_MGR);
2667
2668 DUMPREG(i, DISPC_DATA_CYCLE1);
2669 DUMPREG(i, DISPC_DATA_CYCLE2);
2670 DUMPREG(i, DISPC_DATA_CYCLE3);
2671
2672 if (dss_has_feature(FEAT_CPR)) {
2673 DUMPREG(i, DISPC_CPR_COEF_R);
2674 DUMPREG(i, DISPC_CPR_COEF_G);
2675 DUMPREG(i, DISPC_CPR_COEF_B);
2676 }
2677 }
2678
2679 p_names = ovl_names;
2680
2681 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2682 DUMPREG(i, DISPC_OVL_BA0);
2683 DUMPREG(i, DISPC_OVL_BA1);
2684 DUMPREG(i, DISPC_OVL_POSITION);
2685 DUMPREG(i, DISPC_OVL_SIZE);
2686 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2687 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2688 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2689 DUMPREG(i, DISPC_OVL_ROW_INC);
2690 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2691 if (dss_has_feature(FEAT_PRELOAD))
2692 DUMPREG(i, DISPC_OVL_PRELOAD);
2693
2694 if (i == OMAP_DSS_GFX) {
2695 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2696 DUMPREG(i, DISPC_OVL_TABLE_BA);
2697 continue;
2698 }
2699
2700 DUMPREG(i, DISPC_OVL_FIR);
2701 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2702 DUMPREG(i, DISPC_OVL_ACCU0);
2703 DUMPREG(i, DISPC_OVL_ACCU1);
2704 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2705 DUMPREG(i, DISPC_OVL_BA0_UV);
2706 DUMPREG(i, DISPC_OVL_BA1_UV);
2707 DUMPREG(i, DISPC_OVL_FIR2);
2708 DUMPREG(i, DISPC_OVL_ACCU2_0);
2709 DUMPREG(i, DISPC_OVL_ACCU2_1);
2710 }
2711 if (dss_has_feature(FEAT_ATTR2))
2712 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2713 if (dss_has_feature(FEAT_PRELOAD))
2714 DUMPREG(i, DISPC_OVL_PRELOAD);
2715 }
2716
2717 #undef DISPC_REG
2718 #undef DUMPREG
2719
2720 #define DISPC_REG(plane, name, i) name(plane, i)
2721 #define DUMPREG(plane, name, i) \
2722 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2723 46 - strlen(#name) - strlen(p_names[plane]), " ", \
2724 dispc_read_reg(DISPC_REG(plane, name, i)))
2725
2726 /* Video pipeline coefficient registers */
2727
2728 /* start from OMAP_DSS_VIDEO1 */
2729 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2730 for (j = 0; j < 8; j++)
2731 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2732
2733 for (j = 0; j < 8; j++)
2734 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2735
2736 for (j = 0; j < 5; j++)
2737 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2738
2739 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2740 for (j = 0; j < 8; j++)
2741 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2742 }
2743
2744 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2745 for (j = 0; j < 8; j++)
2746 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2747
2748 for (j = 0; j < 8; j++)
2749 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2750
2751 for (j = 0; j < 8; j++)
2752 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2753 }
2754 }
2755
2756 dispc_runtime_put();
2757
2758 #undef DISPC_REG
2759 #undef DUMPREG
2760 }
2761
2762 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2763 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2764 u8 acb)
2765 {
2766 u32 l = 0;
2767
2768 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2769 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2770
2771 l |= FLD_VAL(onoff, 17, 17);
2772 l |= FLD_VAL(rf, 16, 16);
2773 l |= FLD_VAL(ieo, 15, 15);
2774 l |= FLD_VAL(ipc, 14, 14);
2775 l |= FLD_VAL(ihs, 13, 13);
2776 l |= FLD_VAL(ivs, 12, 12);
2777 l |= FLD_VAL(acbi, 11, 8);
2778 l |= FLD_VAL(acb, 7, 0);
2779
2780 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2781 }
2782
2783 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2784 enum omap_panel_config config, u8 acbi, u8 acb)
2785 {
2786 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2787 (config & OMAP_DSS_LCD_RF) != 0,
2788 (config & OMAP_DSS_LCD_IEO) != 0,
2789 (config & OMAP_DSS_LCD_IPC) != 0,
2790 (config & OMAP_DSS_LCD_IHS) != 0,
2791 (config & OMAP_DSS_LCD_IVS) != 0,
2792 acbi, acb);
2793 }
2794
2795 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2796 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2797 struct dispc_clock_info *cinfo)
2798 {
2799 u16 pcd_min, pcd_max;
2800 unsigned long best_pck;
2801 u16 best_ld, cur_ld;
2802 u16 best_pd, cur_pd;
2803
2804 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2805 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2806
2807 if (!is_tft)
2808 pcd_min = 3;
2809
2810 best_pck = 0;
2811 best_ld = 0;
2812 best_pd = 0;
2813
2814 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2815 unsigned long lck = fck / cur_ld;
2816
2817 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2818 unsigned long pck = lck / cur_pd;
2819 long old_delta = abs(best_pck - req_pck);
2820 long new_delta = abs(pck - req_pck);
2821
2822 if (best_pck == 0 || new_delta < old_delta) {
2823 best_pck = pck;
2824 best_ld = cur_ld;
2825 best_pd = cur_pd;
2826
2827 if (pck == req_pck)
2828 goto found;
2829 }
2830
2831 if (pck < req_pck)
2832 break;
2833 }
2834
2835 if (lck / pcd_min < req_pck)
2836 break;
2837 }
2838
2839 found:
2840 cinfo->lck_div = best_ld;
2841 cinfo->pck_div = best_pd;
2842 cinfo->lck = fck / cinfo->lck_div;
2843 cinfo->pck = cinfo->lck / cinfo->pck_div;
2844 }
2845
2846 /* calculate clock rates using dividers in cinfo */
2847 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2848 struct dispc_clock_info *cinfo)
2849 {
2850 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2851 return -EINVAL;
2852 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2853 return -EINVAL;
2854
2855 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2856 cinfo->pck = cinfo->lck / cinfo->pck_div;
2857
2858 return 0;
2859 }
2860
2861 int dispc_mgr_set_clock_div(enum omap_channel channel,
2862 struct dispc_clock_info *cinfo)
2863 {
2864 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2865 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2866
2867 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2868
2869 return 0;
2870 }
2871
2872 int dispc_mgr_get_clock_div(enum omap_channel channel,
2873 struct dispc_clock_info *cinfo)
2874 {
2875 unsigned long fck;
2876
2877 fck = dispc_fclk_rate();
2878
2879 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2880 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2881
2882 cinfo->lck = fck / cinfo->lck_div;
2883 cinfo->pck = cinfo->lck / cinfo->pck_div;
2884
2885 return 0;
2886 }
2887
2888 /* dispc.irq_lock has to be locked by the caller */
2889 static void _omap_dispc_set_irqs(void)
2890 {
2891 u32 mask;
2892 u32 old_mask;
2893 int i;
2894 struct omap_dispc_isr_data *isr_data;
2895
2896 mask = dispc.irq_error_mask;
2897
2898 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2899 isr_data = &dispc.registered_isr[i];
2900
2901 if (isr_data->isr == NULL)
2902 continue;
2903
2904 mask |= isr_data->mask;
2905 }
2906
2907 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2908 /* clear the irqstatus for newly enabled irqs */
2909 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2910
2911 dispc_write_reg(DISPC_IRQENABLE, mask);
2912 }
2913
2914 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2915 {
2916 int i;
2917 int ret;
2918 unsigned long flags;
2919 struct omap_dispc_isr_data *isr_data;
2920
2921 if (isr == NULL)
2922 return -EINVAL;
2923
2924 spin_lock_irqsave(&dispc.irq_lock, flags);
2925
2926 /* check for duplicate entry */
2927 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2928 isr_data = &dispc.registered_isr[i];
2929 if (isr_data->isr == isr && isr_data->arg == arg &&
2930 isr_data->mask == mask) {
2931 ret = -EINVAL;
2932 goto err;
2933 }
2934 }
2935
2936 isr_data = NULL;
2937 ret = -EBUSY;
2938
2939 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2940 isr_data = &dispc.registered_isr[i];
2941
2942 if (isr_data->isr != NULL)
2943 continue;
2944
2945 isr_data->isr = isr;
2946 isr_data->arg = arg;
2947 isr_data->mask = mask;
2948 ret = 0;
2949
2950 break;
2951 }
2952
2953 if (ret)
2954 goto err;
2955
2956 _omap_dispc_set_irqs();
2957
2958 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2959
2960 return 0;
2961 err:
2962 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2963
2964 return ret;
2965 }
2966 EXPORT_SYMBOL(omap_dispc_register_isr);
2967
2968 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2969 {
2970 int i;
2971 unsigned long flags;
2972 int ret = -EINVAL;
2973 struct omap_dispc_isr_data *isr_data;
2974
2975 spin_lock_irqsave(&dispc.irq_lock, flags);
2976
2977 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2978 isr_data = &dispc.registered_isr[i];
2979 if (isr_data->isr != isr || isr_data->arg != arg ||
2980 isr_data->mask != mask)
2981 continue;
2982
2983 /* found the correct isr */
2984
2985 isr_data->isr = NULL;
2986 isr_data->arg = NULL;
2987 isr_data->mask = 0;
2988
2989 ret = 0;
2990 break;
2991 }
2992
2993 if (ret == 0)
2994 _omap_dispc_set_irqs();
2995
2996 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2997
2998 return ret;
2999 }
3000 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3001
3002 #ifdef DEBUG
3003 static void print_irq_status(u32 status)
3004 {
3005 if ((status & dispc.irq_error_mask) == 0)
3006 return;
3007
3008 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3009
3010 #define PIS(x) \
3011 if (status & DISPC_IRQ_##x) \
3012 printk(#x " ");
3013 PIS(GFX_FIFO_UNDERFLOW);
3014 PIS(OCP_ERR);
3015 PIS(VID1_FIFO_UNDERFLOW);
3016 PIS(VID2_FIFO_UNDERFLOW);
3017 if (dss_feat_get_num_ovls() > 3)
3018 PIS(VID3_FIFO_UNDERFLOW);
3019 PIS(SYNC_LOST);
3020 PIS(SYNC_LOST_DIGIT);
3021 if (dss_has_feature(FEAT_MGR_LCD2))
3022 PIS(SYNC_LOST2);
3023 #undef PIS
3024
3025 printk("\n");
3026 }
3027 #endif
3028
3029 /* Called from dss.c. Note that we don't touch clocks here,
3030 * but we presume they are on because we got an IRQ. However,
3031 * an irq handler may turn the clocks off, so we may not have
3032 * clock later in the function. */
3033 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3034 {
3035 int i;
3036 u32 irqstatus, irqenable;
3037 u32 handledirqs = 0;
3038 u32 unhandled_errors;
3039 struct omap_dispc_isr_data *isr_data;
3040 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3041
3042 spin_lock(&dispc.irq_lock);
3043
3044 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3045 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3046
3047 /* IRQ is not for us */
3048 if (!(irqstatus & irqenable)) {
3049 spin_unlock(&dispc.irq_lock);
3050 return IRQ_NONE;
3051 }
3052
3053 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3054 spin_lock(&dispc.irq_stats_lock);
3055 dispc.irq_stats.irq_count++;
3056 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3057 spin_unlock(&dispc.irq_stats_lock);
3058 #endif
3059
3060 #ifdef DEBUG
3061 if (dss_debug)
3062 print_irq_status(irqstatus);
3063 #endif
3064 /* Ack the interrupt. Do it here before clocks are possibly turned
3065 * off */
3066 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3067 /* flush posted write */
3068 dispc_read_reg(DISPC_IRQSTATUS);
3069
3070 /* make a copy and unlock, so that isrs can unregister
3071 * themselves */
3072 memcpy(registered_isr, dispc.registered_isr,
3073 sizeof(registered_isr));
3074
3075 spin_unlock(&dispc.irq_lock);
3076
3077 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3078 isr_data = &registered_isr[i];
3079
3080 if (!isr_data->isr)
3081 continue;
3082
3083 if (isr_data->mask & irqstatus) {
3084 isr_data->isr(isr_data->arg, irqstatus);
3085 handledirqs |= isr_data->mask;
3086 }
3087 }
3088
3089 spin_lock(&dispc.irq_lock);
3090
3091 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3092
3093 if (unhandled_errors) {
3094 dispc.error_irqs |= unhandled_errors;
3095
3096 dispc.irq_error_mask &= ~unhandled_errors;
3097 _omap_dispc_set_irqs();
3098
3099 schedule_work(&dispc.error_work);
3100 }
3101
3102 spin_unlock(&dispc.irq_lock);
3103
3104 return IRQ_HANDLED;
3105 }
3106
3107 static void dispc_error_worker(struct work_struct *work)
3108 {
3109 int i;
3110 u32 errors;
3111 unsigned long flags;
3112 static const unsigned fifo_underflow_bits[] = {
3113 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3114 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3115 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3116 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3117 };
3118
3119 static const unsigned sync_lost_bits[] = {
3120 DISPC_IRQ_SYNC_LOST,
3121 DISPC_IRQ_SYNC_LOST_DIGIT,
3122 DISPC_IRQ_SYNC_LOST2,
3123 };
3124
3125 spin_lock_irqsave(&dispc.irq_lock, flags);
3126 errors = dispc.error_irqs;
3127 dispc.error_irqs = 0;
3128 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3129
3130 dispc_runtime_get();
3131
3132 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3133 struct omap_overlay *ovl;
3134 unsigned bit;
3135
3136 ovl = omap_dss_get_overlay(i);
3137 bit = fifo_underflow_bits[i];
3138
3139 if (bit & errors) {
3140 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3141 ovl->name);
3142 dispc_ovl_enable(ovl->id, false);
3143 dispc_mgr_go(ovl->manager->id);
3144 mdelay(50);
3145 }
3146 }
3147
3148 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3149 struct omap_overlay_manager *mgr;
3150 unsigned bit;
3151
3152 mgr = omap_dss_get_overlay_manager(i);
3153 bit = sync_lost_bits[i];
3154
3155 if (bit & errors) {
3156 struct omap_dss_device *dssdev = mgr->device;
3157 bool enable;
3158
3159 DSSERR("SYNC_LOST on channel %s, restarting the output "
3160 "with video overlays disabled\n",
3161 mgr->name);
3162
3163 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3164 dssdev->driver->disable(dssdev);
3165
3166 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3167 struct omap_overlay *ovl;
3168 ovl = omap_dss_get_overlay(i);
3169
3170 if (ovl->id != OMAP_DSS_GFX &&
3171 ovl->manager == mgr)
3172 dispc_ovl_enable(ovl->id, false);
3173 }
3174
3175 dispc_mgr_go(mgr->id);
3176 mdelay(50);
3177
3178 if (enable)
3179 dssdev->driver->enable(dssdev);
3180 }
3181 }
3182
3183 if (errors & DISPC_IRQ_OCP_ERR) {
3184 DSSERR("OCP_ERR\n");
3185 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3186 struct omap_overlay_manager *mgr;
3187 mgr = omap_dss_get_overlay_manager(i);
3188 mgr->device->driver->disable(mgr->device);
3189 }
3190 }
3191
3192 spin_lock_irqsave(&dispc.irq_lock, flags);
3193 dispc.irq_error_mask |= errors;
3194 _omap_dispc_set_irqs();
3195 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3196
3197 dispc_runtime_put();
3198 }
3199
3200 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3201 {
3202 void dispc_irq_wait_handler(void *data, u32 mask)
3203 {
3204 complete((struct completion *)data);
3205 }
3206
3207 int r;
3208 DECLARE_COMPLETION_ONSTACK(completion);
3209
3210 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3211 irqmask);
3212
3213 if (r)
3214 return r;
3215
3216 timeout = wait_for_completion_timeout(&completion, timeout);
3217
3218 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3219
3220 if (timeout == 0)
3221 return -ETIMEDOUT;
3222
3223 if (timeout == -ERESTARTSYS)
3224 return -ERESTARTSYS;
3225
3226 return 0;
3227 }
3228
3229 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3230 unsigned long timeout)
3231 {
3232 void dispc_irq_wait_handler(void *data, u32 mask)
3233 {
3234 complete((struct completion *)data);
3235 }
3236
3237 int r;
3238 DECLARE_COMPLETION_ONSTACK(completion);
3239
3240 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3241 irqmask);
3242
3243 if (r)
3244 return r;
3245
3246 timeout = wait_for_completion_interruptible_timeout(&completion,
3247 timeout);
3248
3249 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3250
3251 if (timeout == 0)
3252 return -ETIMEDOUT;
3253
3254 if (timeout == -ERESTARTSYS)
3255 return -ERESTARTSYS;
3256
3257 return 0;
3258 }
3259
3260 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3261 void dispc_fake_vsync_irq(void)
3262 {
3263 u32 irqstatus = DISPC_IRQ_VSYNC;
3264 int i;
3265
3266 WARN_ON(!in_interrupt());
3267
3268 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3269 struct omap_dispc_isr_data *isr_data;
3270 isr_data = &dispc.registered_isr[i];
3271
3272 if (!isr_data->isr)
3273 continue;
3274
3275 if (isr_data->mask & irqstatus)
3276 isr_data->isr(isr_data->arg, irqstatus);
3277 }
3278 }
3279 #endif
3280
3281 static void _omap_dispc_initialize_irq(void)
3282 {
3283 unsigned long flags;
3284
3285 spin_lock_irqsave(&dispc.irq_lock, flags);
3286
3287 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3288
3289 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3290 if (dss_has_feature(FEAT_MGR_LCD2))
3291 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3292 if (dss_feat_get_num_ovls() > 3)
3293 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3294
3295 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3296 * so clear it */
3297 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3298
3299 _omap_dispc_set_irqs();
3300
3301 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3302 }
3303
3304 void dispc_enable_sidle(void)
3305 {
3306 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3307 }
3308
3309 void dispc_disable_sidle(void)
3310 {
3311 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3312 }
3313
3314 static void _omap_dispc_initial_config(void)
3315 {
3316 u32 l;
3317
3318 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3319 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3320 l = dispc_read_reg(DISPC_DIVISOR);
3321 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3322 l = FLD_MOD(l, 1, 0, 0);
3323 l = FLD_MOD(l, 1, 23, 16);
3324 dispc_write_reg(DISPC_DIVISOR, l);
3325 }
3326
3327 /* FUNCGATED */
3328 if (dss_has_feature(FEAT_FUNCGATED))
3329 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3330
3331 /* L3 firewall setting: enable access to OCM RAM */
3332 /* XXX this should be somewhere in plat-omap */
3333 if (cpu_is_omap24xx())
3334 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3335
3336 _dispc_setup_color_conv_coef();
3337
3338 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3339
3340 dispc_read_plane_fifo_sizes();
3341
3342 dispc_configure_burst_sizes();
3343
3344 dispc_ovl_enable_zorder_planes();
3345 }
3346
3347 /* DISPC HW IP initialisation */
3348 static int omap_dispchw_probe(struct platform_device *pdev)
3349 {
3350 u32 rev;
3351 int r = 0;
3352 struct resource *dispc_mem;
3353 struct clk *clk;
3354
3355 dispc.pdev = pdev;
3356
3357 clk = clk_get(&pdev->dev, "fck");
3358 if (IS_ERR(clk)) {
3359 DSSERR("can't get fck\n");
3360 r = PTR_ERR(clk);
3361 goto err_get_clk;
3362 }
3363
3364 dispc.dss_clk = clk;
3365
3366 spin_lock_init(&dispc.irq_lock);
3367
3368 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3369 spin_lock_init(&dispc.irq_stats_lock);
3370 dispc.irq_stats.last_reset = jiffies;
3371 #endif
3372
3373 INIT_WORK(&dispc.error_work, dispc_error_worker);
3374
3375 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3376 if (!dispc_mem) {
3377 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3378 r = -EINVAL;
3379 goto err_ioremap;
3380 }
3381 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3382 if (!dispc.base) {
3383 DSSERR("can't ioremap DISPC\n");
3384 r = -ENOMEM;
3385 goto err_ioremap;
3386 }
3387 dispc.irq = platform_get_irq(dispc.pdev, 0);
3388 if (dispc.irq < 0) {
3389 DSSERR("platform_get_irq failed\n");
3390 r = -ENODEV;
3391 goto err_irq;
3392 }
3393
3394 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3395 "OMAP DISPC", dispc.pdev);
3396 if (r < 0) {
3397 DSSERR("request_irq failed\n");
3398 goto err_irq;
3399 }
3400
3401 pm_runtime_enable(&pdev->dev);
3402
3403 r = dispc_runtime_get();
3404 if (r)
3405 goto err_runtime_get;
3406
3407 _omap_dispc_initial_config();
3408
3409 _omap_dispc_initialize_irq();
3410
3411 rev = dispc_read_reg(DISPC_REVISION);
3412 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3413 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3414
3415 dispc_runtime_put();
3416
3417 return 0;
3418
3419 err_runtime_get:
3420 pm_runtime_disable(&pdev->dev);
3421 free_irq(dispc.irq, dispc.pdev);
3422 err_irq:
3423 iounmap(dispc.base);
3424 err_ioremap:
3425 clk_put(dispc.dss_clk);
3426 err_get_clk:
3427 return r;
3428 }
3429
3430 static int omap_dispchw_remove(struct platform_device *pdev)
3431 {
3432 pm_runtime_disable(&pdev->dev);
3433
3434 clk_put(dispc.dss_clk);
3435
3436 free_irq(dispc.irq, dispc.pdev);
3437 iounmap(dispc.base);
3438 return 0;
3439 }
3440
3441 static int dispc_runtime_suspend(struct device *dev)
3442 {
3443 dispc_save_context();
3444 dss_runtime_put();
3445
3446 return 0;
3447 }
3448
3449 static int dispc_runtime_resume(struct device *dev)
3450 {
3451 int r;
3452
3453 r = dss_runtime_get();
3454 if (r < 0)
3455 return r;
3456
3457 dispc_restore_context();
3458
3459 return 0;
3460 }
3461
3462 static const struct dev_pm_ops dispc_pm_ops = {
3463 .runtime_suspend = dispc_runtime_suspend,
3464 .runtime_resume = dispc_runtime_resume,
3465 };
3466
3467 static struct platform_driver omap_dispchw_driver = {
3468 .probe = omap_dispchw_probe,
3469 .remove = omap_dispchw_remove,
3470 .driver = {
3471 .name = "omapdss_dispc",
3472 .owner = THIS_MODULE,
3473 .pm = &dispc_pm_ops,
3474 },
3475 };
3476
3477 int dispc_init_platform_driver(void)
3478 {
3479 return platform_driver_register(&omap_dispchw_driver);
3480 }
3481
3482 void dispc_uninit_platform_driver(void)
3483 {
3484 return platform_driver_unregister(&omap_dispchw_driver);
3485 }
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