2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
47 #include "dss_features.h"
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg
{ u16 idx
; };
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
102 /* DSI_PLL_CTRL_SCP */
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203 typedef void (*omap_dsi_isr_t
) (void *arg
, u32 mask
);
205 #define DSI_MAX_NR_ISRS 2
206 #define DSI_MAX_NR_LANES 5
208 enum dsi_lane_function
{
217 struct dsi_lane_config
{
218 enum dsi_lane_function function
;
222 struct dsi_isr_data
{
230 DSI_FIFO_SIZE_32
= 1,
231 DSI_FIFO_SIZE_64
= 2,
232 DSI_FIFO_SIZE_96
= 3,
233 DSI_FIFO_SIZE_128
= 4,
237 DSI_VC_SOURCE_L4
= 0,
241 struct dsi_update_region
{
243 struct omap_dss_device
*device
;
246 struct dsi_irq_stats
{
247 unsigned long last_reset
;
249 unsigned dsi_irqs
[32];
250 unsigned vc_irqs
[4][32];
251 unsigned cio_irqs
[32];
254 struct dsi_isr_tables
{
255 struct dsi_isr_data isr_table
[DSI_MAX_NR_ISRS
];
256 struct dsi_isr_data isr_table_vc
[4][DSI_MAX_NR_ISRS
];
257 struct dsi_isr_data isr_table_cio
[DSI_MAX_NR_ISRS
];
261 struct platform_device
*pdev
;
269 int (*enable_pads
)(int dsi_id
, unsigned lane_mask
);
270 void (*disable_pads
)(int dsi_id
, unsigned lane_mask
);
272 struct dsi_clock_info current_cinfo
;
274 bool vdds_dsi_enabled
;
275 struct regulator
*vdds_dsi_reg
;
278 enum dsi_vc_source source
;
279 struct omap_dss_device
*dssdev
;
280 enum fifo_size fifo_size
;
285 struct semaphore bus_lock
;
290 struct dsi_isr_tables isr_tables
;
291 /* space for a copy used by the interrupt handler */
292 struct dsi_isr_tables isr_tables_copy
;
295 struct dsi_update_region update_region
;
300 void (*framedone_callback
)(int, void *);
301 void *framedone_data
;
303 struct delayed_work framedone_timeout_work
;
305 #ifdef DSI_CATCH_MISSING_TE
306 struct timer_list te_timer
;
309 unsigned long cache_req_pck
;
310 unsigned long cache_clk_freq
;
311 struct dsi_clock_info cache_cinfo
;
314 spinlock_t errors_lock
;
316 ktime_t perf_setup_time
;
317 ktime_t perf_start_time
;
322 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
323 spinlock_t irq_stats_lock
;
324 struct dsi_irq_stats irq_stats
;
326 /* DSI PLL Parameter Ranges */
327 unsigned long regm_max
, regn_max
;
328 unsigned long regm_dispc_max
, regm_dsi_max
;
329 unsigned long fint_min
, fint_max
;
330 unsigned long lpdiv_max
;
332 unsigned num_lanes_supported
;
334 struct dsi_lane_config lanes
[DSI_MAX_NR_LANES
];
335 unsigned num_lanes_used
;
337 unsigned scp_clk_refcount
;
340 struct dsi_packet_sent_handler_data
{
341 struct platform_device
*dsidev
;
342 struct completion
*completion
;
345 static struct platform_device
*dsi_pdev_map
[MAX_NUM_DSI
];
348 static unsigned int dsi_perf
;
349 module_param_named(dsi_perf
, dsi_perf
, bool, 0644);
352 static inline struct dsi_data
*dsi_get_dsidrv_data(struct platform_device
*dsidev
)
354 return dev_get_drvdata(&dsidev
->dev
);
357 static inline struct platform_device
*dsi_get_dsidev_from_dssdev(struct omap_dss_device
*dssdev
)
359 return dsi_pdev_map
[dssdev
->phy
.dsi
.module
];
362 struct platform_device
*dsi_get_dsidev_from_id(int module
)
364 return dsi_pdev_map
[module
];
367 static inline int dsi_get_dsidev_id(struct platform_device
*dsidev
)
372 static inline void dsi_write_reg(struct platform_device
*dsidev
,
373 const struct dsi_reg idx
, u32 val
)
375 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
377 __raw_writel(val
, dsi
->base
+ idx
.idx
);
380 static inline u32
dsi_read_reg(struct platform_device
*dsidev
,
381 const struct dsi_reg idx
)
383 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
385 return __raw_readl(dsi
->base
+ idx
.idx
);
388 void dsi_bus_lock(struct omap_dss_device
*dssdev
)
390 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
391 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
393 down(&dsi
->bus_lock
);
395 EXPORT_SYMBOL(dsi_bus_lock
);
397 void dsi_bus_unlock(struct omap_dss_device
*dssdev
)
399 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
400 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
404 EXPORT_SYMBOL(dsi_bus_unlock
);
406 static bool dsi_bus_is_locked(struct platform_device
*dsidev
)
408 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
410 return dsi
->bus_lock
.count
== 0;
413 static void dsi_completion_handler(void *data
, u32 mask
)
415 complete((struct completion
*)data
);
418 static inline int wait_for_bit_change(struct platform_device
*dsidev
,
419 const struct dsi_reg idx
, int bitnum
, int value
)
423 while (REG_GET(dsidev
, idx
, bitnum
, bitnum
) != value
) {
431 u8
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt
)
434 case OMAP_DSS_DSI_FMT_RGB888
:
435 case OMAP_DSS_DSI_FMT_RGB666
:
437 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
439 case OMAP_DSS_DSI_FMT_RGB565
:
447 static void dsi_perf_mark_setup(struct platform_device
*dsidev
)
449 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
450 dsi
->perf_setup_time
= ktime_get();
453 static void dsi_perf_mark_start(struct platform_device
*dsidev
)
455 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
456 dsi
->perf_start_time
= ktime_get();
459 static void dsi_perf_show(struct platform_device
*dsidev
, const char *name
)
461 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
462 struct omap_dss_device
*dssdev
= dsi
->update_region
.device
;
463 ktime_t t
, setup_time
, trans_time
;
465 u32 setup_us
, trans_us
, total_us
;
472 setup_time
= ktime_sub(dsi
->perf_start_time
, dsi
->perf_setup_time
);
473 setup_us
= (u32
)ktime_to_us(setup_time
);
477 trans_time
= ktime_sub(t
, dsi
->perf_start_time
);
478 trans_us
= (u32
)ktime_to_us(trans_time
);
482 total_us
= setup_us
+ trans_us
;
484 total_bytes
= dsi
->update_region
.w
*
485 dsi
->update_region
.h
*
486 dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
) / 8;
488 printk(KERN_INFO
"DSI(%s): %u us + %u us = %u us (%uHz), "
489 "%u bytes, %u kbytes/sec\n",
494 1000*1000 / total_us
,
496 total_bytes
* 1000 / total_us
);
499 static inline void dsi_perf_mark_setup(struct platform_device
*dsidev
)
503 static inline void dsi_perf_mark_start(struct platform_device
*dsidev
)
507 static inline void dsi_perf_show(struct platform_device
*dsidev
,
513 static void print_irq_status(u32 status
)
519 if ((status
& ~DSI_IRQ_CHANNEL_MASK
) == 0)
522 printk(KERN_DEBUG
"DSI IRQ: 0x%x: ", status
);
525 if (status & DSI_IRQ_##x) \
551 static void print_irq_status_vc(int channel
, u32 status
)
557 if ((status
& ~DSI_VC_IRQ_PACKET_SENT
) == 0)
560 printk(KERN_DEBUG
"DSI VC(%d) IRQ 0x%x: ", channel
, status
);
563 if (status & DSI_VC_IRQ_##x) \
580 static void print_irq_status_cio(u32 status
)
585 printk(KERN_DEBUG
"DSI CIO IRQ 0x%x: ", status
);
588 if (status & DSI_CIO_IRQ_##x) \
602 PIS(ERRCONTENTIONLP0_1
);
603 PIS(ERRCONTENTIONLP1_1
);
604 PIS(ERRCONTENTIONLP0_2
);
605 PIS(ERRCONTENTIONLP1_2
);
606 PIS(ERRCONTENTIONLP0_3
);
607 PIS(ERRCONTENTIONLP1_3
);
608 PIS(ULPSACTIVENOT_ALL0
);
609 PIS(ULPSACTIVENOT_ALL1
);
615 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
616 static void dsi_collect_irq_stats(struct platform_device
*dsidev
, u32 irqstatus
,
617 u32
*vcstatus
, u32 ciostatus
)
619 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
622 spin_lock(&dsi
->irq_stats_lock
);
624 dsi
->irq_stats
.irq_count
++;
625 dss_collect_irq_stats(irqstatus
, dsi
->irq_stats
.dsi_irqs
);
627 for (i
= 0; i
< 4; ++i
)
628 dss_collect_irq_stats(vcstatus
[i
], dsi
->irq_stats
.vc_irqs
[i
]);
630 dss_collect_irq_stats(ciostatus
, dsi
->irq_stats
.cio_irqs
);
632 spin_unlock(&dsi
->irq_stats_lock
);
635 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
638 static int debug_irq
;
640 static void dsi_handle_irq_errors(struct platform_device
*dsidev
, u32 irqstatus
,
641 u32
*vcstatus
, u32 ciostatus
)
643 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
646 if (irqstatus
& DSI_IRQ_ERROR_MASK
) {
647 DSSERR("DSI error, irqstatus %x\n", irqstatus
);
648 print_irq_status(irqstatus
);
649 spin_lock(&dsi
->errors_lock
);
650 dsi
->errors
|= irqstatus
& DSI_IRQ_ERROR_MASK
;
651 spin_unlock(&dsi
->errors_lock
);
652 } else if (debug_irq
) {
653 print_irq_status(irqstatus
);
656 for (i
= 0; i
< 4; ++i
) {
657 if (vcstatus
[i
] & DSI_VC_IRQ_ERROR_MASK
) {
658 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
660 print_irq_status_vc(i
, vcstatus
[i
]);
661 } else if (debug_irq
) {
662 print_irq_status_vc(i
, vcstatus
[i
]);
666 if (ciostatus
& DSI_CIO_IRQ_ERROR_MASK
) {
667 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus
);
668 print_irq_status_cio(ciostatus
);
669 } else if (debug_irq
) {
670 print_irq_status_cio(ciostatus
);
674 static void dsi_call_isrs(struct dsi_isr_data
*isr_array
,
675 unsigned isr_array_size
, u32 irqstatus
)
677 struct dsi_isr_data
*isr_data
;
680 for (i
= 0; i
< isr_array_size
; i
++) {
681 isr_data
= &isr_array
[i
];
682 if (isr_data
->isr
&& isr_data
->mask
& irqstatus
)
683 isr_data
->isr(isr_data
->arg
, irqstatus
);
687 static void dsi_handle_isrs(struct dsi_isr_tables
*isr_tables
,
688 u32 irqstatus
, u32
*vcstatus
, u32 ciostatus
)
692 dsi_call_isrs(isr_tables
->isr_table
,
693 ARRAY_SIZE(isr_tables
->isr_table
),
696 for (i
= 0; i
< 4; ++i
) {
697 if (vcstatus
[i
] == 0)
699 dsi_call_isrs(isr_tables
->isr_table_vc
[i
],
700 ARRAY_SIZE(isr_tables
->isr_table_vc
[i
]),
705 dsi_call_isrs(isr_tables
->isr_table_cio
,
706 ARRAY_SIZE(isr_tables
->isr_table_cio
),
710 static irqreturn_t
omap_dsi_irq_handler(int irq
, void *arg
)
712 struct platform_device
*dsidev
;
713 struct dsi_data
*dsi
;
714 u32 irqstatus
, vcstatus
[4], ciostatus
;
717 dsidev
= (struct platform_device
*) arg
;
718 dsi
= dsi_get_dsidrv_data(dsidev
);
720 spin_lock(&dsi
->irq_lock
);
722 irqstatus
= dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
724 /* IRQ is not for us */
726 spin_unlock(&dsi
->irq_lock
);
730 dsi_write_reg(dsidev
, DSI_IRQSTATUS
, irqstatus
& ~DSI_IRQ_CHANNEL_MASK
);
731 /* flush posted write */
732 dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
734 for (i
= 0; i
< 4; ++i
) {
735 if ((irqstatus
& (1 << i
)) == 0) {
740 vcstatus
[i
] = dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
742 dsi_write_reg(dsidev
, DSI_VC_IRQSTATUS(i
), vcstatus
[i
]);
743 /* flush posted write */
744 dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
747 if (irqstatus
& DSI_IRQ_COMPLEXIO_ERR
) {
748 ciostatus
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
750 dsi_write_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
, ciostatus
);
751 /* flush posted write */
752 dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
757 #ifdef DSI_CATCH_MISSING_TE
758 if (irqstatus
& DSI_IRQ_TE_TRIGGER
)
759 del_timer(&dsi
->te_timer
);
762 /* make a copy and unlock, so that isrs can unregister
764 memcpy(&dsi
->isr_tables_copy
, &dsi
->isr_tables
,
765 sizeof(dsi
->isr_tables
));
767 spin_unlock(&dsi
->irq_lock
);
769 dsi_handle_isrs(&dsi
->isr_tables_copy
, irqstatus
, vcstatus
, ciostatus
);
771 dsi_handle_irq_errors(dsidev
, irqstatus
, vcstatus
, ciostatus
);
773 dsi_collect_irq_stats(dsidev
, irqstatus
, vcstatus
, ciostatus
);
778 /* dsi->irq_lock has to be locked by the caller */
779 static void _omap_dsi_configure_irqs(struct platform_device
*dsidev
,
780 struct dsi_isr_data
*isr_array
,
781 unsigned isr_array_size
, u32 default_mask
,
782 const struct dsi_reg enable_reg
,
783 const struct dsi_reg status_reg
)
785 struct dsi_isr_data
*isr_data
;
792 for (i
= 0; i
< isr_array_size
; i
++) {
793 isr_data
= &isr_array
[i
];
795 if (isr_data
->isr
== NULL
)
798 mask
|= isr_data
->mask
;
801 old_mask
= dsi_read_reg(dsidev
, enable_reg
);
802 /* clear the irqstatus for newly enabled irqs */
803 dsi_write_reg(dsidev
, status_reg
, (mask
^ old_mask
) & mask
);
804 dsi_write_reg(dsidev
, enable_reg
, mask
);
806 /* flush posted writes */
807 dsi_read_reg(dsidev
, enable_reg
);
808 dsi_read_reg(dsidev
, status_reg
);
811 /* dsi->irq_lock has to be locked by the caller */
812 static void _omap_dsi_set_irqs(struct platform_device
*dsidev
)
814 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
815 u32 mask
= DSI_IRQ_ERROR_MASK
;
816 #ifdef DSI_CATCH_MISSING_TE
817 mask
|= DSI_IRQ_TE_TRIGGER
;
819 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table
,
820 ARRAY_SIZE(dsi
->isr_tables
.isr_table
), mask
,
821 DSI_IRQENABLE
, DSI_IRQSTATUS
);
824 /* dsi->irq_lock has to be locked by the caller */
825 static void _omap_dsi_set_irqs_vc(struct platform_device
*dsidev
, int vc
)
827 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
829 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_vc
[vc
],
830 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[vc
]),
831 DSI_VC_IRQ_ERROR_MASK
,
832 DSI_VC_IRQENABLE(vc
), DSI_VC_IRQSTATUS(vc
));
835 /* dsi->irq_lock has to be locked by the caller */
836 static void _omap_dsi_set_irqs_cio(struct platform_device
*dsidev
)
838 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
840 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_cio
,
841 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
),
842 DSI_CIO_IRQ_ERROR_MASK
,
843 DSI_COMPLEXIO_IRQ_ENABLE
, DSI_COMPLEXIO_IRQ_STATUS
);
846 static void _dsi_initialize_irq(struct platform_device
*dsidev
)
848 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
852 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
854 memset(&dsi
->isr_tables
, 0, sizeof(dsi
->isr_tables
));
856 _omap_dsi_set_irqs(dsidev
);
857 for (vc
= 0; vc
< 4; ++vc
)
858 _omap_dsi_set_irqs_vc(dsidev
, vc
);
859 _omap_dsi_set_irqs_cio(dsidev
);
861 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
864 static int _dsi_register_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
865 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
867 struct dsi_isr_data
*isr_data
;
873 /* check for duplicate entry and find a free slot */
875 for (i
= 0; i
< isr_array_size
; i
++) {
876 isr_data
= &isr_array
[i
];
878 if (isr_data
->isr
== isr
&& isr_data
->arg
== arg
&&
879 isr_data
->mask
== mask
) {
883 if (isr_data
->isr
== NULL
&& free_idx
== -1)
890 isr_data
= &isr_array
[free_idx
];
893 isr_data
->mask
= mask
;
898 static int _dsi_unregister_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
899 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
901 struct dsi_isr_data
*isr_data
;
904 for (i
= 0; i
< isr_array_size
; i
++) {
905 isr_data
= &isr_array
[i
];
906 if (isr_data
->isr
!= isr
|| isr_data
->arg
!= arg
||
907 isr_data
->mask
!= mask
)
910 isr_data
->isr
= NULL
;
911 isr_data
->arg
= NULL
;
920 static int dsi_register_isr(struct platform_device
*dsidev
, omap_dsi_isr_t isr
,
923 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
927 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
929 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
930 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
933 _omap_dsi_set_irqs(dsidev
);
935 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
940 static int dsi_unregister_isr(struct platform_device
*dsidev
,
941 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
943 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
947 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
949 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
950 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
953 _omap_dsi_set_irqs(dsidev
);
955 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
960 static int dsi_register_isr_vc(struct platform_device
*dsidev
, int channel
,
961 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
963 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
967 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
969 r
= _dsi_register_isr(isr
, arg
, mask
,
970 dsi
->isr_tables
.isr_table_vc
[channel
],
971 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
974 _omap_dsi_set_irqs_vc(dsidev
, channel
);
976 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
981 static int dsi_unregister_isr_vc(struct platform_device
*dsidev
, int channel
,
982 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
984 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
988 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
990 r
= _dsi_unregister_isr(isr
, arg
, mask
,
991 dsi
->isr_tables
.isr_table_vc
[channel
],
992 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
995 _omap_dsi_set_irqs_vc(dsidev
, channel
);
997 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1002 static int dsi_register_isr_cio(struct platform_device
*dsidev
,
1003 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1005 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1006 unsigned long flags
;
1009 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1011 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1012 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1015 _omap_dsi_set_irqs_cio(dsidev
);
1017 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1022 static int dsi_unregister_isr_cio(struct platform_device
*dsidev
,
1023 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1025 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1026 unsigned long flags
;
1029 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1031 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1032 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1035 _omap_dsi_set_irqs_cio(dsidev
);
1037 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1042 static u32
dsi_get_errors(struct platform_device
*dsidev
)
1044 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1045 unsigned long flags
;
1047 spin_lock_irqsave(&dsi
->errors_lock
, flags
);
1050 spin_unlock_irqrestore(&dsi
->errors_lock
, flags
);
1054 int dsi_runtime_get(struct platform_device
*dsidev
)
1057 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1059 DSSDBG("dsi_runtime_get\n");
1061 r
= pm_runtime_get_sync(&dsi
->pdev
->dev
);
1063 return r
< 0 ? r
: 0;
1066 void dsi_runtime_put(struct platform_device
*dsidev
)
1068 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1071 DSSDBG("dsi_runtime_put\n");
1073 r
= pm_runtime_put(&dsi
->pdev
->dev
);
1077 /* source clock for DSI PLL. this could also be PCLKFREE */
1078 static inline void dsi_enable_pll_clock(struct platform_device
*dsidev
,
1081 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1084 clk_enable(dsi
->sys_clk
);
1086 clk_disable(dsi
->sys_clk
);
1088 if (enable
&& dsi
->pll_locked
) {
1089 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1)
1090 DSSERR("cannot lock PLL when enabling clocks\n");
1095 static void _dsi_print_reset_status(struct platform_device
*dsidev
)
1103 /* A dummy read using the SCP interface to any DSIPHY register is
1104 * required after DSIPHY reset to complete the reset of the DSI complex
1106 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
1108 printk(KERN_DEBUG
"DSI resets: ");
1110 l
= dsi_read_reg(dsidev
, DSI_PLL_STATUS
);
1111 printk("PLL (%d) ", FLD_GET(l
, 0, 0));
1113 l
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
);
1114 printk("CIO (%d) ", FLD_GET(l
, 29, 29));
1116 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
)) {
1126 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
1127 printk("PHY (%x%x%x, %d, %d, %d)\n",
1133 FLD_GET(l
, 31, 31));
1136 #define _dsi_print_reset_status(x)
1139 static inline int dsi_if_enable(struct platform_device
*dsidev
, bool enable
)
1141 DSSDBG("dsi_if_enable(%d)\n", enable
);
1143 enable
= enable
? 1 : 0;
1144 REG_FLD_MOD(dsidev
, DSI_CTRL
, enable
, 0, 0); /* IF_EN */
1146 if (wait_for_bit_change(dsidev
, DSI_CTRL
, 0, enable
) != enable
) {
1147 DSSERR("Failed to set dsi_if_enable to %d\n", enable
);
1154 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device
*dsidev
)
1156 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1158 return dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
;
1161 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device
*dsidev
)
1163 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1165 return dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
;
1168 static unsigned long dsi_get_txbyteclkhs(struct platform_device
*dsidev
)
1170 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1172 return dsi
->current_cinfo
.clkin4ddr
/ 16;
1175 static unsigned long dsi_fclk_rate(struct platform_device
*dsidev
)
1178 int dsi_module
= dsi_get_dsidev_id(dsidev
);
1179 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1181 if (dss_get_dsi_clk_source(dsi_module
) == OMAP_DSS_CLK_SRC_FCK
) {
1182 /* DSI FCLK source is DSS_CLK_FCK */
1183 r
= clk_get_rate(dsi
->dss_clk
);
1185 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1186 r
= dsi_get_pll_hsdiv_dsi_rate(dsidev
);
1192 static int dsi_set_lp_clk_divisor(struct omap_dss_device
*dssdev
)
1194 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
1195 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1196 unsigned long dsi_fclk
;
1197 unsigned lp_clk_div
;
1198 unsigned long lp_clk
;
1200 lp_clk_div
= dssdev
->clocks
.dsi
.lp_clk_div
;
1202 if (lp_clk_div
== 0 || lp_clk_div
> dsi
->lpdiv_max
)
1205 dsi_fclk
= dsi_fclk_rate(dsidev
);
1207 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
1209 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div
, lp_clk
);
1210 dsi
->current_cinfo
.lp_clk
= lp_clk
;
1211 dsi
->current_cinfo
.lp_clk_div
= lp_clk_div
;
1213 /* LP_CLK_DIVISOR */
1214 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, lp_clk_div
, 12, 0);
1216 /* LP_RX_SYNCHRO_ENABLE */
1217 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, dsi_fclk
> 30000000 ? 1 : 0, 21, 21);
1222 static void dsi_enable_scp_clk(struct platform_device
*dsidev
)
1224 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1226 if (dsi
->scp_clk_refcount
++ == 0)
1227 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 14, 14); /* CIO_CLK_ICG */
1230 static void dsi_disable_scp_clk(struct platform_device
*dsidev
)
1232 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1234 WARN_ON(dsi
->scp_clk_refcount
== 0);
1235 if (--dsi
->scp_clk_refcount
== 0)
1236 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 14, 14); /* CIO_CLK_ICG */
1239 enum dsi_pll_power_state
{
1240 DSI_PLL_POWER_OFF
= 0x0,
1241 DSI_PLL_POWER_ON_HSCLK
= 0x1,
1242 DSI_PLL_POWER_ON_ALL
= 0x2,
1243 DSI_PLL_POWER_ON_DIV
= 0x3,
1246 static int dsi_pll_power(struct platform_device
*dsidev
,
1247 enum dsi_pll_power_state state
)
1251 /* DSI-PLL power command 0x3 is not working */
1252 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG
) &&
1253 state
== DSI_PLL_POWER_ON_DIV
)
1254 state
= DSI_PLL_POWER_ON_ALL
;
1257 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, state
, 31, 30);
1259 /* PLL_PWR_STATUS */
1260 while (FLD_GET(dsi_read_reg(dsidev
, DSI_CLK_CTRL
), 29, 28) != state
) {
1262 DSSERR("Failed to set DSI PLL power mode to %d\n",
1272 /* calculate clock rates using dividers in cinfo */
1273 static int dsi_calc_clock_rates(struct omap_dss_device
*dssdev
,
1274 struct dsi_clock_info
*cinfo
)
1276 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
1277 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1279 if (cinfo
->regn
== 0 || cinfo
->regn
> dsi
->regn_max
)
1282 if (cinfo
->regm
== 0 || cinfo
->regm
> dsi
->regm_max
)
1285 if (cinfo
->regm_dispc
> dsi
->regm_dispc_max
)
1288 if (cinfo
->regm_dsi
> dsi
->regm_dsi_max
)
1291 if (cinfo
->use_sys_clk
) {
1292 cinfo
->clkin
= clk_get_rate(dsi
->sys_clk
);
1293 /* XXX it is unclear if highfreq should be used
1294 * with DSS_SYS_CLK source also */
1295 cinfo
->highfreq
= 0;
1297 cinfo
->clkin
= dispc_mgr_pclk_rate(dssdev
->manager
->id
);
1299 if (cinfo
->clkin
< 32000000)
1300 cinfo
->highfreq
= 0;
1302 cinfo
->highfreq
= 1;
1305 cinfo
->fint
= cinfo
->clkin
/ (cinfo
->regn
* (cinfo
->highfreq
? 2 : 1));
1307 if (cinfo
->fint
> dsi
->fint_max
|| cinfo
->fint
< dsi
->fint_min
)
1310 cinfo
->clkin4ddr
= 2 * cinfo
->regm
* cinfo
->fint
;
1312 if (cinfo
->clkin4ddr
> 1800 * 1000 * 1000)
1315 if (cinfo
->regm_dispc
> 0)
1316 cinfo
->dsi_pll_hsdiv_dispc_clk
=
1317 cinfo
->clkin4ddr
/ cinfo
->regm_dispc
;
1319 cinfo
->dsi_pll_hsdiv_dispc_clk
= 0;
1321 if (cinfo
->regm_dsi
> 0)
1322 cinfo
->dsi_pll_hsdiv_dsi_clk
=
1323 cinfo
->clkin4ddr
/ cinfo
->regm_dsi
;
1325 cinfo
->dsi_pll_hsdiv_dsi_clk
= 0;
1330 int dsi_pll_calc_clock_div_pck(struct platform_device
*dsidev
, bool is_tft
,
1331 unsigned long req_pck
, struct dsi_clock_info
*dsi_cinfo
,
1332 struct dispc_clock_info
*dispc_cinfo
)
1334 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1335 struct dsi_clock_info cur
, best
;
1336 struct dispc_clock_info best_dispc
;
1337 int min_fck_per_pck
;
1339 unsigned long dss_sys_clk
, max_dss_fck
;
1341 dss_sys_clk
= clk_get_rate(dsi
->sys_clk
);
1343 max_dss_fck
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
1345 if (req_pck
== dsi
->cache_req_pck
&&
1346 dsi
->cache_cinfo
.clkin
== dss_sys_clk
) {
1347 DSSDBG("DSI clock info found from cache\n");
1348 *dsi_cinfo
= dsi
->cache_cinfo
;
1349 dispc_find_clk_divs(is_tft
, req_pck
,
1350 dsi_cinfo
->dsi_pll_hsdiv_dispc_clk
, dispc_cinfo
);
1354 min_fck_per_pck
= CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
;
1356 if (min_fck_per_pck
&&
1357 req_pck
* min_fck_per_pck
> max_dss_fck
) {
1358 DSSERR("Requested pixel clock not possible with the current "
1359 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1360 "the constraint off.\n");
1361 min_fck_per_pck
= 0;
1364 DSSDBG("dsi_pll_calc\n");
1367 memset(&best
, 0, sizeof(best
));
1368 memset(&best_dispc
, 0, sizeof(best_dispc
));
1370 memset(&cur
, 0, sizeof(cur
));
1371 cur
.clkin
= dss_sys_clk
;
1372 cur
.use_sys_clk
= 1;
1375 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1376 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1377 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1378 for (cur
.regn
= 1; cur
.regn
< dsi
->regn_max
; ++cur
.regn
) {
1379 if (cur
.highfreq
== 0)
1380 cur
.fint
= cur
.clkin
/ cur
.regn
;
1382 cur
.fint
= cur
.clkin
/ (2 * cur
.regn
);
1384 if (cur
.fint
> dsi
->fint_max
|| cur
.fint
< dsi
->fint_min
)
1387 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1388 for (cur
.regm
= 1; cur
.regm
< dsi
->regm_max
; ++cur
.regm
) {
1391 a
= 2 * cur
.regm
* (cur
.clkin
/1000);
1392 b
= cur
.regn
* (cur
.highfreq
+ 1);
1393 cur
.clkin4ddr
= a
/ b
* 1000;
1395 if (cur
.clkin4ddr
> 1800 * 1000 * 1000)
1398 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1399 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1400 for (cur
.regm_dispc
= 1; cur
.regm_dispc
<
1401 dsi
->regm_dispc_max
; ++cur
.regm_dispc
) {
1402 struct dispc_clock_info cur_dispc
;
1403 cur
.dsi_pll_hsdiv_dispc_clk
=
1404 cur
.clkin4ddr
/ cur
.regm_dispc
;
1406 /* this will narrow down the search a bit,
1407 * but still give pixclocks below what was
1409 if (cur
.dsi_pll_hsdiv_dispc_clk
< req_pck
)
1412 if (cur
.dsi_pll_hsdiv_dispc_clk
> max_dss_fck
)
1415 if (min_fck_per_pck
&&
1416 cur
.dsi_pll_hsdiv_dispc_clk
<
1417 req_pck
* min_fck_per_pck
)
1422 dispc_find_clk_divs(is_tft
, req_pck
,
1423 cur
.dsi_pll_hsdiv_dispc_clk
,
1426 if (abs(cur_dispc
.pck
- req_pck
) <
1427 abs(best_dispc
.pck
- req_pck
)) {
1429 best_dispc
= cur_dispc
;
1431 if (cur_dispc
.pck
== req_pck
)
1439 if (min_fck_per_pck
) {
1440 DSSERR("Could not find suitable clock settings.\n"
1441 "Turning FCK/PCK constraint off and"
1443 min_fck_per_pck
= 0;
1447 DSSERR("Could not find suitable clock settings.\n");
1452 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1454 best
.dsi_pll_hsdiv_dsi_clk
= 0;
1459 *dispc_cinfo
= best_dispc
;
1461 dsi
->cache_req_pck
= req_pck
;
1462 dsi
->cache_clk_freq
= 0;
1463 dsi
->cache_cinfo
= best
;
1468 int dsi_pll_set_clock_div(struct platform_device
*dsidev
,
1469 struct dsi_clock_info
*cinfo
)
1471 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1475 u8 regn_start
, regn_end
, regm_start
, regm_end
;
1476 u8 regm_dispc_start
, regm_dispc_end
, regm_dsi_start
, regm_dsi_end
;
1480 dsi
->current_cinfo
.use_sys_clk
= cinfo
->use_sys_clk
;
1481 dsi
->current_cinfo
.highfreq
= cinfo
->highfreq
;
1483 dsi
->current_cinfo
.fint
= cinfo
->fint
;
1484 dsi
->current_cinfo
.clkin4ddr
= cinfo
->clkin4ddr
;
1485 dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
=
1486 cinfo
->dsi_pll_hsdiv_dispc_clk
;
1487 dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
=
1488 cinfo
->dsi_pll_hsdiv_dsi_clk
;
1490 dsi
->current_cinfo
.regn
= cinfo
->regn
;
1491 dsi
->current_cinfo
.regm
= cinfo
->regm
;
1492 dsi
->current_cinfo
.regm_dispc
= cinfo
->regm_dispc
;
1493 dsi
->current_cinfo
.regm_dsi
= cinfo
->regm_dsi
;
1495 DSSDBG("DSI Fint %ld\n", cinfo
->fint
);
1497 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1498 cinfo
->use_sys_clk
? "dss_sys_clk" : "pclkfree",
1502 /* DSIPHY == CLKIN4DDR */
1503 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1507 cinfo
->highfreq
+ 1,
1510 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1511 cinfo
->clkin4ddr
/ 1000 / 1000 / 2);
1513 DSSDBG("Clock lane freq %ld Hz\n", cinfo
->clkin4ddr
/ 4);
1515 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo
->regm_dispc
,
1516 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1517 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1518 cinfo
->dsi_pll_hsdiv_dispc_clk
);
1519 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo
->regm_dsi
,
1520 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1521 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1522 cinfo
->dsi_pll_hsdiv_dsi_clk
);
1524 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN
, ®n_start
, ®n_end
);
1525 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM
, ®m_start
, ®m_end
);
1526 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC
, ®m_dispc_start
,
1528 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI
, ®m_dsi_start
,
1531 /* DSI_PLL_AUTOMODE = manual */
1532 REG_FLD_MOD(dsidev
, DSI_PLL_CONTROL
, 0, 0, 0);
1534 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION1
);
1535 l
= FLD_MOD(l
, 1, 0, 0); /* DSI_PLL_STOPMODE */
1537 l
= FLD_MOD(l
, cinfo
->regn
- 1, regn_start
, regn_end
);
1539 l
= FLD_MOD(l
, cinfo
->regm
, regm_start
, regm_end
);
1541 l
= FLD_MOD(l
, cinfo
->regm_dispc
> 0 ? cinfo
->regm_dispc
- 1 : 0,
1542 regm_dispc_start
, regm_dispc_end
);
1543 /* DSIPROTO_CLOCK_DIV */
1544 l
= FLD_MOD(l
, cinfo
->regm_dsi
> 0 ? cinfo
->regm_dsi
- 1 : 0,
1545 regm_dsi_start
, regm_dsi_end
);
1546 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION1
, l
);
1548 BUG_ON(cinfo
->fint
< dsi
->fint_min
|| cinfo
->fint
> dsi
->fint_max
);
1550 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL
)) {
1551 f
= cinfo
->fint
< 1000000 ? 0x3 :
1552 cinfo
->fint
< 1250000 ? 0x4 :
1553 cinfo
->fint
< 1500000 ? 0x5 :
1554 cinfo
->fint
< 1750000 ? 0x6 :
1558 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1560 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL
))
1561 l
= FLD_MOD(l
, f
, 4, 1); /* DSI_PLL_FREQSEL */
1562 l
= FLD_MOD(l
, cinfo
->use_sys_clk
? 0 : 1,
1563 11, 11); /* DSI_PLL_CLKSEL */
1564 l
= FLD_MOD(l
, cinfo
->highfreq
,
1565 12, 12); /* DSI_PLL_HIGHFREQ */
1566 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1567 l
= FLD_MOD(l
, 0, 14, 14); /* DSIPHY_CLKINEN */
1568 l
= FLD_MOD(l
, 1, 20, 20); /* DSI_HSDIVBYPASS */
1569 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1571 REG_FLD_MOD(dsidev
, DSI_PLL_GO
, 1, 0, 0); /* DSI_PLL_GO */
1573 if (wait_for_bit_change(dsidev
, DSI_PLL_GO
, 0, 0) != 0) {
1574 DSSERR("dsi pll go bit not going down.\n");
1579 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1) {
1580 DSSERR("cannot lock PLL\n");
1585 dsi
->pll_locked
= 1;
1587 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1588 l
= FLD_MOD(l
, 0, 0, 0); /* DSI_PLL_IDLE */
1589 l
= FLD_MOD(l
, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1590 l
= FLD_MOD(l
, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1591 l
= FLD_MOD(l
, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1592 l
= FLD_MOD(l
, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1593 l
= FLD_MOD(l
, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1594 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1595 l
= FLD_MOD(l
, 1, 14, 14); /* DSIPHY_CLKINEN */
1596 l
= FLD_MOD(l
, 0, 15, 15); /* DSI_BYPASSEN */
1597 l
= FLD_MOD(l
, 1, 16, 16); /* DSS_CLOCK_EN */
1598 l
= FLD_MOD(l
, 0, 17, 17); /* DSS_CLOCK_PWDN */
1599 l
= FLD_MOD(l
, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1600 l
= FLD_MOD(l
, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1601 l
= FLD_MOD(l
, 0, 20, 20); /* DSI_HSDIVBYPASS */
1602 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1604 DSSDBG("PLL config done\n");
1609 int dsi_pll_init(struct platform_device
*dsidev
, bool enable_hsclk
,
1612 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1614 enum dsi_pll_power_state pwstate
;
1616 DSSDBG("PLL init\n");
1618 if (dsi
->vdds_dsi_reg
== NULL
) {
1619 struct regulator
*vdds_dsi
;
1621 vdds_dsi
= regulator_get(&dsi
->pdev
->dev
, "vdds_dsi");
1623 if (IS_ERR(vdds_dsi
)) {
1624 DSSERR("can't get VDDS_DSI regulator\n");
1625 return PTR_ERR(vdds_dsi
);
1628 dsi
->vdds_dsi_reg
= vdds_dsi
;
1631 dsi_enable_pll_clock(dsidev
, 1);
1633 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1635 dsi_enable_scp_clk(dsidev
);
1637 if (!dsi
->vdds_dsi_enabled
) {
1638 r
= regulator_enable(dsi
->vdds_dsi_reg
);
1641 dsi
->vdds_dsi_enabled
= true;
1644 /* XXX PLL does not come out of reset without this... */
1645 dispc_pck_free_enable(1);
1647 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 0, 1) != 1) {
1648 DSSERR("PLL not coming out of reset.\n");
1650 dispc_pck_free_enable(0);
1654 /* XXX ... but if left on, we get problems when planes do not
1655 * fill the whole display. No idea about this */
1656 dispc_pck_free_enable(0);
1658 if (enable_hsclk
&& enable_hsdiv
)
1659 pwstate
= DSI_PLL_POWER_ON_ALL
;
1660 else if (enable_hsclk
)
1661 pwstate
= DSI_PLL_POWER_ON_HSCLK
;
1662 else if (enable_hsdiv
)
1663 pwstate
= DSI_PLL_POWER_ON_DIV
;
1665 pwstate
= DSI_PLL_POWER_OFF
;
1667 r
= dsi_pll_power(dsidev
, pwstate
);
1672 DSSDBG("PLL init done\n");
1676 if (dsi
->vdds_dsi_enabled
) {
1677 regulator_disable(dsi
->vdds_dsi_reg
);
1678 dsi
->vdds_dsi_enabled
= false;
1681 dsi_disable_scp_clk(dsidev
);
1682 dsi_enable_pll_clock(dsidev
, 0);
1686 void dsi_pll_uninit(struct platform_device
*dsidev
, bool disconnect_lanes
)
1688 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1690 dsi
->pll_locked
= 0;
1691 dsi_pll_power(dsidev
, DSI_PLL_POWER_OFF
);
1692 if (disconnect_lanes
) {
1693 WARN_ON(!dsi
->vdds_dsi_enabled
);
1694 regulator_disable(dsi
->vdds_dsi_reg
);
1695 dsi
->vdds_dsi_enabled
= false;
1698 dsi_disable_scp_clk(dsidev
);
1699 dsi_enable_pll_clock(dsidev
, 0);
1701 DSSDBG("PLL uninit done\n");
1704 static void dsi_dump_dsidev_clocks(struct platform_device
*dsidev
,
1707 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1708 struct dsi_clock_info
*cinfo
= &dsi
->current_cinfo
;
1709 enum omap_dss_clk_source dispc_clk_src
, dsi_clk_src
;
1710 int dsi_module
= dsi_get_dsidev_id(dsidev
);
1712 dispc_clk_src
= dss_get_dispc_clk_source();
1713 dsi_clk_src
= dss_get_dsi_clk_source(dsi_module
);
1715 if (dsi_runtime_get(dsidev
))
1718 seq_printf(s
, "- DSI%d PLL -\n", dsi_module
+ 1);
1720 seq_printf(s
, "dsi pll source = %s\n",
1721 cinfo
->use_sys_clk
? "dss_sys_clk" : "pclkfree");
1723 seq_printf(s
, "Fint\t\t%-16luregn %u\n", cinfo
->fint
, cinfo
->regn
);
1725 seq_printf(s
, "CLKIN4DDR\t%-16luregm %u\n",
1726 cinfo
->clkin4ddr
, cinfo
->regm
);
1728 seq_printf(s
, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1729 dss_get_generic_clk_source_name(dispc_clk_src
),
1730 dss_feat_get_clk_source_name(dispc_clk_src
),
1731 cinfo
->dsi_pll_hsdiv_dispc_clk
,
1733 dispc_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1736 seq_printf(s
, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1737 dss_get_generic_clk_source_name(dsi_clk_src
),
1738 dss_feat_get_clk_source_name(dsi_clk_src
),
1739 cinfo
->dsi_pll_hsdiv_dsi_clk
,
1741 dsi_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1744 seq_printf(s
, "- DSI%d -\n", dsi_module
+ 1);
1746 seq_printf(s
, "dsi fclk source = %s (%s)\n",
1747 dss_get_generic_clk_source_name(dsi_clk_src
),
1748 dss_feat_get_clk_source_name(dsi_clk_src
));
1750 seq_printf(s
, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev
));
1752 seq_printf(s
, "DDR_CLK\t\t%lu\n",
1753 cinfo
->clkin4ddr
/ 4);
1755 seq_printf(s
, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev
));
1757 seq_printf(s
, "LP_CLK\t\t%lu\n", cinfo
->lp_clk
);
1759 dsi_runtime_put(dsidev
);
1762 void dsi_dump_clocks(struct seq_file
*s
)
1764 struct platform_device
*dsidev
;
1767 for (i
= 0; i
< MAX_NUM_DSI
; i
++) {
1768 dsidev
= dsi_get_dsidev_from_id(i
);
1770 dsi_dump_dsidev_clocks(dsidev
, s
);
1774 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1775 static void dsi_dump_dsidev_irqs(struct platform_device
*dsidev
,
1778 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1779 unsigned long flags
;
1780 struct dsi_irq_stats stats
;
1781 int dsi_module
= dsi_get_dsidev_id(dsidev
);
1783 spin_lock_irqsave(&dsi
->irq_stats_lock
, flags
);
1785 stats
= dsi
->irq_stats
;
1786 memset(&dsi
->irq_stats
, 0, sizeof(dsi
->irq_stats
));
1787 dsi
->irq_stats
.last_reset
= jiffies
;
1789 spin_unlock_irqrestore(&dsi
->irq_stats_lock
, flags
);
1791 seq_printf(s
, "period %u ms\n",
1792 jiffies_to_msecs(jiffies
- stats
.last_reset
));
1794 seq_printf(s
, "irqs %d\n", stats
.irq_count
);
1796 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1798 seq_printf(s
, "-- DSI%d interrupts --\n", dsi_module
+ 1);
1814 PIS(LDO_POWER_GOOD
);
1819 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1820 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1821 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1822 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1823 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1825 seq_printf(s
, "-- VC interrupts --\n");
1834 PIS(PP_BUSY_CHANGE
);
1838 seq_printf(s, "%-20s %10d\n", #x, \
1839 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1841 seq_printf(s
, "-- CIO interrupts --\n");
1854 PIS(ERRCONTENTIONLP0_1
);
1855 PIS(ERRCONTENTIONLP1_1
);
1856 PIS(ERRCONTENTIONLP0_2
);
1857 PIS(ERRCONTENTIONLP1_2
);
1858 PIS(ERRCONTENTIONLP0_3
);
1859 PIS(ERRCONTENTIONLP1_3
);
1860 PIS(ULPSACTIVENOT_ALL0
);
1861 PIS(ULPSACTIVENOT_ALL1
);
1865 static void dsi1_dump_irqs(struct seq_file
*s
)
1867 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1869 dsi_dump_dsidev_irqs(dsidev
, s
);
1872 static void dsi2_dump_irqs(struct seq_file
*s
)
1874 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
1876 dsi_dump_dsidev_irqs(dsidev
, s
);
1879 void dsi_create_debugfs_files_irq(struct dentry
*debugfs_dir
,
1880 const struct file_operations
*debug_fops
)
1882 struct platform_device
*dsidev
;
1884 dsidev
= dsi_get_dsidev_from_id(0);
1886 debugfs_create_file("dsi1_irqs", S_IRUGO
, debugfs_dir
,
1887 &dsi1_dump_irqs
, debug_fops
);
1889 dsidev
= dsi_get_dsidev_from_id(1);
1891 debugfs_create_file("dsi2_irqs", S_IRUGO
, debugfs_dir
,
1892 &dsi2_dump_irqs
, debug_fops
);
1896 static void dsi_dump_dsidev_regs(struct platform_device
*dsidev
,
1899 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1901 if (dsi_runtime_get(dsidev
))
1903 dsi_enable_scp_clk(dsidev
);
1905 DUMPREG(DSI_REVISION
);
1906 DUMPREG(DSI_SYSCONFIG
);
1907 DUMPREG(DSI_SYSSTATUS
);
1908 DUMPREG(DSI_IRQSTATUS
);
1909 DUMPREG(DSI_IRQENABLE
);
1911 DUMPREG(DSI_COMPLEXIO_CFG1
);
1912 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS
);
1913 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE
);
1914 DUMPREG(DSI_CLK_CTRL
);
1915 DUMPREG(DSI_TIMING1
);
1916 DUMPREG(DSI_TIMING2
);
1917 DUMPREG(DSI_VM_TIMING1
);
1918 DUMPREG(DSI_VM_TIMING2
);
1919 DUMPREG(DSI_VM_TIMING3
);
1920 DUMPREG(DSI_CLK_TIMING
);
1921 DUMPREG(DSI_TX_FIFO_VC_SIZE
);
1922 DUMPREG(DSI_RX_FIFO_VC_SIZE
);
1923 DUMPREG(DSI_COMPLEXIO_CFG2
);
1924 DUMPREG(DSI_RX_FIFO_VC_FULLNESS
);
1925 DUMPREG(DSI_VM_TIMING4
);
1926 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS
);
1927 DUMPREG(DSI_VM_TIMING5
);
1928 DUMPREG(DSI_VM_TIMING6
);
1929 DUMPREG(DSI_VM_TIMING7
);
1930 DUMPREG(DSI_STOPCLK_TIMING
);
1932 DUMPREG(DSI_VC_CTRL(0));
1933 DUMPREG(DSI_VC_TE(0));
1934 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1935 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1936 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1937 DUMPREG(DSI_VC_IRQSTATUS(0));
1938 DUMPREG(DSI_VC_IRQENABLE(0));
1940 DUMPREG(DSI_VC_CTRL(1));
1941 DUMPREG(DSI_VC_TE(1));
1942 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1943 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1944 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1945 DUMPREG(DSI_VC_IRQSTATUS(1));
1946 DUMPREG(DSI_VC_IRQENABLE(1));
1948 DUMPREG(DSI_VC_CTRL(2));
1949 DUMPREG(DSI_VC_TE(2));
1950 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1951 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1952 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1953 DUMPREG(DSI_VC_IRQSTATUS(2));
1954 DUMPREG(DSI_VC_IRQENABLE(2));
1956 DUMPREG(DSI_VC_CTRL(3));
1957 DUMPREG(DSI_VC_TE(3));
1958 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1959 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1960 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1961 DUMPREG(DSI_VC_IRQSTATUS(3));
1962 DUMPREG(DSI_VC_IRQENABLE(3));
1964 DUMPREG(DSI_DSIPHY_CFG0
);
1965 DUMPREG(DSI_DSIPHY_CFG1
);
1966 DUMPREG(DSI_DSIPHY_CFG2
);
1967 DUMPREG(DSI_DSIPHY_CFG5
);
1969 DUMPREG(DSI_PLL_CONTROL
);
1970 DUMPREG(DSI_PLL_STATUS
);
1971 DUMPREG(DSI_PLL_GO
);
1972 DUMPREG(DSI_PLL_CONFIGURATION1
);
1973 DUMPREG(DSI_PLL_CONFIGURATION2
);
1975 dsi_disable_scp_clk(dsidev
);
1976 dsi_runtime_put(dsidev
);
1980 static void dsi1_dump_regs(struct seq_file
*s
)
1982 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1984 dsi_dump_dsidev_regs(dsidev
, s
);
1987 static void dsi2_dump_regs(struct seq_file
*s
)
1989 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
1991 dsi_dump_dsidev_regs(dsidev
, s
);
1994 void dsi_create_debugfs_files_reg(struct dentry
*debugfs_dir
,
1995 const struct file_operations
*debug_fops
)
1997 struct platform_device
*dsidev
;
1999 dsidev
= dsi_get_dsidev_from_id(0);
2001 debugfs_create_file("dsi1_regs", S_IRUGO
, debugfs_dir
,
2002 &dsi1_dump_regs
, debug_fops
);
2004 dsidev
= dsi_get_dsidev_from_id(1);
2006 debugfs_create_file("dsi2_regs", S_IRUGO
, debugfs_dir
,
2007 &dsi2_dump_regs
, debug_fops
);
2009 enum dsi_cio_power_state
{
2010 DSI_COMPLEXIO_POWER_OFF
= 0x0,
2011 DSI_COMPLEXIO_POWER_ON
= 0x1,
2012 DSI_COMPLEXIO_POWER_ULPS
= 0x2,
2015 static int dsi_cio_power(struct platform_device
*dsidev
,
2016 enum dsi_cio_power_state state
)
2021 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG1
, state
, 28, 27);
2024 while (FLD_GET(dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
),
2027 DSSERR("failed to set complexio power state to "
2037 static unsigned dsi_get_line_buf_size(struct platform_device
*dsidev
)
2041 /* line buffer on OMAP3 is 1024 x 24bits */
2042 /* XXX: for some reason using full buffer size causes
2043 * considerable TX slowdown with update sizes that fill the
2045 if (!dss_has_feature(FEAT_DSI_GNQ
))
2048 val
= REG_GET(dsidev
, DSI_GNQ
, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2052 return 512 * 3; /* 512x24 bits */
2054 return 682 * 3; /* 682x24 bits */
2056 return 853 * 3; /* 853x24 bits */
2058 return 1024 * 3; /* 1024x24 bits */
2060 return 1194 * 3; /* 1194x24 bits */
2062 return 1365 * 3; /* 1365x24 bits */
2068 static int dsi_parse_lane_config(struct omap_dss_device
*dssdev
)
2070 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2071 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2072 u8 lanes
[DSI_MAX_NR_LANES
];
2073 u8 polarities
[DSI_MAX_NR_LANES
];
2076 static const enum dsi_lane_function functions
[] = {
2084 lanes
[0] = dssdev
->phy
.dsi
.clk_lane
;
2085 lanes
[1] = dssdev
->phy
.dsi
.data1_lane
;
2086 lanes
[2] = dssdev
->phy
.dsi
.data2_lane
;
2087 lanes
[3] = dssdev
->phy
.dsi
.data3_lane
;
2088 lanes
[4] = dssdev
->phy
.dsi
.data4_lane
;
2089 polarities
[0] = dssdev
->phy
.dsi
.clk_pol
;
2090 polarities
[1] = dssdev
->phy
.dsi
.data1_pol
;
2091 polarities
[2] = dssdev
->phy
.dsi
.data2_pol
;
2092 polarities
[3] = dssdev
->phy
.dsi
.data3_pol
;
2093 polarities
[4] = dssdev
->phy
.dsi
.data4_pol
;
2097 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
)
2098 dsi
->lanes
[i
].function
= DSI_LANE_UNUSED
;
2100 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2103 if (lanes
[i
] == DSI_LANE_UNUSED
)
2108 if (num
>= dsi
->num_lanes_supported
)
2111 if (dsi
->lanes
[num
].function
!= DSI_LANE_UNUSED
)
2114 dsi
->lanes
[num
].function
= functions
[i
];
2115 dsi
->lanes
[num
].polarity
= polarities
[i
];
2119 if (num_lanes
< 2 || num_lanes
> dsi
->num_lanes_supported
)
2122 dsi
->num_lanes_used
= num_lanes
;
2127 static int dsi_set_lane_config(struct omap_dss_device
*dssdev
)
2129 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2130 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2131 static const u8 offsets
[] = { 0, 4, 8, 12, 16 };
2132 static const enum dsi_lane_function functions
[] = {
2142 r
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
);
2144 for (i
= 0; i
< dsi
->num_lanes_used
; ++i
) {
2145 unsigned offset
= offsets
[i
];
2146 unsigned polarity
, lane_number
;
2149 for (t
= 0; t
< dsi
->num_lanes_supported
; ++t
)
2150 if (dsi
->lanes
[t
].function
== functions
[i
])
2153 if (t
== dsi
->num_lanes_supported
)
2157 polarity
= dsi
->lanes
[t
].polarity
;
2159 r
= FLD_MOD(r
, lane_number
+ 1, offset
+ 2, offset
);
2160 r
= FLD_MOD(r
, polarity
, offset
+ 3, offset
+ 3);
2163 /* clear the unused lanes */
2164 for (; i
< dsi
->num_lanes_supported
; ++i
) {
2165 unsigned offset
= offsets
[i
];
2167 r
= FLD_MOD(r
, 0, offset
+ 2, offset
);
2168 r
= FLD_MOD(r
, 0, offset
+ 3, offset
+ 3);
2171 dsi_write_reg(dsidev
, DSI_COMPLEXIO_CFG1
, r
);
2176 static inline unsigned ns2ddr(struct platform_device
*dsidev
, unsigned ns
)
2178 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2180 /* convert time in ns to ddr ticks, rounding up */
2181 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2182 return (ns
* (ddr_clk
/ 1000 / 1000) + 999) / 1000;
2185 static inline unsigned ddr2ns(struct platform_device
*dsidev
, unsigned ddr
)
2187 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2189 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2190 return ddr
* 1000 * 1000 / (ddr_clk
/ 1000);
2193 static void dsi_cio_timings(struct platform_device
*dsidev
)
2196 u32 ths_prepare
, ths_prepare_ths_zero
, ths_trail
, ths_exit
;
2197 u32 tlpx_half
, tclk_trail
, tclk_zero
;
2200 /* calculate timings */
2202 /* 1 * DDR_CLK = 2 * UI */
2204 /* min 40ns + 4*UI max 85ns + 6*UI */
2205 ths_prepare
= ns2ddr(dsidev
, 70) + 2;
2207 /* min 145ns + 10*UI */
2208 ths_prepare_ths_zero
= ns2ddr(dsidev
, 175) + 2;
2210 /* min max(8*UI, 60ns+4*UI) */
2211 ths_trail
= ns2ddr(dsidev
, 60) + 5;
2214 ths_exit
= ns2ddr(dsidev
, 145);
2217 tlpx_half
= ns2ddr(dsidev
, 25);
2220 tclk_trail
= ns2ddr(dsidev
, 60) + 2;
2222 /* min 38ns, max 95ns */
2223 tclk_prepare
= ns2ddr(dsidev
, 65);
2225 /* min tclk-prepare + tclk-zero = 300ns */
2226 tclk_zero
= ns2ddr(dsidev
, 260);
2228 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2229 ths_prepare
, ddr2ns(dsidev
, ths_prepare
),
2230 ths_prepare_ths_zero
, ddr2ns(dsidev
, ths_prepare_ths_zero
));
2231 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2232 ths_trail
, ddr2ns(dsidev
, ths_trail
),
2233 ths_exit
, ddr2ns(dsidev
, ths_exit
));
2235 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2236 "tclk_zero %u (%uns)\n",
2237 tlpx_half
, ddr2ns(dsidev
, tlpx_half
),
2238 tclk_trail
, ddr2ns(dsidev
, tclk_trail
),
2239 tclk_zero
, ddr2ns(dsidev
, tclk_zero
));
2240 DSSDBG("tclk_prepare %u (%uns)\n",
2241 tclk_prepare
, ddr2ns(dsidev
, tclk_prepare
));
2243 /* program timings */
2245 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
2246 r
= FLD_MOD(r
, ths_prepare
, 31, 24);
2247 r
= FLD_MOD(r
, ths_prepare_ths_zero
, 23, 16);
2248 r
= FLD_MOD(r
, ths_trail
, 15, 8);
2249 r
= FLD_MOD(r
, ths_exit
, 7, 0);
2250 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG0
, r
);
2252 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
2253 r
= FLD_MOD(r
, tlpx_half
, 22, 16);
2254 r
= FLD_MOD(r
, tclk_trail
, 15, 8);
2255 r
= FLD_MOD(r
, tclk_zero
, 7, 0);
2256 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG1
, r
);
2258 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
2259 r
= FLD_MOD(r
, tclk_prepare
, 7, 0);
2260 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG2
, r
);
2263 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2264 static void dsi_cio_enable_lane_override(struct omap_dss_device
*dssdev
,
2265 unsigned mask_p
, unsigned mask_n
)
2267 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2268 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2271 u8 lptxscp_start
= dsi
->num_lanes_supported
== 3 ? 22 : 26;
2275 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2276 unsigned p
= dsi
->lanes
[i
].polarity
;
2278 if (mask_p
& (1 << i
))
2279 l
|= 1 << (i
* 2 + (p
? 0 : 1));
2281 if (mask_n
& (1 << i
))
2282 l
|= 1 << (i
* 2 + (p
? 1 : 0));
2286 * Bits in REGLPTXSCPDAT4TO0DXDY:
2294 /* Set the lane override configuration */
2296 /* REGLPTXSCPDAT4TO0DXDY */
2297 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, l
, lptxscp_start
, 17);
2299 /* Enable lane override */
2302 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 1, 27, 27);
2305 static void dsi_cio_disable_lane_override(struct platform_device
*dsidev
)
2307 /* Disable lane override */
2308 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 27, 27); /* ENLPTXSCPDAT */
2309 /* Reset the lane override configuration */
2310 /* REGLPTXSCPDAT4TO0DXDY */
2311 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 22, 17);
2314 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device
*dssdev
)
2316 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2317 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2319 bool in_use
[DSI_MAX_NR_LANES
];
2320 static const u8 offsets_old
[] = { 28, 27, 26 };
2321 static const u8 offsets_new
[] = { 24, 25, 26, 27, 28 };
2324 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
))
2325 offsets
= offsets_old
;
2327 offsets
= offsets_new
;
2329 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
)
2330 in_use
[i
] = dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
;
2337 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2340 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2341 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2345 if (ok
== dsi
->num_lanes_supported
)
2349 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2350 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2353 DSSERR("CIO TXCLKESC%d domain not coming " \
2354 "out of reset\n", i
);
2363 /* return bitmask of enabled lanes, lane0 being the lsb */
2364 static unsigned dsi_get_lane_mask(struct omap_dss_device
*dssdev
)
2366 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2367 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2371 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2372 if (dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
)
2379 static int dsi_cio_init(struct omap_dss_device
*dssdev
)
2381 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2382 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2388 r
= dsi
->enable_pads(dsidev
->id
, dsi_get_lane_mask(dssdev
));
2392 dsi_enable_scp_clk(dsidev
);
2394 /* A dummy read using the SCP interface to any DSIPHY register is
2395 * required after DSIPHY reset to complete the reset of the DSI complex
2397 dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2399 if (wait_for_bit_change(dsidev
, DSI_DSIPHY_CFG5
, 30, 1) != 1) {
2400 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2402 goto err_scp_clk_dom
;
2405 r
= dsi_set_lane_config(dssdev
);
2407 goto err_scp_clk_dom
;
2409 /* set TX STOP MODE timer to maximum for this operation */
2410 l
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2411 l
= FLD_MOD(l
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2412 l
= FLD_MOD(l
, 1, 14, 14); /* STOP_STATE_X16_IO */
2413 l
= FLD_MOD(l
, 1, 13, 13); /* STOP_STATE_X4_IO */
2414 l
= FLD_MOD(l
, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2415 dsi_write_reg(dsidev
, DSI_TIMING1
, l
);
2417 if (dsi
->ulps_enabled
) {
2421 DSSDBG("manual ulps exit\n");
2423 /* ULPS is exited by Mark-1 state for 1ms, followed by
2424 * stop state. DSS HW cannot do this via the normal
2425 * ULPS exit sequence, as after reset the DSS HW thinks
2426 * that we are not in ULPS mode, and refuses to send the
2427 * sequence. So we need to send the ULPS exit sequence
2428 * manually by setting positive lines high and negative lines
2434 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2435 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
2440 dsi_cio_enable_lane_override(dssdev
, mask_p
, 0);
2443 r
= dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ON
);
2447 if (wait_for_bit_change(dsidev
, DSI_COMPLEXIO_CFG1
, 29, 1) != 1) {
2448 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2450 goto err_cio_pwr_dom
;
2453 dsi_if_enable(dsidev
, true);
2454 dsi_if_enable(dsidev
, false);
2455 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 20, 20); /* LP_CLK_ENABLE */
2457 r
= dsi_cio_wait_tx_clk_esc_reset(dssdev
);
2459 goto err_tx_clk_esc_rst
;
2461 if (dsi
->ulps_enabled
) {
2462 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2463 ktime_t wait
= ns_to_ktime(1000 * 1000);
2464 set_current_state(TASK_UNINTERRUPTIBLE
);
2465 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
2467 /* Disable the override. The lanes should be set to Mark-11
2468 * state by the HW */
2469 dsi_cio_disable_lane_override(dsidev
);
2472 /* FORCE_TX_STOP_MODE_IO */
2473 REG_FLD_MOD(dsidev
, DSI_TIMING1
, 0, 15, 15);
2475 dsi_cio_timings(dsidev
);
2477 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
2478 /* DDR_CLK_ALWAYS_ON */
2479 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
,
2480 dssdev
->panel
.dsi_vm_data
.ddr_clk_always_on
, 13, 13);
2483 dsi
->ulps_enabled
= false;
2485 DSSDBG("CIO init done\n");
2490 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 20, 20); /* LP_CLK_ENABLE */
2492 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2494 if (dsi
->ulps_enabled
)
2495 dsi_cio_disable_lane_override(dsidev
);
2497 dsi_disable_scp_clk(dsidev
);
2498 dsi
->disable_pads(dsidev
->id
, dsi_get_lane_mask(dssdev
));
2502 static void dsi_cio_uninit(struct omap_dss_device
*dssdev
)
2504 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2505 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2507 /* DDR_CLK_ALWAYS_ON */
2508 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
2510 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2511 dsi_disable_scp_clk(dsidev
);
2512 dsi
->disable_pads(dsidev
->id
, dsi_get_lane_mask(dssdev
));
2515 static void dsi_config_tx_fifo(struct platform_device
*dsidev
,
2516 enum fifo_size size1
, enum fifo_size size2
,
2517 enum fifo_size size3
, enum fifo_size size4
)
2519 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2524 dsi
->vc
[0].fifo_size
= size1
;
2525 dsi
->vc
[1].fifo_size
= size2
;
2526 dsi
->vc
[2].fifo_size
= size3
;
2527 dsi
->vc
[3].fifo_size
= size4
;
2529 for (i
= 0; i
< 4; i
++) {
2531 int size
= dsi
->vc
[i
].fifo_size
;
2533 if (add
+ size
> 4) {
2534 DSSERR("Illegal FIFO configuration\n");
2538 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2540 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2544 dsi_write_reg(dsidev
, DSI_TX_FIFO_VC_SIZE
, r
);
2547 static void dsi_config_rx_fifo(struct platform_device
*dsidev
,
2548 enum fifo_size size1
, enum fifo_size size2
,
2549 enum fifo_size size3
, enum fifo_size size4
)
2551 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2556 dsi
->vc
[0].fifo_size
= size1
;
2557 dsi
->vc
[1].fifo_size
= size2
;
2558 dsi
->vc
[2].fifo_size
= size3
;
2559 dsi
->vc
[3].fifo_size
= size4
;
2561 for (i
= 0; i
< 4; i
++) {
2563 int size
= dsi
->vc
[i
].fifo_size
;
2565 if (add
+ size
> 4) {
2566 DSSERR("Illegal FIFO configuration\n");
2570 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2572 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2576 dsi_write_reg(dsidev
, DSI_RX_FIFO_VC_SIZE
, r
);
2579 static int dsi_force_tx_stop_mode_io(struct platform_device
*dsidev
)
2583 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2584 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2585 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
2587 if (wait_for_bit_change(dsidev
, DSI_TIMING1
, 15, 0) != 0) {
2588 DSSERR("TX_STOP bit not going down\n");
2595 static bool dsi_vc_is_enabled(struct platform_device
*dsidev
, int channel
)
2597 return REG_GET(dsidev
, DSI_VC_CTRL(channel
), 0, 0);
2600 static void dsi_packet_sent_handler_vp(void *data
, u32 mask
)
2602 struct dsi_packet_sent_handler_data
*vp_data
=
2603 (struct dsi_packet_sent_handler_data
*) data
;
2604 struct dsi_data
*dsi
= dsi_get_dsidrv_data(vp_data
->dsidev
);
2605 const int channel
= dsi
->update_channel
;
2606 u8 bit
= dsi
->te_enabled
? 30 : 31;
2608 if (REG_GET(vp_data
->dsidev
, DSI_VC_TE(channel
), bit
, bit
) == 0)
2609 complete(vp_data
->completion
);
2612 static int dsi_sync_vc_vp(struct platform_device
*dsidev
, int channel
)
2614 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2615 DECLARE_COMPLETION_ONSTACK(completion
);
2616 struct dsi_packet_sent_handler_data vp_data
= { dsidev
, &completion
};
2620 bit
= dsi
->te_enabled
? 30 : 31;
2622 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2623 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2627 /* Wait for completion only if TE_EN/TE_START is still set */
2628 if (REG_GET(dsidev
, DSI_VC_TE(channel
), bit
, bit
)) {
2629 if (wait_for_completion_timeout(&completion
,
2630 msecs_to_jiffies(10)) == 0) {
2631 DSSERR("Failed to complete previous frame transfer\n");
2637 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2638 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2642 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2643 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2648 static void dsi_packet_sent_handler_l4(void *data
, u32 mask
)
2650 struct dsi_packet_sent_handler_data
*l4_data
=
2651 (struct dsi_packet_sent_handler_data
*) data
;
2652 struct dsi_data
*dsi
= dsi_get_dsidrv_data(l4_data
->dsidev
);
2653 const int channel
= dsi
->update_channel
;
2655 if (REG_GET(l4_data
->dsidev
, DSI_VC_CTRL(channel
), 5, 5) == 0)
2656 complete(l4_data
->completion
);
2659 static int dsi_sync_vc_l4(struct platform_device
*dsidev
, int channel
)
2661 DECLARE_COMPLETION_ONSTACK(completion
);
2662 struct dsi_packet_sent_handler_data l4_data
= { dsidev
, &completion
};
2665 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2666 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2670 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2671 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 5, 5)) {
2672 if (wait_for_completion_timeout(&completion
,
2673 msecs_to_jiffies(10)) == 0) {
2674 DSSERR("Failed to complete previous l4 transfer\n");
2680 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2681 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2685 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2686 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2691 static int dsi_sync_vc(struct platform_device
*dsidev
, int channel
)
2693 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2695 WARN_ON(!dsi_bus_is_locked(dsidev
));
2697 WARN_ON(in_interrupt());
2699 if (!dsi_vc_is_enabled(dsidev
, channel
))
2702 switch (dsi
->vc
[channel
].source
) {
2703 case DSI_VC_SOURCE_VP
:
2704 return dsi_sync_vc_vp(dsidev
, channel
);
2705 case DSI_VC_SOURCE_L4
:
2706 return dsi_sync_vc_l4(dsidev
, channel
);
2712 static int dsi_vc_enable(struct platform_device
*dsidev
, int channel
,
2715 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2718 enable
= enable
? 1 : 0;
2720 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 0, 0);
2722 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
),
2723 0, enable
) != enable
) {
2724 DSSERR("Failed to set dsi_vc_enable to %d\n", enable
);
2731 static void dsi_vc_initial_config(struct platform_device
*dsidev
, int channel
)
2735 DSSDBGF("%d", channel
);
2737 r
= dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2739 if (FLD_GET(r
, 15, 15)) /* VC_BUSY */
2740 DSSERR("VC(%d) busy when trying to configure it!\n",
2743 r
= FLD_MOD(r
, 0, 1, 1); /* SOURCE, 0 = L4 */
2744 r
= FLD_MOD(r
, 0, 2, 2); /* BTA_SHORT_EN */
2745 r
= FLD_MOD(r
, 0, 3, 3); /* BTA_LONG_EN */
2746 r
= FLD_MOD(r
, 0, 4, 4); /* MODE, 0 = command */
2747 r
= FLD_MOD(r
, 1, 7, 7); /* CS_TX_EN */
2748 r
= FLD_MOD(r
, 1, 8, 8); /* ECC_TX_EN */
2749 r
= FLD_MOD(r
, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2750 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH
))
2751 r
= FLD_MOD(r
, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2753 r
= FLD_MOD(r
, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2754 r
= FLD_MOD(r
, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2756 dsi_write_reg(dsidev
, DSI_VC_CTRL(channel
), r
);
2759 static int dsi_vc_config_source(struct platform_device
*dsidev
, int channel
,
2760 enum dsi_vc_source source
)
2762 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2764 if (dsi
->vc
[channel
].source
== source
)
2767 DSSDBGF("%d", channel
);
2769 dsi_sync_vc(dsidev
, channel
);
2771 dsi_vc_enable(dsidev
, channel
, 0);
2774 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
), 15, 0) != 0) {
2775 DSSERR("vc(%d) busy when trying to config for VP\n", channel
);
2779 /* SOURCE, 0 = L4, 1 = video port */
2780 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), source
, 1, 1);
2782 /* DCS_CMD_ENABLE */
2783 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
2784 bool enable
= source
== DSI_VC_SOURCE_VP
;
2785 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 30, 30);
2788 dsi_vc_enable(dsidev
, channel
, 1);
2790 dsi
->vc
[channel
].source
= source
;
2795 void omapdss_dsi_vc_enable_hs(struct omap_dss_device
*dssdev
, int channel
,
2798 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2800 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel
, enable
);
2802 WARN_ON(!dsi_bus_is_locked(dsidev
));
2804 dsi_vc_enable(dsidev
, channel
, 0);
2805 dsi_if_enable(dsidev
, 0);
2807 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 9, 9);
2809 dsi_vc_enable(dsidev
, channel
, 1);
2810 dsi_if_enable(dsidev
, 1);
2812 dsi_force_tx_stop_mode_io(dsidev
);
2814 /* start the DDR clock by sending a NULL packet */
2815 if (dssdev
->panel
.dsi_vm_data
.ddr_clk_always_on
&& enable
)
2816 dsi_vc_send_null(dssdev
, channel
);
2818 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs
);
2820 static void dsi_vc_flush_long_data(struct platform_device
*dsidev
, int channel
)
2822 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2824 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2825 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2829 (val
>> 24) & 0xff);
2833 static void dsi_show_rx_ack_with_err(u16 err
)
2835 DSSERR("\tACK with ERROR (%#x):\n", err
);
2837 DSSERR("\t\tSoT Error\n");
2839 DSSERR("\t\tSoT Sync Error\n");
2841 DSSERR("\t\tEoT Sync Error\n");
2843 DSSERR("\t\tEscape Mode Entry Command Error\n");
2845 DSSERR("\t\tLP Transmit Sync Error\n");
2847 DSSERR("\t\tHS Receive Timeout Error\n");
2849 DSSERR("\t\tFalse Control Error\n");
2851 DSSERR("\t\t(reserved7)\n");
2853 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2855 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2856 if (err
& (1 << 10))
2857 DSSERR("\t\tChecksum Error\n");
2858 if (err
& (1 << 11))
2859 DSSERR("\t\tData type not recognized\n");
2860 if (err
& (1 << 12))
2861 DSSERR("\t\tInvalid VC ID\n");
2862 if (err
& (1 << 13))
2863 DSSERR("\t\tInvalid Transmission Length\n");
2864 if (err
& (1 << 14))
2865 DSSERR("\t\t(reserved14)\n");
2866 if (err
& (1 << 15))
2867 DSSERR("\t\tDSI Protocol Violation\n");
2870 static u16
dsi_vc_flush_receive_data(struct platform_device
*dsidev
,
2873 /* RX_FIFO_NOT_EMPTY */
2874 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2877 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2878 DSSERR("\trawval %#08x\n", val
);
2879 dt
= FLD_GET(val
, 5, 0);
2880 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
2881 u16 err
= FLD_GET(val
, 23, 8);
2882 dsi_show_rx_ack_with_err(err
);
2883 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
) {
2884 DSSERR("\tDCS short response, 1 byte: %#x\n",
2885 FLD_GET(val
, 23, 8));
2886 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
) {
2887 DSSERR("\tDCS short response, 2 byte: %#x\n",
2888 FLD_GET(val
, 23, 8));
2889 } else if (dt
== MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
) {
2890 DSSERR("\tDCS long response, len %d\n",
2891 FLD_GET(val
, 23, 8));
2892 dsi_vc_flush_long_data(dsidev
, channel
);
2894 DSSERR("\tunknown datatype 0x%02x\n", dt
);
2900 static int dsi_vc_send_bta(struct platform_device
*dsidev
, int channel
)
2902 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2904 if (dsi
->debug_write
|| dsi
->debug_read
)
2905 DSSDBG("dsi_vc_send_bta %d\n", channel
);
2907 WARN_ON(!dsi_bus_is_locked(dsidev
));
2909 /* RX_FIFO_NOT_EMPTY */
2910 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2911 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2912 dsi_vc_flush_receive_data(dsidev
, channel
);
2915 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 6, 6); /* BTA_EN */
2917 /* flush posted write */
2918 dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2923 int dsi_vc_send_bta_sync(struct omap_dss_device
*dssdev
, int channel
)
2925 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2926 DECLARE_COMPLETION_ONSTACK(completion
);
2930 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2931 &completion
, DSI_VC_IRQ_BTA
);
2935 r
= dsi_register_isr(dsidev
, dsi_completion_handler
, &completion
,
2936 DSI_IRQ_ERROR_MASK
);
2940 r
= dsi_vc_send_bta(dsidev
, channel
);
2944 if (wait_for_completion_timeout(&completion
,
2945 msecs_to_jiffies(500)) == 0) {
2946 DSSERR("Failed to receive BTA\n");
2951 err
= dsi_get_errors(dsidev
);
2953 DSSERR("Error while sending BTA: %x\n", err
);
2958 dsi_unregister_isr(dsidev
, dsi_completion_handler
, &completion
,
2959 DSI_IRQ_ERROR_MASK
);
2961 dsi_unregister_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2962 &completion
, DSI_VC_IRQ_BTA
);
2966 EXPORT_SYMBOL(dsi_vc_send_bta_sync
);
2968 static inline void dsi_vc_write_long_header(struct platform_device
*dsidev
,
2969 int channel
, u8 data_type
, u16 len
, u8 ecc
)
2971 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2975 WARN_ON(!dsi_bus_is_locked(dsidev
));
2977 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
2979 val
= FLD_VAL(data_id
, 7, 0) | FLD_VAL(len
, 23, 8) |
2980 FLD_VAL(ecc
, 31, 24);
2982 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_HEADER(channel
), val
);
2985 static inline void dsi_vc_write_long_payload(struct platform_device
*dsidev
,
2986 int channel
, u8 b1
, u8 b2
, u8 b3
, u8 b4
)
2990 val
= b4
<< 24 | b3
<< 16 | b2
<< 8 | b1
<< 0;
2992 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2993 b1, b2, b3, b4, val); */
2995 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_PAYLOAD(channel
), val
);
2998 static int dsi_vc_send_long(struct platform_device
*dsidev
, int channel
,
2999 u8 data_type
, u8
*data
, u16 len
, u8 ecc
)
3002 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3008 if (dsi
->debug_write
)
3009 DSSDBG("dsi_vc_send_long, %d bytes\n", len
);
3012 if (dsi
->vc
[channel
].fifo_size
* 32 * 4 < len
+ 4) {
3013 DSSERR("unable to send long packet: packet too long.\n");
3017 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
3019 dsi_vc_write_long_header(dsidev
, channel
, data_type
, len
, ecc
);
3022 for (i
= 0; i
< len
>> 2; i
++) {
3023 if (dsi
->debug_write
)
3024 DSSDBG("\tsending full packet %d\n", i
);
3031 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, b4
);
3036 b1
= 0; b2
= 0; b3
= 0;
3038 if (dsi
->debug_write
)
3039 DSSDBG("\tsending remainder bytes %d\n", i
);
3056 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, 0);
3062 static int dsi_vc_send_short(struct platform_device
*dsidev
, int channel
,
3063 u8 data_type
, u16 data
, u8 ecc
)
3065 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3069 WARN_ON(!dsi_bus_is_locked(dsidev
));
3071 if (dsi
->debug_write
)
3072 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3074 data_type
, data
& 0xff, (data
>> 8) & 0xff);
3076 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
3078 if (FLD_GET(dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
)), 16, 16)) {
3079 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3083 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
3085 r
= (data_id
<< 0) | (data
<< 8) | (ecc
<< 24);
3087 dsi_write_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
), r
);
3092 int dsi_vc_send_null(struct omap_dss_device
*dssdev
, int channel
)
3094 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3096 return dsi_vc_send_long(dsidev
, channel
, MIPI_DSI_NULL_PACKET
, NULL
,
3099 EXPORT_SYMBOL(dsi_vc_send_null
);
3101 static int dsi_vc_write_nosync_common(struct omap_dss_device
*dssdev
,
3102 int channel
, u8
*data
, int len
, enum dss_dsi_content_type type
)
3104 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3108 BUG_ON(type
== DSS_DSI_CONTENT_DCS
);
3109 r
= dsi_vc_send_short(dsidev
, channel
,
3110 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
, 0, 0);
3111 } else if (len
== 1) {
3112 r
= dsi_vc_send_short(dsidev
, channel
,
3113 type
== DSS_DSI_CONTENT_GENERIC
?
3114 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
3115 MIPI_DSI_DCS_SHORT_WRITE
, data
[0], 0);
3116 } else if (len
== 2) {
3117 r
= dsi_vc_send_short(dsidev
, channel
,
3118 type
== DSS_DSI_CONTENT_GENERIC
?
3119 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
3120 MIPI_DSI_DCS_SHORT_WRITE_PARAM
,
3121 data
[0] | (data
[1] << 8), 0);
3123 r
= dsi_vc_send_long(dsidev
, channel
,
3124 type
== DSS_DSI_CONTENT_GENERIC
?
3125 MIPI_DSI_GENERIC_LONG_WRITE
:
3126 MIPI_DSI_DCS_LONG_WRITE
, data
, len
, 0);
3132 int dsi_vc_dcs_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3135 return dsi_vc_write_nosync_common(dssdev
, channel
, data
, len
,
3136 DSS_DSI_CONTENT_DCS
);
3138 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync
);
3140 int dsi_vc_generic_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3143 return dsi_vc_write_nosync_common(dssdev
, channel
, data
, len
,
3144 DSS_DSI_CONTENT_GENERIC
);
3146 EXPORT_SYMBOL(dsi_vc_generic_write_nosync
);
3148 static int dsi_vc_write_common(struct omap_dss_device
*dssdev
, int channel
,
3149 u8
*data
, int len
, enum dss_dsi_content_type type
)
3151 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3154 r
= dsi_vc_write_nosync_common(dssdev
, channel
, data
, len
, type
);
3158 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3162 /* RX_FIFO_NOT_EMPTY */
3163 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
3164 DSSERR("rx fifo not empty after write, dumping data:\n");
3165 dsi_vc_flush_receive_data(dsidev
, channel
);
3172 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3173 channel
, data
[0], len
);
3177 int dsi_vc_dcs_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3180 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3181 DSS_DSI_CONTENT_DCS
);
3183 EXPORT_SYMBOL(dsi_vc_dcs_write
);
3185 int dsi_vc_generic_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3188 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3189 DSS_DSI_CONTENT_GENERIC
);
3191 EXPORT_SYMBOL(dsi_vc_generic_write
);
3193 int dsi_vc_dcs_write_0(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
)
3195 return dsi_vc_dcs_write(dssdev
, channel
, &dcs_cmd
, 1);
3197 EXPORT_SYMBOL(dsi_vc_dcs_write_0
);
3199 int dsi_vc_generic_write_0(struct omap_dss_device
*dssdev
, int channel
)
3201 return dsi_vc_generic_write(dssdev
, channel
, NULL
, 0);
3203 EXPORT_SYMBOL(dsi_vc_generic_write_0
);
3205 int dsi_vc_dcs_write_1(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3211 return dsi_vc_dcs_write(dssdev
, channel
, buf
, 2);
3213 EXPORT_SYMBOL(dsi_vc_dcs_write_1
);
3215 int dsi_vc_generic_write_1(struct omap_dss_device
*dssdev
, int channel
,
3218 return dsi_vc_generic_write(dssdev
, channel
, ¶m
, 1);
3220 EXPORT_SYMBOL(dsi_vc_generic_write_1
);
3222 int dsi_vc_generic_write_2(struct omap_dss_device
*dssdev
, int channel
,
3223 u8 param1
, u8 param2
)
3228 return dsi_vc_generic_write(dssdev
, channel
, buf
, 2);
3230 EXPORT_SYMBOL(dsi_vc_generic_write_2
);
3232 static int dsi_vc_dcs_send_read_request(struct omap_dss_device
*dssdev
,
3233 int channel
, u8 dcs_cmd
)
3235 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3236 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3239 if (dsi
->debug_read
)
3240 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3243 r
= dsi_vc_send_short(dsidev
, channel
, MIPI_DSI_DCS_READ
, dcs_cmd
, 0);
3245 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3246 " failed\n", channel
, dcs_cmd
);
3253 static int dsi_vc_generic_send_read_request(struct omap_dss_device
*dssdev
,
3254 int channel
, u8
*reqdata
, int reqlen
)
3256 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3257 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3262 if (dsi
->debug_read
)
3263 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3267 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
;
3269 } else if (reqlen
== 1) {
3270 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
;
3272 } else if (reqlen
== 2) {
3273 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
;
3274 data
= reqdata
[0] | (reqdata
[1] << 8);
3279 r
= dsi_vc_send_short(dsidev
, channel
, data_type
, data
, 0);
3281 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3282 " failed\n", channel
, reqlen
);
3289 static int dsi_vc_read_rx_fifo(struct platform_device
*dsidev
, int channel
,
3290 u8
*buf
, int buflen
, enum dss_dsi_content_type type
)
3292 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3297 /* RX_FIFO_NOT_EMPTY */
3298 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20) == 0) {
3299 DSSERR("RX fifo empty when trying to read.\n");
3304 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
3305 if (dsi
->debug_read
)
3306 DSSDBG("\theader: %08x\n", val
);
3307 dt
= FLD_GET(val
, 5, 0);
3308 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
3309 u16 err
= FLD_GET(val
, 23, 8);
3310 dsi_show_rx_ack_with_err(err
);
3314 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3315 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE
:
3316 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
)) {
3317 u8 data
= FLD_GET(val
, 15, 8);
3318 if (dsi
->debug_read
)
3319 DSSDBG("\t%s short response, 1 byte: %02x\n",
3320 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3331 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3332 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE
:
3333 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
)) {
3334 u16 data
= FLD_GET(val
, 23, 8);
3335 if (dsi
->debug_read
)
3336 DSSDBG("\t%s short response, 2 byte: %04x\n",
3337 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3345 buf
[0] = data
& 0xff;
3346 buf
[1] = (data
>> 8) & 0xff;
3349 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3350 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
3351 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
)) {
3353 int len
= FLD_GET(val
, 23, 8);
3354 if (dsi
->debug_read
)
3355 DSSDBG("\t%s long response, len %d\n",
3356 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3364 /* two byte checksum ends the packet, not included in len */
3365 for (w
= 0; w
< len
+ 2;) {
3367 val
= dsi_read_reg(dsidev
,
3368 DSI_VC_SHORT_PACKET_HEADER(channel
));
3369 if (dsi
->debug_read
)
3370 DSSDBG("\t\t%02x %02x %02x %02x\n",
3374 (val
>> 24) & 0xff);
3376 for (b
= 0; b
< 4; ++b
) {
3378 buf
[w
] = (val
>> (b
* 8)) & 0xff;
3379 /* we discard the 2 byte checksum */
3386 DSSERR("\tunknown datatype 0x%02x\n", dt
);
3393 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel
,
3394 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" : "DCS");
3399 int dsi_vc_dcs_read(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3400 u8
*buf
, int buflen
)
3402 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3405 r
= dsi_vc_dcs_send_read_request(dssdev
, channel
, dcs_cmd
);
3409 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3413 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3414 DSS_DSI_CONTENT_DCS
);
3425 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel
, dcs_cmd
);
3428 EXPORT_SYMBOL(dsi_vc_dcs_read
);
3430 static int dsi_vc_generic_read(struct omap_dss_device
*dssdev
, int channel
,
3431 u8
*reqdata
, int reqlen
, u8
*buf
, int buflen
)
3433 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3436 r
= dsi_vc_generic_send_read_request(dssdev
, channel
, reqdata
, reqlen
);
3440 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3444 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3445 DSS_DSI_CONTENT_GENERIC
);
3457 int dsi_vc_generic_read_0(struct omap_dss_device
*dssdev
, int channel
, u8
*buf
,
3462 r
= dsi_vc_generic_read(dssdev
, channel
, NULL
, 0, buf
, buflen
);
3464 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel
);
3470 EXPORT_SYMBOL(dsi_vc_generic_read_0
);
3472 int dsi_vc_generic_read_1(struct omap_dss_device
*dssdev
, int channel
, u8 param
,
3473 u8
*buf
, int buflen
)
3477 r
= dsi_vc_generic_read(dssdev
, channel
, ¶m
, 1, buf
, buflen
);
3479 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel
);
3485 EXPORT_SYMBOL(dsi_vc_generic_read_1
);
3487 int dsi_vc_generic_read_2(struct omap_dss_device
*dssdev
, int channel
,
3488 u8 param1
, u8 param2
, u8
*buf
, int buflen
)
3493 reqdata
[0] = param1
;
3494 reqdata
[1] = param2
;
3496 r
= dsi_vc_generic_read(dssdev
, channel
, reqdata
, 2, buf
, buflen
);
3498 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel
);
3504 EXPORT_SYMBOL(dsi_vc_generic_read_2
);
3506 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device
*dssdev
, int channel
,
3509 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3511 return dsi_vc_send_short(dsidev
, channel
,
3512 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
, len
, 0);
3514 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size
);
3516 static int dsi_enter_ulps(struct platform_device
*dsidev
)
3518 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3519 DECLARE_COMPLETION_ONSTACK(completion
);
3524 WARN_ON(!dsi_bus_is_locked(dsidev
));
3526 WARN_ON(dsi
->ulps_enabled
);
3528 if (dsi
->ulps_enabled
)
3531 if (REG_GET(dsidev
, DSI_CLK_CTRL
, 13, 13)) {
3532 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3536 dsi_sync_vc(dsidev
, 0);
3537 dsi_sync_vc(dsidev
, 1);
3538 dsi_sync_vc(dsidev
, 2);
3539 dsi_sync_vc(dsidev
, 3);
3541 dsi_force_tx_stop_mode_io(dsidev
);
3543 dsi_vc_enable(dsidev
, 0, false);
3544 dsi_vc_enable(dsidev
, 1, false);
3545 dsi_vc_enable(dsidev
, 2, false);
3546 dsi_vc_enable(dsidev
, 3, false);
3548 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 16, 16)) { /* HS_BUSY */
3549 DSSERR("HS busy when enabling ULPS\n");
3553 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 17, 17)) { /* LP_BUSY */
3554 DSSERR("LP busy when enabling ULPS\n");
3558 r
= dsi_register_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3559 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3563 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3564 /* LANEx_ULPS_SIG2 */
3565 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, (1 << 0) | (1 << 1) | (1 << 2),
3568 /* flush posted write and wait for SCP interface to finish the write */
3569 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3571 if (wait_for_completion_timeout(&completion
,
3572 msecs_to_jiffies(1000)) == 0) {
3573 DSSERR("ULPS enable timeout\n");
3578 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3579 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3581 /* Reset LANEx_ULPS_SIG2 */
3582 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, (0 << 0) | (0 << 1) | (0 << 2),
3585 /* flush posted write and wait for SCP interface to finish the write */
3586 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3588 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ULPS
);
3590 dsi_if_enable(dsidev
, false);
3592 dsi
->ulps_enabled
= true;
3597 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3598 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3602 static void dsi_set_lp_rx_timeout(struct platform_device
*dsidev
,
3603 unsigned ticks
, bool x4
, bool x16
)
3606 unsigned long total_ticks
;
3609 BUG_ON(ticks
> 0x1fff);
3611 /* ticks in DSI_FCK */
3612 fck
= dsi_fclk_rate(dsidev
);
3614 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3615 r
= FLD_MOD(r
, 1, 15, 15); /* LP_RX_TO */
3616 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3617 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3618 r
= FLD_MOD(r
, ticks
, 12, 0); /* LP_RX_COUNTER */
3619 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3621 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3623 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3625 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3626 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3629 static void dsi_set_ta_timeout(struct platform_device
*dsidev
, unsigned ticks
,
3633 unsigned long total_ticks
;
3636 BUG_ON(ticks
> 0x1fff);
3638 /* ticks in DSI_FCK */
3639 fck
= dsi_fclk_rate(dsidev
);
3641 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3642 r
= FLD_MOD(r
, 1, 31, 31); /* TA_TO */
3643 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* TA_TO_X16 */
3644 r
= FLD_MOD(r
, x8
? 1 : 0, 29, 29); /* TA_TO_X8 */
3645 r
= FLD_MOD(r
, ticks
, 28, 16); /* TA_TO_COUNTER */
3646 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3648 total_ticks
= ticks
* (x16
? 16 : 1) * (x8
? 8 : 1);
3650 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3652 ticks
, x8
? " x8" : "", x16
? " x16" : "",
3653 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3656 static void dsi_set_stop_state_counter(struct platform_device
*dsidev
,
3657 unsigned ticks
, bool x4
, bool x16
)
3660 unsigned long total_ticks
;
3663 BUG_ON(ticks
> 0x1fff);
3665 /* ticks in DSI_FCK */
3666 fck
= dsi_fclk_rate(dsidev
);
3668 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3669 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3670 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3671 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3672 r
= FLD_MOD(r
, ticks
, 12, 0); /* STOP_STATE_COUNTER_IO */
3673 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3675 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3677 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3679 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3680 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3683 static void dsi_set_hs_tx_timeout(struct platform_device
*dsidev
,
3684 unsigned ticks
, bool x4
, bool x16
)
3687 unsigned long total_ticks
;
3690 BUG_ON(ticks
> 0x1fff);
3692 /* ticks in TxByteClkHS */
3693 fck
= dsi_get_txbyteclkhs(dsidev
);
3695 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3696 r
= FLD_MOD(r
, 1, 31, 31); /* HS_TX_TO */
3697 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3698 r
= FLD_MOD(r
, x4
? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3699 r
= FLD_MOD(r
, ticks
, 28, 16); /* HS_TX_TO_COUNTER */
3700 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3702 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3704 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3706 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3707 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3710 static void dsi_config_vp_num_line_buffers(struct omap_dss_device
*dssdev
)
3712 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3713 int num_line_buffers
;
3715 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3716 int bpp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
);
3717 unsigned line_buf_size
= dsi_get_line_buf_size(dsidev
);
3718 struct omap_video_timings
*timings
= &dssdev
->panel
.timings
;
3720 * Don't use line buffers if width is greater than the video
3721 * port's line buffer size
3723 if (line_buf_size
<= timings
->x_res
* bpp
/ 8)
3724 num_line_buffers
= 0;
3726 num_line_buffers
= 2;
3728 /* Use maximum number of line buffers in command mode */
3729 num_line_buffers
= 2;
3733 REG_FLD_MOD(dsidev
, DSI_CTRL
, num_line_buffers
, 13, 12);
3736 static void dsi_config_vp_sync_events(struct omap_dss_device
*dssdev
)
3738 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3739 int de_pol
= dssdev
->panel
.dsi_vm_data
.vp_de_pol
;
3740 int hsync_pol
= dssdev
->panel
.dsi_vm_data
.vp_hsync_pol
;
3741 int vsync_pol
= dssdev
->panel
.dsi_vm_data
.vp_vsync_pol
;
3742 bool vsync_end
= dssdev
->panel
.dsi_vm_data
.vp_vsync_end
;
3743 bool hsync_end
= dssdev
->panel
.dsi_vm_data
.vp_hsync_end
;
3746 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3747 r
= FLD_MOD(r
, de_pol
, 9, 9); /* VP_DE_POL */
3748 r
= FLD_MOD(r
, hsync_pol
, 10, 10); /* VP_HSYNC_POL */
3749 r
= FLD_MOD(r
, vsync_pol
, 11, 11); /* VP_VSYNC_POL */
3750 r
= FLD_MOD(r
, 1, 15, 15); /* VP_VSYNC_START */
3751 r
= FLD_MOD(r
, vsync_end
, 16, 16); /* VP_VSYNC_END */
3752 r
= FLD_MOD(r
, 1, 17, 17); /* VP_HSYNC_START */
3753 r
= FLD_MOD(r
, hsync_end
, 18, 18); /* VP_HSYNC_END */
3754 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3757 static void dsi_config_blanking_modes(struct omap_dss_device
*dssdev
)
3759 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3760 int blanking_mode
= dssdev
->panel
.dsi_vm_data
.blanking_mode
;
3761 int hfp_blanking_mode
= dssdev
->panel
.dsi_vm_data
.hfp_blanking_mode
;
3762 int hbp_blanking_mode
= dssdev
->panel
.dsi_vm_data
.hbp_blanking_mode
;
3763 int hsa_blanking_mode
= dssdev
->panel
.dsi_vm_data
.hsa_blanking_mode
;
3767 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3768 * 1 = Long blanking packets are sent in corresponding blanking periods
3770 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3771 r
= FLD_MOD(r
, blanking_mode
, 20, 20); /* BLANKING_MODE */
3772 r
= FLD_MOD(r
, hfp_blanking_mode
, 21, 21); /* HFP_BLANKING */
3773 r
= FLD_MOD(r
, hbp_blanking_mode
, 22, 22); /* HBP_BLANKING */
3774 r
= FLD_MOD(r
, hsa_blanking_mode
, 23, 23); /* HSA_BLANKING */
3775 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3778 static int dsi_proto_config(struct omap_dss_device
*dssdev
)
3780 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3784 dsi_config_tx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3789 dsi_config_rx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3794 /* XXX what values for the timeouts? */
3795 dsi_set_stop_state_counter(dsidev
, 0x1000, false, false);
3796 dsi_set_ta_timeout(dsidev
, 0x1fff, true, true);
3797 dsi_set_lp_rx_timeout(dsidev
, 0x1fff, true, true);
3798 dsi_set_hs_tx_timeout(dsidev
, 0x1fff, true, true);
3800 switch (dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
)) {
3814 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3815 r
= FLD_MOD(r
, 1, 1, 1); /* CS_RX_EN */
3816 r
= FLD_MOD(r
, 1, 2, 2); /* ECC_RX_EN */
3817 r
= FLD_MOD(r
, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3818 r
= FLD_MOD(r
, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3819 r
= FLD_MOD(r
, buswidth
, 7, 6); /* VP_DATA_BUS_WIDTH */
3820 r
= FLD_MOD(r
, 0, 8, 8); /* VP_CLK_POL */
3821 r
= FLD_MOD(r
, 1, 14, 14); /* TRIGGER_RESET_MODE */
3822 r
= FLD_MOD(r
, 1, 19, 19); /* EOT_ENABLE */
3823 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
3824 r
= FLD_MOD(r
, 1, 24, 24); /* DCS_CMD_ENABLE */
3825 /* DCS_CMD_CODE, 1=start, 0=continue */
3826 r
= FLD_MOD(r
, 0, 25, 25);
3829 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3831 dsi_config_vp_num_line_buffers(dssdev
);
3833 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3834 dsi_config_vp_sync_events(dssdev
);
3835 dsi_config_blanking_modes(dssdev
);
3838 dsi_vc_initial_config(dsidev
, 0);
3839 dsi_vc_initial_config(dsidev
, 1);
3840 dsi_vc_initial_config(dsidev
, 2);
3841 dsi_vc_initial_config(dsidev
, 3);
3846 static void dsi_proto_timings(struct omap_dss_device
*dssdev
)
3848 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3849 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3850 unsigned tlpx
, tclk_zero
, tclk_prepare
, tclk_trail
;
3851 unsigned tclk_pre
, tclk_post
;
3852 unsigned ths_prepare
, ths_prepare_ths_zero
, ths_zero
;
3853 unsigned ths_trail
, ths_exit
;
3854 unsigned ddr_clk_pre
, ddr_clk_post
;
3855 unsigned enter_hs_mode_lat
, exit_hs_mode_lat
;
3857 int ndl
= dsi
->num_lanes_used
- 1;
3860 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
3861 ths_prepare
= FLD_GET(r
, 31, 24);
3862 ths_prepare_ths_zero
= FLD_GET(r
, 23, 16);
3863 ths_zero
= ths_prepare_ths_zero
- ths_prepare
;
3864 ths_trail
= FLD_GET(r
, 15, 8);
3865 ths_exit
= FLD_GET(r
, 7, 0);
3867 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
3868 tlpx
= FLD_GET(r
, 22, 16) * 2;
3869 tclk_trail
= FLD_GET(r
, 15, 8);
3870 tclk_zero
= FLD_GET(r
, 7, 0);
3872 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
3873 tclk_prepare
= FLD_GET(r
, 7, 0);
3877 /* min 60ns + 52*UI */
3878 tclk_post
= ns2ddr(dsidev
, 60) + 26;
3880 ths_eot
= DIV_ROUND_UP(4, ndl
);
3882 ddr_clk_pre
= DIV_ROUND_UP(tclk_pre
+ tlpx
+ tclk_zero
+ tclk_prepare
,
3884 ddr_clk_post
= DIV_ROUND_UP(tclk_post
+ ths_trail
, 4) + ths_eot
;
3886 BUG_ON(ddr_clk_pre
== 0 || ddr_clk_pre
> 255);
3887 BUG_ON(ddr_clk_post
== 0 || ddr_clk_post
> 255);
3889 r
= dsi_read_reg(dsidev
, DSI_CLK_TIMING
);
3890 r
= FLD_MOD(r
, ddr_clk_pre
, 15, 8);
3891 r
= FLD_MOD(r
, ddr_clk_post
, 7, 0);
3892 dsi_write_reg(dsidev
, DSI_CLK_TIMING
, r
);
3894 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3898 enter_hs_mode_lat
= 1 + DIV_ROUND_UP(tlpx
, 4) +
3899 DIV_ROUND_UP(ths_prepare
, 4) +
3900 DIV_ROUND_UP(ths_zero
+ 3, 4);
3902 exit_hs_mode_lat
= DIV_ROUND_UP(ths_trail
+ ths_exit
, 4) + 1 + ths_eot
;
3904 r
= FLD_VAL(enter_hs_mode_lat
, 31, 16) |
3905 FLD_VAL(exit_hs_mode_lat
, 15, 0);
3906 dsi_write_reg(dsidev
, DSI_VM_TIMING7
, r
);
3908 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3909 enter_hs_mode_lat
, exit_hs_mode_lat
);
3911 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3912 /* TODO: Implement a video mode check_timings function */
3913 int hsa
= dssdev
->panel
.dsi_vm_data
.hsa
;
3914 int hfp
= dssdev
->panel
.dsi_vm_data
.hfp
;
3915 int hbp
= dssdev
->panel
.dsi_vm_data
.hbp
;
3916 int vsa
= dssdev
->panel
.dsi_vm_data
.vsa
;
3917 int vfp
= dssdev
->panel
.dsi_vm_data
.vfp
;
3918 int vbp
= dssdev
->panel
.dsi_vm_data
.vbp
;
3919 int window_sync
= dssdev
->panel
.dsi_vm_data
.window_sync
;
3920 bool hsync_end
= dssdev
->panel
.dsi_vm_data
.vp_hsync_end
;
3921 struct omap_video_timings
*timings
= &dssdev
->panel
.timings
;
3922 int bpp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
);
3923 int tl
, t_he
, width_bytes
;
3926 ((hsa
== 0 && ndl
== 3) ? 1 : DIV_ROUND_UP(4, ndl
)) : 0;
3928 width_bytes
= DIV_ROUND_UP(timings
->x_res
* bpp
, 8);
3930 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3931 tl
= DIV_ROUND_UP(4, ndl
) + (hsync_end
? hsa
: 0) + t_he
+ hfp
+
3932 DIV_ROUND_UP(width_bytes
+ 6, ndl
) + hbp
;
3934 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp
,
3935 hfp
, hsync_end
? hsa
: 0, tl
);
3936 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp
, vfp
,
3937 vsa
, timings
->y_res
);
3939 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING1
);
3940 r
= FLD_MOD(r
, hbp
, 11, 0); /* HBP */
3941 r
= FLD_MOD(r
, hfp
, 23, 12); /* HFP */
3942 r
= FLD_MOD(r
, hsync_end
? hsa
: 0, 31, 24); /* HSA */
3943 dsi_write_reg(dsidev
, DSI_VM_TIMING1
, r
);
3945 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING2
);
3946 r
= FLD_MOD(r
, vbp
, 7, 0); /* VBP */
3947 r
= FLD_MOD(r
, vfp
, 15, 8); /* VFP */
3948 r
= FLD_MOD(r
, vsa
, 23, 16); /* VSA */
3949 r
= FLD_MOD(r
, window_sync
, 27, 24); /* WINDOW_SYNC */
3950 dsi_write_reg(dsidev
, DSI_VM_TIMING2
, r
);
3952 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING3
);
3953 r
= FLD_MOD(r
, timings
->y_res
, 14, 0); /* VACT */
3954 r
= FLD_MOD(r
, tl
, 31, 16); /* TL */
3955 dsi_write_reg(dsidev
, DSI_VM_TIMING3
, r
);
3959 int dsi_video_mode_enable(struct omap_dss_device
*dssdev
, int channel
)
3961 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3962 int bpp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
);
3966 switch (dssdev
->panel
.dsi_pix_fmt
) {
3967 case OMAP_DSS_DSI_FMT_RGB888
:
3968 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
3970 case OMAP_DSS_DSI_FMT_RGB666
:
3971 data_type
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
3973 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
3974 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
3976 case OMAP_DSS_DSI_FMT_RGB565
:
3977 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
3983 dsi_if_enable(dsidev
, false);
3984 dsi_vc_enable(dsidev
, channel
, false);
3986 /* MODE, 1 = video mode */
3987 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 4, 4);
3989 word_count
= DIV_ROUND_UP(dssdev
->panel
.timings
.x_res
* bpp
, 8);
3991 dsi_vc_write_long_header(dsidev
, channel
, data_type
, word_count
, 0);
3993 dsi_vc_enable(dsidev
, channel
, true);
3994 dsi_if_enable(dsidev
, true);
3996 dssdev
->manager
->enable(dssdev
->manager
);
4000 EXPORT_SYMBOL(dsi_video_mode_enable
);
4002 void dsi_video_mode_disable(struct omap_dss_device
*dssdev
, int channel
)
4004 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4006 dsi_if_enable(dsidev
, false);
4007 dsi_vc_enable(dsidev
, channel
, false);
4009 /* MODE, 0 = command mode */
4010 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 0, 4, 4);
4012 dsi_vc_enable(dsidev
, channel
, true);
4013 dsi_if_enable(dsidev
, true);
4015 dssdev
->manager
->disable(dssdev
->manager
);
4017 EXPORT_SYMBOL(dsi_video_mode_disable
);
4019 static void dsi_update_screen_dispc(struct omap_dss_device
*dssdev
,
4020 u16 x
, u16 y
, u16 w
, u16 h
)
4022 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4023 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4028 unsigned packet_payload
;
4029 unsigned packet_len
;
4032 const unsigned channel
= dsi
->update_channel
;
4033 const unsigned line_buf_size
= dsi_get_line_buf_size(dsidev
);
4035 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4038 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_VP
);
4040 bytespp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
) / 8;
4041 bytespl
= w
* bytespp
;
4042 bytespf
= bytespl
* h
;
4044 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4045 * number of lines in a packet. See errata about VP_CLK_RATIO */
4047 if (bytespf
< line_buf_size
)
4048 packet_payload
= bytespf
;
4050 packet_payload
= (line_buf_size
) / bytespl
* bytespl
;
4052 packet_len
= packet_payload
+ 1; /* 1 byte for DCS cmd */
4053 total_len
= (bytespf
/ packet_payload
) * packet_len
;
4055 if (bytespf
% packet_payload
)
4056 total_len
+= (bytespf
% packet_payload
) + 1;
4058 l
= FLD_VAL(total_len
, 23, 0); /* TE_SIZE */
4059 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4061 dsi_vc_write_long_header(dsidev
, channel
, MIPI_DSI_DCS_LONG_WRITE
,
4064 if (dsi
->te_enabled
)
4065 l
= FLD_MOD(l
, 1, 30, 30); /* TE_EN */
4067 l
= FLD_MOD(l
, 1, 31, 31); /* TE_START */
4068 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4070 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4071 * because DSS interrupts are not capable of waking up the CPU and the
4072 * framedone interrupt could be delayed for quite a long time. I think
4073 * the same goes for any DSS interrupts, but for some reason I have not
4074 * seen the problem anywhere else than here.
4076 dispc_disable_sidle();
4078 dsi_perf_mark_start(dsidev
);
4080 r
= schedule_delayed_work(&dsi
->framedone_timeout_work
,
4081 msecs_to_jiffies(250));
4084 dss_start_update(dssdev
);
4086 if (dsi
->te_enabled
) {
4087 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4088 * for TE is longer than the timer allows */
4089 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 0, 15, 15); /* LP_RX_TO */
4091 dsi_vc_send_bta(dsidev
, channel
);
4093 #ifdef DSI_CATCH_MISSING_TE
4094 mod_timer(&dsi
->te_timer
, jiffies
+ msecs_to_jiffies(250));
4099 #ifdef DSI_CATCH_MISSING_TE
4100 static void dsi_te_timeout(unsigned long arg
)
4102 DSSERR("TE not received for 250ms!\n");
4106 static void dsi_handle_framedone(struct platform_device
*dsidev
, int error
)
4108 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4110 /* SIDLEMODE back to smart-idle */
4111 dispc_enable_sidle();
4113 if (dsi
->te_enabled
) {
4114 /* enable LP_RX_TO again after the TE */
4115 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
4118 dsi
->framedone_callback(error
, dsi
->framedone_data
);
4121 dsi_perf_show(dsidev
, "DISPC");
4124 static void dsi_framedone_timeout_work_callback(struct work_struct
*work
)
4126 struct dsi_data
*dsi
= container_of(work
, struct dsi_data
,
4127 framedone_timeout_work
.work
);
4128 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4129 * 250ms which would conflict with this timeout work. What should be
4130 * done is first cancel the transfer on the HW, and then cancel the
4131 * possibly scheduled framedone work. However, cancelling the transfer
4132 * on the HW is buggy, and would probably require resetting the whole
4135 DSSERR("Framedone not received for 250ms!\n");
4137 dsi_handle_framedone(dsi
->pdev
, -ETIMEDOUT
);
4140 static void dsi_framedone_irq_callback(void *data
, u32 mask
)
4142 struct omap_dss_device
*dssdev
= (struct omap_dss_device
*) data
;
4143 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4144 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4146 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4147 * turns itself off. However, DSI still has the pixels in its buffers,
4148 * and is sending the data.
4151 __cancel_delayed_work(&dsi
->framedone_timeout_work
);
4153 dsi_handle_framedone(dsidev
, 0);
4155 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4156 dispc_fake_vsync_irq();
4160 int omap_dsi_prepare_update(struct omap_dss_device
*dssdev
,
4161 u16
*x
, u16
*y
, u16
*w
, u16
*h
,
4162 bool enlarge_update_area
)
4164 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4167 dssdev
->driver
->get_resolution(dssdev
, &dw
, &dh
);
4169 if (*x
> dw
|| *y
> dh
)
4181 if (*w
== 0 || *h
== 0)
4184 dsi_perf_mark_setup(dsidev
);
4186 dss_setup_partial_planes(dssdev
, x
, y
, w
, h
,
4187 enlarge_update_area
);
4188 dispc_mgr_set_lcd_size(dssdev
->manager
->id
, *w
, *h
);
4192 EXPORT_SYMBOL(omap_dsi_prepare_update
);
4194 int omap_dsi_update(struct omap_dss_device
*dssdev
,
4196 u16 x
, u16 y
, u16 w
, u16 h
,
4197 void (*callback
)(int, void *), void *data
)
4199 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4200 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4202 dsi
->update_channel
= channel
;
4204 /* OMAP DSS cannot send updates of odd widths.
4205 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4206 * here to make sure we catch erroneous updates. Otherwise we'll only
4207 * see rather obscure HW error happening, as DSS halts. */
4210 dsi
->framedone_callback
= callback
;
4211 dsi
->framedone_data
= data
;
4213 dsi
->update_region
.x
= x
;
4214 dsi
->update_region
.y
= y
;
4215 dsi
->update_region
.w
= w
;
4216 dsi
->update_region
.h
= h
;
4217 dsi
->update_region
.device
= dssdev
;
4219 dsi_update_screen_dispc(dssdev
, x
, y
, w
, h
);
4223 EXPORT_SYMBOL(omap_dsi_update
);
4227 static int dsi_display_init_dispc(struct omap_dss_device
*dssdev
)
4231 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_CMD_MODE
) {
4233 struct omap_video_timings timings
= {
4242 irq
= dssdev
->manager
->id
== OMAP_DSS_CHANNEL_LCD
?
4243 DISPC_IRQ_FRAMEDONE
: DISPC_IRQ_FRAMEDONE2
;
4245 r
= omap_dispc_register_isr(dsi_framedone_irq_callback
,
4246 (void *) dssdev
, irq
);
4248 DSSERR("can't get FRAMEDONE irq\n");
4252 dispc_mgr_enable_stallmode(dssdev
->manager
->id
, true);
4253 dispc_mgr_enable_fifohandcheck(dssdev
->manager
->id
, 1);
4255 dispc_mgr_set_lcd_timings(dssdev
->manager
->id
, &timings
);
4257 dispc_mgr_enable_stallmode(dssdev
->manager
->id
, false);
4258 dispc_mgr_enable_fifohandcheck(dssdev
->manager
->id
, 0);
4260 dispc_mgr_set_lcd_timings(dssdev
->manager
->id
,
4261 &dssdev
->panel
.timings
);
4264 dispc_mgr_set_lcd_display_type(dssdev
->manager
->id
,
4265 OMAP_DSS_LCD_DISPLAY_TFT
);
4266 dispc_mgr_set_tft_data_lines(dssdev
->manager
->id
,
4267 dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
));
4271 static void dsi_display_uninit_dispc(struct omap_dss_device
*dssdev
)
4273 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_CMD_MODE
) {
4276 irq
= dssdev
->manager
->id
== OMAP_DSS_CHANNEL_LCD
?
4277 DISPC_IRQ_FRAMEDONE
: DISPC_IRQ_FRAMEDONE2
;
4279 omap_dispc_unregister_isr(dsi_framedone_irq_callback
,
4280 (void *) dssdev
, irq
);
4284 static int dsi_configure_dsi_clocks(struct omap_dss_device
*dssdev
)
4286 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4287 struct dsi_clock_info cinfo
;
4290 /* we always use DSS_CLK_SYSCK as input clock */
4291 cinfo
.use_sys_clk
= true;
4292 cinfo
.regn
= dssdev
->clocks
.dsi
.regn
;
4293 cinfo
.regm
= dssdev
->clocks
.dsi
.regm
;
4294 cinfo
.regm_dispc
= dssdev
->clocks
.dsi
.regm_dispc
;
4295 cinfo
.regm_dsi
= dssdev
->clocks
.dsi
.regm_dsi
;
4296 r
= dsi_calc_clock_rates(dssdev
, &cinfo
);
4298 DSSERR("Failed to calc dsi clocks\n");
4302 r
= dsi_pll_set_clock_div(dsidev
, &cinfo
);
4304 DSSERR("Failed to set dsi clocks\n");
4311 static int dsi_configure_dispc_clocks(struct omap_dss_device
*dssdev
)
4313 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4314 struct dispc_clock_info dispc_cinfo
;
4316 unsigned long long fck
;
4318 fck
= dsi_get_pll_hsdiv_dispc_rate(dsidev
);
4320 dispc_cinfo
.lck_div
= dssdev
->clocks
.dispc
.channel
.lck_div
;
4321 dispc_cinfo
.pck_div
= dssdev
->clocks
.dispc
.channel
.pck_div
;
4323 r
= dispc_calc_clock_rates(fck
, &dispc_cinfo
);
4325 DSSERR("Failed to calc dispc clocks\n");
4329 r
= dispc_mgr_set_clock_div(dssdev
->manager
->id
, &dispc_cinfo
);
4331 DSSERR("Failed to set dispc clocks\n");
4338 static int dsi_display_init_dsi(struct omap_dss_device
*dssdev
)
4340 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4341 int dsi_module
= dsi_get_dsidev_id(dsidev
);
4344 r
= dsi_parse_lane_config(dssdev
);
4346 DSSERR("illegal lane config");
4350 r
= dsi_pll_init(dsidev
, true, true);
4354 r
= dsi_configure_dsi_clocks(dssdev
);
4358 dss_select_dispc_clk_source(dssdev
->clocks
.dispc
.dispc_fclk_src
);
4359 dss_select_dsi_clk_source(dsi_module
, dssdev
->clocks
.dsi
.dsi_fclk_src
);
4360 dss_select_lcd_clk_source(dssdev
->manager
->id
,
4361 dssdev
->clocks
.dispc
.channel
.lcd_clk_src
);
4365 r
= dsi_configure_dispc_clocks(dssdev
);
4369 r
= dsi_cio_init(dssdev
);
4373 _dsi_print_reset_status(dsidev
);
4375 dsi_proto_timings(dssdev
);
4376 dsi_set_lp_clk_divisor(dssdev
);
4379 _dsi_print_reset_status(dsidev
);
4381 r
= dsi_proto_config(dssdev
);
4385 /* enable interface */
4386 dsi_vc_enable(dsidev
, 0, 1);
4387 dsi_vc_enable(dsidev
, 1, 1);
4388 dsi_vc_enable(dsidev
, 2, 1);
4389 dsi_vc_enable(dsidev
, 3, 1);
4390 dsi_if_enable(dsidev
, 1);
4391 dsi_force_tx_stop_mode_io(dsidev
);
4395 dsi_cio_uninit(dssdev
);
4397 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK
);
4398 dss_select_dsi_clk_source(dsi_module
, OMAP_DSS_CLK_SRC_FCK
);
4399 dss_select_lcd_clk_source(dssdev
->manager
->id
, OMAP_DSS_CLK_SRC_FCK
);
4402 dsi_pll_uninit(dsidev
, true);
4407 static void dsi_display_uninit_dsi(struct omap_dss_device
*dssdev
,
4408 bool disconnect_lanes
, bool enter_ulps
)
4410 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4411 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4412 int dsi_module
= dsi_get_dsidev_id(dsidev
);
4414 if (enter_ulps
&& !dsi
->ulps_enabled
)
4415 dsi_enter_ulps(dsidev
);
4417 /* disable interface */
4418 dsi_if_enable(dsidev
, 0);
4419 dsi_vc_enable(dsidev
, 0, 0);
4420 dsi_vc_enable(dsidev
, 1, 0);
4421 dsi_vc_enable(dsidev
, 2, 0);
4422 dsi_vc_enable(dsidev
, 3, 0);
4424 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK
);
4425 dss_select_dsi_clk_source(dsi_module
, OMAP_DSS_CLK_SRC_FCK
);
4426 dss_select_lcd_clk_source(dssdev
->manager
->id
, OMAP_DSS_CLK_SRC_FCK
);
4427 dsi_cio_uninit(dssdev
);
4428 dsi_pll_uninit(dsidev
, disconnect_lanes
);
4431 int omapdss_dsi_display_enable(struct omap_dss_device
*dssdev
)
4433 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4434 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4437 DSSDBG("dsi_display_enable\n");
4439 WARN_ON(!dsi_bus_is_locked(dsidev
));
4441 mutex_lock(&dsi
->lock
);
4443 if (dssdev
->manager
== NULL
) {
4444 DSSERR("failed to enable display: no manager\n");
4449 r
= omap_dss_start_device(dssdev
);
4451 DSSERR("failed to start device\n");
4455 r
= dsi_runtime_get(dsidev
);
4459 dsi_enable_pll_clock(dsidev
, 1);
4461 _dsi_initialize_irq(dsidev
);
4463 r
= dsi_display_init_dispc(dssdev
);
4465 goto err_init_dispc
;
4467 r
= dsi_display_init_dsi(dssdev
);
4471 mutex_unlock(&dsi
->lock
);
4476 dsi_display_uninit_dispc(dssdev
);
4478 dsi_enable_pll_clock(dsidev
, 0);
4479 dsi_runtime_put(dsidev
);
4481 omap_dss_stop_device(dssdev
);
4483 mutex_unlock(&dsi
->lock
);
4484 DSSDBG("dsi_display_enable FAILED\n");
4487 EXPORT_SYMBOL(omapdss_dsi_display_enable
);
4489 void omapdss_dsi_display_disable(struct omap_dss_device
*dssdev
,
4490 bool disconnect_lanes
, bool enter_ulps
)
4492 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4493 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4495 DSSDBG("dsi_display_disable\n");
4497 WARN_ON(!dsi_bus_is_locked(dsidev
));
4499 mutex_lock(&dsi
->lock
);
4501 dsi_sync_vc(dsidev
, 0);
4502 dsi_sync_vc(dsidev
, 1);
4503 dsi_sync_vc(dsidev
, 2);
4504 dsi_sync_vc(dsidev
, 3);
4506 dsi_display_uninit_dispc(dssdev
);
4508 dsi_display_uninit_dsi(dssdev
, disconnect_lanes
, enter_ulps
);
4510 dsi_runtime_put(dsidev
);
4511 dsi_enable_pll_clock(dsidev
, 0);
4513 omap_dss_stop_device(dssdev
);
4515 mutex_unlock(&dsi
->lock
);
4517 EXPORT_SYMBOL(omapdss_dsi_display_disable
);
4519 int omapdss_dsi_enable_te(struct omap_dss_device
*dssdev
, bool enable
)
4521 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4522 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4524 dsi
->te_enabled
= enable
;
4527 EXPORT_SYMBOL(omapdss_dsi_enable_te
);
4529 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane
,
4530 u32 fifo_size
, u32 burst_size
,
4531 u32
*fifo_low
, u32
*fifo_high
)
4533 *fifo_high
= fifo_size
- burst_size
;
4534 *fifo_low
= fifo_size
- burst_size
* 2;
4537 int dsi_init_display(struct omap_dss_device
*dssdev
)
4539 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4540 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4542 DSSDBG("DSI init\n");
4544 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_CMD_MODE
) {
4545 dssdev
->caps
= OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
|
4546 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
;
4549 if (dsi
->vdds_dsi_reg
== NULL
) {
4550 struct regulator
*vdds_dsi
;
4552 vdds_dsi
= regulator_get(&dsi
->pdev
->dev
, "vdds_dsi");
4554 if (IS_ERR(vdds_dsi
)) {
4555 DSSERR("can't get VDDS_DSI regulator\n");
4556 return PTR_ERR(vdds_dsi
);
4559 dsi
->vdds_dsi_reg
= vdds_dsi
;
4565 int omap_dsi_request_vc(struct omap_dss_device
*dssdev
, int *channel
)
4567 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4568 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4571 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
4572 if (!dsi
->vc
[i
].dssdev
) {
4573 dsi
->vc
[i
].dssdev
= dssdev
;
4579 DSSERR("cannot get VC for display %s", dssdev
->name
);
4582 EXPORT_SYMBOL(omap_dsi_request_vc
);
4584 int omap_dsi_set_vc_id(struct omap_dss_device
*dssdev
, int channel
, int vc_id
)
4586 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4587 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4589 if (vc_id
< 0 || vc_id
> 3) {
4590 DSSERR("VC ID out of range\n");
4594 if (channel
< 0 || channel
> 3) {
4595 DSSERR("Virtual Channel out of range\n");
4599 if (dsi
->vc
[channel
].dssdev
!= dssdev
) {
4600 DSSERR("Virtual Channel not allocated to display %s\n",
4605 dsi
->vc
[channel
].vc_id
= vc_id
;
4609 EXPORT_SYMBOL(omap_dsi_set_vc_id
);
4611 void omap_dsi_release_vc(struct omap_dss_device
*dssdev
, int channel
)
4613 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4614 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4616 if ((channel
>= 0 && channel
<= 3) &&
4617 dsi
->vc
[channel
].dssdev
== dssdev
) {
4618 dsi
->vc
[channel
].dssdev
= NULL
;
4619 dsi
->vc
[channel
].vc_id
= 0;
4622 EXPORT_SYMBOL(omap_dsi_release_vc
);
4624 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device
*dsidev
)
4626 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 7, 1) != 1)
4627 DSSERR("%s (%s) not active\n",
4628 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
4629 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
));
4632 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device
*dsidev
)
4634 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 8, 1) != 1)
4635 DSSERR("%s (%s) not active\n",
4636 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
4637 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
));
4640 static void dsi_calc_clock_param_ranges(struct platform_device
*dsidev
)
4642 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4644 dsi
->regn_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN
);
4645 dsi
->regm_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM
);
4646 dsi
->regm_dispc_max
=
4647 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC
);
4648 dsi
->regm_dsi_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI
);
4649 dsi
->fint_min
= dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT
);
4650 dsi
->fint_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT
);
4651 dsi
->lpdiv_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV
);
4654 static int dsi_get_clocks(struct platform_device
*dsidev
)
4656 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4659 clk
= clk_get(&dsidev
->dev
, "fck");
4661 DSSERR("can't get fck\n");
4662 return PTR_ERR(clk
);
4667 clk
= clk_get(&dsidev
->dev
, "sys_clk");
4669 DSSERR("can't get sys_clk\n");
4670 clk_put(dsi
->dss_clk
);
4671 dsi
->dss_clk
= NULL
;
4672 return PTR_ERR(clk
);
4680 static void dsi_put_clocks(struct platform_device
*dsidev
)
4682 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4685 clk_put(dsi
->dss_clk
);
4687 clk_put(dsi
->sys_clk
);
4690 /* DSI1 HW IP initialisation */
4691 static int omap_dsihw_probe(struct platform_device
*dsidev
)
4693 struct omap_display_platform_data
*dss_plat_data
;
4694 struct omap_dss_board_info
*board_info
;
4696 int r
, i
, dsi_module
= dsi_get_dsidev_id(dsidev
);
4697 struct resource
*dsi_mem
;
4698 struct dsi_data
*dsi
;
4700 dsi
= kzalloc(sizeof(*dsi
), GFP_KERNEL
);
4707 dsi_pdev_map
[dsi_module
] = dsidev
;
4708 dev_set_drvdata(&dsidev
->dev
, dsi
);
4710 dss_plat_data
= dsidev
->dev
.platform_data
;
4711 board_info
= dss_plat_data
->board_data
;
4712 dsi
->enable_pads
= board_info
->dsi_enable_pads
;
4713 dsi
->disable_pads
= board_info
->dsi_disable_pads
;
4715 spin_lock_init(&dsi
->irq_lock
);
4716 spin_lock_init(&dsi
->errors_lock
);
4719 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4720 spin_lock_init(&dsi
->irq_stats_lock
);
4721 dsi
->irq_stats
.last_reset
= jiffies
;
4724 mutex_init(&dsi
->lock
);
4725 sema_init(&dsi
->bus_lock
, 1);
4727 r
= dsi_get_clocks(dsidev
);
4731 pm_runtime_enable(&dsidev
->dev
);
4733 INIT_DELAYED_WORK_DEFERRABLE(&dsi
->framedone_timeout_work
,
4734 dsi_framedone_timeout_work_callback
);
4736 #ifdef DSI_CATCH_MISSING_TE
4737 init_timer(&dsi
->te_timer
);
4738 dsi
->te_timer
.function
= dsi_te_timeout
;
4739 dsi
->te_timer
.data
= 0;
4741 dsi_mem
= platform_get_resource(dsi
->pdev
, IORESOURCE_MEM
, 0);
4743 DSSERR("can't get IORESOURCE_MEM DSI\n");
4747 dsi
->base
= ioremap(dsi_mem
->start
, resource_size(dsi_mem
));
4749 DSSERR("can't ioremap DSI\n");
4753 dsi
->irq
= platform_get_irq(dsi
->pdev
, 0);
4755 DSSERR("platform_get_irq failed\n");
4760 r
= request_irq(dsi
->irq
, omap_dsi_irq_handler
, IRQF_SHARED
,
4761 dev_name(&dsidev
->dev
), dsi
->pdev
);
4763 DSSERR("request_irq failed\n");
4767 /* DSI VCs initialization */
4768 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
4769 dsi
->vc
[i
].source
= DSI_VC_SOURCE_L4
;
4770 dsi
->vc
[i
].dssdev
= NULL
;
4771 dsi
->vc
[i
].vc_id
= 0;
4774 dsi_calc_clock_param_ranges(dsidev
);
4776 r
= dsi_runtime_get(dsidev
);
4780 rev
= dsi_read_reg(dsidev
, DSI_REVISION
);
4781 dev_dbg(&dsidev
->dev
, "OMAP DSI rev %d.%d\n",
4782 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
4784 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4785 * of data to 3 by default */
4786 if (dss_has_feature(FEAT_DSI_GNQ
))
4788 dsi
->num_lanes_supported
= 1 + REG_GET(dsidev
, DSI_GNQ
, 11, 9);
4790 dsi
->num_lanes_supported
= 3;
4792 dsi_runtime_put(dsidev
);
4797 free_irq(dsi
->irq
, dsi
->pdev
);
4801 pm_runtime_disable(&dsidev
->dev
);
4808 static int omap_dsihw_remove(struct platform_device
*dsidev
)
4810 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4812 WARN_ON(dsi
->scp_clk_refcount
> 0);
4814 pm_runtime_disable(&dsidev
->dev
);
4816 dsi_put_clocks(dsidev
);
4818 if (dsi
->vdds_dsi_reg
!= NULL
) {
4819 if (dsi
->vdds_dsi_enabled
) {
4820 regulator_disable(dsi
->vdds_dsi_reg
);
4821 dsi
->vdds_dsi_enabled
= false;
4824 regulator_put(dsi
->vdds_dsi_reg
);
4825 dsi
->vdds_dsi_reg
= NULL
;
4828 free_irq(dsi
->irq
, dsi
->pdev
);
4836 static int dsi_runtime_suspend(struct device
*dev
)
4838 dispc_runtime_put();
4844 static int dsi_runtime_resume(struct device
*dev
)
4848 r
= dss_runtime_get();
4852 r
= dispc_runtime_get();
4864 static const struct dev_pm_ops dsi_pm_ops
= {
4865 .runtime_suspend
= dsi_runtime_suspend
,
4866 .runtime_resume
= dsi_runtime_resume
,
4869 static struct platform_driver omap_dsihw_driver
= {
4870 .probe
= omap_dsihw_probe
,
4871 .remove
= omap_dsihw_remove
,
4873 .name
= "omapdss_dsi",
4874 .owner
= THIS_MODULE
,
4879 int dsi_init_platform_driver(void)
4881 return platform_driver_register(&omap_dsihw_driver
);
4884 void dsi_uninit_platform_driver(void)
4886 return platform_driver_unregister(&omap_dsihw_driver
);