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OMAPDSS: DSI: remove dsi_get_num_lanes_used
[mirror_ubuntu-artful-kernel.git] / drivers / video / omap2 / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
45
46 #include "dss.h"
47 #include "dss_features.h"
48
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
51
52 struct dsi_reg { u16 idx; };
53
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
55
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
58
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
93
94 /* DSIPHY_SCP */
95
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
101
102 /* DSI_PLL_CTRL_SCP */
103
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
109
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
138
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
153
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204
205 #define DSI_MAX_NR_ISRS 2
206 #define DSI_MAX_NR_LANES 5
207
208 enum dsi_lane_function {
209 DSI_LANE_UNUSED = 0,
210 DSI_LANE_CLK,
211 DSI_LANE_DATA1,
212 DSI_LANE_DATA2,
213 DSI_LANE_DATA3,
214 DSI_LANE_DATA4,
215 };
216
217 struct dsi_lane_config {
218 enum dsi_lane_function function;
219 u8 polarity;
220 };
221
222 struct dsi_isr_data {
223 omap_dsi_isr_t isr;
224 void *arg;
225 u32 mask;
226 };
227
228 enum fifo_size {
229 DSI_FIFO_SIZE_0 = 0,
230 DSI_FIFO_SIZE_32 = 1,
231 DSI_FIFO_SIZE_64 = 2,
232 DSI_FIFO_SIZE_96 = 3,
233 DSI_FIFO_SIZE_128 = 4,
234 };
235
236 enum dsi_vc_source {
237 DSI_VC_SOURCE_L4 = 0,
238 DSI_VC_SOURCE_VP,
239 };
240
241 struct dsi_update_region {
242 u16 x, y, w, h;
243 struct omap_dss_device *device;
244 };
245
246 struct dsi_irq_stats {
247 unsigned long last_reset;
248 unsigned irq_count;
249 unsigned dsi_irqs[32];
250 unsigned vc_irqs[4][32];
251 unsigned cio_irqs[32];
252 };
253
254 struct dsi_isr_tables {
255 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
256 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
257 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
258 };
259
260 struct dsi_data {
261 struct platform_device *pdev;
262 void __iomem *base;
263
264 int irq;
265
266 struct clk *dss_clk;
267 struct clk *sys_clk;
268
269 int (*enable_pads)(int dsi_id, unsigned lane_mask);
270 void (*disable_pads)(int dsi_id, unsigned lane_mask);
271
272 struct dsi_clock_info current_cinfo;
273
274 bool vdds_dsi_enabled;
275 struct regulator *vdds_dsi_reg;
276
277 struct {
278 enum dsi_vc_source source;
279 struct omap_dss_device *dssdev;
280 enum fifo_size fifo_size;
281 int vc_id;
282 } vc[4];
283
284 struct mutex lock;
285 struct semaphore bus_lock;
286
287 unsigned pll_locked;
288
289 spinlock_t irq_lock;
290 struct dsi_isr_tables isr_tables;
291 /* space for a copy used by the interrupt handler */
292 struct dsi_isr_tables isr_tables_copy;
293
294 int update_channel;
295 struct dsi_update_region update_region;
296
297 bool te_enabled;
298 bool ulps_enabled;
299
300 void (*framedone_callback)(int, void *);
301 void *framedone_data;
302
303 struct delayed_work framedone_timeout_work;
304
305 #ifdef DSI_CATCH_MISSING_TE
306 struct timer_list te_timer;
307 #endif
308
309 unsigned long cache_req_pck;
310 unsigned long cache_clk_freq;
311 struct dsi_clock_info cache_cinfo;
312
313 u32 errors;
314 spinlock_t errors_lock;
315 #ifdef DEBUG
316 ktime_t perf_setup_time;
317 ktime_t perf_start_time;
318 #endif
319 int debug_read;
320 int debug_write;
321
322 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
323 spinlock_t irq_stats_lock;
324 struct dsi_irq_stats irq_stats;
325 #endif
326 /* DSI PLL Parameter Ranges */
327 unsigned long regm_max, regn_max;
328 unsigned long regm_dispc_max, regm_dsi_max;
329 unsigned long fint_min, fint_max;
330 unsigned long lpdiv_max;
331
332 unsigned num_lanes_supported;
333
334 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
335 unsigned num_lanes_used;
336
337 unsigned scp_clk_refcount;
338 };
339
340 struct dsi_packet_sent_handler_data {
341 struct platform_device *dsidev;
342 struct completion *completion;
343 };
344
345 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
346
347 #ifdef DEBUG
348 static unsigned int dsi_perf;
349 module_param_named(dsi_perf, dsi_perf, bool, 0644);
350 #endif
351
352 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
353 {
354 return dev_get_drvdata(&dsidev->dev);
355 }
356
357 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
358 {
359 return dsi_pdev_map[dssdev->phy.dsi.module];
360 }
361
362 struct platform_device *dsi_get_dsidev_from_id(int module)
363 {
364 return dsi_pdev_map[module];
365 }
366
367 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
368 {
369 return dsidev->id;
370 }
371
372 static inline void dsi_write_reg(struct platform_device *dsidev,
373 const struct dsi_reg idx, u32 val)
374 {
375 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
376
377 __raw_writel(val, dsi->base + idx.idx);
378 }
379
380 static inline u32 dsi_read_reg(struct platform_device *dsidev,
381 const struct dsi_reg idx)
382 {
383 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
384
385 return __raw_readl(dsi->base + idx.idx);
386 }
387
388 void dsi_bus_lock(struct omap_dss_device *dssdev)
389 {
390 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
391 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
392
393 down(&dsi->bus_lock);
394 }
395 EXPORT_SYMBOL(dsi_bus_lock);
396
397 void dsi_bus_unlock(struct omap_dss_device *dssdev)
398 {
399 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
400 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
401
402 up(&dsi->bus_lock);
403 }
404 EXPORT_SYMBOL(dsi_bus_unlock);
405
406 static bool dsi_bus_is_locked(struct platform_device *dsidev)
407 {
408 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
409
410 return dsi->bus_lock.count == 0;
411 }
412
413 static void dsi_completion_handler(void *data, u32 mask)
414 {
415 complete((struct completion *)data);
416 }
417
418 static inline int wait_for_bit_change(struct platform_device *dsidev,
419 const struct dsi_reg idx, int bitnum, int value)
420 {
421 int t = 100000;
422
423 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
424 if (--t == 0)
425 return !value;
426 }
427
428 return value;
429 }
430
431 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
432 {
433 switch (fmt) {
434 case OMAP_DSS_DSI_FMT_RGB888:
435 case OMAP_DSS_DSI_FMT_RGB666:
436 return 24;
437 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
438 return 18;
439 case OMAP_DSS_DSI_FMT_RGB565:
440 return 16;
441 default:
442 BUG();
443 }
444 }
445
446 #ifdef DEBUG
447 static void dsi_perf_mark_setup(struct platform_device *dsidev)
448 {
449 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
450 dsi->perf_setup_time = ktime_get();
451 }
452
453 static void dsi_perf_mark_start(struct platform_device *dsidev)
454 {
455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
456 dsi->perf_start_time = ktime_get();
457 }
458
459 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
460 {
461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
462 struct omap_dss_device *dssdev = dsi->update_region.device;
463 ktime_t t, setup_time, trans_time;
464 u32 total_bytes;
465 u32 setup_us, trans_us, total_us;
466
467 if (!dsi_perf)
468 return;
469
470 t = ktime_get();
471
472 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
473 setup_us = (u32)ktime_to_us(setup_time);
474 if (setup_us == 0)
475 setup_us = 1;
476
477 trans_time = ktime_sub(t, dsi->perf_start_time);
478 trans_us = (u32)ktime_to_us(trans_time);
479 if (trans_us == 0)
480 trans_us = 1;
481
482 total_us = setup_us + trans_us;
483
484 total_bytes = dsi->update_region.w *
485 dsi->update_region.h *
486 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
487
488 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
489 "%u bytes, %u kbytes/sec\n",
490 name,
491 setup_us,
492 trans_us,
493 total_us,
494 1000*1000 / total_us,
495 total_bytes,
496 total_bytes * 1000 / total_us);
497 }
498 #else
499 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
500 {
501 }
502
503 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
504 {
505 }
506
507 static inline void dsi_perf_show(struct platform_device *dsidev,
508 const char *name)
509 {
510 }
511 #endif
512
513 static void print_irq_status(u32 status)
514 {
515 if (status == 0)
516 return;
517
518 #ifndef VERBOSE_IRQ
519 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
520 return;
521 #endif
522 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
523
524 #define PIS(x) \
525 if (status & DSI_IRQ_##x) \
526 printk(#x " ");
527 #ifdef VERBOSE_IRQ
528 PIS(VC0);
529 PIS(VC1);
530 PIS(VC2);
531 PIS(VC3);
532 #endif
533 PIS(WAKEUP);
534 PIS(RESYNC);
535 PIS(PLL_LOCK);
536 PIS(PLL_UNLOCK);
537 PIS(PLL_RECALL);
538 PIS(COMPLEXIO_ERR);
539 PIS(HS_TX_TIMEOUT);
540 PIS(LP_RX_TIMEOUT);
541 PIS(TE_TRIGGER);
542 PIS(ACK_TRIGGER);
543 PIS(SYNC_LOST);
544 PIS(LDO_POWER_GOOD);
545 PIS(TA_TIMEOUT);
546 #undef PIS
547
548 printk("\n");
549 }
550
551 static void print_irq_status_vc(int channel, u32 status)
552 {
553 if (status == 0)
554 return;
555
556 #ifndef VERBOSE_IRQ
557 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
558 return;
559 #endif
560 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
561
562 #define PIS(x) \
563 if (status & DSI_VC_IRQ_##x) \
564 printk(#x " ");
565 PIS(CS);
566 PIS(ECC_CORR);
567 #ifdef VERBOSE_IRQ
568 PIS(PACKET_SENT);
569 #endif
570 PIS(FIFO_TX_OVF);
571 PIS(FIFO_RX_OVF);
572 PIS(BTA);
573 PIS(ECC_NO_CORR);
574 PIS(FIFO_TX_UDF);
575 PIS(PP_BUSY_CHANGE);
576 #undef PIS
577 printk("\n");
578 }
579
580 static void print_irq_status_cio(u32 status)
581 {
582 if (status == 0)
583 return;
584
585 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
586
587 #define PIS(x) \
588 if (status & DSI_CIO_IRQ_##x) \
589 printk(#x " ");
590 PIS(ERRSYNCESC1);
591 PIS(ERRSYNCESC2);
592 PIS(ERRSYNCESC3);
593 PIS(ERRESC1);
594 PIS(ERRESC2);
595 PIS(ERRESC3);
596 PIS(ERRCONTROL1);
597 PIS(ERRCONTROL2);
598 PIS(ERRCONTROL3);
599 PIS(STATEULPS1);
600 PIS(STATEULPS2);
601 PIS(STATEULPS3);
602 PIS(ERRCONTENTIONLP0_1);
603 PIS(ERRCONTENTIONLP1_1);
604 PIS(ERRCONTENTIONLP0_2);
605 PIS(ERRCONTENTIONLP1_2);
606 PIS(ERRCONTENTIONLP0_3);
607 PIS(ERRCONTENTIONLP1_3);
608 PIS(ULPSACTIVENOT_ALL0);
609 PIS(ULPSACTIVENOT_ALL1);
610 #undef PIS
611
612 printk("\n");
613 }
614
615 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
616 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
617 u32 *vcstatus, u32 ciostatus)
618 {
619 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
620 int i;
621
622 spin_lock(&dsi->irq_stats_lock);
623
624 dsi->irq_stats.irq_count++;
625 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
626
627 for (i = 0; i < 4; ++i)
628 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
629
630 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
631
632 spin_unlock(&dsi->irq_stats_lock);
633 }
634 #else
635 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
636 #endif
637
638 static int debug_irq;
639
640 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
641 u32 *vcstatus, u32 ciostatus)
642 {
643 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
644 int i;
645
646 if (irqstatus & DSI_IRQ_ERROR_MASK) {
647 DSSERR("DSI error, irqstatus %x\n", irqstatus);
648 print_irq_status(irqstatus);
649 spin_lock(&dsi->errors_lock);
650 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
651 spin_unlock(&dsi->errors_lock);
652 } else if (debug_irq) {
653 print_irq_status(irqstatus);
654 }
655
656 for (i = 0; i < 4; ++i) {
657 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
658 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
659 i, vcstatus[i]);
660 print_irq_status_vc(i, vcstatus[i]);
661 } else if (debug_irq) {
662 print_irq_status_vc(i, vcstatus[i]);
663 }
664 }
665
666 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
667 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
668 print_irq_status_cio(ciostatus);
669 } else if (debug_irq) {
670 print_irq_status_cio(ciostatus);
671 }
672 }
673
674 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
675 unsigned isr_array_size, u32 irqstatus)
676 {
677 struct dsi_isr_data *isr_data;
678 int i;
679
680 for (i = 0; i < isr_array_size; i++) {
681 isr_data = &isr_array[i];
682 if (isr_data->isr && isr_data->mask & irqstatus)
683 isr_data->isr(isr_data->arg, irqstatus);
684 }
685 }
686
687 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
688 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
689 {
690 int i;
691
692 dsi_call_isrs(isr_tables->isr_table,
693 ARRAY_SIZE(isr_tables->isr_table),
694 irqstatus);
695
696 for (i = 0; i < 4; ++i) {
697 if (vcstatus[i] == 0)
698 continue;
699 dsi_call_isrs(isr_tables->isr_table_vc[i],
700 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
701 vcstatus[i]);
702 }
703
704 if (ciostatus != 0)
705 dsi_call_isrs(isr_tables->isr_table_cio,
706 ARRAY_SIZE(isr_tables->isr_table_cio),
707 ciostatus);
708 }
709
710 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
711 {
712 struct platform_device *dsidev;
713 struct dsi_data *dsi;
714 u32 irqstatus, vcstatus[4], ciostatus;
715 int i;
716
717 dsidev = (struct platform_device *) arg;
718 dsi = dsi_get_dsidrv_data(dsidev);
719
720 spin_lock(&dsi->irq_lock);
721
722 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
723
724 /* IRQ is not for us */
725 if (!irqstatus) {
726 spin_unlock(&dsi->irq_lock);
727 return IRQ_NONE;
728 }
729
730 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
731 /* flush posted write */
732 dsi_read_reg(dsidev, DSI_IRQSTATUS);
733
734 for (i = 0; i < 4; ++i) {
735 if ((irqstatus & (1 << i)) == 0) {
736 vcstatus[i] = 0;
737 continue;
738 }
739
740 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
741
742 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
743 /* flush posted write */
744 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
745 }
746
747 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
748 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
749
750 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
751 /* flush posted write */
752 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
753 } else {
754 ciostatus = 0;
755 }
756
757 #ifdef DSI_CATCH_MISSING_TE
758 if (irqstatus & DSI_IRQ_TE_TRIGGER)
759 del_timer(&dsi->te_timer);
760 #endif
761
762 /* make a copy and unlock, so that isrs can unregister
763 * themselves */
764 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
765 sizeof(dsi->isr_tables));
766
767 spin_unlock(&dsi->irq_lock);
768
769 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
770
771 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
772
773 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
774
775 return IRQ_HANDLED;
776 }
777
778 /* dsi->irq_lock has to be locked by the caller */
779 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
780 struct dsi_isr_data *isr_array,
781 unsigned isr_array_size, u32 default_mask,
782 const struct dsi_reg enable_reg,
783 const struct dsi_reg status_reg)
784 {
785 struct dsi_isr_data *isr_data;
786 u32 mask;
787 u32 old_mask;
788 int i;
789
790 mask = default_mask;
791
792 for (i = 0; i < isr_array_size; i++) {
793 isr_data = &isr_array[i];
794
795 if (isr_data->isr == NULL)
796 continue;
797
798 mask |= isr_data->mask;
799 }
800
801 old_mask = dsi_read_reg(dsidev, enable_reg);
802 /* clear the irqstatus for newly enabled irqs */
803 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
804 dsi_write_reg(dsidev, enable_reg, mask);
805
806 /* flush posted writes */
807 dsi_read_reg(dsidev, enable_reg);
808 dsi_read_reg(dsidev, status_reg);
809 }
810
811 /* dsi->irq_lock has to be locked by the caller */
812 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
813 {
814 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
815 u32 mask = DSI_IRQ_ERROR_MASK;
816 #ifdef DSI_CATCH_MISSING_TE
817 mask |= DSI_IRQ_TE_TRIGGER;
818 #endif
819 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
820 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
821 DSI_IRQENABLE, DSI_IRQSTATUS);
822 }
823
824 /* dsi->irq_lock has to be locked by the caller */
825 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
826 {
827 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
828
829 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
830 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
831 DSI_VC_IRQ_ERROR_MASK,
832 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
833 }
834
835 /* dsi->irq_lock has to be locked by the caller */
836 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
837 {
838 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
839
840 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
841 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
842 DSI_CIO_IRQ_ERROR_MASK,
843 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
844 }
845
846 static void _dsi_initialize_irq(struct platform_device *dsidev)
847 {
848 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
849 unsigned long flags;
850 int vc;
851
852 spin_lock_irqsave(&dsi->irq_lock, flags);
853
854 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
855
856 _omap_dsi_set_irqs(dsidev);
857 for (vc = 0; vc < 4; ++vc)
858 _omap_dsi_set_irqs_vc(dsidev, vc);
859 _omap_dsi_set_irqs_cio(dsidev);
860
861 spin_unlock_irqrestore(&dsi->irq_lock, flags);
862 }
863
864 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
865 struct dsi_isr_data *isr_array, unsigned isr_array_size)
866 {
867 struct dsi_isr_data *isr_data;
868 int free_idx;
869 int i;
870
871 BUG_ON(isr == NULL);
872
873 /* check for duplicate entry and find a free slot */
874 free_idx = -1;
875 for (i = 0; i < isr_array_size; i++) {
876 isr_data = &isr_array[i];
877
878 if (isr_data->isr == isr && isr_data->arg == arg &&
879 isr_data->mask == mask) {
880 return -EINVAL;
881 }
882
883 if (isr_data->isr == NULL && free_idx == -1)
884 free_idx = i;
885 }
886
887 if (free_idx == -1)
888 return -EBUSY;
889
890 isr_data = &isr_array[free_idx];
891 isr_data->isr = isr;
892 isr_data->arg = arg;
893 isr_data->mask = mask;
894
895 return 0;
896 }
897
898 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
899 struct dsi_isr_data *isr_array, unsigned isr_array_size)
900 {
901 struct dsi_isr_data *isr_data;
902 int i;
903
904 for (i = 0; i < isr_array_size; i++) {
905 isr_data = &isr_array[i];
906 if (isr_data->isr != isr || isr_data->arg != arg ||
907 isr_data->mask != mask)
908 continue;
909
910 isr_data->isr = NULL;
911 isr_data->arg = NULL;
912 isr_data->mask = 0;
913
914 return 0;
915 }
916
917 return -EINVAL;
918 }
919
920 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
921 void *arg, u32 mask)
922 {
923 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
924 unsigned long flags;
925 int r;
926
927 spin_lock_irqsave(&dsi->irq_lock, flags);
928
929 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
930 ARRAY_SIZE(dsi->isr_tables.isr_table));
931
932 if (r == 0)
933 _omap_dsi_set_irqs(dsidev);
934
935 spin_unlock_irqrestore(&dsi->irq_lock, flags);
936
937 return r;
938 }
939
940 static int dsi_unregister_isr(struct platform_device *dsidev,
941 omap_dsi_isr_t isr, void *arg, u32 mask)
942 {
943 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
944 unsigned long flags;
945 int r;
946
947 spin_lock_irqsave(&dsi->irq_lock, flags);
948
949 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
950 ARRAY_SIZE(dsi->isr_tables.isr_table));
951
952 if (r == 0)
953 _omap_dsi_set_irqs(dsidev);
954
955 spin_unlock_irqrestore(&dsi->irq_lock, flags);
956
957 return r;
958 }
959
960 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
961 omap_dsi_isr_t isr, void *arg, u32 mask)
962 {
963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
964 unsigned long flags;
965 int r;
966
967 spin_lock_irqsave(&dsi->irq_lock, flags);
968
969 r = _dsi_register_isr(isr, arg, mask,
970 dsi->isr_tables.isr_table_vc[channel],
971 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
972
973 if (r == 0)
974 _omap_dsi_set_irqs_vc(dsidev, channel);
975
976 spin_unlock_irqrestore(&dsi->irq_lock, flags);
977
978 return r;
979 }
980
981 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
982 omap_dsi_isr_t isr, void *arg, u32 mask)
983 {
984 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
985 unsigned long flags;
986 int r;
987
988 spin_lock_irqsave(&dsi->irq_lock, flags);
989
990 r = _dsi_unregister_isr(isr, arg, mask,
991 dsi->isr_tables.isr_table_vc[channel],
992 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
993
994 if (r == 0)
995 _omap_dsi_set_irqs_vc(dsidev, channel);
996
997 spin_unlock_irqrestore(&dsi->irq_lock, flags);
998
999 return r;
1000 }
1001
1002 static int dsi_register_isr_cio(struct platform_device *dsidev,
1003 omap_dsi_isr_t isr, void *arg, u32 mask)
1004 {
1005 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1006 unsigned long flags;
1007 int r;
1008
1009 spin_lock_irqsave(&dsi->irq_lock, flags);
1010
1011 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1012 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1013
1014 if (r == 0)
1015 _omap_dsi_set_irqs_cio(dsidev);
1016
1017 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1018
1019 return r;
1020 }
1021
1022 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1023 omap_dsi_isr_t isr, void *arg, u32 mask)
1024 {
1025 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1026 unsigned long flags;
1027 int r;
1028
1029 spin_lock_irqsave(&dsi->irq_lock, flags);
1030
1031 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1032 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1033
1034 if (r == 0)
1035 _omap_dsi_set_irqs_cio(dsidev);
1036
1037 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1038
1039 return r;
1040 }
1041
1042 static u32 dsi_get_errors(struct platform_device *dsidev)
1043 {
1044 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1045 unsigned long flags;
1046 u32 e;
1047 spin_lock_irqsave(&dsi->errors_lock, flags);
1048 e = dsi->errors;
1049 dsi->errors = 0;
1050 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1051 return e;
1052 }
1053
1054 int dsi_runtime_get(struct platform_device *dsidev)
1055 {
1056 int r;
1057 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1058
1059 DSSDBG("dsi_runtime_get\n");
1060
1061 r = pm_runtime_get_sync(&dsi->pdev->dev);
1062 WARN_ON(r < 0);
1063 return r < 0 ? r : 0;
1064 }
1065
1066 void dsi_runtime_put(struct platform_device *dsidev)
1067 {
1068 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1069 int r;
1070
1071 DSSDBG("dsi_runtime_put\n");
1072
1073 r = pm_runtime_put(&dsi->pdev->dev);
1074 WARN_ON(r < 0);
1075 }
1076
1077 /* source clock for DSI PLL. this could also be PCLKFREE */
1078 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1079 bool enable)
1080 {
1081 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1082
1083 if (enable)
1084 clk_enable(dsi->sys_clk);
1085 else
1086 clk_disable(dsi->sys_clk);
1087
1088 if (enable && dsi->pll_locked) {
1089 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1090 DSSERR("cannot lock PLL when enabling clocks\n");
1091 }
1092 }
1093
1094 #ifdef DEBUG
1095 static void _dsi_print_reset_status(struct platform_device *dsidev)
1096 {
1097 u32 l;
1098 int b0, b1, b2;
1099
1100 if (!dss_debug)
1101 return;
1102
1103 /* A dummy read using the SCP interface to any DSIPHY register is
1104 * required after DSIPHY reset to complete the reset of the DSI complex
1105 * I/O. */
1106 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1107
1108 printk(KERN_DEBUG "DSI resets: ");
1109
1110 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1111 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1112
1113 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1114 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1115
1116 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1117 b0 = 28;
1118 b1 = 27;
1119 b2 = 26;
1120 } else {
1121 b0 = 24;
1122 b1 = 25;
1123 b2 = 26;
1124 }
1125
1126 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1127 printk("PHY (%x%x%x, %d, %d, %d)\n",
1128 FLD_GET(l, b0, b0),
1129 FLD_GET(l, b1, b1),
1130 FLD_GET(l, b2, b2),
1131 FLD_GET(l, 29, 29),
1132 FLD_GET(l, 30, 30),
1133 FLD_GET(l, 31, 31));
1134 }
1135 #else
1136 #define _dsi_print_reset_status(x)
1137 #endif
1138
1139 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1140 {
1141 DSSDBG("dsi_if_enable(%d)\n", enable);
1142
1143 enable = enable ? 1 : 0;
1144 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1145
1146 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1147 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1148 return -EIO;
1149 }
1150
1151 return 0;
1152 }
1153
1154 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1155 {
1156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1157
1158 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1159 }
1160
1161 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1162 {
1163 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1164
1165 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1166 }
1167
1168 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1169 {
1170 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1171
1172 return dsi->current_cinfo.clkin4ddr / 16;
1173 }
1174
1175 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1176 {
1177 unsigned long r;
1178 int dsi_module = dsi_get_dsidev_id(dsidev);
1179 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1180
1181 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1182 /* DSI FCLK source is DSS_CLK_FCK */
1183 r = clk_get_rate(dsi->dss_clk);
1184 } else {
1185 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1186 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1187 }
1188
1189 return r;
1190 }
1191
1192 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1193 {
1194 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1195 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1196 unsigned long dsi_fclk;
1197 unsigned lp_clk_div;
1198 unsigned long lp_clk;
1199
1200 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1201
1202 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1203 return -EINVAL;
1204
1205 dsi_fclk = dsi_fclk_rate(dsidev);
1206
1207 lp_clk = dsi_fclk / 2 / lp_clk_div;
1208
1209 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1210 dsi->current_cinfo.lp_clk = lp_clk;
1211 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1212
1213 /* LP_CLK_DIVISOR */
1214 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1215
1216 /* LP_RX_SYNCHRO_ENABLE */
1217 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1218
1219 return 0;
1220 }
1221
1222 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1223 {
1224 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1225
1226 if (dsi->scp_clk_refcount++ == 0)
1227 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1228 }
1229
1230 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1231 {
1232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1233
1234 WARN_ON(dsi->scp_clk_refcount == 0);
1235 if (--dsi->scp_clk_refcount == 0)
1236 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1237 }
1238
1239 enum dsi_pll_power_state {
1240 DSI_PLL_POWER_OFF = 0x0,
1241 DSI_PLL_POWER_ON_HSCLK = 0x1,
1242 DSI_PLL_POWER_ON_ALL = 0x2,
1243 DSI_PLL_POWER_ON_DIV = 0x3,
1244 };
1245
1246 static int dsi_pll_power(struct platform_device *dsidev,
1247 enum dsi_pll_power_state state)
1248 {
1249 int t = 0;
1250
1251 /* DSI-PLL power command 0x3 is not working */
1252 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1253 state == DSI_PLL_POWER_ON_DIV)
1254 state = DSI_PLL_POWER_ON_ALL;
1255
1256 /* PLL_PWR_CMD */
1257 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1258
1259 /* PLL_PWR_STATUS */
1260 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1261 if (++t > 1000) {
1262 DSSERR("Failed to set DSI PLL power mode to %d\n",
1263 state);
1264 return -ENODEV;
1265 }
1266 udelay(1);
1267 }
1268
1269 return 0;
1270 }
1271
1272 /* calculate clock rates using dividers in cinfo */
1273 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1274 struct dsi_clock_info *cinfo)
1275 {
1276 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1277 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1278
1279 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1280 return -EINVAL;
1281
1282 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1283 return -EINVAL;
1284
1285 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1286 return -EINVAL;
1287
1288 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1289 return -EINVAL;
1290
1291 if (cinfo->use_sys_clk) {
1292 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1293 /* XXX it is unclear if highfreq should be used
1294 * with DSS_SYS_CLK source also */
1295 cinfo->highfreq = 0;
1296 } else {
1297 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1298
1299 if (cinfo->clkin < 32000000)
1300 cinfo->highfreq = 0;
1301 else
1302 cinfo->highfreq = 1;
1303 }
1304
1305 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1306
1307 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1308 return -EINVAL;
1309
1310 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1311
1312 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1313 return -EINVAL;
1314
1315 if (cinfo->regm_dispc > 0)
1316 cinfo->dsi_pll_hsdiv_dispc_clk =
1317 cinfo->clkin4ddr / cinfo->regm_dispc;
1318 else
1319 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1320
1321 if (cinfo->regm_dsi > 0)
1322 cinfo->dsi_pll_hsdiv_dsi_clk =
1323 cinfo->clkin4ddr / cinfo->regm_dsi;
1324 else
1325 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1326
1327 return 0;
1328 }
1329
1330 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1331 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1332 struct dispc_clock_info *dispc_cinfo)
1333 {
1334 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1335 struct dsi_clock_info cur, best;
1336 struct dispc_clock_info best_dispc;
1337 int min_fck_per_pck;
1338 int match = 0;
1339 unsigned long dss_sys_clk, max_dss_fck;
1340
1341 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1342
1343 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1344
1345 if (req_pck == dsi->cache_req_pck &&
1346 dsi->cache_cinfo.clkin == dss_sys_clk) {
1347 DSSDBG("DSI clock info found from cache\n");
1348 *dsi_cinfo = dsi->cache_cinfo;
1349 dispc_find_clk_divs(is_tft, req_pck,
1350 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1351 return 0;
1352 }
1353
1354 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1355
1356 if (min_fck_per_pck &&
1357 req_pck * min_fck_per_pck > max_dss_fck) {
1358 DSSERR("Requested pixel clock not possible with the current "
1359 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1360 "the constraint off.\n");
1361 min_fck_per_pck = 0;
1362 }
1363
1364 DSSDBG("dsi_pll_calc\n");
1365
1366 retry:
1367 memset(&best, 0, sizeof(best));
1368 memset(&best_dispc, 0, sizeof(best_dispc));
1369
1370 memset(&cur, 0, sizeof(cur));
1371 cur.clkin = dss_sys_clk;
1372 cur.use_sys_clk = 1;
1373 cur.highfreq = 0;
1374
1375 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1376 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1377 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1378 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1379 if (cur.highfreq == 0)
1380 cur.fint = cur.clkin / cur.regn;
1381 else
1382 cur.fint = cur.clkin / (2 * cur.regn);
1383
1384 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1385 continue;
1386
1387 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1388 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1389 unsigned long a, b;
1390
1391 a = 2 * cur.regm * (cur.clkin/1000);
1392 b = cur.regn * (cur.highfreq + 1);
1393 cur.clkin4ddr = a / b * 1000;
1394
1395 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1396 break;
1397
1398 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1399 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1400 for (cur.regm_dispc = 1; cur.regm_dispc <
1401 dsi->regm_dispc_max; ++cur.regm_dispc) {
1402 struct dispc_clock_info cur_dispc;
1403 cur.dsi_pll_hsdiv_dispc_clk =
1404 cur.clkin4ddr / cur.regm_dispc;
1405
1406 /* this will narrow down the search a bit,
1407 * but still give pixclocks below what was
1408 * requested */
1409 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1410 break;
1411
1412 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1413 continue;
1414
1415 if (min_fck_per_pck &&
1416 cur.dsi_pll_hsdiv_dispc_clk <
1417 req_pck * min_fck_per_pck)
1418 continue;
1419
1420 match = 1;
1421
1422 dispc_find_clk_divs(is_tft, req_pck,
1423 cur.dsi_pll_hsdiv_dispc_clk,
1424 &cur_dispc);
1425
1426 if (abs(cur_dispc.pck - req_pck) <
1427 abs(best_dispc.pck - req_pck)) {
1428 best = cur;
1429 best_dispc = cur_dispc;
1430
1431 if (cur_dispc.pck == req_pck)
1432 goto found;
1433 }
1434 }
1435 }
1436 }
1437 found:
1438 if (!match) {
1439 if (min_fck_per_pck) {
1440 DSSERR("Could not find suitable clock settings.\n"
1441 "Turning FCK/PCK constraint off and"
1442 "trying again.\n");
1443 min_fck_per_pck = 0;
1444 goto retry;
1445 }
1446
1447 DSSERR("Could not find suitable clock settings.\n");
1448
1449 return -EINVAL;
1450 }
1451
1452 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1453 best.regm_dsi = 0;
1454 best.dsi_pll_hsdiv_dsi_clk = 0;
1455
1456 if (dsi_cinfo)
1457 *dsi_cinfo = best;
1458 if (dispc_cinfo)
1459 *dispc_cinfo = best_dispc;
1460
1461 dsi->cache_req_pck = req_pck;
1462 dsi->cache_clk_freq = 0;
1463 dsi->cache_cinfo = best;
1464
1465 return 0;
1466 }
1467
1468 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1469 struct dsi_clock_info *cinfo)
1470 {
1471 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1472 int r = 0;
1473 u32 l;
1474 int f = 0;
1475 u8 regn_start, regn_end, regm_start, regm_end;
1476 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1477
1478 DSSDBGF();
1479
1480 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1481 dsi->current_cinfo.highfreq = cinfo->highfreq;
1482
1483 dsi->current_cinfo.fint = cinfo->fint;
1484 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1485 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1486 cinfo->dsi_pll_hsdiv_dispc_clk;
1487 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1488 cinfo->dsi_pll_hsdiv_dsi_clk;
1489
1490 dsi->current_cinfo.regn = cinfo->regn;
1491 dsi->current_cinfo.regm = cinfo->regm;
1492 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1493 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1494
1495 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1496
1497 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1498 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1499 cinfo->clkin,
1500 cinfo->highfreq);
1501
1502 /* DSIPHY == CLKIN4DDR */
1503 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1504 cinfo->regm,
1505 cinfo->regn,
1506 cinfo->clkin,
1507 cinfo->highfreq + 1,
1508 cinfo->clkin4ddr);
1509
1510 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1511 cinfo->clkin4ddr / 1000 / 1000 / 2);
1512
1513 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1514
1515 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1516 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1517 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1518 cinfo->dsi_pll_hsdiv_dispc_clk);
1519 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1520 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1521 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1522 cinfo->dsi_pll_hsdiv_dsi_clk);
1523
1524 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1525 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1526 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1527 &regm_dispc_end);
1528 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1529 &regm_dsi_end);
1530
1531 /* DSI_PLL_AUTOMODE = manual */
1532 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1533
1534 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1535 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1536 /* DSI_PLL_REGN */
1537 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1538 /* DSI_PLL_REGM */
1539 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1540 /* DSI_CLOCK_DIV */
1541 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1542 regm_dispc_start, regm_dispc_end);
1543 /* DSIPROTO_CLOCK_DIV */
1544 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1545 regm_dsi_start, regm_dsi_end);
1546 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1547
1548 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1549
1550 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1551 f = cinfo->fint < 1000000 ? 0x3 :
1552 cinfo->fint < 1250000 ? 0x4 :
1553 cinfo->fint < 1500000 ? 0x5 :
1554 cinfo->fint < 1750000 ? 0x6 :
1555 0x7;
1556 }
1557
1558 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1559
1560 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1561 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1562 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1563 11, 11); /* DSI_PLL_CLKSEL */
1564 l = FLD_MOD(l, cinfo->highfreq,
1565 12, 12); /* DSI_PLL_HIGHFREQ */
1566 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1567 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1568 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1569 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1570
1571 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1572
1573 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1574 DSSERR("dsi pll go bit not going down.\n");
1575 r = -EIO;
1576 goto err;
1577 }
1578
1579 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1580 DSSERR("cannot lock PLL\n");
1581 r = -EIO;
1582 goto err;
1583 }
1584
1585 dsi->pll_locked = 1;
1586
1587 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1588 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1589 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1590 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1591 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1592 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1593 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1594 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1595 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1596 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1597 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1598 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1599 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1600 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1601 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1602 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1603
1604 DSSDBG("PLL config done\n");
1605 err:
1606 return r;
1607 }
1608
1609 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1610 bool enable_hsdiv)
1611 {
1612 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1613 int r = 0;
1614 enum dsi_pll_power_state pwstate;
1615
1616 DSSDBG("PLL init\n");
1617
1618 if (dsi->vdds_dsi_reg == NULL) {
1619 struct regulator *vdds_dsi;
1620
1621 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1622
1623 if (IS_ERR(vdds_dsi)) {
1624 DSSERR("can't get VDDS_DSI regulator\n");
1625 return PTR_ERR(vdds_dsi);
1626 }
1627
1628 dsi->vdds_dsi_reg = vdds_dsi;
1629 }
1630
1631 dsi_enable_pll_clock(dsidev, 1);
1632 /*
1633 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1634 */
1635 dsi_enable_scp_clk(dsidev);
1636
1637 if (!dsi->vdds_dsi_enabled) {
1638 r = regulator_enable(dsi->vdds_dsi_reg);
1639 if (r)
1640 goto err0;
1641 dsi->vdds_dsi_enabled = true;
1642 }
1643
1644 /* XXX PLL does not come out of reset without this... */
1645 dispc_pck_free_enable(1);
1646
1647 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1648 DSSERR("PLL not coming out of reset.\n");
1649 r = -ENODEV;
1650 dispc_pck_free_enable(0);
1651 goto err1;
1652 }
1653
1654 /* XXX ... but if left on, we get problems when planes do not
1655 * fill the whole display. No idea about this */
1656 dispc_pck_free_enable(0);
1657
1658 if (enable_hsclk && enable_hsdiv)
1659 pwstate = DSI_PLL_POWER_ON_ALL;
1660 else if (enable_hsclk)
1661 pwstate = DSI_PLL_POWER_ON_HSCLK;
1662 else if (enable_hsdiv)
1663 pwstate = DSI_PLL_POWER_ON_DIV;
1664 else
1665 pwstate = DSI_PLL_POWER_OFF;
1666
1667 r = dsi_pll_power(dsidev, pwstate);
1668
1669 if (r)
1670 goto err1;
1671
1672 DSSDBG("PLL init done\n");
1673
1674 return 0;
1675 err1:
1676 if (dsi->vdds_dsi_enabled) {
1677 regulator_disable(dsi->vdds_dsi_reg);
1678 dsi->vdds_dsi_enabled = false;
1679 }
1680 err0:
1681 dsi_disable_scp_clk(dsidev);
1682 dsi_enable_pll_clock(dsidev, 0);
1683 return r;
1684 }
1685
1686 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1687 {
1688 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1689
1690 dsi->pll_locked = 0;
1691 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1692 if (disconnect_lanes) {
1693 WARN_ON(!dsi->vdds_dsi_enabled);
1694 regulator_disable(dsi->vdds_dsi_reg);
1695 dsi->vdds_dsi_enabled = false;
1696 }
1697
1698 dsi_disable_scp_clk(dsidev);
1699 dsi_enable_pll_clock(dsidev, 0);
1700
1701 DSSDBG("PLL uninit done\n");
1702 }
1703
1704 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1705 struct seq_file *s)
1706 {
1707 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1708 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1709 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1710 int dsi_module = dsi_get_dsidev_id(dsidev);
1711
1712 dispc_clk_src = dss_get_dispc_clk_source();
1713 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1714
1715 if (dsi_runtime_get(dsidev))
1716 return;
1717
1718 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1719
1720 seq_printf(s, "dsi pll source = %s\n",
1721 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1722
1723 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1724
1725 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1726 cinfo->clkin4ddr, cinfo->regm);
1727
1728 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1729 dss_get_generic_clk_source_name(dispc_clk_src),
1730 dss_feat_get_clk_source_name(dispc_clk_src),
1731 cinfo->dsi_pll_hsdiv_dispc_clk,
1732 cinfo->regm_dispc,
1733 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1734 "off" : "on");
1735
1736 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1737 dss_get_generic_clk_source_name(dsi_clk_src),
1738 dss_feat_get_clk_source_name(dsi_clk_src),
1739 cinfo->dsi_pll_hsdiv_dsi_clk,
1740 cinfo->regm_dsi,
1741 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1742 "off" : "on");
1743
1744 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1745
1746 seq_printf(s, "dsi fclk source = %s (%s)\n",
1747 dss_get_generic_clk_source_name(dsi_clk_src),
1748 dss_feat_get_clk_source_name(dsi_clk_src));
1749
1750 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1751
1752 seq_printf(s, "DDR_CLK\t\t%lu\n",
1753 cinfo->clkin4ddr / 4);
1754
1755 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1756
1757 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1758
1759 dsi_runtime_put(dsidev);
1760 }
1761
1762 void dsi_dump_clocks(struct seq_file *s)
1763 {
1764 struct platform_device *dsidev;
1765 int i;
1766
1767 for (i = 0; i < MAX_NUM_DSI; i++) {
1768 dsidev = dsi_get_dsidev_from_id(i);
1769 if (dsidev)
1770 dsi_dump_dsidev_clocks(dsidev, s);
1771 }
1772 }
1773
1774 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1775 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1776 struct seq_file *s)
1777 {
1778 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1779 unsigned long flags;
1780 struct dsi_irq_stats stats;
1781 int dsi_module = dsi_get_dsidev_id(dsidev);
1782
1783 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1784
1785 stats = dsi->irq_stats;
1786 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1787 dsi->irq_stats.last_reset = jiffies;
1788
1789 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1790
1791 seq_printf(s, "period %u ms\n",
1792 jiffies_to_msecs(jiffies - stats.last_reset));
1793
1794 seq_printf(s, "irqs %d\n", stats.irq_count);
1795 #define PIS(x) \
1796 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1797
1798 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1799 PIS(VC0);
1800 PIS(VC1);
1801 PIS(VC2);
1802 PIS(VC3);
1803 PIS(WAKEUP);
1804 PIS(RESYNC);
1805 PIS(PLL_LOCK);
1806 PIS(PLL_UNLOCK);
1807 PIS(PLL_RECALL);
1808 PIS(COMPLEXIO_ERR);
1809 PIS(HS_TX_TIMEOUT);
1810 PIS(LP_RX_TIMEOUT);
1811 PIS(TE_TRIGGER);
1812 PIS(ACK_TRIGGER);
1813 PIS(SYNC_LOST);
1814 PIS(LDO_POWER_GOOD);
1815 PIS(TA_TIMEOUT);
1816 #undef PIS
1817
1818 #define PIS(x) \
1819 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1820 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1821 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1822 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1823 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1824
1825 seq_printf(s, "-- VC interrupts --\n");
1826 PIS(CS);
1827 PIS(ECC_CORR);
1828 PIS(PACKET_SENT);
1829 PIS(FIFO_TX_OVF);
1830 PIS(FIFO_RX_OVF);
1831 PIS(BTA);
1832 PIS(ECC_NO_CORR);
1833 PIS(FIFO_TX_UDF);
1834 PIS(PP_BUSY_CHANGE);
1835 #undef PIS
1836
1837 #define PIS(x) \
1838 seq_printf(s, "%-20s %10d\n", #x, \
1839 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1840
1841 seq_printf(s, "-- CIO interrupts --\n");
1842 PIS(ERRSYNCESC1);
1843 PIS(ERRSYNCESC2);
1844 PIS(ERRSYNCESC3);
1845 PIS(ERRESC1);
1846 PIS(ERRESC2);
1847 PIS(ERRESC3);
1848 PIS(ERRCONTROL1);
1849 PIS(ERRCONTROL2);
1850 PIS(ERRCONTROL3);
1851 PIS(STATEULPS1);
1852 PIS(STATEULPS2);
1853 PIS(STATEULPS3);
1854 PIS(ERRCONTENTIONLP0_1);
1855 PIS(ERRCONTENTIONLP1_1);
1856 PIS(ERRCONTENTIONLP0_2);
1857 PIS(ERRCONTENTIONLP1_2);
1858 PIS(ERRCONTENTIONLP0_3);
1859 PIS(ERRCONTENTIONLP1_3);
1860 PIS(ULPSACTIVENOT_ALL0);
1861 PIS(ULPSACTIVENOT_ALL1);
1862 #undef PIS
1863 }
1864
1865 static void dsi1_dump_irqs(struct seq_file *s)
1866 {
1867 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1868
1869 dsi_dump_dsidev_irqs(dsidev, s);
1870 }
1871
1872 static void dsi2_dump_irqs(struct seq_file *s)
1873 {
1874 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1875
1876 dsi_dump_dsidev_irqs(dsidev, s);
1877 }
1878
1879 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1880 const struct file_operations *debug_fops)
1881 {
1882 struct platform_device *dsidev;
1883
1884 dsidev = dsi_get_dsidev_from_id(0);
1885 if (dsidev)
1886 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1887 &dsi1_dump_irqs, debug_fops);
1888
1889 dsidev = dsi_get_dsidev_from_id(1);
1890 if (dsidev)
1891 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1892 &dsi2_dump_irqs, debug_fops);
1893 }
1894 #endif
1895
1896 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1897 struct seq_file *s)
1898 {
1899 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1900
1901 if (dsi_runtime_get(dsidev))
1902 return;
1903 dsi_enable_scp_clk(dsidev);
1904
1905 DUMPREG(DSI_REVISION);
1906 DUMPREG(DSI_SYSCONFIG);
1907 DUMPREG(DSI_SYSSTATUS);
1908 DUMPREG(DSI_IRQSTATUS);
1909 DUMPREG(DSI_IRQENABLE);
1910 DUMPREG(DSI_CTRL);
1911 DUMPREG(DSI_COMPLEXIO_CFG1);
1912 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1913 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1914 DUMPREG(DSI_CLK_CTRL);
1915 DUMPREG(DSI_TIMING1);
1916 DUMPREG(DSI_TIMING2);
1917 DUMPREG(DSI_VM_TIMING1);
1918 DUMPREG(DSI_VM_TIMING2);
1919 DUMPREG(DSI_VM_TIMING3);
1920 DUMPREG(DSI_CLK_TIMING);
1921 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1922 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1923 DUMPREG(DSI_COMPLEXIO_CFG2);
1924 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1925 DUMPREG(DSI_VM_TIMING4);
1926 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1927 DUMPREG(DSI_VM_TIMING5);
1928 DUMPREG(DSI_VM_TIMING6);
1929 DUMPREG(DSI_VM_TIMING7);
1930 DUMPREG(DSI_STOPCLK_TIMING);
1931
1932 DUMPREG(DSI_VC_CTRL(0));
1933 DUMPREG(DSI_VC_TE(0));
1934 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1935 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1936 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1937 DUMPREG(DSI_VC_IRQSTATUS(0));
1938 DUMPREG(DSI_VC_IRQENABLE(0));
1939
1940 DUMPREG(DSI_VC_CTRL(1));
1941 DUMPREG(DSI_VC_TE(1));
1942 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1943 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1944 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1945 DUMPREG(DSI_VC_IRQSTATUS(1));
1946 DUMPREG(DSI_VC_IRQENABLE(1));
1947
1948 DUMPREG(DSI_VC_CTRL(2));
1949 DUMPREG(DSI_VC_TE(2));
1950 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1951 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1952 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1953 DUMPREG(DSI_VC_IRQSTATUS(2));
1954 DUMPREG(DSI_VC_IRQENABLE(2));
1955
1956 DUMPREG(DSI_VC_CTRL(3));
1957 DUMPREG(DSI_VC_TE(3));
1958 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1959 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1960 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1961 DUMPREG(DSI_VC_IRQSTATUS(3));
1962 DUMPREG(DSI_VC_IRQENABLE(3));
1963
1964 DUMPREG(DSI_DSIPHY_CFG0);
1965 DUMPREG(DSI_DSIPHY_CFG1);
1966 DUMPREG(DSI_DSIPHY_CFG2);
1967 DUMPREG(DSI_DSIPHY_CFG5);
1968
1969 DUMPREG(DSI_PLL_CONTROL);
1970 DUMPREG(DSI_PLL_STATUS);
1971 DUMPREG(DSI_PLL_GO);
1972 DUMPREG(DSI_PLL_CONFIGURATION1);
1973 DUMPREG(DSI_PLL_CONFIGURATION2);
1974
1975 dsi_disable_scp_clk(dsidev);
1976 dsi_runtime_put(dsidev);
1977 #undef DUMPREG
1978 }
1979
1980 static void dsi1_dump_regs(struct seq_file *s)
1981 {
1982 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1983
1984 dsi_dump_dsidev_regs(dsidev, s);
1985 }
1986
1987 static void dsi2_dump_regs(struct seq_file *s)
1988 {
1989 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1990
1991 dsi_dump_dsidev_regs(dsidev, s);
1992 }
1993
1994 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1995 const struct file_operations *debug_fops)
1996 {
1997 struct platform_device *dsidev;
1998
1999 dsidev = dsi_get_dsidev_from_id(0);
2000 if (dsidev)
2001 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
2002 &dsi1_dump_regs, debug_fops);
2003
2004 dsidev = dsi_get_dsidev_from_id(1);
2005 if (dsidev)
2006 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2007 &dsi2_dump_regs, debug_fops);
2008 }
2009 enum dsi_cio_power_state {
2010 DSI_COMPLEXIO_POWER_OFF = 0x0,
2011 DSI_COMPLEXIO_POWER_ON = 0x1,
2012 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2013 };
2014
2015 static int dsi_cio_power(struct platform_device *dsidev,
2016 enum dsi_cio_power_state state)
2017 {
2018 int t = 0;
2019
2020 /* PWR_CMD */
2021 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2022
2023 /* PWR_STATUS */
2024 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2025 26, 25) != state) {
2026 if (++t > 1000) {
2027 DSSERR("failed to set complexio power state to "
2028 "%d\n", state);
2029 return -ENODEV;
2030 }
2031 udelay(1);
2032 }
2033
2034 return 0;
2035 }
2036
2037 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2038 {
2039 int val;
2040
2041 /* line buffer on OMAP3 is 1024 x 24bits */
2042 /* XXX: for some reason using full buffer size causes
2043 * considerable TX slowdown with update sizes that fill the
2044 * whole buffer */
2045 if (!dss_has_feature(FEAT_DSI_GNQ))
2046 return 1023 * 3;
2047
2048 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2049
2050 switch (val) {
2051 case 1:
2052 return 512 * 3; /* 512x24 bits */
2053 case 2:
2054 return 682 * 3; /* 682x24 bits */
2055 case 3:
2056 return 853 * 3; /* 853x24 bits */
2057 case 4:
2058 return 1024 * 3; /* 1024x24 bits */
2059 case 5:
2060 return 1194 * 3; /* 1194x24 bits */
2061 case 6:
2062 return 1365 * 3; /* 1365x24 bits */
2063 default:
2064 BUG();
2065 }
2066 }
2067
2068 static int dsi_parse_lane_config(struct omap_dss_device *dssdev)
2069 {
2070 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2071 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2072 u8 lanes[DSI_MAX_NR_LANES];
2073 u8 polarities[DSI_MAX_NR_LANES];
2074 int num_lanes, i;
2075
2076 static const enum dsi_lane_function functions[] = {
2077 DSI_LANE_CLK,
2078 DSI_LANE_DATA1,
2079 DSI_LANE_DATA2,
2080 DSI_LANE_DATA3,
2081 DSI_LANE_DATA4,
2082 };
2083
2084 lanes[0] = dssdev->phy.dsi.clk_lane;
2085 lanes[1] = dssdev->phy.dsi.data1_lane;
2086 lanes[2] = dssdev->phy.dsi.data2_lane;
2087 lanes[3] = dssdev->phy.dsi.data3_lane;
2088 lanes[4] = dssdev->phy.dsi.data4_lane;
2089 polarities[0] = dssdev->phy.dsi.clk_pol;
2090 polarities[1] = dssdev->phy.dsi.data1_pol;
2091 polarities[2] = dssdev->phy.dsi.data2_pol;
2092 polarities[3] = dssdev->phy.dsi.data3_pol;
2093 polarities[4] = dssdev->phy.dsi.data4_pol;
2094
2095 num_lanes = 0;
2096
2097 for (i = 0; i < dsi->num_lanes_supported; ++i)
2098 dsi->lanes[i].function = DSI_LANE_UNUSED;
2099
2100 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2101 int num;
2102
2103 if (lanes[i] == DSI_LANE_UNUSED)
2104 break;
2105
2106 num = lanes[i] - 1;
2107
2108 if (num >= dsi->num_lanes_supported)
2109 return -EINVAL;
2110
2111 if (dsi->lanes[num].function != DSI_LANE_UNUSED)
2112 return -EINVAL;
2113
2114 dsi->lanes[num].function = functions[i];
2115 dsi->lanes[num].polarity = polarities[i];
2116 num_lanes++;
2117 }
2118
2119 if (num_lanes < 2 || num_lanes > dsi->num_lanes_supported)
2120 return -EINVAL;
2121
2122 dsi->num_lanes_used = num_lanes;
2123
2124 return 0;
2125 }
2126
2127 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2128 {
2129 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2130 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2131 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2132 static const enum dsi_lane_function functions[] = {
2133 DSI_LANE_CLK,
2134 DSI_LANE_DATA1,
2135 DSI_LANE_DATA2,
2136 DSI_LANE_DATA3,
2137 DSI_LANE_DATA4,
2138 };
2139 u32 r;
2140 int i;
2141
2142 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2143
2144 for (i = 0; i < dsi->num_lanes_used; ++i) {
2145 unsigned offset = offsets[i];
2146 unsigned polarity, lane_number;
2147 unsigned t;
2148
2149 for (t = 0; t < dsi->num_lanes_supported; ++t)
2150 if (dsi->lanes[t].function == functions[i])
2151 break;
2152
2153 if (t == dsi->num_lanes_supported)
2154 return -EINVAL;
2155
2156 lane_number = t;
2157 polarity = dsi->lanes[t].polarity;
2158
2159 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2160 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2161 }
2162
2163 /* clear the unused lanes */
2164 for (; i < dsi->num_lanes_supported; ++i) {
2165 unsigned offset = offsets[i];
2166
2167 r = FLD_MOD(r, 0, offset + 2, offset);
2168 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2169 }
2170
2171 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2172
2173 return 0;
2174 }
2175
2176 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2177 {
2178 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2179
2180 /* convert time in ns to ddr ticks, rounding up */
2181 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2182 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2183 }
2184
2185 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2186 {
2187 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2188
2189 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2190 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2191 }
2192
2193 static void dsi_cio_timings(struct platform_device *dsidev)
2194 {
2195 u32 r;
2196 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2197 u32 tlpx_half, tclk_trail, tclk_zero;
2198 u32 tclk_prepare;
2199
2200 /* calculate timings */
2201
2202 /* 1 * DDR_CLK = 2 * UI */
2203
2204 /* min 40ns + 4*UI max 85ns + 6*UI */
2205 ths_prepare = ns2ddr(dsidev, 70) + 2;
2206
2207 /* min 145ns + 10*UI */
2208 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2209
2210 /* min max(8*UI, 60ns+4*UI) */
2211 ths_trail = ns2ddr(dsidev, 60) + 5;
2212
2213 /* min 100ns */
2214 ths_exit = ns2ddr(dsidev, 145);
2215
2216 /* tlpx min 50n */
2217 tlpx_half = ns2ddr(dsidev, 25);
2218
2219 /* min 60ns */
2220 tclk_trail = ns2ddr(dsidev, 60) + 2;
2221
2222 /* min 38ns, max 95ns */
2223 tclk_prepare = ns2ddr(dsidev, 65);
2224
2225 /* min tclk-prepare + tclk-zero = 300ns */
2226 tclk_zero = ns2ddr(dsidev, 260);
2227
2228 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2229 ths_prepare, ddr2ns(dsidev, ths_prepare),
2230 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2231 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2232 ths_trail, ddr2ns(dsidev, ths_trail),
2233 ths_exit, ddr2ns(dsidev, ths_exit));
2234
2235 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2236 "tclk_zero %u (%uns)\n",
2237 tlpx_half, ddr2ns(dsidev, tlpx_half),
2238 tclk_trail, ddr2ns(dsidev, tclk_trail),
2239 tclk_zero, ddr2ns(dsidev, tclk_zero));
2240 DSSDBG("tclk_prepare %u (%uns)\n",
2241 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2242
2243 /* program timings */
2244
2245 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2246 r = FLD_MOD(r, ths_prepare, 31, 24);
2247 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2248 r = FLD_MOD(r, ths_trail, 15, 8);
2249 r = FLD_MOD(r, ths_exit, 7, 0);
2250 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2251
2252 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2253 r = FLD_MOD(r, tlpx_half, 22, 16);
2254 r = FLD_MOD(r, tclk_trail, 15, 8);
2255 r = FLD_MOD(r, tclk_zero, 7, 0);
2256 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2257
2258 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2259 r = FLD_MOD(r, tclk_prepare, 7, 0);
2260 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2261 }
2262
2263 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2264 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2265 unsigned mask_p, unsigned mask_n)
2266 {
2267 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2268 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2269 int i;
2270 u32 l;
2271 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2272
2273 l = 0;
2274
2275 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2276 unsigned p = dsi->lanes[i].polarity;
2277
2278 if (mask_p & (1 << i))
2279 l |= 1 << (i * 2 + (p ? 0 : 1));
2280
2281 if (mask_n & (1 << i))
2282 l |= 1 << (i * 2 + (p ? 1 : 0));
2283 }
2284
2285 /*
2286 * Bits in REGLPTXSCPDAT4TO0DXDY:
2287 * 17: DY0 18: DX0
2288 * 19: DY1 20: DX1
2289 * 21: DY2 22: DX2
2290 * 23: DY3 24: DX3
2291 * 25: DY4 26: DX4
2292 */
2293
2294 /* Set the lane override configuration */
2295
2296 /* REGLPTXSCPDAT4TO0DXDY */
2297 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2298
2299 /* Enable lane override */
2300
2301 /* ENLPTXSCPDAT */
2302 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2303 }
2304
2305 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2306 {
2307 /* Disable lane override */
2308 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2309 /* Reset the lane override configuration */
2310 /* REGLPTXSCPDAT4TO0DXDY */
2311 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2312 }
2313
2314 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2315 {
2316 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2317 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2318 int t, i;
2319 bool in_use[DSI_MAX_NR_LANES];
2320 static const u8 offsets_old[] = { 28, 27, 26 };
2321 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2322 const u8 *offsets;
2323
2324 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2325 offsets = offsets_old;
2326 else
2327 offsets = offsets_new;
2328
2329 for (i = 0; i < dsi->num_lanes_supported; ++i)
2330 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2331
2332 t = 100000;
2333 while (true) {
2334 u32 l;
2335 int ok;
2336
2337 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2338
2339 ok = 0;
2340 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2341 if (!in_use[i] || (l & (1 << offsets[i])))
2342 ok++;
2343 }
2344
2345 if (ok == dsi->num_lanes_supported)
2346 break;
2347
2348 if (--t == 0) {
2349 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2350 if (!in_use[i] || (l & (1 << offsets[i])))
2351 continue;
2352
2353 DSSERR("CIO TXCLKESC%d domain not coming " \
2354 "out of reset\n", i);
2355 }
2356 return -EIO;
2357 }
2358 }
2359
2360 return 0;
2361 }
2362
2363 /* return bitmask of enabled lanes, lane0 being the lsb */
2364 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2365 {
2366 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2367 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2368 unsigned mask = 0;
2369 int i;
2370
2371 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2372 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2373 mask |= 1 << i;
2374 }
2375
2376 return mask;
2377 }
2378
2379 static int dsi_cio_init(struct omap_dss_device *dssdev)
2380 {
2381 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2382 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2383 int r;
2384 u32 l;
2385
2386 DSSDBGF();
2387
2388 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2389 if (r)
2390 return r;
2391
2392 dsi_enable_scp_clk(dsidev);
2393
2394 /* A dummy read using the SCP interface to any DSIPHY register is
2395 * required after DSIPHY reset to complete the reset of the DSI complex
2396 * I/O. */
2397 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2398
2399 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2400 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2401 r = -EIO;
2402 goto err_scp_clk_dom;
2403 }
2404
2405 r = dsi_set_lane_config(dssdev);
2406 if (r)
2407 goto err_scp_clk_dom;
2408
2409 /* set TX STOP MODE timer to maximum for this operation */
2410 l = dsi_read_reg(dsidev, DSI_TIMING1);
2411 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2412 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2413 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2414 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2415 dsi_write_reg(dsidev, DSI_TIMING1, l);
2416
2417 if (dsi->ulps_enabled) {
2418 unsigned mask_p;
2419 int i;
2420
2421 DSSDBG("manual ulps exit\n");
2422
2423 /* ULPS is exited by Mark-1 state for 1ms, followed by
2424 * stop state. DSS HW cannot do this via the normal
2425 * ULPS exit sequence, as after reset the DSS HW thinks
2426 * that we are not in ULPS mode, and refuses to send the
2427 * sequence. So we need to send the ULPS exit sequence
2428 * manually by setting positive lines high and negative lines
2429 * low for 1ms.
2430 */
2431
2432 mask_p = 0;
2433
2434 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2435 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2436 continue;
2437 mask_p |= 1 << i;
2438 }
2439
2440 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2441 }
2442
2443 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2444 if (r)
2445 goto err_cio_pwr;
2446
2447 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2448 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2449 r = -ENODEV;
2450 goto err_cio_pwr_dom;
2451 }
2452
2453 dsi_if_enable(dsidev, true);
2454 dsi_if_enable(dsidev, false);
2455 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2456
2457 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2458 if (r)
2459 goto err_tx_clk_esc_rst;
2460
2461 if (dsi->ulps_enabled) {
2462 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2463 ktime_t wait = ns_to_ktime(1000 * 1000);
2464 set_current_state(TASK_UNINTERRUPTIBLE);
2465 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2466
2467 /* Disable the override. The lanes should be set to Mark-11
2468 * state by the HW */
2469 dsi_cio_disable_lane_override(dsidev);
2470 }
2471
2472 /* FORCE_TX_STOP_MODE_IO */
2473 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2474
2475 dsi_cio_timings(dsidev);
2476
2477 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2478 /* DDR_CLK_ALWAYS_ON */
2479 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2480 dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2481 }
2482
2483 dsi->ulps_enabled = false;
2484
2485 DSSDBG("CIO init done\n");
2486
2487 return 0;
2488
2489 err_tx_clk_esc_rst:
2490 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2491 err_cio_pwr_dom:
2492 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2493 err_cio_pwr:
2494 if (dsi->ulps_enabled)
2495 dsi_cio_disable_lane_override(dsidev);
2496 err_scp_clk_dom:
2497 dsi_disable_scp_clk(dsidev);
2498 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2499 return r;
2500 }
2501
2502 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2503 {
2504 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2505 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2506
2507 /* DDR_CLK_ALWAYS_ON */
2508 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2509
2510 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2511 dsi_disable_scp_clk(dsidev);
2512 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2513 }
2514
2515 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2516 enum fifo_size size1, enum fifo_size size2,
2517 enum fifo_size size3, enum fifo_size size4)
2518 {
2519 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2520 u32 r = 0;
2521 int add = 0;
2522 int i;
2523
2524 dsi->vc[0].fifo_size = size1;
2525 dsi->vc[1].fifo_size = size2;
2526 dsi->vc[2].fifo_size = size3;
2527 dsi->vc[3].fifo_size = size4;
2528
2529 for (i = 0; i < 4; i++) {
2530 u8 v;
2531 int size = dsi->vc[i].fifo_size;
2532
2533 if (add + size > 4) {
2534 DSSERR("Illegal FIFO configuration\n");
2535 BUG();
2536 }
2537
2538 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2539 r |= v << (8 * i);
2540 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2541 add += size;
2542 }
2543
2544 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2545 }
2546
2547 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2548 enum fifo_size size1, enum fifo_size size2,
2549 enum fifo_size size3, enum fifo_size size4)
2550 {
2551 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2552 u32 r = 0;
2553 int add = 0;
2554 int i;
2555
2556 dsi->vc[0].fifo_size = size1;
2557 dsi->vc[1].fifo_size = size2;
2558 dsi->vc[2].fifo_size = size3;
2559 dsi->vc[3].fifo_size = size4;
2560
2561 for (i = 0; i < 4; i++) {
2562 u8 v;
2563 int size = dsi->vc[i].fifo_size;
2564
2565 if (add + size > 4) {
2566 DSSERR("Illegal FIFO configuration\n");
2567 BUG();
2568 }
2569
2570 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2571 r |= v << (8 * i);
2572 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2573 add += size;
2574 }
2575
2576 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2577 }
2578
2579 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2580 {
2581 u32 r;
2582
2583 r = dsi_read_reg(dsidev, DSI_TIMING1);
2584 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2585 dsi_write_reg(dsidev, DSI_TIMING1, r);
2586
2587 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2588 DSSERR("TX_STOP bit not going down\n");
2589 return -EIO;
2590 }
2591
2592 return 0;
2593 }
2594
2595 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2596 {
2597 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2598 }
2599
2600 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2601 {
2602 struct dsi_packet_sent_handler_data *vp_data =
2603 (struct dsi_packet_sent_handler_data *) data;
2604 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2605 const int channel = dsi->update_channel;
2606 u8 bit = dsi->te_enabled ? 30 : 31;
2607
2608 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2609 complete(vp_data->completion);
2610 }
2611
2612 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2613 {
2614 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2615 DECLARE_COMPLETION_ONSTACK(completion);
2616 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2617 int r = 0;
2618 u8 bit;
2619
2620 bit = dsi->te_enabled ? 30 : 31;
2621
2622 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2623 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2624 if (r)
2625 goto err0;
2626
2627 /* Wait for completion only if TE_EN/TE_START is still set */
2628 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2629 if (wait_for_completion_timeout(&completion,
2630 msecs_to_jiffies(10)) == 0) {
2631 DSSERR("Failed to complete previous frame transfer\n");
2632 r = -EIO;
2633 goto err1;
2634 }
2635 }
2636
2637 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2638 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2639
2640 return 0;
2641 err1:
2642 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2643 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2644 err0:
2645 return r;
2646 }
2647
2648 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2649 {
2650 struct dsi_packet_sent_handler_data *l4_data =
2651 (struct dsi_packet_sent_handler_data *) data;
2652 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2653 const int channel = dsi->update_channel;
2654
2655 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2656 complete(l4_data->completion);
2657 }
2658
2659 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2660 {
2661 DECLARE_COMPLETION_ONSTACK(completion);
2662 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2663 int r = 0;
2664
2665 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2666 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2667 if (r)
2668 goto err0;
2669
2670 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2671 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2672 if (wait_for_completion_timeout(&completion,
2673 msecs_to_jiffies(10)) == 0) {
2674 DSSERR("Failed to complete previous l4 transfer\n");
2675 r = -EIO;
2676 goto err1;
2677 }
2678 }
2679
2680 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2681 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2682
2683 return 0;
2684 err1:
2685 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2686 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2687 err0:
2688 return r;
2689 }
2690
2691 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2692 {
2693 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2694
2695 WARN_ON(!dsi_bus_is_locked(dsidev));
2696
2697 WARN_ON(in_interrupt());
2698
2699 if (!dsi_vc_is_enabled(dsidev, channel))
2700 return 0;
2701
2702 switch (dsi->vc[channel].source) {
2703 case DSI_VC_SOURCE_VP:
2704 return dsi_sync_vc_vp(dsidev, channel);
2705 case DSI_VC_SOURCE_L4:
2706 return dsi_sync_vc_l4(dsidev, channel);
2707 default:
2708 BUG();
2709 }
2710 }
2711
2712 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2713 bool enable)
2714 {
2715 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2716 channel, enable);
2717
2718 enable = enable ? 1 : 0;
2719
2720 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2721
2722 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2723 0, enable) != enable) {
2724 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2725 return -EIO;
2726 }
2727
2728 return 0;
2729 }
2730
2731 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2732 {
2733 u32 r;
2734
2735 DSSDBGF("%d", channel);
2736
2737 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2738
2739 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2740 DSSERR("VC(%d) busy when trying to configure it!\n",
2741 channel);
2742
2743 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2744 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2745 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2746 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2747 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2748 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2749 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2750 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2751 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2752
2753 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2754 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2755
2756 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2757 }
2758
2759 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2760 enum dsi_vc_source source)
2761 {
2762 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2763
2764 if (dsi->vc[channel].source == source)
2765 return 0;
2766
2767 DSSDBGF("%d", channel);
2768
2769 dsi_sync_vc(dsidev, channel);
2770
2771 dsi_vc_enable(dsidev, channel, 0);
2772
2773 /* VC_BUSY */
2774 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2775 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2776 return -EIO;
2777 }
2778
2779 /* SOURCE, 0 = L4, 1 = video port */
2780 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2781
2782 /* DCS_CMD_ENABLE */
2783 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2784 bool enable = source == DSI_VC_SOURCE_VP;
2785 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2786 }
2787
2788 dsi_vc_enable(dsidev, channel, 1);
2789
2790 dsi->vc[channel].source = source;
2791
2792 return 0;
2793 }
2794
2795 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2796 bool enable)
2797 {
2798 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2799
2800 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2801
2802 WARN_ON(!dsi_bus_is_locked(dsidev));
2803
2804 dsi_vc_enable(dsidev, channel, 0);
2805 dsi_if_enable(dsidev, 0);
2806
2807 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2808
2809 dsi_vc_enable(dsidev, channel, 1);
2810 dsi_if_enable(dsidev, 1);
2811
2812 dsi_force_tx_stop_mode_io(dsidev);
2813
2814 /* start the DDR clock by sending a NULL packet */
2815 if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2816 dsi_vc_send_null(dssdev, channel);
2817 }
2818 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2819
2820 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2821 {
2822 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2823 u32 val;
2824 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2825 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2826 (val >> 0) & 0xff,
2827 (val >> 8) & 0xff,
2828 (val >> 16) & 0xff,
2829 (val >> 24) & 0xff);
2830 }
2831 }
2832
2833 static void dsi_show_rx_ack_with_err(u16 err)
2834 {
2835 DSSERR("\tACK with ERROR (%#x):\n", err);
2836 if (err & (1 << 0))
2837 DSSERR("\t\tSoT Error\n");
2838 if (err & (1 << 1))
2839 DSSERR("\t\tSoT Sync Error\n");
2840 if (err & (1 << 2))
2841 DSSERR("\t\tEoT Sync Error\n");
2842 if (err & (1 << 3))
2843 DSSERR("\t\tEscape Mode Entry Command Error\n");
2844 if (err & (1 << 4))
2845 DSSERR("\t\tLP Transmit Sync Error\n");
2846 if (err & (1 << 5))
2847 DSSERR("\t\tHS Receive Timeout Error\n");
2848 if (err & (1 << 6))
2849 DSSERR("\t\tFalse Control Error\n");
2850 if (err & (1 << 7))
2851 DSSERR("\t\t(reserved7)\n");
2852 if (err & (1 << 8))
2853 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2854 if (err & (1 << 9))
2855 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2856 if (err & (1 << 10))
2857 DSSERR("\t\tChecksum Error\n");
2858 if (err & (1 << 11))
2859 DSSERR("\t\tData type not recognized\n");
2860 if (err & (1 << 12))
2861 DSSERR("\t\tInvalid VC ID\n");
2862 if (err & (1 << 13))
2863 DSSERR("\t\tInvalid Transmission Length\n");
2864 if (err & (1 << 14))
2865 DSSERR("\t\t(reserved14)\n");
2866 if (err & (1 << 15))
2867 DSSERR("\t\tDSI Protocol Violation\n");
2868 }
2869
2870 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2871 int channel)
2872 {
2873 /* RX_FIFO_NOT_EMPTY */
2874 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2875 u32 val;
2876 u8 dt;
2877 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2878 DSSERR("\trawval %#08x\n", val);
2879 dt = FLD_GET(val, 5, 0);
2880 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2881 u16 err = FLD_GET(val, 23, 8);
2882 dsi_show_rx_ack_with_err(err);
2883 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2884 DSSERR("\tDCS short response, 1 byte: %#x\n",
2885 FLD_GET(val, 23, 8));
2886 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2887 DSSERR("\tDCS short response, 2 byte: %#x\n",
2888 FLD_GET(val, 23, 8));
2889 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2890 DSSERR("\tDCS long response, len %d\n",
2891 FLD_GET(val, 23, 8));
2892 dsi_vc_flush_long_data(dsidev, channel);
2893 } else {
2894 DSSERR("\tunknown datatype 0x%02x\n", dt);
2895 }
2896 }
2897 return 0;
2898 }
2899
2900 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2901 {
2902 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2903
2904 if (dsi->debug_write || dsi->debug_read)
2905 DSSDBG("dsi_vc_send_bta %d\n", channel);
2906
2907 WARN_ON(!dsi_bus_is_locked(dsidev));
2908
2909 /* RX_FIFO_NOT_EMPTY */
2910 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2911 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2912 dsi_vc_flush_receive_data(dsidev, channel);
2913 }
2914
2915 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2916
2917 /* flush posted write */
2918 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2919
2920 return 0;
2921 }
2922
2923 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2924 {
2925 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2926 DECLARE_COMPLETION_ONSTACK(completion);
2927 int r = 0;
2928 u32 err;
2929
2930 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2931 &completion, DSI_VC_IRQ_BTA);
2932 if (r)
2933 goto err0;
2934
2935 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2936 DSI_IRQ_ERROR_MASK);
2937 if (r)
2938 goto err1;
2939
2940 r = dsi_vc_send_bta(dsidev, channel);
2941 if (r)
2942 goto err2;
2943
2944 if (wait_for_completion_timeout(&completion,
2945 msecs_to_jiffies(500)) == 0) {
2946 DSSERR("Failed to receive BTA\n");
2947 r = -EIO;
2948 goto err2;
2949 }
2950
2951 err = dsi_get_errors(dsidev);
2952 if (err) {
2953 DSSERR("Error while sending BTA: %x\n", err);
2954 r = -EIO;
2955 goto err2;
2956 }
2957 err2:
2958 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2959 DSI_IRQ_ERROR_MASK);
2960 err1:
2961 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2962 &completion, DSI_VC_IRQ_BTA);
2963 err0:
2964 return r;
2965 }
2966 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2967
2968 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2969 int channel, u8 data_type, u16 len, u8 ecc)
2970 {
2971 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2972 u32 val;
2973 u8 data_id;
2974
2975 WARN_ON(!dsi_bus_is_locked(dsidev));
2976
2977 data_id = data_type | dsi->vc[channel].vc_id << 6;
2978
2979 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2980 FLD_VAL(ecc, 31, 24);
2981
2982 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2983 }
2984
2985 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2986 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2987 {
2988 u32 val;
2989
2990 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2991
2992 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2993 b1, b2, b3, b4, val); */
2994
2995 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2996 }
2997
2998 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2999 u8 data_type, u8 *data, u16 len, u8 ecc)
3000 {
3001 /*u32 val; */
3002 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3003 int i;
3004 u8 *p;
3005 int r = 0;
3006 u8 b1, b2, b3, b4;
3007
3008 if (dsi->debug_write)
3009 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3010
3011 /* len + header */
3012 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3013 DSSERR("unable to send long packet: packet too long.\n");
3014 return -EINVAL;
3015 }
3016
3017 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3018
3019 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3020
3021 p = data;
3022 for (i = 0; i < len >> 2; i++) {
3023 if (dsi->debug_write)
3024 DSSDBG("\tsending full packet %d\n", i);
3025
3026 b1 = *p++;
3027 b2 = *p++;
3028 b3 = *p++;
3029 b4 = *p++;
3030
3031 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3032 }
3033
3034 i = len % 4;
3035 if (i) {
3036 b1 = 0; b2 = 0; b3 = 0;
3037
3038 if (dsi->debug_write)
3039 DSSDBG("\tsending remainder bytes %d\n", i);
3040
3041 switch (i) {
3042 case 3:
3043 b1 = *p++;
3044 b2 = *p++;
3045 b3 = *p++;
3046 break;
3047 case 2:
3048 b1 = *p++;
3049 b2 = *p++;
3050 break;
3051 case 1:
3052 b1 = *p++;
3053 break;
3054 }
3055
3056 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3057 }
3058
3059 return r;
3060 }
3061
3062 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3063 u8 data_type, u16 data, u8 ecc)
3064 {
3065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3066 u32 r;
3067 u8 data_id;
3068
3069 WARN_ON(!dsi_bus_is_locked(dsidev));
3070
3071 if (dsi->debug_write)
3072 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3073 channel,
3074 data_type, data & 0xff, (data >> 8) & 0xff);
3075
3076 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3077
3078 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3079 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3080 return -EINVAL;
3081 }
3082
3083 data_id = data_type | dsi->vc[channel].vc_id << 6;
3084
3085 r = (data_id << 0) | (data << 8) | (ecc << 24);
3086
3087 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3088
3089 return 0;
3090 }
3091
3092 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3093 {
3094 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3095
3096 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3097 0, 0);
3098 }
3099 EXPORT_SYMBOL(dsi_vc_send_null);
3100
3101 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3102 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3103 {
3104 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3105 int r;
3106
3107 if (len == 0) {
3108 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3109 r = dsi_vc_send_short(dsidev, channel,
3110 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3111 } else if (len == 1) {
3112 r = dsi_vc_send_short(dsidev, channel,
3113 type == DSS_DSI_CONTENT_GENERIC ?
3114 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3115 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3116 } else if (len == 2) {
3117 r = dsi_vc_send_short(dsidev, channel,
3118 type == DSS_DSI_CONTENT_GENERIC ?
3119 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3120 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3121 data[0] | (data[1] << 8), 0);
3122 } else {
3123 r = dsi_vc_send_long(dsidev, channel,
3124 type == DSS_DSI_CONTENT_GENERIC ?
3125 MIPI_DSI_GENERIC_LONG_WRITE :
3126 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3127 }
3128
3129 return r;
3130 }
3131
3132 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3133 u8 *data, int len)
3134 {
3135 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3136 DSS_DSI_CONTENT_DCS);
3137 }
3138 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3139
3140 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3141 u8 *data, int len)
3142 {
3143 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3144 DSS_DSI_CONTENT_GENERIC);
3145 }
3146 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3147
3148 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3149 u8 *data, int len, enum dss_dsi_content_type type)
3150 {
3151 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3152 int r;
3153
3154 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3155 if (r)
3156 goto err;
3157
3158 r = dsi_vc_send_bta_sync(dssdev, channel);
3159 if (r)
3160 goto err;
3161
3162 /* RX_FIFO_NOT_EMPTY */
3163 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3164 DSSERR("rx fifo not empty after write, dumping data:\n");
3165 dsi_vc_flush_receive_data(dsidev, channel);
3166 r = -EIO;
3167 goto err;
3168 }
3169
3170 return 0;
3171 err:
3172 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3173 channel, data[0], len);
3174 return r;
3175 }
3176
3177 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3178 int len)
3179 {
3180 return dsi_vc_write_common(dssdev, channel, data, len,
3181 DSS_DSI_CONTENT_DCS);
3182 }
3183 EXPORT_SYMBOL(dsi_vc_dcs_write);
3184
3185 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3186 int len)
3187 {
3188 return dsi_vc_write_common(dssdev, channel, data, len,
3189 DSS_DSI_CONTENT_GENERIC);
3190 }
3191 EXPORT_SYMBOL(dsi_vc_generic_write);
3192
3193 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3194 {
3195 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3196 }
3197 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3198
3199 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3200 {
3201 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3202 }
3203 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3204
3205 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3206 u8 param)
3207 {
3208 u8 buf[2];
3209 buf[0] = dcs_cmd;
3210 buf[1] = param;
3211 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3212 }
3213 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3214
3215 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3216 u8 param)
3217 {
3218 return dsi_vc_generic_write(dssdev, channel, &param, 1);
3219 }
3220 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3221
3222 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3223 u8 param1, u8 param2)
3224 {
3225 u8 buf[2];
3226 buf[0] = param1;
3227 buf[1] = param2;
3228 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3229 }
3230 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3231
3232 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3233 int channel, u8 dcs_cmd)
3234 {
3235 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3236 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3237 int r;
3238
3239 if (dsi->debug_read)
3240 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3241 channel, dcs_cmd);
3242
3243 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3244 if (r) {
3245 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3246 " failed\n", channel, dcs_cmd);
3247 return r;
3248 }
3249
3250 return 0;
3251 }
3252
3253 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3254 int channel, u8 *reqdata, int reqlen)
3255 {
3256 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3257 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3258 u16 data;
3259 u8 data_type;
3260 int r;
3261
3262 if (dsi->debug_read)
3263 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3264 channel, reqlen);
3265
3266 if (reqlen == 0) {
3267 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3268 data = 0;
3269 } else if (reqlen == 1) {
3270 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3271 data = reqdata[0];
3272 } else if (reqlen == 2) {
3273 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3274 data = reqdata[0] | (reqdata[1] << 8);
3275 } else {
3276 BUG();
3277 }
3278
3279 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3280 if (r) {
3281 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3282 " failed\n", channel, reqlen);
3283 return r;
3284 }
3285
3286 return 0;
3287 }
3288
3289 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3290 u8 *buf, int buflen, enum dss_dsi_content_type type)
3291 {
3292 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3293 u32 val;
3294 u8 dt;
3295 int r;
3296
3297 /* RX_FIFO_NOT_EMPTY */
3298 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3299 DSSERR("RX fifo empty when trying to read.\n");
3300 r = -EIO;
3301 goto err;
3302 }
3303
3304 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3305 if (dsi->debug_read)
3306 DSSDBG("\theader: %08x\n", val);
3307 dt = FLD_GET(val, 5, 0);
3308 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3309 u16 err = FLD_GET(val, 23, 8);
3310 dsi_show_rx_ack_with_err(err);
3311 r = -EIO;
3312 goto err;
3313
3314 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3315 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3316 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3317 u8 data = FLD_GET(val, 15, 8);
3318 if (dsi->debug_read)
3319 DSSDBG("\t%s short response, 1 byte: %02x\n",
3320 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3321 "DCS", data);
3322
3323 if (buflen < 1) {
3324 r = -EIO;
3325 goto err;
3326 }
3327
3328 buf[0] = data;
3329
3330 return 1;
3331 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3332 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3333 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3334 u16 data = FLD_GET(val, 23, 8);
3335 if (dsi->debug_read)
3336 DSSDBG("\t%s short response, 2 byte: %04x\n",
3337 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3338 "DCS", data);
3339
3340 if (buflen < 2) {
3341 r = -EIO;
3342 goto err;
3343 }
3344
3345 buf[0] = data & 0xff;
3346 buf[1] = (data >> 8) & 0xff;
3347
3348 return 2;
3349 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3350 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3351 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3352 int w;
3353 int len = FLD_GET(val, 23, 8);
3354 if (dsi->debug_read)
3355 DSSDBG("\t%s long response, len %d\n",
3356 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3357 "DCS", len);
3358
3359 if (len > buflen) {
3360 r = -EIO;
3361 goto err;
3362 }
3363
3364 /* two byte checksum ends the packet, not included in len */
3365 for (w = 0; w < len + 2;) {
3366 int b;
3367 val = dsi_read_reg(dsidev,
3368 DSI_VC_SHORT_PACKET_HEADER(channel));
3369 if (dsi->debug_read)
3370 DSSDBG("\t\t%02x %02x %02x %02x\n",
3371 (val >> 0) & 0xff,
3372 (val >> 8) & 0xff,
3373 (val >> 16) & 0xff,
3374 (val >> 24) & 0xff);
3375
3376 for (b = 0; b < 4; ++b) {
3377 if (w < len)
3378 buf[w] = (val >> (b * 8)) & 0xff;
3379 /* we discard the 2 byte checksum */
3380 ++w;
3381 }
3382 }
3383
3384 return len;
3385 } else {
3386 DSSERR("\tunknown datatype 0x%02x\n", dt);
3387 r = -EIO;
3388 goto err;
3389 }
3390
3391 BUG();
3392 err:
3393 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3394 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3395
3396 return r;
3397 }
3398
3399 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3400 u8 *buf, int buflen)
3401 {
3402 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3403 int r;
3404
3405 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3406 if (r)
3407 goto err;
3408
3409 r = dsi_vc_send_bta_sync(dssdev, channel);
3410 if (r)
3411 goto err;
3412
3413 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3414 DSS_DSI_CONTENT_DCS);
3415 if (r < 0)
3416 goto err;
3417
3418 if (r != buflen) {
3419 r = -EIO;
3420 goto err;
3421 }
3422
3423 return 0;
3424 err:
3425 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3426 return r;
3427 }
3428 EXPORT_SYMBOL(dsi_vc_dcs_read);
3429
3430 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3431 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3432 {
3433 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3434 int r;
3435
3436 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3437 if (r)
3438 return r;
3439
3440 r = dsi_vc_send_bta_sync(dssdev, channel);
3441 if (r)
3442 return r;
3443
3444 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3445 DSS_DSI_CONTENT_GENERIC);
3446 if (r < 0)
3447 return r;
3448
3449 if (r != buflen) {
3450 r = -EIO;
3451 return r;
3452 }
3453
3454 return 0;
3455 }
3456
3457 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3458 int buflen)
3459 {
3460 int r;
3461
3462 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3463 if (r) {
3464 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3465 return r;
3466 }
3467
3468 return 0;
3469 }
3470 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3471
3472 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3473 u8 *buf, int buflen)
3474 {
3475 int r;
3476
3477 r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3478 if (r) {
3479 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3480 return r;
3481 }
3482
3483 return 0;
3484 }
3485 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3486
3487 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3488 u8 param1, u8 param2, u8 *buf, int buflen)
3489 {
3490 int r;
3491 u8 reqdata[2];
3492
3493 reqdata[0] = param1;
3494 reqdata[1] = param2;
3495
3496 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3497 if (r) {
3498 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3499 return r;
3500 }
3501
3502 return 0;
3503 }
3504 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3505
3506 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3507 u16 len)
3508 {
3509 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3510
3511 return dsi_vc_send_short(dsidev, channel,
3512 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3513 }
3514 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3515
3516 static int dsi_enter_ulps(struct platform_device *dsidev)
3517 {
3518 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3519 DECLARE_COMPLETION_ONSTACK(completion);
3520 int r;
3521
3522 DSSDBGF();
3523
3524 WARN_ON(!dsi_bus_is_locked(dsidev));
3525
3526 WARN_ON(dsi->ulps_enabled);
3527
3528 if (dsi->ulps_enabled)
3529 return 0;
3530
3531 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3532 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3533 return -EIO;
3534 }
3535
3536 dsi_sync_vc(dsidev, 0);
3537 dsi_sync_vc(dsidev, 1);
3538 dsi_sync_vc(dsidev, 2);
3539 dsi_sync_vc(dsidev, 3);
3540
3541 dsi_force_tx_stop_mode_io(dsidev);
3542
3543 dsi_vc_enable(dsidev, 0, false);
3544 dsi_vc_enable(dsidev, 1, false);
3545 dsi_vc_enable(dsidev, 2, false);
3546 dsi_vc_enable(dsidev, 3, false);
3547
3548 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3549 DSSERR("HS busy when enabling ULPS\n");
3550 return -EIO;
3551 }
3552
3553 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3554 DSSERR("LP busy when enabling ULPS\n");
3555 return -EIO;
3556 }
3557
3558 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3559 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3560 if (r)
3561 return r;
3562
3563 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3564 /* LANEx_ULPS_SIG2 */
3565 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3566 7, 5);
3567
3568 /* flush posted write and wait for SCP interface to finish the write */
3569 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3570
3571 if (wait_for_completion_timeout(&completion,
3572 msecs_to_jiffies(1000)) == 0) {
3573 DSSERR("ULPS enable timeout\n");
3574 r = -EIO;
3575 goto err;
3576 }
3577
3578 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3579 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3580
3581 /* Reset LANEx_ULPS_SIG2 */
3582 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3583 7, 5);
3584
3585 /* flush posted write and wait for SCP interface to finish the write */
3586 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3587
3588 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3589
3590 dsi_if_enable(dsidev, false);
3591
3592 dsi->ulps_enabled = true;
3593
3594 return 0;
3595
3596 err:
3597 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3598 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3599 return r;
3600 }
3601
3602 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3603 unsigned ticks, bool x4, bool x16)
3604 {
3605 unsigned long fck;
3606 unsigned long total_ticks;
3607 u32 r;
3608
3609 BUG_ON(ticks > 0x1fff);
3610
3611 /* ticks in DSI_FCK */
3612 fck = dsi_fclk_rate(dsidev);
3613
3614 r = dsi_read_reg(dsidev, DSI_TIMING2);
3615 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3616 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3617 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3618 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3619 dsi_write_reg(dsidev, DSI_TIMING2, r);
3620
3621 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3622
3623 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3624 total_ticks,
3625 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3626 (total_ticks * 1000) / (fck / 1000 / 1000));
3627 }
3628
3629 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3630 bool x8, bool x16)
3631 {
3632 unsigned long fck;
3633 unsigned long total_ticks;
3634 u32 r;
3635
3636 BUG_ON(ticks > 0x1fff);
3637
3638 /* ticks in DSI_FCK */
3639 fck = dsi_fclk_rate(dsidev);
3640
3641 r = dsi_read_reg(dsidev, DSI_TIMING1);
3642 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3643 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3644 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3645 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3646 dsi_write_reg(dsidev, DSI_TIMING1, r);
3647
3648 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3649
3650 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3651 total_ticks,
3652 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3653 (total_ticks * 1000) / (fck / 1000 / 1000));
3654 }
3655
3656 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3657 unsigned ticks, bool x4, bool x16)
3658 {
3659 unsigned long fck;
3660 unsigned long total_ticks;
3661 u32 r;
3662
3663 BUG_ON(ticks > 0x1fff);
3664
3665 /* ticks in DSI_FCK */
3666 fck = dsi_fclk_rate(dsidev);
3667
3668 r = dsi_read_reg(dsidev, DSI_TIMING1);
3669 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3670 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3671 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3672 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3673 dsi_write_reg(dsidev, DSI_TIMING1, r);
3674
3675 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3676
3677 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3678 total_ticks,
3679 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3680 (total_ticks * 1000) / (fck / 1000 / 1000));
3681 }
3682
3683 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3684 unsigned ticks, bool x4, bool x16)
3685 {
3686 unsigned long fck;
3687 unsigned long total_ticks;
3688 u32 r;
3689
3690 BUG_ON(ticks > 0x1fff);
3691
3692 /* ticks in TxByteClkHS */
3693 fck = dsi_get_txbyteclkhs(dsidev);
3694
3695 r = dsi_read_reg(dsidev, DSI_TIMING2);
3696 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3697 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3698 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3699 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3700 dsi_write_reg(dsidev, DSI_TIMING2, r);
3701
3702 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3703
3704 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3705 total_ticks,
3706 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3707 (total_ticks * 1000) / (fck / 1000 / 1000));
3708 }
3709
3710 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3711 {
3712 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3713 int num_line_buffers;
3714
3715 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3716 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3717 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3718 struct omap_video_timings *timings = &dssdev->panel.timings;
3719 /*
3720 * Don't use line buffers if width is greater than the video
3721 * port's line buffer size
3722 */
3723 if (line_buf_size <= timings->x_res * bpp / 8)
3724 num_line_buffers = 0;
3725 else
3726 num_line_buffers = 2;
3727 } else {
3728 /* Use maximum number of line buffers in command mode */
3729 num_line_buffers = 2;
3730 }
3731
3732 /* LINE_BUFFER */
3733 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3734 }
3735
3736 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3737 {
3738 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3739 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3740 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3741 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3742 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3743 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3744 u32 r;
3745
3746 r = dsi_read_reg(dsidev, DSI_CTRL);
3747 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
3748 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
3749 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
3750 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3751 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3752 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3753 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3754 dsi_write_reg(dsidev, DSI_CTRL, r);
3755 }
3756
3757 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3758 {
3759 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3760 int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3761 int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3762 int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3763 int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3764 u32 r;
3765
3766 /*
3767 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3768 * 1 = Long blanking packets are sent in corresponding blanking periods
3769 */
3770 r = dsi_read_reg(dsidev, DSI_CTRL);
3771 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3772 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3773 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3774 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3775 dsi_write_reg(dsidev, DSI_CTRL, r);
3776 }
3777
3778 static int dsi_proto_config(struct omap_dss_device *dssdev)
3779 {
3780 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3781 u32 r;
3782 int buswidth = 0;
3783
3784 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3785 DSI_FIFO_SIZE_32,
3786 DSI_FIFO_SIZE_32,
3787 DSI_FIFO_SIZE_32);
3788
3789 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3790 DSI_FIFO_SIZE_32,
3791 DSI_FIFO_SIZE_32,
3792 DSI_FIFO_SIZE_32);
3793
3794 /* XXX what values for the timeouts? */
3795 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3796 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3797 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3798 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3799
3800 switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3801 case 16:
3802 buswidth = 0;
3803 break;
3804 case 18:
3805 buswidth = 1;
3806 break;
3807 case 24:
3808 buswidth = 2;
3809 break;
3810 default:
3811 BUG();
3812 }
3813
3814 r = dsi_read_reg(dsidev, DSI_CTRL);
3815 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3816 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3817 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3818 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3819 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3820 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3821 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3822 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3823 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3824 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3825 /* DCS_CMD_CODE, 1=start, 0=continue */
3826 r = FLD_MOD(r, 0, 25, 25);
3827 }
3828
3829 dsi_write_reg(dsidev, DSI_CTRL, r);
3830
3831 dsi_config_vp_num_line_buffers(dssdev);
3832
3833 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3834 dsi_config_vp_sync_events(dssdev);
3835 dsi_config_blanking_modes(dssdev);
3836 }
3837
3838 dsi_vc_initial_config(dsidev, 0);
3839 dsi_vc_initial_config(dsidev, 1);
3840 dsi_vc_initial_config(dsidev, 2);
3841 dsi_vc_initial_config(dsidev, 3);
3842
3843 return 0;
3844 }
3845
3846 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3847 {
3848 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3849 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3850 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3851 unsigned tclk_pre, tclk_post;
3852 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3853 unsigned ths_trail, ths_exit;
3854 unsigned ddr_clk_pre, ddr_clk_post;
3855 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3856 unsigned ths_eot;
3857 int ndl = dsi->num_lanes_used - 1;
3858 u32 r;
3859
3860 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3861 ths_prepare = FLD_GET(r, 31, 24);
3862 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3863 ths_zero = ths_prepare_ths_zero - ths_prepare;
3864 ths_trail = FLD_GET(r, 15, 8);
3865 ths_exit = FLD_GET(r, 7, 0);
3866
3867 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3868 tlpx = FLD_GET(r, 22, 16) * 2;
3869 tclk_trail = FLD_GET(r, 15, 8);
3870 tclk_zero = FLD_GET(r, 7, 0);
3871
3872 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3873 tclk_prepare = FLD_GET(r, 7, 0);
3874
3875 /* min 8*UI */
3876 tclk_pre = 20;
3877 /* min 60ns + 52*UI */
3878 tclk_post = ns2ddr(dsidev, 60) + 26;
3879
3880 ths_eot = DIV_ROUND_UP(4, ndl);
3881
3882 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3883 4);
3884 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3885
3886 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3887 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3888
3889 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3890 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3891 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3892 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3893
3894 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3895 ddr_clk_pre,
3896 ddr_clk_post);
3897
3898 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3899 DIV_ROUND_UP(ths_prepare, 4) +
3900 DIV_ROUND_UP(ths_zero + 3, 4);
3901
3902 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3903
3904 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3905 FLD_VAL(exit_hs_mode_lat, 15, 0);
3906 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3907
3908 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3909 enter_hs_mode_lat, exit_hs_mode_lat);
3910
3911 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3912 /* TODO: Implement a video mode check_timings function */
3913 int hsa = dssdev->panel.dsi_vm_data.hsa;
3914 int hfp = dssdev->panel.dsi_vm_data.hfp;
3915 int hbp = dssdev->panel.dsi_vm_data.hbp;
3916 int vsa = dssdev->panel.dsi_vm_data.vsa;
3917 int vfp = dssdev->panel.dsi_vm_data.vfp;
3918 int vbp = dssdev->panel.dsi_vm_data.vbp;
3919 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3920 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3921 struct omap_video_timings *timings = &dssdev->panel.timings;
3922 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3923 int tl, t_he, width_bytes;
3924
3925 t_he = hsync_end ?
3926 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3927
3928 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3929
3930 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3931 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3932 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3933
3934 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3935 hfp, hsync_end ? hsa : 0, tl);
3936 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3937 vsa, timings->y_res);
3938
3939 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3940 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3941 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3942 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3943 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3944
3945 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3946 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3947 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3948 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3949 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3950 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3951
3952 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3953 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3954 r = FLD_MOD(r, tl, 31, 16); /* TL */
3955 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3956 }
3957 }
3958
3959 int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
3960 {
3961 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3962 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3963 u8 data_type;
3964 u16 word_count;
3965
3966 switch (dssdev->panel.dsi_pix_fmt) {
3967 case OMAP_DSS_DSI_FMT_RGB888:
3968 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3969 break;
3970 case OMAP_DSS_DSI_FMT_RGB666:
3971 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3972 break;
3973 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3974 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3975 break;
3976 case OMAP_DSS_DSI_FMT_RGB565:
3977 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3978 break;
3979 default:
3980 BUG();
3981 };
3982
3983 dsi_if_enable(dsidev, false);
3984 dsi_vc_enable(dsidev, channel, false);
3985
3986 /* MODE, 1 = video mode */
3987 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3988
3989 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3990
3991 dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);
3992
3993 dsi_vc_enable(dsidev, channel, true);
3994 dsi_if_enable(dsidev, true);
3995
3996 dssdev->manager->enable(dssdev->manager);
3997
3998 return 0;
3999 }
4000 EXPORT_SYMBOL(dsi_video_mode_enable);
4001
4002 void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
4003 {
4004 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4005
4006 dsi_if_enable(dsidev, false);
4007 dsi_vc_enable(dsidev, channel, false);
4008
4009 /* MODE, 0 = command mode */
4010 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4011
4012 dsi_vc_enable(dsidev, channel, true);
4013 dsi_if_enable(dsidev, true);
4014
4015 dssdev->manager->disable(dssdev->manager);
4016 }
4017 EXPORT_SYMBOL(dsi_video_mode_disable);
4018
4019 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4020 u16 x, u16 y, u16 w, u16 h)
4021 {
4022 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4023 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4024 unsigned bytespp;
4025 unsigned bytespl;
4026 unsigned bytespf;
4027 unsigned total_len;
4028 unsigned packet_payload;
4029 unsigned packet_len;
4030 u32 l;
4031 int r;
4032 const unsigned channel = dsi->update_channel;
4033 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4034
4035 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4036 x, y, w, h);
4037
4038 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4039
4040 bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4041 bytespl = w * bytespp;
4042 bytespf = bytespl * h;
4043
4044 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4045 * number of lines in a packet. See errata about VP_CLK_RATIO */
4046
4047 if (bytespf < line_buf_size)
4048 packet_payload = bytespf;
4049 else
4050 packet_payload = (line_buf_size) / bytespl * bytespl;
4051
4052 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4053 total_len = (bytespf / packet_payload) * packet_len;
4054
4055 if (bytespf % packet_payload)
4056 total_len += (bytespf % packet_payload) + 1;
4057
4058 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4059 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4060
4061 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4062 packet_len, 0);
4063
4064 if (dsi->te_enabled)
4065 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4066 else
4067 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4068 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4069
4070 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4071 * because DSS interrupts are not capable of waking up the CPU and the
4072 * framedone interrupt could be delayed for quite a long time. I think
4073 * the same goes for any DSS interrupts, but for some reason I have not
4074 * seen the problem anywhere else than here.
4075 */
4076 dispc_disable_sidle();
4077
4078 dsi_perf_mark_start(dsidev);
4079
4080 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4081 msecs_to_jiffies(250));
4082 BUG_ON(r == 0);
4083
4084 dss_start_update(dssdev);
4085
4086 if (dsi->te_enabled) {
4087 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4088 * for TE is longer than the timer allows */
4089 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4090
4091 dsi_vc_send_bta(dsidev, channel);
4092
4093 #ifdef DSI_CATCH_MISSING_TE
4094 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4095 #endif
4096 }
4097 }
4098
4099 #ifdef DSI_CATCH_MISSING_TE
4100 static void dsi_te_timeout(unsigned long arg)
4101 {
4102 DSSERR("TE not received for 250ms!\n");
4103 }
4104 #endif
4105
4106 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4107 {
4108 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4109
4110 /* SIDLEMODE back to smart-idle */
4111 dispc_enable_sidle();
4112
4113 if (dsi->te_enabled) {
4114 /* enable LP_RX_TO again after the TE */
4115 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4116 }
4117
4118 dsi->framedone_callback(error, dsi->framedone_data);
4119
4120 if (!error)
4121 dsi_perf_show(dsidev, "DISPC");
4122 }
4123
4124 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4125 {
4126 struct dsi_data *dsi = container_of(work, struct dsi_data,
4127 framedone_timeout_work.work);
4128 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4129 * 250ms which would conflict with this timeout work. What should be
4130 * done is first cancel the transfer on the HW, and then cancel the
4131 * possibly scheduled framedone work. However, cancelling the transfer
4132 * on the HW is buggy, and would probably require resetting the whole
4133 * DSI */
4134
4135 DSSERR("Framedone not received for 250ms!\n");
4136
4137 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4138 }
4139
4140 static void dsi_framedone_irq_callback(void *data, u32 mask)
4141 {
4142 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4143 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4144 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4145
4146 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4147 * turns itself off. However, DSI still has the pixels in its buffers,
4148 * and is sending the data.
4149 */
4150
4151 __cancel_delayed_work(&dsi->framedone_timeout_work);
4152
4153 dsi_handle_framedone(dsidev, 0);
4154
4155 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4156 dispc_fake_vsync_irq();
4157 #endif
4158 }
4159
4160 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
4161 u16 *x, u16 *y, u16 *w, u16 *h,
4162 bool enlarge_update_area)
4163 {
4164 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4165 u16 dw, dh;
4166
4167 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4168
4169 if (*x > dw || *y > dh)
4170 return -EINVAL;
4171
4172 if (*x + *w > dw)
4173 return -EINVAL;
4174
4175 if (*y + *h > dh)
4176 return -EINVAL;
4177
4178 if (*w == 1)
4179 return -EINVAL;
4180
4181 if (*w == 0 || *h == 0)
4182 return -EINVAL;
4183
4184 dsi_perf_mark_setup(dsidev);
4185
4186 dss_setup_partial_planes(dssdev, x, y, w, h,
4187 enlarge_update_area);
4188 dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
4189
4190 return 0;
4191 }
4192 EXPORT_SYMBOL(omap_dsi_prepare_update);
4193
4194 int omap_dsi_update(struct omap_dss_device *dssdev,
4195 int channel,
4196 u16 x, u16 y, u16 w, u16 h,
4197 void (*callback)(int, void *), void *data)
4198 {
4199 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4200 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4201
4202 dsi->update_channel = channel;
4203
4204 /* OMAP DSS cannot send updates of odd widths.
4205 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4206 * here to make sure we catch erroneous updates. Otherwise we'll only
4207 * see rather obscure HW error happening, as DSS halts. */
4208 BUG_ON(x % 2 == 1);
4209
4210 dsi->framedone_callback = callback;
4211 dsi->framedone_data = data;
4212
4213 dsi->update_region.x = x;
4214 dsi->update_region.y = y;
4215 dsi->update_region.w = w;
4216 dsi->update_region.h = h;
4217 dsi->update_region.device = dssdev;
4218
4219 dsi_update_screen_dispc(dssdev, x, y, w, h);
4220
4221 return 0;
4222 }
4223 EXPORT_SYMBOL(omap_dsi_update);
4224
4225 /* Display funcs */
4226
4227 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4228 {
4229 int r;
4230
4231 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4232 u32 irq;
4233 struct omap_video_timings timings = {
4234 .hsw = 1,
4235 .hfp = 1,
4236 .hbp = 1,
4237 .vsw = 1,
4238 .vfp = 0,
4239 .vbp = 0,
4240 };
4241
4242 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4243 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4244
4245 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4246 (void *) dssdev, irq);
4247 if (r) {
4248 DSSERR("can't get FRAMEDONE irq\n");
4249 return r;
4250 }
4251
4252 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4253 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4254
4255 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4256 } else {
4257 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4258 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4259
4260 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4261 &dssdev->panel.timings);
4262 }
4263
4264 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4265 OMAP_DSS_LCD_DISPLAY_TFT);
4266 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4267 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4268 return 0;
4269 }
4270
4271 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4272 {
4273 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4274 u32 irq;
4275
4276 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4277 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4278
4279 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4280 (void *) dssdev, irq);
4281 }
4282 }
4283
4284 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4285 {
4286 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4287 struct dsi_clock_info cinfo;
4288 int r;
4289
4290 /* we always use DSS_CLK_SYSCK as input clock */
4291 cinfo.use_sys_clk = true;
4292 cinfo.regn = dssdev->clocks.dsi.regn;
4293 cinfo.regm = dssdev->clocks.dsi.regm;
4294 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4295 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4296 r = dsi_calc_clock_rates(dssdev, &cinfo);
4297 if (r) {
4298 DSSERR("Failed to calc dsi clocks\n");
4299 return r;
4300 }
4301
4302 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4303 if (r) {
4304 DSSERR("Failed to set dsi clocks\n");
4305 return r;
4306 }
4307
4308 return 0;
4309 }
4310
4311 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4312 {
4313 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4314 struct dispc_clock_info dispc_cinfo;
4315 int r;
4316 unsigned long long fck;
4317
4318 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4319
4320 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4321 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4322
4323 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4324 if (r) {
4325 DSSERR("Failed to calc dispc clocks\n");
4326 return r;
4327 }
4328
4329 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4330 if (r) {
4331 DSSERR("Failed to set dispc clocks\n");
4332 return r;
4333 }
4334
4335 return 0;
4336 }
4337
4338 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4339 {
4340 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4341 int dsi_module = dsi_get_dsidev_id(dsidev);
4342 int r;
4343
4344 r = dsi_parse_lane_config(dssdev);
4345 if (r) {
4346 DSSERR("illegal lane config");
4347 goto err0;
4348 }
4349
4350 r = dsi_pll_init(dsidev, true, true);
4351 if (r)
4352 goto err0;
4353
4354 r = dsi_configure_dsi_clocks(dssdev);
4355 if (r)
4356 goto err1;
4357
4358 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4359 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4360 dss_select_lcd_clk_source(dssdev->manager->id,
4361 dssdev->clocks.dispc.channel.lcd_clk_src);
4362
4363 DSSDBG("PLL OK\n");
4364
4365 r = dsi_configure_dispc_clocks(dssdev);
4366 if (r)
4367 goto err2;
4368
4369 r = dsi_cio_init(dssdev);
4370 if (r)
4371 goto err2;
4372
4373 _dsi_print_reset_status(dsidev);
4374
4375 dsi_proto_timings(dssdev);
4376 dsi_set_lp_clk_divisor(dssdev);
4377
4378 if (1)
4379 _dsi_print_reset_status(dsidev);
4380
4381 r = dsi_proto_config(dssdev);
4382 if (r)
4383 goto err3;
4384
4385 /* enable interface */
4386 dsi_vc_enable(dsidev, 0, 1);
4387 dsi_vc_enable(dsidev, 1, 1);
4388 dsi_vc_enable(dsidev, 2, 1);
4389 dsi_vc_enable(dsidev, 3, 1);
4390 dsi_if_enable(dsidev, 1);
4391 dsi_force_tx_stop_mode_io(dsidev);
4392
4393 return 0;
4394 err3:
4395 dsi_cio_uninit(dssdev);
4396 err2:
4397 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4398 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4399 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4400
4401 err1:
4402 dsi_pll_uninit(dsidev, true);
4403 err0:
4404 return r;
4405 }
4406
4407 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4408 bool disconnect_lanes, bool enter_ulps)
4409 {
4410 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4411 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4412 int dsi_module = dsi_get_dsidev_id(dsidev);
4413
4414 if (enter_ulps && !dsi->ulps_enabled)
4415 dsi_enter_ulps(dsidev);
4416
4417 /* disable interface */
4418 dsi_if_enable(dsidev, 0);
4419 dsi_vc_enable(dsidev, 0, 0);
4420 dsi_vc_enable(dsidev, 1, 0);
4421 dsi_vc_enable(dsidev, 2, 0);
4422 dsi_vc_enable(dsidev, 3, 0);
4423
4424 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4425 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4426 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4427 dsi_cio_uninit(dssdev);
4428 dsi_pll_uninit(dsidev, disconnect_lanes);
4429 }
4430
4431 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4432 {
4433 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4434 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4435 int r = 0;
4436
4437 DSSDBG("dsi_display_enable\n");
4438
4439 WARN_ON(!dsi_bus_is_locked(dsidev));
4440
4441 mutex_lock(&dsi->lock);
4442
4443 if (dssdev->manager == NULL) {
4444 DSSERR("failed to enable display: no manager\n");
4445 r = -ENODEV;
4446 goto err_start_dev;
4447 }
4448
4449 r = omap_dss_start_device(dssdev);
4450 if (r) {
4451 DSSERR("failed to start device\n");
4452 goto err_start_dev;
4453 }
4454
4455 r = dsi_runtime_get(dsidev);
4456 if (r)
4457 goto err_get_dsi;
4458
4459 dsi_enable_pll_clock(dsidev, 1);
4460
4461 _dsi_initialize_irq(dsidev);
4462
4463 r = dsi_display_init_dispc(dssdev);
4464 if (r)
4465 goto err_init_dispc;
4466
4467 r = dsi_display_init_dsi(dssdev);
4468 if (r)
4469 goto err_init_dsi;
4470
4471 mutex_unlock(&dsi->lock);
4472
4473 return 0;
4474
4475 err_init_dsi:
4476 dsi_display_uninit_dispc(dssdev);
4477 err_init_dispc:
4478 dsi_enable_pll_clock(dsidev, 0);
4479 dsi_runtime_put(dsidev);
4480 err_get_dsi:
4481 omap_dss_stop_device(dssdev);
4482 err_start_dev:
4483 mutex_unlock(&dsi->lock);
4484 DSSDBG("dsi_display_enable FAILED\n");
4485 return r;
4486 }
4487 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4488
4489 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4490 bool disconnect_lanes, bool enter_ulps)
4491 {
4492 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4493 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4494
4495 DSSDBG("dsi_display_disable\n");
4496
4497 WARN_ON(!dsi_bus_is_locked(dsidev));
4498
4499 mutex_lock(&dsi->lock);
4500
4501 dsi_sync_vc(dsidev, 0);
4502 dsi_sync_vc(dsidev, 1);
4503 dsi_sync_vc(dsidev, 2);
4504 dsi_sync_vc(dsidev, 3);
4505
4506 dsi_display_uninit_dispc(dssdev);
4507
4508 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4509
4510 dsi_runtime_put(dsidev);
4511 dsi_enable_pll_clock(dsidev, 0);
4512
4513 omap_dss_stop_device(dssdev);
4514
4515 mutex_unlock(&dsi->lock);
4516 }
4517 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4518
4519 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4520 {
4521 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4522 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4523
4524 dsi->te_enabled = enable;
4525 return 0;
4526 }
4527 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4528
4529 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4530 u32 fifo_size, u32 burst_size,
4531 u32 *fifo_low, u32 *fifo_high)
4532 {
4533 *fifo_high = fifo_size - burst_size;
4534 *fifo_low = fifo_size - burst_size * 2;
4535 }
4536
4537 int dsi_init_display(struct omap_dss_device *dssdev)
4538 {
4539 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4540 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4541
4542 DSSDBG("DSI init\n");
4543
4544 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4545 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4546 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4547 }
4548
4549 if (dsi->vdds_dsi_reg == NULL) {
4550 struct regulator *vdds_dsi;
4551
4552 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4553
4554 if (IS_ERR(vdds_dsi)) {
4555 DSSERR("can't get VDDS_DSI regulator\n");
4556 return PTR_ERR(vdds_dsi);
4557 }
4558
4559 dsi->vdds_dsi_reg = vdds_dsi;
4560 }
4561
4562 return 0;
4563 }
4564
4565 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4566 {
4567 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4568 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4569 int i;
4570
4571 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4572 if (!dsi->vc[i].dssdev) {
4573 dsi->vc[i].dssdev = dssdev;
4574 *channel = i;
4575 return 0;
4576 }
4577 }
4578
4579 DSSERR("cannot get VC for display %s", dssdev->name);
4580 return -ENOSPC;
4581 }
4582 EXPORT_SYMBOL(omap_dsi_request_vc);
4583
4584 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4585 {
4586 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4587 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4588
4589 if (vc_id < 0 || vc_id > 3) {
4590 DSSERR("VC ID out of range\n");
4591 return -EINVAL;
4592 }
4593
4594 if (channel < 0 || channel > 3) {
4595 DSSERR("Virtual Channel out of range\n");
4596 return -EINVAL;
4597 }
4598
4599 if (dsi->vc[channel].dssdev != dssdev) {
4600 DSSERR("Virtual Channel not allocated to display %s\n",
4601 dssdev->name);
4602 return -EINVAL;
4603 }
4604
4605 dsi->vc[channel].vc_id = vc_id;
4606
4607 return 0;
4608 }
4609 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4610
4611 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4612 {
4613 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4614 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4615
4616 if ((channel >= 0 && channel <= 3) &&
4617 dsi->vc[channel].dssdev == dssdev) {
4618 dsi->vc[channel].dssdev = NULL;
4619 dsi->vc[channel].vc_id = 0;
4620 }
4621 }
4622 EXPORT_SYMBOL(omap_dsi_release_vc);
4623
4624 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4625 {
4626 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4627 DSSERR("%s (%s) not active\n",
4628 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4629 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4630 }
4631
4632 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4633 {
4634 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4635 DSSERR("%s (%s) not active\n",
4636 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4637 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4638 }
4639
4640 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4641 {
4642 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4643
4644 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4645 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4646 dsi->regm_dispc_max =
4647 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4648 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4649 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4650 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4651 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4652 }
4653
4654 static int dsi_get_clocks(struct platform_device *dsidev)
4655 {
4656 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4657 struct clk *clk;
4658
4659 clk = clk_get(&dsidev->dev, "fck");
4660 if (IS_ERR(clk)) {
4661 DSSERR("can't get fck\n");
4662 return PTR_ERR(clk);
4663 }
4664
4665 dsi->dss_clk = clk;
4666
4667 clk = clk_get(&dsidev->dev, "sys_clk");
4668 if (IS_ERR(clk)) {
4669 DSSERR("can't get sys_clk\n");
4670 clk_put(dsi->dss_clk);
4671 dsi->dss_clk = NULL;
4672 return PTR_ERR(clk);
4673 }
4674
4675 dsi->sys_clk = clk;
4676
4677 return 0;
4678 }
4679
4680 static void dsi_put_clocks(struct platform_device *dsidev)
4681 {
4682 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4683
4684 if (dsi->dss_clk)
4685 clk_put(dsi->dss_clk);
4686 if (dsi->sys_clk)
4687 clk_put(dsi->sys_clk);
4688 }
4689
4690 /* DSI1 HW IP initialisation */
4691 static int omap_dsihw_probe(struct platform_device *dsidev)
4692 {
4693 struct omap_display_platform_data *dss_plat_data;
4694 struct omap_dss_board_info *board_info;
4695 u32 rev;
4696 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4697 struct resource *dsi_mem;
4698 struct dsi_data *dsi;
4699
4700 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4701 if (!dsi) {
4702 r = -ENOMEM;
4703 goto err_alloc;
4704 }
4705
4706 dsi->pdev = dsidev;
4707 dsi_pdev_map[dsi_module] = dsidev;
4708 dev_set_drvdata(&dsidev->dev, dsi);
4709
4710 dss_plat_data = dsidev->dev.platform_data;
4711 board_info = dss_plat_data->board_data;
4712 dsi->enable_pads = board_info->dsi_enable_pads;
4713 dsi->disable_pads = board_info->dsi_disable_pads;
4714
4715 spin_lock_init(&dsi->irq_lock);
4716 spin_lock_init(&dsi->errors_lock);
4717 dsi->errors = 0;
4718
4719 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4720 spin_lock_init(&dsi->irq_stats_lock);
4721 dsi->irq_stats.last_reset = jiffies;
4722 #endif
4723
4724 mutex_init(&dsi->lock);
4725 sema_init(&dsi->bus_lock, 1);
4726
4727 r = dsi_get_clocks(dsidev);
4728 if (r)
4729 goto err_get_clk;
4730
4731 pm_runtime_enable(&dsidev->dev);
4732
4733 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4734 dsi_framedone_timeout_work_callback);
4735
4736 #ifdef DSI_CATCH_MISSING_TE
4737 init_timer(&dsi->te_timer);
4738 dsi->te_timer.function = dsi_te_timeout;
4739 dsi->te_timer.data = 0;
4740 #endif
4741 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4742 if (!dsi_mem) {
4743 DSSERR("can't get IORESOURCE_MEM DSI\n");
4744 r = -EINVAL;
4745 goto err_ioremap;
4746 }
4747 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4748 if (!dsi->base) {
4749 DSSERR("can't ioremap DSI\n");
4750 r = -ENOMEM;
4751 goto err_ioremap;
4752 }
4753 dsi->irq = platform_get_irq(dsi->pdev, 0);
4754 if (dsi->irq < 0) {
4755 DSSERR("platform_get_irq failed\n");
4756 r = -ENODEV;
4757 goto err_get_irq;
4758 }
4759
4760 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4761 dev_name(&dsidev->dev), dsi->pdev);
4762 if (r < 0) {
4763 DSSERR("request_irq failed\n");
4764 goto err_get_irq;
4765 }
4766
4767 /* DSI VCs initialization */
4768 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4769 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4770 dsi->vc[i].dssdev = NULL;
4771 dsi->vc[i].vc_id = 0;
4772 }
4773
4774 dsi_calc_clock_param_ranges(dsidev);
4775
4776 r = dsi_runtime_get(dsidev);
4777 if (r)
4778 goto err_get_dsi;
4779
4780 rev = dsi_read_reg(dsidev, DSI_REVISION);
4781 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4782 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4783
4784 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4785 * of data to 3 by default */
4786 if (dss_has_feature(FEAT_DSI_GNQ))
4787 /* NB_DATA_LANES */
4788 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4789 else
4790 dsi->num_lanes_supported = 3;
4791
4792 dsi_runtime_put(dsidev);
4793
4794 return 0;
4795
4796 err_get_dsi:
4797 free_irq(dsi->irq, dsi->pdev);
4798 err_get_irq:
4799 iounmap(dsi->base);
4800 err_ioremap:
4801 pm_runtime_disable(&dsidev->dev);
4802 err_get_clk:
4803 kfree(dsi);
4804 err_alloc:
4805 return r;
4806 }
4807
4808 static int omap_dsihw_remove(struct platform_device *dsidev)
4809 {
4810 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4811
4812 WARN_ON(dsi->scp_clk_refcount > 0);
4813
4814 pm_runtime_disable(&dsidev->dev);
4815
4816 dsi_put_clocks(dsidev);
4817
4818 if (dsi->vdds_dsi_reg != NULL) {
4819 if (dsi->vdds_dsi_enabled) {
4820 regulator_disable(dsi->vdds_dsi_reg);
4821 dsi->vdds_dsi_enabled = false;
4822 }
4823
4824 regulator_put(dsi->vdds_dsi_reg);
4825 dsi->vdds_dsi_reg = NULL;
4826 }
4827
4828 free_irq(dsi->irq, dsi->pdev);
4829 iounmap(dsi->base);
4830
4831 kfree(dsi);
4832
4833 return 0;
4834 }
4835
4836 static int dsi_runtime_suspend(struct device *dev)
4837 {
4838 dispc_runtime_put();
4839 dss_runtime_put();
4840
4841 return 0;
4842 }
4843
4844 static int dsi_runtime_resume(struct device *dev)
4845 {
4846 int r;
4847
4848 r = dss_runtime_get();
4849 if (r)
4850 goto err_get_dss;
4851
4852 r = dispc_runtime_get();
4853 if (r)
4854 goto err_get_dispc;
4855
4856 return 0;
4857
4858 err_get_dispc:
4859 dss_runtime_put();
4860 err_get_dss:
4861 return r;
4862 }
4863
4864 static const struct dev_pm_ops dsi_pm_ops = {
4865 .runtime_suspend = dsi_runtime_suspend,
4866 .runtime_resume = dsi_runtime_resume,
4867 };
4868
4869 static struct platform_driver omap_dsihw_driver = {
4870 .probe = omap_dsihw_probe,
4871 .remove = omap_dsihw_remove,
4872 .driver = {
4873 .name = "omapdss_dsi",
4874 .owner = THIS_MODULE,
4875 .pm = &dsi_pm_ops,
4876 },
4877 };
4878
4879 int dsi_init_platform_driver(void)
4880 {
4881 return platform_driver_register(&omap_dsihw_driver);
4882 }
4883
4884 void dsi_uninit_platform_driver(void)
4885 {
4886 return platform_driver_unregister(&omap_dsihw_driver);
4887 }
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