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OMAPDSS: DSI: flush posted write in send_bta
[mirror_ubuntu-artful-kernel.git] / drivers / video / omap2 / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
45
46 #include "dss.h"
47 #include "dss_features.h"
48
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
51
52 struct dsi_reg { u16 idx; };
53
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
55
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
58
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
93
94 /* DSIPHY_SCP */
95
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
101
102 /* DSI_PLL_CTRL_SCP */
103
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
109
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
138
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
153
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204
205 #define DSI_MAX_NR_ISRS 2
206
207 struct dsi_isr_data {
208 omap_dsi_isr_t isr;
209 void *arg;
210 u32 mask;
211 };
212
213 enum fifo_size {
214 DSI_FIFO_SIZE_0 = 0,
215 DSI_FIFO_SIZE_32 = 1,
216 DSI_FIFO_SIZE_64 = 2,
217 DSI_FIFO_SIZE_96 = 3,
218 DSI_FIFO_SIZE_128 = 4,
219 };
220
221 enum dsi_vc_source {
222 DSI_VC_SOURCE_L4 = 0,
223 DSI_VC_SOURCE_VP,
224 };
225
226 enum dsi_lane {
227 DSI_CLK_P = 1 << 0,
228 DSI_CLK_N = 1 << 1,
229 DSI_DATA1_P = 1 << 2,
230 DSI_DATA1_N = 1 << 3,
231 DSI_DATA2_P = 1 << 4,
232 DSI_DATA2_N = 1 << 5,
233 DSI_DATA3_P = 1 << 6,
234 DSI_DATA3_N = 1 << 7,
235 DSI_DATA4_P = 1 << 8,
236 DSI_DATA4_N = 1 << 9,
237 };
238
239 struct dsi_update_region {
240 u16 x, y, w, h;
241 struct omap_dss_device *device;
242 };
243
244 struct dsi_irq_stats {
245 unsigned long last_reset;
246 unsigned irq_count;
247 unsigned dsi_irqs[32];
248 unsigned vc_irqs[4][32];
249 unsigned cio_irqs[32];
250 };
251
252 struct dsi_isr_tables {
253 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
254 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
255 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
256 };
257
258 struct dsi_data {
259 struct platform_device *pdev;
260 void __iomem *base;
261
262 int irq;
263
264 struct clk *dss_clk;
265 struct clk *sys_clk;
266
267 int (*enable_pads)(int dsi_id, unsigned lane_mask);
268 void (*disable_pads)(int dsi_id, unsigned lane_mask);
269
270 struct dsi_clock_info current_cinfo;
271
272 bool vdds_dsi_enabled;
273 struct regulator *vdds_dsi_reg;
274
275 struct {
276 enum dsi_vc_source source;
277 struct omap_dss_device *dssdev;
278 enum fifo_size fifo_size;
279 int vc_id;
280 } vc[4];
281
282 struct mutex lock;
283 struct semaphore bus_lock;
284
285 unsigned pll_locked;
286
287 spinlock_t irq_lock;
288 struct dsi_isr_tables isr_tables;
289 /* space for a copy used by the interrupt handler */
290 struct dsi_isr_tables isr_tables_copy;
291
292 int update_channel;
293 struct dsi_update_region update_region;
294
295 bool te_enabled;
296 bool ulps_enabled;
297
298 void (*framedone_callback)(int, void *);
299 void *framedone_data;
300
301 struct delayed_work framedone_timeout_work;
302
303 #ifdef DSI_CATCH_MISSING_TE
304 struct timer_list te_timer;
305 #endif
306
307 unsigned long cache_req_pck;
308 unsigned long cache_clk_freq;
309 struct dsi_clock_info cache_cinfo;
310
311 u32 errors;
312 spinlock_t errors_lock;
313 #ifdef DEBUG
314 ktime_t perf_setup_time;
315 ktime_t perf_start_time;
316 #endif
317 int debug_read;
318 int debug_write;
319
320 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
321 spinlock_t irq_stats_lock;
322 struct dsi_irq_stats irq_stats;
323 #endif
324 /* DSI PLL Parameter Ranges */
325 unsigned long regm_max, regn_max;
326 unsigned long regm_dispc_max, regm_dsi_max;
327 unsigned long fint_min, fint_max;
328 unsigned long lpdiv_max;
329
330 int num_data_lanes;
331
332 unsigned scp_clk_refcount;
333 };
334
335 struct dsi_packet_sent_handler_data {
336 struct platform_device *dsidev;
337 struct completion *completion;
338 };
339
340 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
341
342 #ifdef DEBUG
343 static unsigned int dsi_perf;
344 module_param_named(dsi_perf, dsi_perf, bool, 0644);
345 #endif
346
347 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
348 {
349 return dev_get_drvdata(&dsidev->dev);
350 }
351
352 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
353 {
354 return dsi_pdev_map[dssdev->phy.dsi.module];
355 }
356
357 struct platform_device *dsi_get_dsidev_from_id(int module)
358 {
359 return dsi_pdev_map[module];
360 }
361
362 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
363 {
364 return dsidev->id;
365 }
366
367 static inline void dsi_write_reg(struct platform_device *dsidev,
368 const struct dsi_reg idx, u32 val)
369 {
370 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
371
372 __raw_writel(val, dsi->base + idx.idx);
373 }
374
375 static inline u32 dsi_read_reg(struct platform_device *dsidev,
376 const struct dsi_reg idx)
377 {
378 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
379
380 return __raw_readl(dsi->base + idx.idx);
381 }
382
383 void dsi_bus_lock(struct omap_dss_device *dssdev)
384 {
385 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
387
388 down(&dsi->bus_lock);
389 }
390 EXPORT_SYMBOL(dsi_bus_lock);
391
392 void dsi_bus_unlock(struct omap_dss_device *dssdev)
393 {
394 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
395 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
396
397 up(&dsi->bus_lock);
398 }
399 EXPORT_SYMBOL(dsi_bus_unlock);
400
401 static bool dsi_bus_is_locked(struct platform_device *dsidev)
402 {
403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
404
405 return dsi->bus_lock.count == 0;
406 }
407
408 static void dsi_completion_handler(void *data, u32 mask)
409 {
410 complete((struct completion *)data);
411 }
412
413 static inline int wait_for_bit_change(struct platform_device *dsidev,
414 const struct dsi_reg idx, int bitnum, int value)
415 {
416 int t = 100000;
417
418 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
419 if (--t == 0)
420 return !value;
421 }
422
423 return value;
424 }
425
426 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
427 {
428 switch (fmt) {
429 case OMAP_DSS_DSI_FMT_RGB888:
430 case OMAP_DSS_DSI_FMT_RGB666:
431 return 24;
432 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
433 return 18;
434 case OMAP_DSS_DSI_FMT_RGB565:
435 return 16;
436 default:
437 BUG();
438 }
439 }
440
441 #ifdef DEBUG
442 static void dsi_perf_mark_setup(struct platform_device *dsidev)
443 {
444 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
445 dsi->perf_setup_time = ktime_get();
446 }
447
448 static void dsi_perf_mark_start(struct platform_device *dsidev)
449 {
450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
451 dsi->perf_start_time = ktime_get();
452 }
453
454 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
455 {
456 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
457 struct omap_dss_device *dssdev = dsi->update_region.device;
458 ktime_t t, setup_time, trans_time;
459 u32 total_bytes;
460 u32 setup_us, trans_us, total_us;
461
462 if (!dsi_perf)
463 return;
464
465 t = ktime_get();
466
467 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
468 setup_us = (u32)ktime_to_us(setup_time);
469 if (setup_us == 0)
470 setup_us = 1;
471
472 trans_time = ktime_sub(t, dsi->perf_start_time);
473 trans_us = (u32)ktime_to_us(trans_time);
474 if (trans_us == 0)
475 trans_us = 1;
476
477 total_us = setup_us + trans_us;
478
479 total_bytes = dsi->update_region.w *
480 dsi->update_region.h *
481 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
482
483 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
484 "%u bytes, %u kbytes/sec\n",
485 name,
486 setup_us,
487 trans_us,
488 total_us,
489 1000*1000 / total_us,
490 total_bytes,
491 total_bytes * 1000 / total_us);
492 }
493 #else
494 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
495 {
496 }
497
498 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
499 {
500 }
501
502 static inline void dsi_perf_show(struct platform_device *dsidev,
503 const char *name)
504 {
505 }
506 #endif
507
508 static void print_irq_status(u32 status)
509 {
510 if (status == 0)
511 return;
512
513 #ifndef VERBOSE_IRQ
514 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
515 return;
516 #endif
517 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
518
519 #define PIS(x) \
520 if (status & DSI_IRQ_##x) \
521 printk(#x " ");
522 #ifdef VERBOSE_IRQ
523 PIS(VC0);
524 PIS(VC1);
525 PIS(VC2);
526 PIS(VC3);
527 #endif
528 PIS(WAKEUP);
529 PIS(RESYNC);
530 PIS(PLL_LOCK);
531 PIS(PLL_UNLOCK);
532 PIS(PLL_RECALL);
533 PIS(COMPLEXIO_ERR);
534 PIS(HS_TX_TIMEOUT);
535 PIS(LP_RX_TIMEOUT);
536 PIS(TE_TRIGGER);
537 PIS(ACK_TRIGGER);
538 PIS(SYNC_LOST);
539 PIS(LDO_POWER_GOOD);
540 PIS(TA_TIMEOUT);
541 #undef PIS
542
543 printk("\n");
544 }
545
546 static void print_irq_status_vc(int channel, u32 status)
547 {
548 if (status == 0)
549 return;
550
551 #ifndef VERBOSE_IRQ
552 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
553 return;
554 #endif
555 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
556
557 #define PIS(x) \
558 if (status & DSI_VC_IRQ_##x) \
559 printk(#x " ");
560 PIS(CS);
561 PIS(ECC_CORR);
562 #ifdef VERBOSE_IRQ
563 PIS(PACKET_SENT);
564 #endif
565 PIS(FIFO_TX_OVF);
566 PIS(FIFO_RX_OVF);
567 PIS(BTA);
568 PIS(ECC_NO_CORR);
569 PIS(FIFO_TX_UDF);
570 PIS(PP_BUSY_CHANGE);
571 #undef PIS
572 printk("\n");
573 }
574
575 static void print_irq_status_cio(u32 status)
576 {
577 if (status == 0)
578 return;
579
580 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
581
582 #define PIS(x) \
583 if (status & DSI_CIO_IRQ_##x) \
584 printk(#x " ");
585 PIS(ERRSYNCESC1);
586 PIS(ERRSYNCESC2);
587 PIS(ERRSYNCESC3);
588 PIS(ERRESC1);
589 PIS(ERRESC2);
590 PIS(ERRESC3);
591 PIS(ERRCONTROL1);
592 PIS(ERRCONTROL2);
593 PIS(ERRCONTROL3);
594 PIS(STATEULPS1);
595 PIS(STATEULPS2);
596 PIS(STATEULPS3);
597 PIS(ERRCONTENTIONLP0_1);
598 PIS(ERRCONTENTIONLP1_1);
599 PIS(ERRCONTENTIONLP0_2);
600 PIS(ERRCONTENTIONLP1_2);
601 PIS(ERRCONTENTIONLP0_3);
602 PIS(ERRCONTENTIONLP1_3);
603 PIS(ULPSACTIVENOT_ALL0);
604 PIS(ULPSACTIVENOT_ALL1);
605 #undef PIS
606
607 printk("\n");
608 }
609
610 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
611 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
612 u32 *vcstatus, u32 ciostatus)
613 {
614 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
615 int i;
616
617 spin_lock(&dsi->irq_stats_lock);
618
619 dsi->irq_stats.irq_count++;
620 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
621
622 for (i = 0; i < 4; ++i)
623 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
624
625 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
626
627 spin_unlock(&dsi->irq_stats_lock);
628 }
629 #else
630 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
631 #endif
632
633 static int debug_irq;
634
635 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
636 u32 *vcstatus, u32 ciostatus)
637 {
638 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
639 int i;
640
641 if (irqstatus & DSI_IRQ_ERROR_MASK) {
642 DSSERR("DSI error, irqstatus %x\n", irqstatus);
643 print_irq_status(irqstatus);
644 spin_lock(&dsi->errors_lock);
645 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
646 spin_unlock(&dsi->errors_lock);
647 } else if (debug_irq) {
648 print_irq_status(irqstatus);
649 }
650
651 for (i = 0; i < 4; ++i) {
652 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
653 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
654 i, vcstatus[i]);
655 print_irq_status_vc(i, vcstatus[i]);
656 } else if (debug_irq) {
657 print_irq_status_vc(i, vcstatus[i]);
658 }
659 }
660
661 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
662 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
663 print_irq_status_cio(ciostatus);
664 } else if (debug_irq) {
665 print_irq_status_cio(ciostatus);
666 }
667 }
668
669 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
670 unsigned isr_array_size, u32 irqstatus)
671 {
672 struct dsi_isr_data *isr_data;
673 int i;
674
675 for (i = 0; i < isr_array_size; i++) {
676 isr_data = &isr_array[i];
677 if (isr_data->isr && isr_data->mask & irqstatus)
678 isr_data->isr(isr_data->arg, irqstatus);
679 }
680 }
681
682 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
683 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
684 {
685 int i;
686
687 dsi_call_isrs(isr_tables->isr_table,
688 ARRAY_SIZE(isr_tables->isr_table),
689 irqstatus);
690
691 for (i = 0; i < 4; ++i) {
692 if (vcstatus[i] == 0)
693 continue;
694 dsi_call_isrs(isr_tables->isr_table_vc[i],
695 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
696 vcstatus[i]);
697 }
698
699 if (ciostatus != 0)
700 dsi_call_isrs(isr_tables->isr_table_cio,
701 ARRAY_SIZE(isr_tables->isr_table_cio),
702 ciostatus);
703 }
704
705 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
706 {
707 struct platform_device *dsidev;
708 struct dsi_data *dsi;
709 u32 irqstatus, vcstatus[4], ciostatus;
710 int i;
711
712 dsidev = (struct platform_device *) arg;
713 dsi = dsi_get_dsidrv_data(dsidev);
714
715 spin_lock(&dsi->irq_lock);
716
717 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
718
719 /* IRQ is not for us */
720 if (!irqstatus) {
721 spin_unlock(&dsi->irq_lock);
722 return IRQ_NONE;
723 }
724
725 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
726 /* flush posted write */
727 dsi_read_reg(dsidev, DSI_IRQSTATUS);
728
729 for (i = 0; i < 4; ++i) {
730 if ((irqstatus & (1 << i)) == 0) {
731 vcstatus[i] = 0;
732 continue;
733 }
734
735 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
736
737 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
738 /* flush posted write */
739 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
740 }
741
742 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
743 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
744
745 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
746 /* flush posted write */
747 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
748 } else {
749 ciostatus = 0;
750 }
751
752 #ifdef DSI_CATCH_MISSING_TE
753 if (irqstatus & DSI_IRQ_TE_TRIGGER)
754 del_timer(&dsi->te_timer);
755 #endif
756
757 /* make a copy and unlock, so that isrs can unregister
758 * themselves */
759 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
760 sizeof(dsi->isr_tables));
761
762 spin_unlock(&dsi->irq_lock);
763
764 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
765
766 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
767
768 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
769
770 return IRQ_HANDLED;
771 }
772
773 /* dsi->irq_lock has to be locked by the caller */
774 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
775 struct dsi_isr_data *isr_array,
776 unsigned isr_array_size, u32 default_mask,
777 const struct dsi_reg enable_reg,
778 const struct dsi_reg status_reg)
779 {
780 struct dsi_isr_data *isr_data;
781 u32 mask;
782 u32 old_mask;
783 int i;
784
785 mask = default_mask;
786
787 for (i = 0; i < isr_array_size; i++) {
788 isr_data = &isr_array[i];
789
790 if (isr_data->isr == NULL)
791 continue;
792
793 mask |= isr_data->mask;
794 }
795
796 old_mask = dsi_read_reg(dsidev, enable_reg);
797 /* clear the irqstatus for newly enabled irqs */
798 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
799 dsi_write_reg(dsidev, enable_reg, mask);
800
801 /* flush posted writes */
802 dsi_read_reg(dsidev, enable_reg);
803 dsi_read_reg(dsidev, status_reg);
804 }
805
806 /* dsi->irq_lock has to be locked by the caller */
807 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
808 {
809 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
810 u32 mask = DSI_IRQ_ERROR_MASK;
811 #ifdef DSI_CATCH_MISSING_TE
812 mask |= DSI_IRQ_TE_TRIGGER;
813 #endif
814 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
815 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
816 DSI_IRQENABLE, DSI_IRQSTATUS);
817 }
818
819 /* dsi->irq_lock has to be locked by the caller */
820 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
821 {
822 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
823
824 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
825 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
826 DSI_VC_IRQ_ERROR_MASK,
827 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
828 }
829
830 /* dsi->irq_lock has to be locked by the caller */
831 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
832 {
833 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
834
835 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
836 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
837 DSI_CIO_IRQ_ERROR_MASK,
838 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
839 }
840
841 static void _dsi_initialize_irq(struct platform_device *dsidev)
842 {
843 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
844 unsigned long flags;
845 int vc;
846
847 spin_lock_irqsave(&dsi->irq_lock, flags);
848
849 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
850
851 _omap_dsi_set_irqs(dsidev);
852 for (vc = 0; vc < 4; ++vc)
853 _omap_dsi_set_irqs_vc(dsidev, vc);
854 _omap_dsi_set_irqs_cio(dsidev);
855
856 spin_unlock_irqrestore(&dsi->irq_lock, flags);
857 }
858
859 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
860 struct dsi_isr_data *isr_array, unsigned isr_array_size)
861 {
862 struct dsi_isr_data *isr_data;
863 int free_idx;
864 int i;
865
866 BUG_ON(isr == NULL);
867
868 /* check for duplicate entry and find a free slot */
869 free_idx = -1;
870 for (i = 0; i < isr_array_size; i++) {
871 isr_data = &isr_array[i];
872
873 if (isr_data->isr == isr && isr_data->arg == arg &&
874 isr_data->mask == mask) {
875 return -EINVAL;
876 }
877
878 if (isr_data->isr == NULL && free_idx == -1)
879 free_idx = i;
880 }
881
882 if (free_idx == -1)
883 return -EBUSY;
884
885 isr_data = &isr_array[free_idx];
886 isr_data->isr = isr;
887 isr_data->arg = arg;
888 isr_data->mask = mask;
889
890 return 0;
891 }
892
893 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
894 struct dsi_isr_data *isr_array, unsigned isr_array_size)
895 {
896 struct dsi_isr_data *isr_data;
897 int i;
898
899 for (i = 0; i < isr_array_size; i++) {
900 isr_data = &isr_array[i];
901 if (isr_data->isr != isr || isr_data->arg != arg ||
902 isr_data->mask != mask)
903 continue;
904
905 isr_data->isr = NULL;
906 isr_data->arg = NULL;
907 isr_data->mask = 0;
908
909 return 0;
910 }
911
912 return -EINVAL;
913 }
914
915 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
916 void *arg, u32 mask)
917 {
918 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
919 unsigned long flags;
920 int r;
921
922 spin_lock_irqsave(&dsi->irq_lock, flags);
923
924 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
925 ARRAY_SIZE(dsi->isr_tables.isr_table));
926
927 if (r == 0)
928 _omap_dsi_set_irqs(dsidev);
929
930 spin_unlock_irqrestore(&dsi->irq_lock, flags);
931
932 return r;
933 }
934
935 static int dsi_unregister_isr(struct platform_device *dsidev,
936 omap_dsi_isr_t isr, void *arg, u32 mask)
937 {
938 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
939 unsigned long flags;
940 int r;
941
942 spin_lock_irqsave(&dsi->irq_lock, flags);
943
944 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
945 ARRAY_SIZE(dsi->isr_tables.isr_table));
946
947 if (r == 0)
948 _omap_dsi_set_irqs(dsidev);
949
950 spin_unlock_irqrestore(&dsi->irq_lock, flags);
951
952 return r;
953 }
954
955 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
956 omap_dsi_isr_t isr, void *arg, u32 mask)
957 {
958 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
959 unsigned long flags;
960 int r;
961
962 spin_lock_irqsave(&dsi->irq_lock, flags);
963
964 r = _dsi_register_isr(isr, arg, mask,
965 dsi->isr_tables.isr_table_vc[channel],
966 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
967
968 if (r == 0)
969 _omap_dsi_set_irqs_vc(dsidev, channel);
970
971 spin_unlock_irqrestore(&dsi->irq_lock, flags);
972
973 return r;
974 }
975
976 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
977 omap_dsi_isr_t isr, void *arg, u32 mask)
978 {
979 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
980 unsigned long flags;
981 int r;
982
983 spin_lock_irqsave(&dsi->irq_lock, flags);
984
985 r = _dsi_unregister_isr(isr, arg, mask,
986 dsi->isr_tables.isr_table_vc[channel],
987 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
988
989 if (r == 0)
990 _omap_dsi_set_irqs_vc(dsidev, channel);
991
992 spin_unlock_irqrestore(&dsi->irq_lock, flags);
993
994 return r;
995 }
996
997 static int dsi_register_isr_cio(struct platform_device *dsidev,
998 omap_dsi_isr_t isr, void *arg, u32 mask)
999 {
1000 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1001 unsigned long flags;
1002 int r;
1003
1004 spin_lock_irqsave(&dsi->irq_lock, flags);
1005
1006 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1007 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1008
1009 if (r == 0)
1010 _omap_dsi_set_irqs_cio(dsidev);
1011
1012 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1013
1014 return r;
1015 }
1016
1017 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1018 omap_dsi_isr_t isr, void *arg, u32 mask)
1019 {
1020 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1021 unsigned long flags;
1022 int r;
1023
1024 spin_lock_irqsave(&dsi->irq_lock, flags);
1025
1026 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1027 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1028
1029 if (r == 0)
1030 _omap_dsi_set_irqs_cio(dsidev);
1031
1032 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1033
1034 return r;
1035 }
1036
1037 static u32 dsi_get_errors(struct platform_device *dsidev)
1038 {
1039 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1040 unsigned long flags;
1041 u32 e;
1042 spin_lock_irqsave(&dsi->errors_lock, flags);
1043 e = dsi->errors;
1044 dsi->errors = 0;
1045 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1046 return e;
1047 }
1048
1049 int dsi_runtime_get(struct platform_device *dsidev)
1050 {
1051 int r;
1052 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1053
1054 DSSDBG("dsi_runtime_get\n");
1055
1056 r = pm_runtime_get_sync(&dsi->pdev->dev);
1057 WARN_ON(r < 0);
1058 return r < 0 ? r : 0;
1059 }
1060
1061 void dsi_runtime_put(struct platform_device *dsidev)
1062 {
1063 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1064 int r;
1065
1066 DSSDBG("dsi_runtime_put\n");
1067
1068 r = pm_runtime_put(&dsi->pdev->dev);
1069 WARN_ON(r < 0);
1070 }
1071
1072 /* source clock for DSI PLL. this could also be PCLKFREE */
1073 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1074 bool enable)
1075 {
1076 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1077
1078 if (enable)
1079 clk_enable(dsi->sys_clk);
1080 else
1081 clk_disable(dsi->sys_clk);
1082
1083 if (enable && dsi->pll_locked) {
1084 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1085 DSSERR("cannot lock PLL when enabling clocks\n");
1086 }
1087 }
1088
1089 #ifdef DEBUG
1090 static void _dsi_print_reset_status(struct platform_device *dsidev)
1091 {
1092 u32 l;
1093 int b0, b1, b2;
1094
1095 if (!dss_debug)
1096 return;
1097
1098 /* A dummy read using the SCP interface to any DSIPHY register is
1099 * required after DSIPHY reset to complete the reset of the DSI complex
1100 * I/O. */
1101 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1102
1103 printk(KERN_DEBUG "DSI resets: ");
1104
1105 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1106 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1107
1108 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1109 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1110
1111 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1112 b0 = 28;
1113 b1 = 27;
1114 b2 = 26;
1115 } else {
1116 b0 = 24;
1117 b1 = 25;
1118 b2 = 26;
1119 }
1120
1121 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1122 printk("PHY (%x%x%x, %d, %d, %d)\n",
1123 FLD_GET(l, b0, b0),
1124 FLD_GET(l, b1, b1),
1125 FLD_GET(l, b2, b2),
1126 FLD_GET(l, 29, 29),
1127 FLD_GET(l, 30, 30),
1128 FLD_GET(l, 31, 31));
1129 }
1130 #else
1131 #define _dsi_print_reset_status(x)
1132 #endif
1133
1134 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1135 {
1136 DSSDBG("dsi_if_enable(%d)\n", enable);
1137
1138 enable = enable ? 1 : 0;
1139 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1140
1141 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1142 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1143 return -EIO;
1144 }
1145
1146 return 0;
1147 }
1148
1149 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1150 {
1151 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1152
1153 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1154 }
1155
1156 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1157 {
1158 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1159
1160 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1161 }
1162
1163 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1164 {
1165 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1166
1167 return dsi->current_cinfo.clkin4ddr / 16;
1168 }
1169
1170 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1171 {
1172 unsigned long r;
1173 int dsi_module = dsi_get_dsidev_id(dsidev);
1174 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1175
1176 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1177 /* DSI FCLK source is DSS_CLK_FCK */
1178 r = clk_get_rate(dsi->dss_clk);
1179 } else {
1180 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1181 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1182 }
1183
1184 return r;
1185 }
1186
1187 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1188 {
1189 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1190 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1191 unsigned long dsi_fclk;
1192 unsigned lp_clk_div;
1193 unsigned long lp_clk;
1194
1195 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1196
1197 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1198 return -EINVAL;
1199
1200 dsi_fclk = dsi_fclk_rate(dsidev);
1201
1202 lp_clk = dsi_fclk / 2 / lp_clk_div;
1203
1204 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1205 dsi->current_cinfo.lp_clk = lp_clk;
1206 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1207
1208 /* LP_CLK_DIVISOR */
1209 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1210
1211 /* LP_RX_SYNCHRO_ENABLE */
1212 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1213
1214 return 0;
1215 }
1216
1217 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1218 {
1219 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1220
1221 if (dsi->scp_clk_refcount++ == 0)
1222 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1223 }
1224
1225 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1226 {
1227 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1228
1229 WARN_ON(dsi->scp_clk_refcount == 0);
1230 if (--dsi->scp_clk_refcount == 0)
1231 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1232 }
1233
1234 enum dsi_pll_power_state {
1235 DSI_PLL_POWER_OFF = 0x0,
1236 DSI_PLL_POWER_ON_HSCLK = 0x1,
1237 DSI_PLL_POWER_ON_ALL = 0x2,
1238 DSI_PLL_POWER_ON_DIV = 0x3,
1239 };
1240
1241 static int dsi_pll_power(struct platform_device *dsidev,
1242 enum dsi_pll_power_state state)
1243 {
1244 int t = 0;
1245
1246 /* DSI-PLL power command 0x3 is not working */
1247 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1248 state == DSI_PLL_POWER_ON_DIV)
1249 state = DSI_PLL_POWER_ON_ALL;
1250
1251 /* PLL_PWR_CMD */
1252 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1253
1254 /* PLL_PWR_STATUS */
1255 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1256 if (++t > 1000) {
1257 DSSERR("Failed to set DSI PLL power mode to %d\n",
1258 state);
1259 return -ENODEV;
1260 }
1261 udelay(1);
1262 }
1263
1264 return 0;
1265 }
1266
1267 /* calculate clock rates using dividers in cinfo */
1268 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1269 struct dsi_clock_info *cinfo)
1270 {
1271 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1272 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1273
1274 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1275 return -EINVAL;
1276
1277 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1278 return -EINVAL;
1279
1280 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1281 return -EINVAL;
1282
1283 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1284 return -EINVAL;
1285
1286 if (cinfo->use_sys_clk) {
1287 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1288 /* XXX it is unclear if highfreq should be used
1289 * with DSS_SYS_CLK source also */
1290 cinfo->highfreq = 0;
1291 } else {
1292 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1293
1294 if (cinfo->clkin < 32000000)
1295 cinfo->highfreq = 0;
1296 else
1297 cinfo->highfreq = 1;
1298 }
1299
1300 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1301
1302 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1303 return -EINVAL;
1304
1305 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1306
1307 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1308 return -EINVAL;
1309
1310 if (cinfo->regm_dispc > 0)
1311 cinfo->dsi_pll_hsdiv_dispc_clk =
1312 cinfo->clkin4ddr / cinfo->regm_dispc;
1313 else
1314 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1315
1316 if (cinfo->regm_dsi > 0)
1317 cinfo->dsi_pll_hsdiv_dsi_clk =
1318 cinfo->clkin4ddr / cinfo->regm_dsi;
1319 else
1320 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1321
1322 return 0;
1323 }
1324
1325 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1326 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1327 struct dispc_clock_info *dispc_cinfo)
1328 {
1329 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1330 struct dsi_clock_info cur, best;
1331 struct dispc_clock_info best_dispc;
1332 int min_fck_per_pck;
1333 int match = 0;
1334 unsigned long dss_sys_clk, max_dss_fck;
1335
1336 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1337
1338 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1339
1340 if (req_pck == dsi->cache_req_pck &&
1341 dsi->cache_cinfo.clkin == dss_sys_clk) {
1342 DSSDBG("DSI clock info found from cache\n");
1343 *dsi_cinfo = dsi->cache_cinfo;
1344 dispc_find_clk_divs(is_tft, req_pck,
1345 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1346 return 0;
1347 }
1348
1349 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1350
1351 if (min_fck_per_pck &&
1352 req_pck * min_fck_per_pck > max_dss_fck) {
1353 DSSERR("Requested pixel clock not possible with the current "
1354 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1355 "the constraint off.\n");
1356 min_fck_per_pck = 0;
1357 }
1358
1359 DSSDBG("dsi_pll_calc\n");
1360
1361 retry:
1362 memset(&best, 0, sizeof(best));
1363 memset(&best_dispc, 0, sizeof(best_dispc));
1364
1365 memset(&cur, 0, sizeof(cur));
1366 cur.clkin = dss_sys_clk;
1367 cur.use_sys_clk = 1;
1368 cur.highfreq = 0;
1369
1370 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1371 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1372 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1373 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1374 if (cur.highfreq == 0)
1375 cur.fint = cur.clkin / cur.regn;
1376 else
1377 cur.fint = cur.clkin / (2 * cur.regn);
1378
1379 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1380 continue;
1381
1382 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1383 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1384 unsigned long a, b;
1385
1386 a = 2 * cur.regm * (cur.clkin/1000);
1387 b = cur.regn * (cur.highfreq + 1);
1388 cur.clkin4ddr = a / b * 1000;
1389
1390 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1391 break;
1392
1393 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1394 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1395 for (cur.regm_dispc = 1; cur.regm_dispc <
1396 dsi->regm_dispc_max; ++cur.regm_dispc) {
1397 struct dispc_clock_info cur_dispc;
1398 cur.dsi_pll_hsdiv_dispc_clk =
1399 cur.clkin4ddr / cur.regm_dispc;
1400
1401 /* this will narrow down the search a bit,
1402 * but still give pixclocks below what was
1403 * requested */
1404 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1405 break;
1406
1407 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1408 continue;
1409
1410 if (min_fck_per_pck &&
1411 cur.dsi_pll_hsdiv_dispc_clk <
1412 req_pck * min_fck_per_pck)
1413 continue;
1414
1415 match = 1;
1416
1417 dispc_find_clk_divs(is_tft, req_pck,
1418 cur.dsi_pll_hsdiv_dispc_clk,
1419 &cur_dispc);
1420
1421 if (abs(cur_dispc.pck - req_pck) <
1422 abs(best_dispc.pck - req_pck)) {
1423 best = cur;
1424 best_dispc = cur_dispc;
1425
1426 if (cur_dispc.pck == req_pck)
1427 goto found;
1428 }
1429 }
1430 }
1431 }
1432 found:
1433 if (!match) {
1434 if (min_fck_per_pck) {
1435 DSSERR("Could not find suitable clock settings.\n"
1436 "Turning FCK/PCK constraint off and"
1437 "trying again.\n");
1438 min_fck_per_pck = 0;
1439 goto retry;
1440 }
1441
1442 DSSERR("Could not find suitable clock settings.\n");
1443
1444 return -EINVAL;
1445 }
1446
1447 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1448 best.regm_dsi = 0;
1449 best.dsi_pll_hsdiv_dsi_clk = 0;
1450
1451 if (dsi_cinfo)
1452 *dsi_cinfo = best;
1453 if (dispc_cinfo)
1454 *dispc_cinfo = best_dispc;
1455
1456 dsi->cache_req_pck = req_pck;
1457 dsi->cache_clk_freq = 0;
1458 dsi->cache_cinfo = best;
1459
1460 return 0;
1461 }
1462
1463 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1464 struct dsi_clock_info *cinfo)
1465 {
1466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1467 int r = 0;
1468 u32 l;
1469 int f = 0;
1470 u8 regn_start, regn_end, regm_start, regm_end;
1471 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1472
1473 DSSDBGF();
1474
1475 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1476 dsi->current_cinfo.highfreq = cinfo->highfreq;
1477
1478 dsi->current_cinfo.fint = cinfo->fint;
1479 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1480 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1481 cinfo->dsi_pll_hsdiv_dispc_clk;
1482 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1483 cinfo->dsi_pll_hsdiv_dsi_clk;
1484
1485 dsi->current_cinfo.regn = cinfo->regn;
1486 dsi->current_cinfo.regm = cinfo->regm;
1487 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1488 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1489
1490 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1491
1492 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1493 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1494 cinfo->clkin,
1495 cinfo->highfreq);
1496
1497 /* DSIPHY == CLKIN4DDR */
1498 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1499 cinfo->regm,
1500 cinfo->regn,
1501 cinfo->clkin,
1502 cinfo->highfreq + 1,
1503 cinfo->clkin4ddr);
1504
1505 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1506 cinfo->clkin4ddr / 1000 / 1000 / 2);
1507
1508 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1509
1510 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1511 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1512 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1513 cinfo->dsi_pll_hsdiv_dispc_clk);
1514 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1515 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1516 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1517 cinfo->dsi_pll_hsdiv_dsi_clk);
1518
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1520 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1521 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1522 &regm_dispc_end);
1523 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1524 &regm_dsi_end);
1525
1526 /* DSI_PLL_AUTOMODE = manual */
1527 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1528
1529 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1530 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1531 /* DSI_PLL_REGN */
1532 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1533 /* DSI_PLL_REGM */
1534 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1535 /* DSI_CLOCK_DIV */
1536 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1537 regm_dispc_start, regm_dispc_end);
1538 /* DSIPROTO_CLOCK_DIV */
1539 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1540 regm_dsi_start, regm_dsi_end);
1541 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1542
1543 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1544
1545 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1546 f = cinfo->fint < 1000000 ? 0x3 :
1547 cinfo->fint < 1250000 ? 0x4 :
1548 cinfo->fint < 1500000 ? 0x5 :
1549 cinfo->fint < 1750000 ? 0x6 :
1550 0x7;
1551 }
1552
1553 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1554
1555 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1556 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1557 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1558 11, 11); /* DSI_PLL_CLKSEL */
1559 l = FLD_MOD(l, cinfo->highfreq,
1560 12, 12); /* DSI_PLL_HIGHFREQ */
1561 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1562 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1563 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1564 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1565
1566 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1567
1568 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1569 DSSERR("dsi pll go bit not going down.\n");
1570 r = -EIO;
1571 goto err;
1572 }
1573
1574 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1575 DSSERR("cannot lock PLL\n");
1576 r = -EIO;
1577 goto err;
1578 }
1579
1580 dsi->pll_locked = 1;
1581
1582 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1583 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1584 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1585 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1586 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1587 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1588 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1589 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1590 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1591 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1592 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1593 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1594 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1595 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1596 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1597 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1598
1599 DSSDBG("PLL config done\n");
1600 err:
1601 return r;
1602 }
1603
1604 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1605 bool enable_hsdiv)
1606 {
1607 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1608 int r = 0;
1609 enum dsi_pll_power_state pwstate;
1610
1611 DSSDBG("PLL init\n");
1612
1613 if (dsi->vdds_dsi_reg == NULL) {
1614 struct regulator *vdds_dsi;
1615
1616 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1617
1618 if (IS_ERR(vdds_dsi)) {
1619 DSSERR("can't get VDDS_DSI regulator\n");
1620 return PTR_ERR(vdds_dsi);
1621 }
1622
1623 dsi->vdds_dsi_reg = vdds_dsi;
1624 }
1625
1626 dsi_enable_pll_clock(dsidev, 1);
1627 /*
1628 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1629 */
1630 dsi_enable_scp_clk(dsidev);
1631
1632 if (!dsi->vdds_dsi_enabled) {
1633 r = regulator_enable(dsi->vdds_dsi_reg);
1634 if (r)
1635 goto err0;
1636 dsi->vdds_dsi_enabled = true;
1637 }
1638
1639 /* XXX PLL does not come out of reset without this... */
1640 dispc_pck_free_enable(1);
1641
1642 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1643 DSSERR("PLL not coming out of reset.\n");
1644 r = -ENODEV;
1645 dispc_pck_free_enable(0);
1646 goto err1;
1647 }
1648
1649 /* XXX ... but if left on, we get problems when planes do not
1650 * fill the whole display. No idea about this */
1651 dispc_pck_free_enable(0);
1652
1653 if (enable_hsclk && enable_hsdiv)
1654 pwstate = DSI_PLL_POWER_ON_ALL;
1655 else if (enable_hsclk)
1656 pwstate = DSI_PLL_POWER_ON_HSCLK;
1657 else if (enable_hsdiv)
1658 pwstate = DSI_PLL_POWER_ON_DIV;
1659 else
1660 pwstate = DSI_PLL_POWER_OFF;
1661
1662 r = dsi_pll_power(dsidev, pwstate);
1663
1664 if (r)
1665 goto err1;
1666
1667 DSSDBG("PLL init done\n");
1668
1669 return 0;
1670 err1:
1671 if (dsi->vdds_dsi_enabled) {
1672 regulator_disable(dsi->vdds_dsi_reg);
1673 dsi->vdds_dsi_enabled = false;
1674 }
1675 err0:
1676 dsi_disable_scp_clk(dsidev);
1677 dsi_enable_pll_clock(dsidev, 0);
1678 return r;
1679 }
1680
1681 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1682 {
1683 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1684
1685 dsi->pll_locked = 0;
1686 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1687 if (disconnect_lanes) {
1688 WARN_ON(!dsi->vdds_dsi_enabled);
1689 regulator_disable(dsi->vdds_dsi_reg);
1690 dsi->vdds_dsi_enabled = false;
1691 }
1692
1693 dsi_disable_scp_clk(dsidev);
1694 dsi_enable_pll_clock(dsidev, 0);
1695
1696 DSSDBG("PLL uninit done\n");
1697 }
1698
1699 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1700 struct seq_file *s)
1701 {
1702 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1703 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1704 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1705 int dsi_module = dsi_get_dsidev_id(dsidev);
1706
1707 dispc_clk_src = dss_get_dispc_clk_source();
1708 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1709
1710 if (dsi_runtime_get(dsidev))
1711 return;
1712
1713 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1714
1715 seq_printf(s, "dsi pll source = %s\n",
1716 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1717
1718 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1719
1720 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1721 cinfo->clkin4ddr, cinfo->regm);
1722
1723 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1724 dss_get_generic_clk_source_name(dispc_clk_src),
1725 dss_feat_get_clk_source_name(dispc_clk_src),
1726 cinfo->dsi_pll_hsdiv_dispc_clk,
1727 cinfo->regm_dispc,
1728 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1729 "off" : "on");
1730
1731 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1732 dss_get_generic_clk_source_name(dsi_clk_src),
1733 dss_feat_get_clk_source_name(dsi_clk_src),
1734 cinfo->dsi_pll_hsdiv_dsi_clk,
1735 cinfo->regm_dsi,
1736 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1737 "off" : "on");
1738
1739 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1740
1741 seq_printf(s, "dsi fclk source = %s (%s)\n",
1742 dss_get_generic_clk_source_name(dsi_clk_src),
1743 dss_feat_get_clk_source_name(dsi_clk_src));
1744
1745 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1746
1747 seq_printf(s, "DDR_CLK\t\t%lu\n",
1748 cinfo->clkin4ddr / 4);
1749
1750 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1751
1752 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1753
1754 dsi_runtime_put(dsidev);
1755 }
1756
1757 void dsi_dump_clocks(struct seq_file *s)
1758 {
1759 struct platform_device *dsidev;
1760 int i;
1761
1762 for (i = 0; i < MAX_NUM_DSI; i++) {
1763 dsidev = dsi_get_dsidev_from_id(i);
1764 if (dsidev)
1765 dsi_dump_dsidev_clocks(dsidev, s);
1766 }
1767 }
1768
1769 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1770 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1771 struct seq_file *s)
1772 {
1773 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1774 unsigned long flags;
1775 struct dsi_irq_stats stats;
1776 int dsi_module = dsi_get_dsidev_id(dsidev);
1777
1778 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1779
1780 stats = dsi->irq_stats;
1781 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1782 dsi->irq_stats.last_reset = jiffies;
1783
1784 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1785
1786 seq_printf(s, "period %u ms\n",
1787 jiffies_to_msecs(jiffies - stats.last_reset));
1788
1789 seq_printf(s, "irqs %d\n", stats.irq_count);
1790 #define PIS(x) \
1791 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1792
1793 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1794 PIS(VC0);
1795 PIS(VC1);
1796 PIS(VC2);
1797 PIS(VC3);
1798 PIS(WAKEUP);
1799 PIS(RESYNC);
1800 PIS(PLL_LOCK);
1801 PIS(PLL_UNLOCK);
1802 PIS(PLL_RECALL);
1803 PIS(COMPLEXIO_ERR);
1804 PIS(HS_TX_TIMEOUT);
1805 PIS(LP_RX_TIMEOUT);
1806 PIS(TE_TRIGGER);
1807 PIS(ACK_TRIGGER);
1808 PIS(SYNC_LOST);
1809 PIS(LDO_POWER_GOOD);
1810 PIS(TA_TIMEOUT);
1811 #undef PIS
1812
1813 #define PIS(x) \
1814 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1815 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1816 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1817 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1818 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1819
1820 seq_printf(s, "-- VC interrupts --\n");
1821 PIS(CS);
1822 PIS(ECC_CORR);
1823 PIS(PACKET_SENT);
1824 PIS(FIFO_TX_OVF);
1825 PIS(FIFO_RX_OVF);
1826 PIS(BTA);
1827 PIS(ECC_NO_CORR);
1828 PIS(FIFO_TX_UDF);
1829 PIS(PP_BUSY_CHANGE);
1830 #undef PIS
1831
1832 #define PIS(x) \
1833 seq_printf(s, "%-20s %10d\n", #x, \
1834 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1835
1836 seq_printf(s, "-- CIO interrupts --\n");
1837 PIS(ERRSYNCESC1);
1838 PIS(ERRSYNCESC2);
1839 PIS(ERRSYNCESC3);
1840 PIS(ERRESC1);
1841 PIS(ERRESC2);
1842 PIS(ERRESC3);
1843 PIS(ERRCONTROL1);
1844 PIS(ERRCONTROL2);
1845 PIS(ERRCONTROL3);
1846 PIS(STATEULPS1);
1847 PIS(STATEULPS2);
1848 PIS(STATEULPS3);
1849 PIS(ERRCONTENTIONLP0_1);
1850 PIS(ERRCONTENTIONLP1_1);
1851 PIS(ERRCONTENTIONLP0_2);
1852 PIS(ERRCONTENTIONLP1_2);
1853 PIS(ERRCONTENTIONLP0_3);
1854 PIS(ERRCONTENTIONLP1_3);
1855 PIS(ULPSACTIVENOT_ALL0);
1856 PIS(ULPSACTIVENOT_ALL1);
1857 #undef PIS
1858 }
1859
1860 static void dsi1_dump_irqs(struct seq_file *s)
1861 {
1862 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1863
1864 dsi_dump_dsidev_irqs(dsidev, s);
1865 }
1866
1867 static void dsi2_dump_irqs(struct seq_file *s)
1868 {
1869 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1870
1871 dsi_dump_dsidev_irqs(dsidev, s);
1872 }
1873
1874 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1875 const struct file_operations *debug_fops)
1876 {
1877 struct platform_device *dsidev;
1878
1879 dsidev = dsi_get_dsidev_from_id(0);
1880 if (dsidev)
1881 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1882 &dsi1_dump_irqs, debug_fops);
1883
1884 dsidev = dsi_get_dsidev_from_id(1);
1885 if (dsidev)
1886 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1887 &dsi2_dump_irqs, debug_fops);
1888 }
1889 #endif
1890
1891 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1892 struct seq_file *s)
1893 {
1894 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1895
1896 if (dsi_runtime_get(dsidev))
1897 return;
1898 dsi_enable_scp_clk(dsidev);
1899
1900 DUMPREG(DSI_REVISION);
1901 DUMPREG(DSI_SYSCONFIG);
1902 DUMPREG(DSI_SYSSTATUS);
1903 DUMPREG(DSI_IRQSTATUS);
1904 DUMPREG(DSI_IRQENABLE);
1905 DUMPREG(DSI_CTRL);
1906 DUMPREG(DSI_COMPLEXIO_CFG1);
1907 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1908 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1909 DUMPREG(DSI_CLK_CTRL);
1910 DUMPREG(DSI_TIMING1);
1911 DUMPREG(DSI_TIMING2);
1912 DUMPREG(DSI_VM_TIMING1);
1913 DUMPREG(DSI_VM_TIMING2);
1914 DUMPREG(DSI_VM_TIMING3);
1915 DUMPREG(DSI_CLK_TIMING);
1916 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1917 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1918 DUMPREG(DSI_COMPLEXIO_CFG2);
1919 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1920 DUMPREG(DSI_VM_TIMING4);
1921 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1922 DUMPREG(DSI_VM_TIMING5);
1923 DUMPREG(DSI_VM_TIMING6);
1924 DUMPREG(DSI_VM_TIMING7);
1925 DUMPREG(DSI_STOPCLK_TIMING);
1926
1927 DUMPREG(DSI_VC_CTRL(0));
1928 DUMPREG(DSI_VC_TE(0));
1929 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1930 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1931 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1932 DUMPREG(DSI_VC_IRQSTATUS(0));
1933 DUMPREG(DSI_VC_IRQENABLE(0));
1934
1935 DUMPREG(DSI_VC_CTRL(1));
1936 DUMPREG(DSI_VC_TE(1));
1937 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1938 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1939 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1940 DUMPREG(DSI_VC_IRQSTATUS(1));
1941 DUMPREG(DSI_VC_IRQENABLE(1));
1942
1943 DUMPREG(DSI_VC_CTRL(2));
1944 DUMPREG(DSI_VC_TE(2));
1945 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1946 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1947 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1948 DUMPREG(DSI_VC_IRQSTATUS(2));
1949 DUMPREG(DSI_VC_IRQENABLE(2));
1950
1951 DUMPREG(DSI_VC_CTRL(3));
1952 DUMPREG(DSI_VC_TE(3));
1953 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1954 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1955 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1956 DUMPREG(DSI_VC_IRQSTATUS(3));
1957 DUMPREG(DSI_VC_IRQENABLE(3));
1958
1959 DUMPREG(DSI_DSIPHY_CFG0);
1960 DUMPREG(DSI_DSIPHY_CFG1);
1961 DUMPREG(DSI_DSIPHY_CFG2);
1962 DUMPREG(DSI_DSIPHY_CFG5);
1963
1964 DUMPREG(DSI_PLL_CONTROL);
1965 DUMPREG(DSI_PLL_STATUS);
1966 DUMPREG(DSI_PLL_GO);
1967 DUMPREG(DSI_PLL_CONFIGURATION1);
1968 DUMPREG(DSI_PLL_CONFIGURATION2);
1969
1970 dsi_disable_scp_clk(dsidev);
1971 dsi_runtime_put(dsidev);
1972 #undef DUMPREG
1973 }
1974
1975 static void dsi1_dump_regs(struct seq_file *s)
1976 {
1977 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1978
1979 dsi_dump_dsidev_regs(dsidev, s);
1980 }
1981
1982 static void dsi2_dump_regs(struct seq_file *s)
1983 {
1984 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1985
1986 dsi_dump_dsidev_regs(dsidev, s);
1987 }
1988
1989 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1990 const struct file_operations *debug_fops)
1991 {
1992 struct platform_device *dsidev;
1993
1994 dsidev = dsi_get_dsidev_from_id(0);
1995 if (dsidev)
1996 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1997 &dsi1_dump_regs, debug_fops);
1998
1999 dsidev = dsi_get_dsidev_from_id(1);
2000 if (dsidev)
2001 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2002 &dsi2_dump_regs, debug_fops);
2003 }
2004 enum dsi_cio_power_state {
2005 DSI_COMPLEXIO_POWER_OFF = 0x0,
2006 DSI_COMPLEXIO_POWER_ON = 0x1,
2007 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2008 };
2009
2010 static int dsi_cio_power(struct platform_device *dsidev,
2011 enum dsi_cio_power_state state)
2012 {
2013 int t = 0;
2014
2015 /* PWR_CMD */
2016 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2017
2018 /* PWR_STATUS */
2019 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2020 26, 25) != state) {
2021 if (++t > 1000) {
2022 DSSERR("failed to set complexio power state to "
2023 "%d\n", state);
2024 return -ENODEV;
2025 }
2026 udelay(1);
2027 }
2028
2029 return 0;
2030 }
2031
2032 /* Number of data lanes present on DSI interface */
2033 static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
2034 {
2035 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
2036 * of data lanes as 2 by default */
2037 if (dss_has_feature(FEAT_DSI_GNQ))
2038 return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
2039 else
2040 return 2;
2041 }
2042
2043 /* Number of data lanes used by the dss device */
2044 static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
2045 {
2046 int num_data_lanes = 0;
2047
2048 if (dssdev->phy.dsi.data1_lane != 0)
2049 num_data_lanes++;
2050 if (dssdev->phy.dsi.data2_lane != 0)
2051 num_data_lanes++;
2052 if (dssdev->phy.dsi.data3_lane != 0)
2053 num_data_lanes++;
2054 if (dssdev->phy.dsi.data4_lane != 0)
2055 num_data_lanes++;
2056
2057 return num_data_lanes;
2058 }
2059
2060 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2061 {
2062 int val;
2063
2064 /* line buffer on OMAP3 is 1024 x 24bits */
2065 /* XXX: for some reason using full buffer size causes
2066 * considerable TX slowdown with update sizes that fill the
2067 * whole buffer */
2068 if (!dss_has_feature(FEAT_DSI_GNQ))
2069 return 1023 * 3;
2070
2071 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2072
2073 switch (val) {
2074 case 1:
2075 return 512 * 3; /* 512x24 bits */
2076 case 2:
2077 return 682 * 3; /* 682x24 bits */
2078 case 3:
2079 return 853 * 3; /* 853x24 bits */
2080 case 4:
2081 return 1024 * 3; /* 1024x24 bits */
2082 case 5:
2083 return 1194 * 3; /* 1194x24 bits */
2084 case 6:
2085 return 1365 * 3; /* 1365x24 bits */
2086 default:
2087 BUG();
2088 }
2089 }
2090
2091 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
2092 {
2093 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2094 u32 r;
2095 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2096
2097 int clk_lane = dssdev->phy.dsi.clk_lane;
2098 int data1_lane = dssdev->phy.dsi.data1_lane;
2099 int data2_lane = dssdev->phy.dsi.data2_lane;
2100 int clk_pol = dssdev->phy.dsi.clk_pol;
2101 int data1_pol = dssdev->phy.dsi.data1_pol;
2102 int data2_pol = dssdev->phy.dsi.data2_pol;
2103
2104 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2105 r = FLD_MOD(r, clk_lane, 2, 0);
2106 r = FLD_MOD(r, clk_pol, 3, 3);
2107 r = FLD_MOD(r, data1_lane, 6, 4);
2108 r = FLD_MOD(r, data1_pol, 7, 7);
2109 r = FLD_MOD(r, data2_lane, 10, 8);
2110 r = FLD_MOD(r, data2_pol, 11, 11);
2111 if (num_data_lanes_dssdev > 2) {
2112 int data3_lane = dssdev->phy.dsi.data3_lane;
2113 int data3_pol = dssdev->phy.dsi.data3_pol;
2114
2115 r = FLD_MOD(r, data3_lane, 14, 12);
2116 r = FLD_MOD(r, data3_pol, 15, 15);
2117 }
2118 if (num_data_lanes_dssdev > 3) {
2119 int data4_lane = dssdev->phy.dsi.data4_lane;
2120 int data4_pol = dssdev->phy.dsi.data4_pol;
2121
2122 r = FLD_MOD(r, data4_lane, 18, 16);
2123 r = FLD_MOD(r, data4_pol, 19, 19);
2124 }
2125 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2126
2127 /* The configuration of the DSI complex I/O (number of data lanes,
2128 position, differential order) should not be changed while
2129 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
2130 the hardware to take into account a new configuration of the complex
2131 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
2132 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
2133 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
2134 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
2135 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
2136 DSI complex I/O configuration is unknown. */
2137
2138 /*
2139 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2140 REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
2141 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2142 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2143 */
2144 }
2145
2146 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2147 {
2148 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2149
2150 /* convert time in ns to ddr ticks, rounding up */
2151 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2152 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2153 }
2154
2155 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2156 {
2157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2158
2159 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2160 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2161 }
2162
2163 static void dsi_cio_timings(struct platform_device *dsidev)
2164 {
2165 u32 r;
2166 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2167 u32 tlpx_half, tclk_trail, tclk_zero;
2168 u32 tclk_prepare;
2169
2170 /* calculate timings */
2171
2172 /* 1 * DDR_CLK = 2 * UI */
2173
2174 /* min 40ns + 4*UI max 85ns + 6*UI */
2175 ths_prepare = ns2ddr(dsidev, 70) + 2;
2176
2177 /* min 145ns + 10*UI */
2178 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2179
2180 /* min max(8*UI, 60ns+4*UI) */
2181 ths_trail = ns2ddr(dsidev, 60) + 5;
2182
2183 /* min 100ns */
2184 ths_exit = ns2ddr(dsidev, 145);
2185
2186 /* tlpx min 50n */
2187 tlpx_half = ns2ddr(dsidev, 25);
2188
2189 /* min 60ns */
2190 tclk_trail = ns2ddr(dsidev, 60) + 2;
2191
2192 /* min 38ns, max 95ns */
2193 tclk_prepare = ns2ddr(dsidev, 65);
2194
2195 /* min tclk-prepare + tclk-zero = 300ns */
2196 tclk_zero = ns2ddr(dsidev, 260);
2197
2198 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2199 ths_prepare, ddr2ns(dsidev, ths_prepare),
2200 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2201 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2202 ths_trail, ddr2ns(dsidev, ths_trail),
2203 ths_exit, ddr2ns(dsidev, ths_exit));
2204
2205 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2206 "tclk_zero %u (%uns)\n",
2207 tlpx_half, ddr2ns(dsidev, tlpx_half),
2208 tclk_trail, ddr2ns(dsidev, tclk_trail),
2209 tclk_zero, ddr2ns(dsidev, tclk_zero));
2210 DSSDBG("tclk_prepare %u (%uns)\n",
2211 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2212
2213 /* program timings */
2214
2215 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2216 r = FLD_MOD(r, ths_prepare, 31, 24);
2217 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2218 r = FLD_MOD(r, ths_trail, 15, 8);
2219 r = FLD_MOD(r, ths_exit, 7, 0);
2220 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2221
2222 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2223 r = FLD_MOD(r, tlpx_half, 22, 16);
2224 r = FLD_MOD(r, tclk_trail, 15, 8);
2225 r = FLD_MOD(r, tclk_zero, 7, 0);
2226 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2227
2228 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2229 r = FLD_MOD(r, tclk_prepare, 7, 0);
2230 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2231 }
2232
2233 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2234 enum dsi_lane lanes)
2235 {
2236 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2237 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2238 int clk_lane = dssdev->phy.dsi.clk_lane;
2239 int data1_lane = dssdev->phy.dsi.data1_lane;
2240 int data2_lane = dssdev->phy.dsi.data2_lane;
2241 int data3_lane = dssdev->phy.dsi.data3_lane;
2242 int data4_lane = dssdev->phy.dsi.data4_lane;
2243 int clk_pol = dssdev->phy.dsi.clk_pol;
2244 int data1_pol = dssdev->phy.dsi.data1_pol;
2245 int data2_pol = dssdev->phy.dsi.data2_pol;
2246 int data3_pol = dssdev->phy.dsi.data3_pol;
2247 int data4_pol = dssdev->phy.dsi.data4_pol;
2248
2249 u32 l = 0;
2250 u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2251
2252 if (lanes & DSI_CLK_P)
2253 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
2254 if (lanes & DSI_CLK_N)
2255 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
2256
2257 if (lanes & DSI_DATA1_P)
2258 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
2259 if (lanes & DSI_DATA1_N)
2260 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
2261
2262 if (lanes & DSI_DATA2_P)
2263 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
2264 if (lanes & DSI_DATA2_N)
2265 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
2266
2267 if (lanes & DSI_DATA3_P)
2268 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
2269 if (lanes & DSI_DATA3_N)
2270 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
2271
2272 if (lanes & DSI_DATA4_P)
2273 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
2274 if (lanes & DSI_DATA4_N)
2275 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2276 /*
2277 * Bits in REGLPTXSCPDAT4TO0DXDY:
2278 * 17: DY0 18: DX0
2279 * 19: DY1 20: DX1
2280 * 21: DY2 22: DX2
2281 * 23: DY3 24: DX3
2282 * 25: DY4 26: DX4
2283 */
2284
2285 /* Set the lane override configuration */
2286
2287 /* REGLPTXSCPDAT4TO0DXDY */
2288 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2289
2290 /* Enable lane override */
2291
2292 /* ENLPTXSCPDAT */
2293 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2294 }
2295
2296 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2297 {
2298 /* Disable lane override */
2299 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2300 /* Reset the lane override configuration */
2301 /* REGLPTXSCPDAT4TO0DXDY */
2302 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2303 }
2304
2305 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2306 {
2307 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2308 int t;
2309 int bits[3];
2310 bool in_use[3];
2311
2312 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2313 bits[0] = 28;
2314 bits[1] = 27;
2315 bits[2] = 26;
2316 } else {
2317 bits[0] = 24;
2318 bits[1] = 25;
2319 bits[2] = 26;
2320 }
2321
2322 in_use[0] = false;
2323 in_use[1] = false;
2324 in_use[2] = false;
2325
2326 if (dssdev->phy.dsi.clk_lane != 0)
2327 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2328 if (dssdev->phy.dsi.data1_lane != 0)
2329 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2330 if (dssdev->phy.dsi.data2_lane != 0)
2331 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2332
2333 t = 100000;
2334 while (true) {
2335 u32 l;
2336 int i;
2337 int ok;
2338
2339 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2340
2341 ok = 0;
2342 for (i = 0; i < 3; ++i) {
2343 if (!in_use[i] || (l & (1 << bits[i])))
2344 ok++;
2345 }
2346
2347 if (ok == 3)
2348 break;
2349
2350 if (--t == 0) {
2351 for (i = 0; i < 3; ++i) {
2352 if (!in_use[i] || (l & (1 << bits[i])))
2353 continue;
2354
2355 DSSERR("CIO TXCLKESC%d domain not coming " \
2356 "out of reset\n", i);
2357 }
2358 return -EIO;
2359 }
2360 }
2361
2362 return 0;
2363 }
2364
2365 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2366 {
2367 unsigned lanes = 0;
2368
2369 if (dssdev->phy.dsi.clk_lane != 0)
2370 lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1);
2371 if (dssdev->phy.dsi.data1_lane != 0)
2372 lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1);
2373 if (dssdev->phy.dsi.data2_lane != 0)
2374 lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1);
2375 if (dssdev->phy.dsi.data3_lane != 0)
2376 lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1);
2377 if (dssdev->phy.dsi.data4_lane != 0)
2378 lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1);
2379
2380 return lanes;
2381 }
2382
2383 static int dsi_cio_init(struct omap_dss_device *dssdev)
2384 {
2385 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2387 int r;
2388 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2389 u32 l;
2390
2391 DSSDBGF();
2392
2393 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2394 if (r)
2395 return r;
2396
2397 dsi_enable_scp_clk(dsidev);
2398
2399 /* A dummy read using the SCP interface to any DSIPHY register is
2400 * required after DSIPHY reset to complete the reset of the DSI complex
2401 * I/O. */
2402 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2403
2404 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2405 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2406 r = -EIO;
2407 goto err_scp_clk_dom;
2408 }
2409
2410 dsi_set_lane_config(dssdev);
2411
2412 /* set TX STOP MODE timer to maximum for this operation */
2413 l = dsi_read_reg(dsidev, DSI_TIMING1);
2414 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2415 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2416 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2417 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2418 dsi_write_reg(dsidev, DSI_TIMING1, l);
2419
2420 if (dsi->ulps_enabled) {
2421 u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
2422
2423 DSSDBG("manual ulps exit\n");
2424
2425 /* ULPS is exited by Mark-1 state for 1ms, followed by
2426 * stop state. DSS HW cannot do this via the normal
2427 * ULPS exit sequence, as after reset the DSS HW thinks
2428 * that we are not in ULPS mode, and refuses to send the
2429 * sequence. So we need to send the ULPS exit sequence
2430 * manually.
2431 */
2432
2433 if (num_data_lanes_dssdev > 2)
2434 lane_mask |= DSI_DATA3_P;
2435
2436 if (num_data_lanes_dssdev > 3)
2437 lane_mask |= DSI_DATA4_P;
2438
2439 dsi_cio_enable_lane_override(dssdev, lane_mask);
2440 }
2441
2442 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2443 if (r)
2444 goto err_cio_pwr;
2445
2446 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2447 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2448 r = -ENODEV;
2449 goto err_cio_pwr_dom;
2450 }
2451
2452 dsi_if_enable(dsidev, true);
2453 dsi_if_enable(dsidev, false);
2454 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2455
2456 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2457 if (r)
2458 goto err_tx_clk_esc_rst;
2459
2460 if (dsi->ulps_enabled) {
2461 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2462 ktime_t wait = ns_to_ktime(1000 * 1000);
2463 set_current_state(TASK_UNINTERRUPTIBLE);
2464 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2465
2466 /* Disable the override. The lanes should be set to Mark-11
2467 * state by the HW */
2468 dsi_cio_disable_lane_override(dsidev);
2469 }
2470
2471 /* FORCE_TX_STOP_MODE_IO */
2472 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2473
2474 dsi_cio_timings(dsidev);
2475
2476 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2477 /* DDR_CLK_ALWAYS_ON */
2478 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2479 dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2480 }
2481
2482 dsi->ulps_enabled = false;
2483
2484 DSSDBG("CIO init done\n");
2485
2486 return 0;
2487
2488 err_tx_clk_esc_rst:
2489 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2490 err_cio_pwr_dom:
2491 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2492 err_cio_pwr:
2493 if (dsi->ulps_enabled)
2494 dsi_cio_disable_lane_override(dsidev);
2495 err_scp_clk_dom:
2496 dsi_disable_scp_clk(dsidev);
2497 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2498 return r;
2499 }
2500
2501 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2502 {
2503 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2504 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2505
2506 /* DDR_CLK_ALWAYS_ON */
2507 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2508
2509 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2510 dsi_disable_scp_clk(dsidev);
2511 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2512 }
2513
2514 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2515 enum fifo_size size1, enum fifo_size size2,
2516 enum fifo_size size3, enum fifo_size size4)
2517 {
2518 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2519 u32 r = 0;
2520 int add = 0;
2521 int i;
2522
2523 dsi->vc[0].fifo_size = size1;
2524 dsi->vc[1].fifo_size = size2;
2525 dsi->vc[2].fifo_size = size3;
2526 dsi->vc[3].fifo_size = size4;
2527
2528 for (i = 0; i < 4; i++) {
2529 u8 v;
2530 int size = dsi->vc[i].fifo_size;
2531
2532 if (add + size > 4) {
2533 DSSERR("Illegal FIFO configuration\n");
2534 BUG();
2535 }
2536
2537 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2538 r |= v << (8 * i);
2539 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2540 add += size;
2541 }
2542
2543 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2544 }
2545
2546 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2547 enum fifo_size size1, enum fifo_size size2,
2548 enum fifo_size size3, enum fifo_size size4)
2549 {
2550 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2551 u32 r = 0;
2552 int add = 0;
2553 int i;
2554
2555 dsi->vc[0].fifo_size = size1;
2556 dsi->vc[1].fifo_size = size2;
2557 dsi->vc[2].fifo_size = size3;
2558 dsi->vc[3].fifo_size = size4;
2559
2560 for (i = 0; i < 4; i++) {
2561 u8 v;
2562 int size = dsi->vc[i].fifo_size;
2563
2564 if (add + size > 4) {
2565 DSSERR("Illegal FIFO configuration\n");
2566 BUG();
2567 }
2568
2569 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2570 r |= v << (8 * i);
2571 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2572 add += size;
2573 }
2574
2575 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2576 }
2577
2578 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2579 {
2580 u32 r;
2581
2582 r = dsi_read_reg(dsidev, DSI_TIMING1);
2583 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2584 dsi_write_reg(dsidev, DSI_TIMING1, r);
2585
2586 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2587 DSSERR("TX_STOP bit not going down\n");
2588 return -EIO;
2589 }
2590
2591 return 0;
2592 }
2593
2594 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2595 {
2596 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2597 }
2598
2599 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2600 {
2601 struct dsi_packet_sent_handler_data *vp_data =
2602 (struct dsi_packet_sent_handler_data *) data;
2603 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2604 const int channel = dsi->update_channel;
2605 u8 bit = dsi->te_enabled ? 30 : 31;
2606
2607 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2608 complete(vp_data->completion);
2609 }
2610
2611 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2612 {
2613 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2614 DECLARE_COMPLETION_ONSTACK(completion);
2615 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2616 int r = 0;
2617 u8 bit;
2618
2619 bit = dsi->te_enabled ? 30 : 31;
2620
2621 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2622 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2623 if (r)
2624 goto err0;
2625
2626 /* Wait for completion only if TE_EN/TE_START is still set */
2627 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2628 if (wait_for_completion_timeout(&completion,
2629 msecs_to_jiffies(10)) == 0) {
2630 DSSERR("Failed to complete previous frame transfer\n");
2631 r = -EIO;
2632 goto err1;
2633 }
2634 }
2635
2636 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2637 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2638
2639 return 0;
2640 err1:
2641 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2642 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2643 err0:
2644 return r;
2645 }
2646
2647 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2648 {
2649 struct dsi_packet_sent_handler_data *l4_data =
2650 (struct dsi_packet_sent_handler_data *) data;
2651 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2652 const int channel = dsi->update_channel;
2653
2654 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2655 complete(l4_data->completion);
2656 }
2657
2658 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2659 {
2660 DECLARE_COMPLETION_ONSTACK(completion);
2661 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2662 int r = 0;
2663
2664 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2665 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2666 if (r)
2667 goto err0;
2668
2669 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2670 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2671 if (wait_for_completion_timeout(&completion,
2672 msecs_to_jiffies(10)) == 0) {
2673 DSSERR("Failed to complete previous l4 transfer\n");
2674 r = -EIO;
2675 goto err1;
2676 }
2677 }
2678
2679 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2680 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2681
2682 return 0;
2683 err1:
2684 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2685 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2686 err0:
2687 return r;
2688 }
2689
2690 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2691 {
2692 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2693
2694 WARN_ON(!dsi_bus_is_locked(dsidev));
2695
2696 WARN_ON(in_interrupt());
2697
2698 if (!dsi_vc_is_enabled(dsidev, channel))
2699 return 0;
2700
2701 switch (dsi->vc[channel].source) {
2702 case DSI_VC_SOURCE_VP:
2703 return dsi_sync_vc_vp(dsidev, channel);
2704 case DSI_VC_SOURCE_L4:
2705 return dsi_sync_vc_l4(dsidev, channel);
2706 default:
2707 BUG();
2708 }
2709 }
2710
2711 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2712 bool enable)
2713 {
2714 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2715 channel, enable);
2716
2717 enable = enable ? 1 : 0;
2718
2719 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2720
2721 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2722 0, enable) != enable) {
2723 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2724 return -EIO;
2725 }
2726
2727 return 0;
2728 }
2729
2730 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2731 {
2732 u32 r;
2733
2734 DSSDBGF("%d", channel);
2735
2736 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2737
2738 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2739 DSSERR("VC(%d) busy when trying to configure it!\n",
2740 channel);
2741
2742 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2743 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2744 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2745 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2746 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2747 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2748 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2749 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2750 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2751
2752 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2753 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2754
2755 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2756 }
2757
2758 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2759 enum dsi_vc_source source)
2760 {
2761 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2762
2763 if (dsi->vc[channel].source == source)
2764 return 0;
2765
2766 DSSDBGF("%d", channel);
2767
2768 dsi_sync_vc(dsidev, channel);
2769
2770 dsi_vc_enable(dsidev, channel, 0);
2771
2772 /* VC_BUSY */
2773 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2774 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2775 return -EIO;
2776 }
2777
2778 /* SOURCE, 0 = L4, 1 = video port */
2779 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2780
2781 /* DCS_CMD_ENABLE */
2782 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2783 bool enable = source == DSI_VC_SOURCE_VP;
2784 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2785 }
2786
2787 dsi_vc_enable(dsidev, channel, 1);
2788
2789 dsi->vc[channel].source = source;
2790
2791 return 0;
2792 }
2793
2794 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2795 bool enable)
2796 {
2797 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2798
2799 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2800
2801 WARN_ON(!dsi_bus_is_locked(dsidev));
2802
2803 dsi_vc_enable(dsidev, channel, 0);
2804 dsi_if_enable(dsidev, 0);
2805
2806 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2807
2808 dsi_vc_enable(dsidev, channel, 1);
2809 dsi_if_enable(dsidev, 1);
2810
2811 dsi_force_tx_stop_mode_io(dsidev);
2812
2813 /* start the DDR clock by sending a NULL packet */
2814 if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2815 dsi_vc_send_null(dssdev, channel);
2816 }
2817 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2818
2819 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2820 {
2821 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2822 u32 val;
2823 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2824 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2825 (val >> 0) & 0xff,
2826 (val >> 8) & 0xff,
2827 (val >> 16) & 0xff,
2828 (val >> 24) & 0xff);
2829 }
2830 }
2831
2832 static void dsi_show_rx_ack_with_err(u16 err)
2833 {
2834 DSSERR("\tACK with ERROR (%#x):\n", err);
2835 if (err & (1 << 0))
2836 DSSERR("\t\tSoT Error\n");
2837 if (err & (1 << 1))
2838 DSSERR("\t\tSoT Sync Error\n");
2839 if (err & (1 << 2))
2840 DSSERR("\t\tEoT Sync Error\n");
2841 if (err & (1 << 3))
2842 DSSERR("\t\tEscape Mode Entry Command Error\n");
2843 if (err & (1 << 4))
2844 DSSERR("\t\tLP Transmit Sync Error\n");
2845 if (err & (1 << 5))
2846 DSSERR("\t\tHS Receive Timeout Error\n");
2847 if (err & (1 << 6))
2848 DSSERR("\t\tFalse Control Error\n");
2849 if (err & (1 << 7))
2850 DSSERR("\t\t(reserved7)\n");
2851 if (err & (1 << 8))
2852 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2853 if (err & (1 << 9))
2854 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2855 if (err & (1 << 10))
2856 DSSERR("\t\tChecksum Error\n");
2857 if (err & (1 << 11))
2858 DSSERR("\t\tData type not recognized\n");
2859 if (err & (1 << 12))
2860 DSSERR("\t\tInvalid VC ID\n");
2861 if (err & (1 << 13))
2862 DSSERR("\t\tInvalid Transmission Length\n");
2863 if (err & (1 << 14))
2864 DSSERR("\t\t(reserved14)\n");
2865 if (err & (1 << 15))
2866 DSSERR("\t\tDSI Protocol Violation\n");
2867 }
2868
2869 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2870 int channel)
2871 {
2872 /* RX_FIFO_NOT_EMPTY */
2873 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2874 u32 val;
2875 u8 dt;
2876 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2877 DSSERR("\trawval %#08x\n", val);
2878 dt = FLD_GET(val, 5, 0);
2879 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2880 u16 err = FLD_GET(val, 23, 8);
2881 dsi_show_rx_ack_with_err(err);
2882 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2883 DSSERR("\tDCS short response, 1 byte: %#x\n",
2884 FLD_GET(val, 23, 8));
2885 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2886 DSSERR("\tDCS short response, 2 byte: %#x\n",
2887 FLD_GET(val, 23, 8));
2888 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2889 DSSERR("\tDCS long response, len %d\n",
2890 FLD_GET(val, 23, 8));
2891 dsi_vc_flush_long_data(dsidev, channel);
2892 } else {
2893 DSSERR("\tunknown datatype 0x%02x\n", dt);
2894 }
2895 }
2896 return 0;
2897 }
2898
2899 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2900 {
2901 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2902
2903 if (dsi->debug_write || dsi->debug_read)
2904 DSSDBG("dsi_vc_send_bta %d\n", channel);
2905
2906 WARN_ON(!dsi_bus_is_locked(dsidev));
2907
2908 /* RX_FIFO_NOT_EMPTY */
2909 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2910 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2911 dsi_vc_flush_receive_data(dsidev, channel);
2912 }
2913
2914 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2915
2916 /* flush posted write */
2917 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2918
2919 return 0;
2920 }
2921
2922 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2923 {
2924 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2925 DECLARE_COMPLETION_ONSTACK(completion);
2926 int r = 0;
2927 u32 err;
2928
2929 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2930 &completion, DSI_VC_IRQ_BTA);
2931 if (r)
2932 goto err0;
2933
2934 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2935 DSI_IRQ_ERROR_MASK);
2936 if (r)
2937 goto err1;
2938
2939 r = dsi_vc_send_bta(dsidev, channel);
2940 if (r)
2941 goto err2;
2942
2943 if (wait_for_completion_timeout(&completion,
2944 msecs_to_jiffies(500)) == 0) {
2945 DSSERR("Failed to receive BTA\n");
2946 r = -EIO;
2947 goto err2;
2948 }
2949
2950 err = dsi_get_errors(dsidev);
2951 if (err) {
2952 DSSERR("Error while sending BTA: %x\n", err);
2953 r = -EIO;
2954 goto err2;
2955 }
2956 err2:
2957 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2958 DSI_IRQ_ERROR_MASK);
2959 err1:
2960 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2961 &completion, DSI_VC_IRQ_BTA);
2962 err0:
2963 return r;
2964 }
2965 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2966
2967 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2968 int channel, u8 data_type, u16 len, u8 ecc)
2969 {
2970 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2971 u32 val;
2972 u8 data_id;
2973
2974 WARN_ON(!dsi_bus_is_locked(dsidev));
2975
2976 data_id = data_type | dsi->vc[channel].vc_id << 6;
2977
2978 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2979 FLD_VAL(ecc, 31, 24);
2980
2981 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2982 }
2983
2984 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2985 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2986 {
2987 u32 val;
2988
2989 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2990
2991 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2992 b1, b2, b3, b4, val); */
2993
2994 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2995 }
2996
2997 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2998 u8 data_type, u8 *data, u16 len, u8 ecc)
2999 {
3000 /*u32 val; */
3001 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3002 int i;
3003 u8 *p;
3004 int r = 0;
3005 u8 b1, b2, b3, b4;
3006
3007 if (dsi->debug_write)
3008 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3009
3010 /* len + header */
3011 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3012 DSSERR("unable to send long packet: packet too long.\n");
3013 return -EINVAL;
3014 }
3015
3016 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3017
3018 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3019
3020 p = data;
3021 for (i = 0; i < len >> 2; i++) {
3022 if (dsi->debug_write)
3023 DSSDBG("\tsending full packet %d\n", i);
3024
3025 b1 = *p++;
3026 b2 = *p++;
3027 b3 = *p++;
3028 b4 = *p++;
3029
3030 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3031 }
3032
3033 i = len % 4;
3034 if (i) {
3035 b1 = 0; b2 = 0; b3 = 0;
3036
3037 if (dsi->debug_write)
3038 DSSDBG("\tsending remainder bytes %d\n", i);
3039
3040 switch (i) {
3041 case 3:
3042 b1 = *p++;
3043 b2 = *p++;
3044 b3 = *p++;
3045 break;
3046 case 2:
3047 b1 = *p++;
3048 b2 = *p++;
3049 break;
3050 case 1:
3051 b1 = *p++;
3052 break;
3053 }
3054
3055 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3056 }
3057
3058 return r;
3059 }
3060
3061 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3062 u8 data_type, u16 data, u8 ecc)
3063 {
3064 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3065 u32 r;
3066 u8 data_id;
3067
3068 WARN_ON(!dsi_bus_is_locked(dsidev));
3069
3070 if (dsi->debug_write)
3071 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3072 channel,
3073 data_type, data & 0xff, (data >> 8) & 0xff);
3074
3075 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3076
3077 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3078 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3079 return -EINVAL;
3080 }
3081
3082 data_id = data_type | dsi->vc[channel].vc_id << 6;
3083
3084 r = (data_id << 0) | (data << 8) | (ecc << 24);
3085
3086 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3087
3088 return 0;
3089 }
3090
3091 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3092 {
3093 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3094
3095 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3096 0, 0);
3097 }
3098 EXPORT_SYMBOL(dsi_vc_send_null);
3099
3100 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3101 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3102 {
3103 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3104 int r;
3105
3106 if (len == 0) {
3107 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3108 r = dsi_vc_send_short(dsidev, channel,
3109 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3110 } else if (len == 1) {
3111 r = dsi_vc_send_short(dsidev, channel,
3112 type == DSS_DSI_CONTENT_GENERIC ?
3113 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3114 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3115 } else if (len == 2) {
3116 r = dsi_vc_send_short(dsidev, channel,
3117 type == DSS_DSI_CONTENT_GENERIC ?
3118 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3119 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3120 data[0] | (data[1] << 8), 0);
3121 } else {
3122 r = dsi_vc_send_long(dsidev, channel,
3123 type == DSS_DSI_CONTENT_GENERIC ?
3124 MIPI_DSI_GENERIC_LONG_WRITE :
3125 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3126 }
3127
3128 return r;
3129 }
3130
3131 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3132 u8 *data, int len)
3133 {
3134 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3135 DSS_DSI_CONTENT_DCS);
3136 }
3137 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3138
3139 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3140 u8 *data, int len)
3141 {
3142 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3143 DSS_DSI_CONTENT_GENERIC);
3144 }
3145 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3146
3147 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3148 u8 *data, int len, enum dss_dsi_content_type type)
3149 {
3150 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3151 int r;
3152
3153 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3154 if (r)
3155 goto err;
3156
3157 r = dsi_vc_send_bta_sync(dssdev, channel);
3158 if (r)
3159 goto err;
3160
3161 /* RX_FIFO_NOT_EMPTY */
3162 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3163 DSSERR("rx fifo not empty after write, dumping data:\n");
3164 dsi_vc_flush_receive_data(dsidev, channel);
3165 r = -EIO;
3166 goto err;
3167 }
3168
3169 return 0;
3170 err:
3171 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3172 channel, data[0], len);
3173 return r;
3174 }
3175
3176 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3177 int len)
3178 {
3179 return dsi_vc_write_common(dssdev, channel, data, len,
3180 DSS_DSI_CONTENT_DCS);
3181 }
3182 EXPORT_SYMBOL(dsi_vc_dcs_write);
3183
3184 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3185 int len)
3186 {
3187 return dsi_vc_write_common(dssdev, channel, data, len,
3188 DSS_DSI_CONTENT_GENERIC);
3189 }
3190 EXPORT_SYMBOL(dsi_vc_generic_write);
3191
3192 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3193 {
3194 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3195 }
3196 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3197
3198 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3199 {
3200 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3201 }
3202 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3203
3204 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3205 u8 param)
3206 {
3207 u8 buf[2];
3208 buf[0] = dcs_cmd;
3209 buf[1] = param;
3210 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3211 }
3212 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3213
3214 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3215 u8 param)
3216 {
3217 return dsi_vc_generic_write(dssdev, channel, &param, 1);
3218 }
3219 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3220
3221 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3222 u8 param1, u8 param2)
3223 {
3224 u8 buf[2];
3225 buf[0] = param1;
3226 buf[1] = param2;
3227 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3228 }
3229 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3230
3231 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3232 int channel, u8 dcs_cmd)
3233 {
3234 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3235 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3236 int r;
3237
3238 if (dsi->debug_read)
3239 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3240 channel, dcs_cmd);
3241
3242 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3243 if (r) {
3244 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3245 " failed\n", channel, dcs_cmd);
3246 return r;
3247 }
3248
3249 return 0;
3250 }
3251
3252 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3253 int channel, u8 *reqdata, int reqlen)
3254 {
3255 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3256 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3257 u16 data;
3258 u8 data_type;
3259 int r;
3260
3261 if (dsi->debug_read)
3262 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3263 channel, reqlen);
3264
3265 if (reqlen == 0) {
3266 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3267 data = 0;
3268 } else if (reqlen == 1) {
3269 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3270 data = reqdata[0];
3271 } else if (reqlen == 2) {
3272 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3273 data = reqdata[0] | (reqdata[1] << 8);
3274 } else {
3275 BUG();
3276 }
3277
3278 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3279 if (r) {
3280 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3281 " failed\n", channel, reqlen);
3282 return r;
3283 }
3284
3285 return 0;
3286 }
3287
3288 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3289 u8 *buf, int buflen, enum dss_dsi_content_type type)
3290 {
3291 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3292 u32 val;
3293 u8 dt;
3294 int r;
3295
3296 /* RX_FIFO_NOT_EMPTY */
3297 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3298 DSSERR("RX fifo empty when trying to read.\n");
3299 r = -EIO;
3300 goto err;
3301 }
3302
3303 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3304 if (dsi->debug_read)
3305 DSSDBG("\theader: %08x\n", val);
3306 dt = FLD_GET(val, 5, 0);
3307 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3308 u16 err = FLD_GET(val, 23, 8);
3309 dsi_show_rx_ack_with_err(err);
3310 r = -EIO;
3311 goto err;
3312
3313 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3314 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3315 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3316 u8 data = FLD_GET(val, 15, 8);
3317 if (dsi->debug_read)
3318 DSSDBG("\t%s short response, 1 byte: %02x\n",
3319 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3320 "DCS", data);
3321
3322 if (buflen < 1) {
3323 r = -EIO;
3324 goto err;
3325 }
3326
3327 buf[0] = data;
3328
3329 return 1;
3330 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3331 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3332 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3333 u16 data = FLD_GET(val, 23, 8);
3334 if (dsi->debug_read)
3335 DSSDBG("\t%s short response, 2 byte: %04x\n",
3336 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3337 "DCS", data);
3338
3339 if (buflen < 2) {
3340 r = -EIO;
3341 goto err;
3342 }
3343
3344 buf[0] = data & 0xff;
3345 buf[1] = (data >> 8) & 0xff;
3346
3347 return 2;
3348 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3349 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3350 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3351 int w;
3352 int len = FLD_GET(val, 23, 8);
3353 if (dsi->debug_read)
3354 DSSDBG("\t%s long response, len %d\n",
3355 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3356 "DCS", len);
3357
3358 if (len > buflen) {
3359 r = -EIO;
3360 goto err;
3361 }
3362
3363 /* two byte checksum ends the packet, not included in len */
3364 for (w = 0; w < len + 2;) {
3365 int b;
3366 val = dsi_read_reg(dsidev,
3367 DSI_VC_SHORT_PACKET_HEADER(channel));
3368 if (dsi->debug_read)
3369 DSSDBG("\t\t%02x %02x %02x %02x\n",
3370 (val >> 0) & 0xff,
3371 (val >> 8) & 0xff,
3372 (val >> 16) & 0xff,
3373 (val >> 24) & 0xff);
3374
3375 for (b = 0; b < 4; ++b) {
3376 if (w < len)
3377 buf[w] = (val >> (b * 8)) & 0xff;
3378 /* we discard the 2 byte checksum */
3379 ++w;
3380 }
3381 }
3382
3383 return len;
3384 } else {
3385 DSSERR("\tunknown datatype 0x%02x\n", dt);
3386 r = -EIO;
3387 goto err;
3388 }
3389
3390 BUG();
3391 err:
3392 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3393 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3394
3395 return r;
3396 }
3397
3398 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3399 u8 *buf, int buflen)
3400 {
3401 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3402 int r;
3403
3404 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3405 if (r)
3406 goto err;
3407
3408 r = dsi_vc_send_bta_sync(dssdev, channel);
3409 if (r)
3410 goto err;
3411
3412 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3413 DSS_DSI_CONTENT_DCS);
3414 if (r < 0)
3415 goto err;
3416
3417 if (r != buflen) {
3418 r = -EIO;
3419 goto err;
3420 }
3421
3422 return 0;
3423 err:
3424 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3425 return r;
3426 }
3427 EXPORT_SYMBOL(dsi_vc_dcs_read);
3428
3429 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3430 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3431 {
3432 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3433 int r;
3434
3435 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3436 if (r)
3437 return r;
3438
3439 r = dsi_vc_send_bta_sync(dssdev, channel);
3440 if (r)
3441 return r;
3442
3443 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3444 DSS_DSI_CONTENT_GENERIC);
3445 if (r < 0)
3446 return r;
3447
3448 if (r != buflen) {
3449 r = -EIO;
3450 return r;
3451 }
3452
3453 return 0;
3454 }
3455
3456 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3457 int buflen)
3458 {
3459 int r;
3460
3461 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3462 if (r) {
3463 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3464 return r;
3465 }
3466
3467 return 0;
3468 }
3469 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3470
3471 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3472 u8 *buf, int buflen)
3473 {
3474 int r;
3475
3476 r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3477 if (r) {
3478 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3479 return r;
3480 }
3481
3482 return 0;
3483 }
3484 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3485
3486 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3487 u8 param1, u8 param2, u8 *buf, int buflen)
3488 {
3489 int r;
3490 u8 reqdata[2];
3491
3492 reqdata[0] = param1;
3493 reqdata[1] = param2;
3494
3495 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3496 if (r) {
3497 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3498 return r;
3499 }
3500
3501 return 0;
3502 }
3503 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3504
3505 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3506 u16 len)
3507 {
3508 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3509
3510 return dsi_vc_send_short(dsidev, channel,
3511 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3512 }
3513 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3514
3515 static int dsi_enter_ulps(struct platform_device *dsidev)
3516 {
3517 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3518 DECLARE_COMPLETION_ONSTACK(completion);
3519 int r;
3520
3521 DSSDBGF();
3522
3523 WARN_ON(!dsi_bus_is_locked(dsidev));
3524
3525 WARN_ON(dsi->ulps_enabled);
3526
3527 if (dsi->ulps_enabled)
3528 return 0;
3529
3530 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3531 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3532 return -EIO;
3533 }
3534
3535 dsi_sync_vc(dsidev, 0);
3536 dsi_sync_vc(dsidev, 1);
3537 dsi_sync_vc(dsidev, 2);
3538 dsi_sync_vc(dsidev, 3);
3539
3540 dsi_force_tx_stop_mode_io(dsidev);
3541
3542 dsi_vc_enable(dsidev, 0, false);
3543 dsi_vc_enable(dsidev, 1, false);
3544 dsi_vc_enable(dsidev, 2, false);
3545 dsi_vc_enable(dsidev, 3, false);
3546
3547 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3548 DSSERR("HS busy when enabling ULPS\n");
3549 return -EIO;
3550 }
3551
3552 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3553 DSSERR("LP busy when enabling ULPS\n");
3554 return -EIO;
3555 }
3556
3557 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3558 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3559 if (r)
3560 return r;
3561
3562 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3563 /* LANEx_ULPS_SIG2 */
3564 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3565 7, 5);
3566
3567 /* flush posted write and wait for SCP interface to finish the write */
3568 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3569
3570 if (wait_for_completion_timeout(&completion,
3571 msecs_to_jiffies(1000)) == 0) {
3572 DSSERR("ULPS enable timeout\n");
3573 r = -EIO;
3574 goto err;
3575 }
3576
3577 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3578 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3579
3580 /* Reset LANEx_ULPS_SIG2 */
3581 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3582 7, 5);
3583
3584 /* flush posted write and wait for SCP interface to finish the write */
3585 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3586
3587 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3588
3589 dsi_if_enable(dsidev, false);
3590
3591 dsi->ulps_enabled = true;
3592
3593 return 0;
3594
3595 err:
3596 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3597 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3598 return r;
3599 }
3600
3601 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3602 unsigned ticks, bool x4, bool x16)
3603 {
3604 unsigned long fck;
3605 unsigned long total_ticks;
3606 u32 r;
3607
3608 BUG_ON(ticks > 0x1fff);
3609
3610 /* ticks in DSI_FCK */
3611 fck = dsi_fclk_rate(dsidev);
3612
3613 r = dsi_read_reg(dsidev, DSI_TIMING2);
3614 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3615 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3616 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3617 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3618 dsi_write_reg(dsidev, DSI_TIMING2, r);
3619
3620 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3621
3622 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3623 total_ticks,
3624 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3625 (total_ticks * 1000) / (fck / 1000 / 1000));
3626 }
3627
3628 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3629 bool x8, bool x16)
3630 {
3631 unsigned long fck;
3632 unsigned long total_ticks;
3633 u32 r;
3634
3635 BUG_ON(ticks > 0x1fff);
3636
3637 /* ticks in DSI_FCK */
3638 fck = dsi_fclk_rate(dsidev);
3639
3640 r = dsi_read_reg(dsidev, DSI_TIMING1);
3641 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3642 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3643 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3644 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3645 dsi_write_reg(dsidev, DSI_TIMING1, r);
3646
3647 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3648
3649 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3650 total_ticks,
3651 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3652 (total_ticks * 1000) / (fck / 1000 / 1000));
3653 }
3654
3655 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3656 unsigned ticks, bool x4, bool x16)
3657 {
3658 unsigned long fck;
3659 unsigned long total_ticks;
3660 u32 r;
3661
3662 BUG_ON(ticks > 0x1fff);
3663
3664 /* ticks in DSI_FCK */
3665 fck = dsi_fclk_rate(dsidev);
3666
3667 r = dsi_read_reg(dsidev, DSI_TIMING1);
3668 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3669 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3670 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3671 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3672 dsi_write_reg(dsidev, DSI_TIMING1, r);
3673
3674 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3675
3676 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3677 total_ticks,
3678 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3679 (total_ticks * 1000) / (fck / 1000 / 1000));
3680 }
3681
3682 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3683 unsigned ticks, bool x4, bool x16)
3684 {
3685 unsigned long fck;
3686 unsigned long total_ticks;
3687 u32 r;
3688
3689 BUG_ON(ticks > 0x1fff);
3690
3691 /* ticks in TxByteClkHS */
3692 fck = dsi_get_txbyteclkhs(dsidev);
3693
3694 r = dsi_read_reg(dsidev, DSI_TIMING2);
3695 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3696 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3697 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3698 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3699 dsi_write_reg(dsidev, DSI_TIMING2, r);
3700
3701 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3702
3703 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3704 total_ticks,
3705 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3706 (total_ticks * 1000) / (fck / 1000 / 1000));
3707 }
3708
3709 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3710 {
3711 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3712 int num_line_buffers;
3713
3714 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3715 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3716 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3717 struct omap_video_timings *timings = &dssdev->panel.timings;
3718 /*
3719 * Don't use line buffers if width is greater than the video
3720 * port's line buffer size
3721 */
3722 if (line_buf_size <= timings->x_res * bpp / 8)
3723 num_line_buffers = 0;
3724 else
3725 num_line_buffers = 2;
3726 } else {
3727 /* Use maximum number of line buffers in command mode */
3728 num_line_buffers = 2;
3729 }
3730
3731 /* LINE_BUFFER */
3732 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3733 }
3734
3735 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3736 {
3737 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3738 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3739 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3740 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3741 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3742 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3743 u32 r;
3744
3745 r = dsi_read_reg(dsidev, DSI_CTRL);
3746 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
3747 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
3748 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
3749 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3750 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3751 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3752 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3753 dsi_write_reg(dsidev, DSI_CTRL, r);
3754 }
3755
3756 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3757 {
3758 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3759 int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3760 int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3761 int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3762 int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3763 u32 r;
3764
3765 /*
3766 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3767 * 1 = Long blanking packets are sent in corresponding blanking periods
3768 */
3769 r = dsi_read_reg(dsidev, DSI_CTRL);
3770 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3771 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3772 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3773 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3774 dsi_write_reg(dsidev, DSI_CTRL, r);
3775 }
3776
3777 static int dsi_proto_config(struct omap_dss_device *dssdev)
3778 {
3779 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3780 u32 r;
3781 int buswidth = 0;
3782
3783 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3784 DSI_FIFO_SIZE_32,
3785 DSI_FIFO_SIZE_32,
3786 DSI_FIFO_SIZE_32);
3787
3788 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3789 DSI_FIFO_SIZE_32,
3790 DSI_FIFO_SIZE_32,
3791 DSI_FIFO_SIZE_32);
3792
3793 /* XXX what values for the timeouts? */
3794 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3795 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3796 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3797 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3798
3799 switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3800 case 16:
3801 buswidth = 0;
3802 break;
3803 case 18:
3804 buswidth = 1;
3805 break;
3806 case 24:
3807 buswidth = 2;
3808 break;
3809 default:
3810 BUG();
3811 }
3812
3813 r = dsi_read_reg(dsidev, DSI_CTRL);
3814 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3815 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3816 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3817 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3818 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3819 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3820 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3821 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3822 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3823 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3824 /* DCS_CMD_CODE, 1=start, 0=continue */
3825 r = FLD_MOD(r, 0, 25, 25);
3826 }
3827
3828 dsi_write_reg(dsidev, DSI_CTRL, r);
3829
3830 dsi_config_vp_num_line_buffers(dssdev);
3831
3832 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3833 dsi_config_vp_sync_events(dssdev);
3834 dsi_config_blanking_modes(dssdev);
3835 }
3836
3837 dsi_vc_initial_config(dsidev, 0);
3838 dsi_vc_initial_config(dsidev, 1);
3839 dsi_vc_initial_config(dsidev, 2);
3840 dsi_vc_initial_config(dsidev, 3);
3841
3842 return 0;
3843 }
3844
3845 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3846 {
3847 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3848 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3849 unsigned tclk_pre, tclk_post;
3850 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3851 unsigned ths_trail, ths_exit;
3852 unsigned ddr_clk_pre, ddr_clk_post;
3853 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3854 unsigned ths_eot;
3855 int ndl = dsi_get_num_data_lanes_dssdev(dssdev);
3856 u32 r;
3857
3858 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3859 ths_prepare = FLD_GET(r, 31, 24);
3860 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3861 ths_zero = ths_prepare_ths_zero - ths_prepare;
3862 ths_trail = FLD_GET(r, 15, 8);
3863 ths_exit = FLD_GET(r, 7, 0);
3864
3865 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3866 tlpx = FLD_GET(r, 22, 16) * 2;
3867 tclk_trail = FLD_GET(r, 15, 8);
3868 tclk_zero = FLD_GET(r, 7, 0);
3869
3870 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3871 tclk_prepare = FLD_GET(r, 7, 0);
3872
3873 /* min 8*UI */
3874 tclk_pre = 20;
3875 /* min 60ns + 52*UI */
3876 tclk_post = ns2ddr(dsidev, 60) + 26;
3877
3878 ths_eot = DIV_ROUND_UP(4, ndl);
3879
3880 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3881 4);
3882 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3883
3884 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3885 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3886
3887 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3888 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3889 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3890 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3891
3892 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3893 ddr_clk_pre,
3894 ddr_clk_post);
3895
3896 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3897 DIV_ROUND_UP(ths_prepare, 4) +
3898 DIV_ROUND_UP(ths_zero + 3, 4);
3899
3900 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3901
3902 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3903 FLD_VAL(exit_hs_mode_lat, 15, 0);
3904 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3905
3906 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3907 enter_hs_mode_lat, exit_hs_mode_lat);
3908
3909 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3910 /* TODO: Implement a video mode check_timings function */
3911 int hsa = dssdev->panel.dsi_vm_data.hsa;
3912 int hfp = dssdev->panel.dsi_vm_data.hfp;
3913 int hbp = dssdev->panel.dsi_vm_data.hbp;
3914 int vsa = dssdev->panel.dsi_vm_data.vsa;
3915 int vfp = dssdev->panel.dsi_vm_data.vfp;
3916 int vbp = dssdev->panel.dsi_vm_data.vbp;
3917 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3918 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3919 struct omap_video_timings *timings = &dssdev->panel.timings;
3920 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3921 int tl, t_he, width_bytes;
3922
3923 t_he = hsync_end ?
3924 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3925
3926 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3927
3928 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3929 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3930 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3931
3932 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3933 hfp, hsync_end ? hsa : 0, tl);
3934 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3935 vsa, timings->y_res);
3936
3937 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3938 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3939 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3940 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3941 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3942
3943 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3944 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3945 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3946 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3947 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3948 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3949
3950 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3951 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3952 r = FLD_MOD(r, tl, 31, 16); /* TL */
3953 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3954 }
3955 }
3956
3957 int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
3958 {
3959 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3960 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3961 u8 data_type;
3962 u16 word_count;
3963
3964 switch (dssdev->panel.dsi_pix_fmt) {
3965 case OMAP_DSS_DSI_FMT_RGB888:
3966 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3967 break;
3968 case OMAP_DSS_DSI_FMT_RGB666:
3969 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3970 break;
3971 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3972 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3973 break;
3974 case OMAP_DSS_DSI_FMT_RGB565:
3975 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3976 break;
3977 default:
3978 BUG();
3979 };
3980
3981 dsi_if_enable(dsidev, false);
3982 dsi_vc_enable(dsidev, channel, false);
3983
3984 /* MODE, 1 = video mode */
3985 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3986
3987 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3988
3989 dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);
3990
3991 dsi_vc_enable(dsidev, channel, true);
3992 dsi_if_enable(dsidev, true);
3993
3994 dssdev->manager->enable(dssdev->manager);
3995
3996 return 0;
3997 }
3998 EXPORT_SYMBOL(dsi_video_mode_enable);
3999
4000 void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
4001 {
4002 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4003
4004 dsi_if_enable(dsidev, false);
4005 dsi_vc_enable(dsidev, channel, false);
4006
4007 /* MODE, 0 = command mode */
4008 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4009
4010 dsi_vc_enable(dsidev, channel, true);
4011 dsi_if_enable(dsidev, true);
4012
4013 dssdev->manager->disable(dssdev->manager);
4014 }
4015 EXPORT_SYMBOL(dsi_video_mode_disable);
4016
4017 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4018 u16 x, u16 y, u16 w, u16 h)
4019 {
4020 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4021 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4022 unsigned bytespp;
4023 unsigned bytespl;
4024 unsigned bytespf;
4025 unsigned total_len;
4026 unsigned packet_payload;
4027 unsigned packet_len;
4028 u32 l;
4029 int r;
4030 const unsigned channel = dsi->update_channel;
4031 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4032
4033 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4034 x, y, w, h);
4035
4036 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4037
4038 bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4039 bytespl = w * bytespp;
4040 bytespf = bytespl * h;
4041
4042 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4043 * number of lines in a packet. See errata about VP_CLK_RATIO */
4044
4045 if (bytespf < line_buf_size)
4046 packet_payload = bytespf;
4047 else
4048 packet_payload = (line_buf_size) / bytespl * bytespl;
4049
4050 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4051 total_len = (bytespf / packet_payload) * packet_len;
4052
4053 if (bytespf % packet_payload)
4054 total_len += (bytespf % packet_payload) + 1;
4055
4056 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4057 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4058
4059 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4060 packet_len, 0);
4061
4062 if (dsi->te_enabled)
4063 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4064 else
4065 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4066 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4067
4068 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4069 * because DSS interrupts are not capable of waking up the CPU and the
4070 * framedone interrupt could be delayed for quite a long time. I think
4071 * the same goes for any DSS interrupts, but for some reason I have not
4072 * seen the problem anywhere else than here.
4073 */
4074 dispc_disable_sidle();
4075
4076 dsi_perf_mark_start(dsidev);
4077
4078 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4079 msecs_to_jiffies(250));
4080 BUG_ON(r == 0);
4081
4082 dss_start_update(dssdev);
4083
4084 if (dsi->te_enabled) {
4085 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4086 * for TE is longer than the timer allows */
4087 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4088
4089 dsi_vc_send_bta(dsidev, channel);
4090
4091 #ifdef DSI_CATCH_MISSING_TE
4092 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4093 #endif
4094 }
4095 }
4096
4097 #ifdef DSI_CATCH_MISSING_TE
4098 static void dsi_te_timeout(unsigned long arg)
4099 {
4100 DSSERR("TE not received for 250ms!\n");
4101 }
4102 #endif
4103
4104 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4105 {
4106 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4107
4108 /* SIDLEMODE back to smart-idle */
4109 dispc_enable_sidle();
4110
4111 if (dsi->te_enabled) {
4112 /* enable LP_RX_TO again after the TE */
4113 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4114 }
4115
4116 dsi->framedone_callback(error, dsi->framedone_data);
4117
4118 if (!error)
4119 dsi_perf_show(dsidev, "DISPC");
4120 }
4121
4122 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4123 {
4124 struct dsi_data *dsi = container_of(work, struct dsi_data,
4125 framedone_timeout_work.work);
4126 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4127 * 250ms which would conflict with this timeout work. What should be
4128 * done is first cancel the transfer on the HW, and then cancel the
4129 * possibly scheduled framedone work. However, cancelling the transfer
4130 * on the HW is buggy, and would probably require resetting the whole
4131 * DSI */
4132
4133 DSSERR("Framedone not received for 250ms!\n");
4134
4135 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4136 }
4137
4138 static void dsi_framedone_irq_callback(void *data, u32 mask)
4139 {
4140 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4141 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4142 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4143
4144 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4145 * turns itself off. However, DSI still has the pixels in its buffers,
4146 * and is sending the data.
4147 */
4148
4149 __cancel_delayed_work(&dsi->framedone_timeout_work);
4150
4151 dsi_handle_framedone(dsidev, 0);
4152
4153 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4154 dispc_fake_vsync_irq();
4155 #endif
4156 }
4157
4158 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
4159 u16 *x, u16 *y, u16 *w, u16 *h,
4160 bool enlarge_update_area)
4161 {
4162 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4163 u16 dw, dh;
4164
4165 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4166
4167 if (*x > dw || *y > dh)
4168 return -EINVAL;
4169
4170 if (*x + *w > dw)
4171 return -EINVAL;
4172
4173 if (*y + *h > dh)
4174 return -EINVAL;
4175
4176 if (*w == 1)
4177 return -EINVAL;
4178
4179 if (*w == 0 || *h == 0)
4180 return -EINVAL;
4181
4182 dsi_perf_mark_setup(dsidev);
4183
4184 dss_setup_partial_planes(dssdev, x, y, w, h,
4185 enlarge_update_area);
4186 dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
4187
4188 return 0;
4189 }
4190 EXPORT_SYMBOL(omap_dsi_prepare_update);
4191
4192 int omap_dsi_update(struct omap_dss_device *dssdev,
4193 int channel,
4194 u16 x, u16 y, u16 w, u16 h,
4195 void (*callback)(int, void *), void *data)
4196 {
4197 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4198 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4199
4200 dsi->update_channel = channel;
4201
4202 /* OMAP DSS cannot send updates of odd widths.
4203 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4204 * here to make sure we catch erroneous updates. Otherwise we'll only
4205 * see rather obscure HW error happening, as DSS halts. */
4206 BUG_ON(x % 2 == 1);
4207
4208 dsi->framedone_callback = callback;
4209 dsi->framedone_data = data;
4210
4211 dsi->update_region.x = x;
4212 dsi->update_region.y = y;
4213 dsi->update_region.w = w;
4214 dsi->update_region.h = h;
4215 dsi->update_region.device = dssdev;
4216
4217 dsi_update_screen_dispc(dssdev, x, y, w, h);
4218
4219 return 0;
4220 }
4221 EXPORT_SYMBOL(omap_dsi_update);
4222
4223 /* Display funcs */
4224
4225 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4226 {
4227 int r;
4228
4229 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4230 u32 irq;
4231 struct omap_video_timings timings = {
4232 .hsw = 1,
4233 .hfp = 1,
4234 .hbp = 1,
4235 .vsw = 1,
4236 .vfp = 0,
4237 .vbp = 0,
4238 };
4239
4240 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4241 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4242
4243 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4244 (void *) dssdev, irq);
4245 if (r) {
4246 DSSERR("can't get FRAMEDONE irq\n");
4247 return r;
4248 }
4249
4250 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4251 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4252
4253 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4254 } else {
4255 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4256 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4257
4258 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4259 &dssdev->panel.timings);
4260 }
4261
4262 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4263 OMAP_DSS_LCD_DISPLAY_TFT);
4264 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4265 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4266 return 0;
4267 }
4268
4269 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4270 {
4271 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4272 u32 irq;
4273
4274 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4275 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4276
4277 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4278 (void *) dssdev, irq);
4279 }
4280 }
4281
4282 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4283 {
4284 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4285 struct dsi_clock_info cinfo;
4286 int r;
4287
4288 /* we always use DSS_CLK_SYSCK as input clock */
4289 cinfo.use_sys_clk = true;
4290 cinfo.regn = dssdev->clocks.dsi.regn;
4291 cinfo.regm = dssdev->clocks.dsi.regm;
4292 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4293 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4294 r = dsi_calc_clock_rates(dssdev, &cinfo);
4295 if (r) {
4296 DSSERR("Failed to calc dsi clocks\n");
4297 return r;
4298 }
4299
4300 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4301 if (r) {
4302 DSSERR("Failed to set dsi clocks\n");
4303 return r;
4304 }
4305
4306 return 0;
4307 }
4308
4309 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4310 {
4311 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4312 struct dispc_clock_info dispc_cinfo;
4313 int r;
4314 unsigned long long fck;
4315
4316 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4317
4318 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4319 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4320
4321 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4322 if (r) {
4323 DSSERR("Failed to calc dispc clocks\n");
4324 return r;
4325 }
4326
4327 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4328 if (r) {
4329 DSSERR("Failed to set dispc clocks\n");
4330 return r;
4331 }
4332
4333 return 0;
4334 }
4335
4336 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4337 {
4338 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4339 int dsi_module = dsi_get_dsidev_id(dsidev);
4340 int r;
4341
4342 r = dsi_pll_init(dsidev, true, true);
4343 if (r)
4344 goto err0;
4345
4346 r = dsi_configure_dsi_clocks(dssdev);
4347 if (r)
4348 goto err1;
4349
4350 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4351 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4352 dss_select_lcd_clk_source(dssdev->manager->id,
4353 dssdev->clocks.dispc.channel.lcd_clk_src);
4354
4355 DSSDBG("PLL OK\n");
4356
4357 r = dsi_configure_dispc_clocks(dssdev);
4358 if (r)
4359 goto err2;
4360
4361 r = dsi_cio_init(dssdev);
4362 if (r)
4363 goto err2;
4364
4365 _dsi_print_reset_status(dsidev);
4366
4367 dsi_proto_timings(dssdev);
4368 dsi_set_lp_clk_divisor(dssdev);
4369
4370 if (1)
4371 _dsi_print_reset_status(dsidev);
4372
4373 r = dsi_proto_config(dssdev);
4374 if (r)
4375 goto err3;
4376
4377 /* enable interface */
4378 dsi_vc_enable(dsidev, 0, 1);
4379 dsi_vc_enable(dsidev, 1, 1);
4380 dsi_vc_enable(dsidev, 2, 1);
4381 dsi_vc_enable(dsidev, 3, 1);
4382 dsi_if_enable(dsidev, 1);
4383 dsi_force_tx_stop_mode_io(dsidev);
4384
4385 return 0;
4386 err3:
4387 dsi_cio_uninit(dssdev);
4388 err2:
4389 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4390 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4391 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4392
4393 err1:
4394 dsi_pll_uninit(dsidev, true);
4395 err0:
4396 return r;
4397 }
4398
4399 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4400 bool disconnect_lanes, bool enter_ulps)
4401 {
4402 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4404 int dsi_module = dsi_get_dsidev_id(dsidev);
4405
4406 if (enter_ulps && !dsi->ulps_enabled)
4407 dsi_enter_ulps(dsidev);
4408
4409 /* disable interface */
4410 dsi_if_enable(dsidev, 0);
4411 dsi_vc_enable(dsidev, 0, 0);
4412 dsi_vc_enable(dsidev, 1, 0);
4413 dsi_vc_enable(dsidev, 2, 0);
4414 dsi_vc_enable(dsidev, 3, 0);
4415
4416 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4417 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4418 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4419 dsi_cio_uninit(dssdev);
4420 dsi_pll_uninit(dsidev, disconnect_lanes);
4421 }
4422
4423 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4424 {
4425 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4426 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4427 int r = 0;
4428
4429 DSSDBG("dsi_display_enable\n");
4430
4431 WARN_ON(!dsi_bus_is_locked(dsidev));
4432
4433 mutex_lock(&dsi->lock);
4434
4435 if (dssdev->manager == NULL) {
4436 DSSERR("failed to enable display: no manager\n");
4437 r = -ENODEV;
4438 goto err_start_dev;
4439 }
4440
4441 r = omap_dss_start_device(dssdev);
4442 if (r) {
4443 DSSERR("failed to start device\n");
4444 goto err_start_dev;
4445 }
4446
4447 r = dsi_runtime_get(dsidev);
4448 if (r)
4449 goto err_get_dsi;
4450
4451 dsi_enable_pll_clock(dsidev, 1);
4452
4453 _dsi_initialize_irq(dsidev);
4454
4455 r = dsi_display_init_dispc(dssdev);
4456 if (r)
4457 goto err_init_dispc;
4458
4459 r = dsi_display_init_dsi(dssdev);
4460 if (r)
4461 goto err_init_dsi;
4462
4463 mutex_unlock(&dsi->lock);
4464
4465 return 0;
4466
4467 err_init_dsi:
4468 dsi_display_uninit_dispc(dssdev);
4469 err_init_dispc:
4470 dsi_enable_pll_clock(dsidev, 0);
4471 dsi_runtime_put(dsidev);
4472 err_get_dsi:
4473 omap_dss_stop_device(dssdev);
4474 err_start_dev:
4475 mutex_unlock(&dsi->lock);
4476 DSSDBG("dsi_display_enable FAILED\n");
4477 return r;
4478 }
4479 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4480
4481 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4482 bool disconnect_lanes, bool enter_ulps)
4483 {
4484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4486
4487 DSSDBG("dsi_display_disable\n");
4488
4489 WARN_ON(!dsi_bus_is_locked(dsidev));
4490
4491 mutex_lock(&dsi->lock);
4492
4493 dsi_sync_vc(dsidev, 0);
4494 dsi_sync_vc(dsidev, 1);
4495 dsi_sync_vc(dsidev, 2);
4496 dsi_sync_vc(dsidev, 3);
4497
4498 dsi_display_uninit_dispc(dssdev);
4499
4500 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4501
4502 dsi_runtime_put(dsidev);
4503 dsi_enable_pll_clock(dsidev, 0);
4504
4505 omap_dss_stop_device(dssdev);
4506
4507 mutex_unlock(&dsi->lock);
4508 }
4509 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4510
4511 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4512 {
4513 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4514 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4515
4516 dsi->te_enabled = enable;
4517 return 0;
4518 }
4519 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4520
4521 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4522 u32 fifo_size, u32 burst_size,
4523 u32 *fifo_low, u32 *fifo_high)
4524 {
4525 *fifo_high = fifo_size - burst_size;
4526 *fifo_low = fifo_size - burst_size * 2;
4527 }
4528
4529 int dsi_init_display(struct omap_dss_device *dssdev)
4530 {
4531 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4532 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4533 int dsi_module = dsi_get_dsidev_id(dsidev);
4534
4535 DSSDBG("DSI init\n");
4536
4537 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4538 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4539 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4540 }
4541
4542 if (dsi->vdds_dsi_reg == NULL) {
4543 struct regulator *vdds_dsi;
4544
4545 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4546
4547 if (IS_ERR(vdds_dsi)) {
4548 DSSERR("can't get VDDS_DSI regulator\n");
4549 return PTR_ERR(vdds_dsi);
4550 }
4551
4552 dsi->vdds_dsi_reg = vdds_dsi;
4553 }
4554
4555 if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
4556 DSSERR("DSI%d can't support more than %d data lanes\n",
4557 dsi_module + 1, dsi->num_data_lanes);
4558 return -EINVAL;
4559 }
4560
4561 return 0;
4562 }
4563
4564 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4565 {
4566 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4567 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4568 int i;
4569
4570 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4571 if (!dsi->vc[i].dssdev) {
4572 dsi->vc[i].dssdev = dssdev;
4573 *channel = i;
4574 return 0;
4575 }
4576 }
4577
4578 DSSERR("cannot get VC for display %s", dssdev->name);
4579 return -ENOSPC;
4580 }
4581 EXPORT_SYMBOL(omap_dsi_request_vc);
4582
4583 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4584 {
4585 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4586 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4587
4588 if (vc_id < 0 || vc_id > 3) {
4589 DSSERR("VC ID out of range\n");
4590 return -EINVAL;
4591 }
4592
4593 if (channel < 0 || channel > 3) {
4594 DSSERR("Virtual Channel out of range\n");
4595 return -EINVAL;
4596 }
4597
4598 if (dsi->vc[channel].dssdev != dssdev) {
4599 DSSERR("Virtual Channel not allocated to display %s\n",
4600 dssdev->name);
4601 return -EINVAL;
4602 }
4603
4604 dsi->vc[channel].vc_id = vc_id;
4605
4606 return 0;
4607 }
4608 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4609
4610 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4611 {
4612 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4613 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4614
4615 if ((channel >= 0 && channel <= 3) &&
4616 dsi->vc[channel].dssdev == dssdev) {
4617 dsi->vc[channel].dssdev = NULL;
4618 dsi->vc[channel].vc_id = 0;
4619 }
4620 }
4621 EXPORT_SYMBOL(omap_dsi_release_vc);
4622
4623 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4624 {
4625 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4626 DSSERR("%s (%s) not active\n",
4627 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4628 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4629 }
4630
4631 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4632 {
4633 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4634 DSSERR("%s (%s) not active\n",
4635 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4636 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4637 }
4638
4639 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4640 {
4641 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4642
4643 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4644 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4645 dsi->regm_dispc_max =
4646 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4647 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4648 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4649 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4650 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4651 }
4652
4653 static int dsi_get_clocks(struct platform_device *dsidev)
4654 {
4655 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4656 struct clk *clk;
4657
4658 clk = clk_get(&dsidev->dev, "fck");
4659 if (IS_ERR(clk)) {
4660 DSSERR("can't get fck\n");
4661 return PTR_ERR(clk);
4662 }
4663
4664 dsi->dss_clk = clk;
4665
4666 clk = clk_get(&dsidev->dev, "sys_clk");
4667 if (IS_ERR(clk)) {
4668 DSSERR("can't get sys_clk\n");
4669 clk_put(dsi->dss_clk);
4670 dsi->dss_clk = NULL;
4671 return PTR_ERR(clk);
4672 }
4673
4674 dsi->sys_clk = clk;
4675
4676 return 0;
4677 }
4678
4679 static void dsi_put_clocks(struct platform_device *dsidev)
4680 {
4681 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4682
4683 if (dsi->dss_clk)
4684 clk_put(dsi->dss_clk);
4685 if (dsi->sys_clk)
4686 clk_put(dsi->sys_clk);
4687 }
4688
4689 /* DSI1 HW IP initialisation */
4690 static int omap_dsihw_probe(struct platform_device *dsidev)
4691 {
4692 struct omap_display_platform_data *dss_plat_data;
4693 struct omap_dss_board_info *board_info;
4694 u32 rev;
4695 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4696 struct resource *dsi_mem;
4697 struct dsi_data *dsi;
4698
4699 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4700 if (!dsi) {
4701 r = -ENOMEM;
4702 goto err_alloc;
4703 }
4704
4705 dsi->pdev = dsidev;
4706 dsi_pdev_map[dsi_module] = dsidev;
4707 dev_set_drvdata(&dsidev->dev, dsi);
4708
4709 dss_plat_data = dsidev->dev.platform_data;
4710 board_info = dss_plat_data->board_data;
4711 dsi->enable_pads = board_info->dsi_enable_pads;
4712 dsi->disable_pads = board_info->dsi_disable_pads;
4713
4714 spin_lock_init(&dsi->irq_lock);
4715 spin_lock_init(&dsi->errors_lock);
4716 dsi->errors = 0;
4717
4718 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4719 spin_lock_init(&dsi->irq_stats_lock);
4720 dsi->irq_stats.last_reset = jiffies;
4721 #endif
4722
4723 mutex_init(&dsi->lock);
4724 sema_init(&dsi->bus_lock, 1);
4725
4726 r = dsi_get_clocks(dsidev);
4727 if (r)
4728 goto err_get_clk;
4729
4730 pm_runtime_enable(&dsidev->dev);
4731
4732 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4733 dsi_framedone_timeout_work_callback);
4734
4735 #ifdef DSI_CATCH_MISSING_TE
4736 init_timer(&dsi->te_timer);
4737 dsi->te_timer.function = dsi_te_timeout;
4738 dsi->te_timer.data = 0;
4739 #endif
4740 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4741 if (!dsi_mem) {
4742 DSSERR("can't get IORESOURCE_MEM DSI\n");
4743 r = -EINVAL;
4744 goto err_ioremap;
4745 }
4746 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4747 if (!dsi->base) {
4748 DSSERR("can't ioremap DSI\n");
4749 r = -ENOMEM;
4750 goto err_ioremap;
4751 }
4752 dsi->irq = platform_get_irq(dsi->pdev, 0);
4753 if (dsi->irq < 0) {
4754 DSSERR("platform_get_irq failed\n");
4755 r = -ENODEV;
4756 goto err_get_irq;
4757 }
4758
4759 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4760 dev_name(&dsidev->dev), dsi->pdev);
4761 if (r < 0) {
4762 DSSERR("request_irq failed\n");
4763 goto err_get_irq;
4764 }
4765
4766 /* DSI VCs initialization */
4767 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4768 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4769 dsi->vc[i].dssdev = NULL;
4770 dsi->vc[i].vc_id = 0;
4771 }
4772
4773 dsi_calc_clock_param_ranges(dsidev);
4774
4775 r = dsi_runtime_get(dsidev);
4776 if (r)
4777 goto err_get_dsi;
4778
4779 rev = dsi_read_reg(dsidev, DSI_REVISION);
4780 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4781 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4782
4783 dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
4784
4785 dsi_runtime_put(dsidev);
4786
4787 return 0;
4788
4789 err_get_dsi:
4790 free_irq(dsi->irq, dsi->pdev);
4791 err_get_irq:
4792 iounmap(dsi->base);
4793 err_ioremap:
4794 pm_runtime_disable(&dsidev->dev);
4795 err_get_clk:
4796 kfree(dsi);
4797 err_alloc:
4798 return r;
4799 }
4800
4801 static int omap_dsihw_remove(struct platform_device *dsidev)
4802 {
4803 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4804
4805 WARN_ON(dsi->scp_clk_refcount > 0);
4806
4807 pm_runtime_disable(&dsidev->dev);
4808
4809 dsi_put_clocks(dsidev);
4810
4811 if (dsi->vdds_dsi_reg != NULL) {
4812 if (dsi->vdds_dsi_enabled) {
4813 regulator_disable(dsi->vdds_dsi_reg);
4814 dsi->vdds_dsi_enabled = false;
4815 }
4816
4817 regulator_put(dsi->vdds_dsi_reg);
4818 dsi->vdds_dsi_reg = NULL;
4819 }
4820
4821 free_irq(dsi->irq, dsi->pdev);
4822 iounmap(dsi->base);
4823
4824 kfree(dsi);
4825
4826 return 0;
4827 }
4828
4829 static int dsi_runtime_suspend(struct device *dev)
4830 {
4831 dispc_runtime_put();
4832 dss_runtime_put();
4833
4834 return 0;
4835 }
4836
4837 static int dsi_runtime_resume(struct device *dev)
4838 {
4839 int r;
4840
4841 r = dss_runtime_get();
4842 if (r)
4843 goto err_get_dss;
4844
4845 r = dispc_runtime_get();
4846 if (r)
4847 goto err_get_dispc;
4848
4849 return 0;
4850
4851 err_get_dispc:
4852 dss_runtime_put();
4853 err_get_dss:
4854 return r;
4855 }
4856
4857 static const struct dev_pm_ops dsi_pm_ops = {
4858 .runtime_suspend = dsi_runtime_suspend,
4859 .runtime_resume = dsi_runtime_resume,
4860 };
4861
4862 static struct platform_driver omap_dsihw_driver = {
4863 .probe = omap_dsihw_probe,
4864 .remove = omap_dsihw_remove,
4865 .driver = {
4866 .name = "omapdss_dsi",
4867 .owner = THIS_MODULE,
4868 .pm = &dsi_pm_ops,
4869 },
4870 };
4871
4872 int dsi_init_platform_driver(void)
4873 {
4874 return platform_driver_register(&omap_dsihw_driver);
4875 }
4876
4877 void dsi_uninit_platform_driver(void)
4878 {
4879 return platform_driver_unregister(&omap_dsihw_driver);
4880 }
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