2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
47 #include "dss_features.h"
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg
{ u16 idx
; };
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
102 /* DSI_PLL_CTRL_SCP */
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203 typedef void (*omap_dsi_isr_t
) (void *arg
, u32 mask
);
205 #define DSI_MAX_NR_ISRS 2
206 #define DSI_MAX_NR_LANES 5
208 enum dsi_lane_function
{
217 struct dsi_lane_config
{
218 enum dsi_lane_function function
;
222 struct dsi_isr_data
{
230 DSI_FIFO_SIZE_32
= 1,
231 DSI_FIFO_SIZE_64
= 2,
232 DSI_FIFO_SIZE_96
= 3,
233 DSI_FIFO_SIZE_128
= 4,
237 DSI_VC_SOURCE_L4
= 0,
241 struct dsi_update_region
{
243 struct omap_dss_device
*device
;
246 struct dsi_irq_stats
{
247 unsigned long last_reset
;
249 unsigned dsi_irqs
[32];
250 unsigned vc_irqs
[4][32];
251 unsigned cio_irqs
[32];
254 struct dsi_isr_tables
{
255 struct dsi_isr_data isr_table
[DSI_MAX_NR_ISRS
];
256 struct dsi_isr_data isr_table_vc
[4][DSI_MAX_NR_ISRS
];
257 struct dsi_isr_data isr_table_cio
[DSI_MAX_NR_ISRS
];
261 struct platform_device
*pdev
;
269 int (*enable_pads
)(int dsi_id
, unsigned lane_mask
);
270 void (*disable_pads
)(int dsi_id
, unsigned lane_mask
);
272 struct dsi_clock_info current_cinfo
;
274 bool vdds_dsi_enabled
;
275 struct regulator
*vdds_dsi_reg
;
278 enum dsi_vc_source source
;
279 struct omap_dss_device
*dssdev
;
280 enum fifo_size fifo_size
;
285 struct semaphore bus_lock
;
290 struct dsi_isr_tables isr_tables
;
291 /* space for a copy used by the interrupt handler */
292 struct dsi_isr_tables isr_tables_copy
;
295 struct dsi_update_region update_region
;
300 void (*framedone_callback
)(int, void *);
301 void *framedone_data
;
303 struct delayed_work framedone_timeout_work
;
305 #ifdef DSI_CATCH_MISSING_TE
306 struct timer_list te_timer
;
309 unsigned long cache_req_pck
;
310 unsigned long cache_clk_freq
;
311 struct dsi_clock_info cache_cinfo
;
314 spinlock_t errors_lock
;
316 ktime_t perf_setup_time
;
317 ktime_t perf_start_time
;
322 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
323 spinlock_t irq_stats_lock
;
324 struct dsi_irq_stats irq_stats
;
326 /* DSI PLL Parameter Ranges */
327 unsigned long regm_max
, regn_max
;
328 unsigned long regm_dispc_max
, regm_dsi_max
;
329 unsigned long fint_min
, fint_max
;
330 unsigned long lpdiv_max
;
332 unsigned num_lanes_supported
;
334 struct dsi_lane_config lanes
[DSI_MAX_NR_LANES
];
335 unsigned num_lanes_used
;
337 unsigned scp_clk_refcount
;
340 struct dsi_packet_sent_handler_data
{
341 struct platform_device
*dsidev
;
342 struct completion
*completion
;
345 static struct platform_device
*dsi_pdev_map
[MAX_NUM_DSI
];
348 static unsigned int dsi_perf
;
349 module_param_named(dsi_perf
, dsi_perf
, bool, 0644);
352 static inline struct dsi_data
*dsi_get_dsidrv_data(struct platform_device
*dsidev
)
354 return dev_get_drvdata(&dsidev
->dev
);
357 static inline struct platform_device
*dsi_get_dsidev_from_dssdev(struct omap_dss_device
*dssdev
)
359 return dsi_pdev_map
[dssdev
->phy
.dsi
.module
];
362 struct platform_device
*dsi_get_dsidev_from_id(int module
)
364 return dsi_pdev_map
[module
];
367 static inline int dsi_get_dsidev_id(struct platform_device
*dsidev
)
372 static inline void dsi_write_reg(struct platform_device
*dsidev
,
373 const struct dsi_reg idx
, u32 val
)
375 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
377 __raw_writel(val
, dsi
->base
+ idx
.idx
);
380 static inline u32
dsi_read_reg(struct platform_device
*dsidev
,
381 const struct dsi_reg idx
)
383 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
385 return __raw_readl(dsi
->base
+ idx
.idx
);
388 void dsi_bus_lock(struct omap_dss_device
*dssdev
)
390 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
391 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
393 down(&dsi
->bus_lock
);
395 EXPORT_SYMBOL(dsi_bus_lock
);
397 void dsi_bus_unlock(struct omap_dss_device
*dssdev
)
399 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
400 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
404 EXPORT_SYMBOL(dsi_bus_unlock
);
406 static bool dsi_bus_is_locked(struct platform_device
*dsidev
)
408 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
410 return dsi
->bus_lock
.count
== 0;
413 static void dsi_completion_handler(void *data
, u32 mask
)
415 complete((struct completion
*)data
);
418 static inline int wait_for_bit_change(struct platform_device
*dsidev
,
419 const struct dsi_reg idx
, int bitnum
, int value
)
421 unsigned long timeout
;
425 /* first busyloop to see if the bit changes right away */
428 if (REG_GET(dsidev
, idx
, bitnum
, bitnum
) == value
)
432 /* then loop for 500ms, sleeping for 1ms in between */
433 timeout
= jiffies
+ msecs_to_jiffies(500);
434 while (time_before(jiffies
, timeout
)) {
435 if (REG_GET(dsidev
, idx
, bitnum
, bitnum
) == value
)
438 wait
= ns_to_ktime(1000 * 1000);
439 set_current_state(TASK_UNINTERRUPTIBLE
);
440 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
446 u8
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt
)
449 case OMAP_DSS_DSI_FMT_RGB888
:
450 case OMAP_DSS_DSI_FMT_RGB666
:
452 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
454 case OMAP_DSS_DSI_FMT_RGB565
:
462 static void dsi_perf_mark_setup(struct platform_device
*dsidev
)
464 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
465 dsi
->perf_setup_time
= ktime_get();
468 static void dsi_perf_mark_start(struct platform_device
*dsidev
)
470 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
471 dsi
->perf_start_time
= ktime_get();
474 static void dsi_perf_show(struct platform_device
*dsidev
, const char *name
)
476 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
477 struct omap_dss_device
*dssdev
= dsi
->update_region
.device
;
478 ktime_t t
, setup_time
, trans_time
;
480 u32 setup_us
, trans_us
, total_us
;
487 setup_time
= ktime_sub(dsi
->perf_start_time
, dsi
->perf_setup_time
);
488 setup_us
= (u32
)ktime_to_us(setup_time
);
492 trans_time
= ktime_sub(t
, dsi
->perf_start_time
);
493 trans_us
= (u32
)ktime_to_us(trans_time
);
497 total_us
= setup_us
+ trans_us
;
499 total_bytes
= dsi
->update_region
.w
*
500 dsi
->update_region
.h
*
501 dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
) / 8;
503 printk(KERN_INFO
"DSI(%s): %u us + %u us = %u us (%uHz), "
504 "%u bytes, %u kbytes/sec\n",
509 1000*1000 / total_us
,
511 total_bytes
* 1000 / total_us
);
514 static inline void dsi_perf_mark_setup(struct platform_device
*dsidev
)
518 static inline void dsi_perf_mark_start(struct platform_device
*dsidev
)
522 static inline void dsi_perf_show(struct platform_device
*dsidev
,
528 static void print_irq_status(u32 status
)
534 if ((status
& ~DSI_IRQ_CHANNEL_MASK
) == 0)
537 printk(KERN_DEBUG
"DSI IRQ: 0x%x: ", status
);
540 if (status & DSI_IRQ_##x) \
566 static void print_irq_status_vc(int channel
, u32 status
)
572 if ((status
& ~DSI_VC_IRQ_PACKET_SENT
) == 0)
575 printk(KERN_DEBUG
"DSI VC(%d) IRQ 0x%x: ", channel
, status
);
578 if (status & DSI_VC_IRQ_##x) \
595 static void print_irq_status_cio(u32 status
)
600 printk(KERN_DEBUG
"DSI CIO IRQ 0x%x: ", status
);
603 if (status & DSI_CIO_IRQ_##x) \
617 PIS(ERRCONTENTIONLP0_1
);
618 PIS(ERRCONTENTIONLP1_1
);
619 PIS(ERRCONTENTIONLP0_2
);
620 PIS(ERRCONTENTIONLP1_2
);
621 PIS(ERRCONTENTIONLP0_3
);
622 PIS(ERRCONTENTIONLP1_3
);
623 PIS(ULPSACTIVENOT_ALL0
);
624 PIS(ULPSACTIVENOT_ALL1
);
630 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
631 static void dsi_collect_irq_stats(struct platform_device
*dsidev
, u32 irqstatus
,
632 u32
*vcstatus
, u32 ciostatus
)
634 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
637 spin_lock(&dsi
->irq_stats_lock
);
639 dsi
->irq_stats
.irq_count
++;
640 dss_collect_irq_stats(irqstatus
, dsi
->irq_stats
.dsi_irqs
);
642 for (i
= 0; i
< 4; ++i
)
643 dss_collect_irq_stats(vcstatus
[i
], dsi
->irq_stats
.vc_irqs
[i
]);
645 dss_collect_irq_stats(ciostatus
, dsi
->irq_stats
.cio_irqs
);
647 spin_unlock(&dsi
->irq_stats_lock
);
650 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
653 static int debug_irq
;
655 static void dsi_handle_irq_errors(struct platform_device
*dsidev
, u32 irqstatus
,
656 u32
*vcstatus
, u32 ciostatus
)
658 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
661 if (irqstatus
& DSI_IRQ_ERROR_MASK
) {
662 DSSERR("DSI error, irqstatus %x\n", irqstatus
);
663 print_irq_status(irqstatus
);
664 spin_lock(&dsi
->errors_lock
);
665 dsi
->errors
|= irqstatus
& DSI_IRQ_ERROR_MASK
;
666 spin_unlock(&dsi
->errors_lock
);
667 } else if (debug_irq
) {
668 print_irq_status(irqstatus
);
671 for (i
= 0; i
< 4; ++i
) {
672 if (vcstatus
[i
] & DSI_VC_IRQ_ERROR_MASK
) {
673 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
675 print_irq_status_vc(i
, vcstatus
[i
]);
676 } else if (debug_irq
) {
677 print_irq_status_vc(i
, vcstatus
[i
]);
681 if (ciostatus
& DSI_CIO_IRQ_ERROR_MASK
) {
682 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus
);
683 print_irq_status_cio(ciostatus
);
684 } else if (debug_irq
) {
685 print_irq_status_cio(ciostatus
);
689 static void dsi_call_isrs(struct dsi_isr_data
*isr_array
,
690 unsigned isr_array_size
, u32 irqstatus
)
692 struct dsi_isr_data
*isr_data
;
695 for (i
= 0; i
< isr_array_size
; i
++) {
696 isr_data
= &isr_array
[i
];
697 if (isr_data
->isr
&& isr_data
->mask
& irqstatus
)
698 isr_data
->isr(isr_data
->arg
, irqstatus
);
702 static void dsi_handle_isrs(struct dsi_isr_tables
*isr_tables
,
703 u32 irqstatus
, u32
*vcstatus
, u32 ciostatus
)
707 dsi_call_isrs(isr_tables
->isr_table
,
708 ARRAY_SIZE(isr_tables
->isr_table
),
711 for (i
= 0; i
< 4; ++i
) {
712 if (vcstatus
[i
] == 0)
714 dsi_call_isrs(isr_tables
->isr_table_vc
[i
],
715 ARRAY_SIZE(isr_tables
->isr_table_vc
[i
]),
720 dsi_call_isrs(isr_tables
->isr_table_cio
,
721 ARRAY_SIZE(isr_tables
->isr_table_cio
),
725 static irqreturn_t
omap_dsi_irq_handler(int irq
, void *arg
)
727 struct platform_device
*dsidev
;
728 struct dsi_data
*dsi
;
729 u32 irqstatus
, vcstatus
[4], ciostatus
;
732 dsidev
= (struct platform_device
*) arg
;
733 dsi
= dsi_get_dsidrv_data(dsidev
);
735 spin_lock(&dsi
->irq_lock
);
737 irqstatus
= dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
739 /* IRQ is not for us */
741 spin_unlock(&dsi
->irq_lock
);
745 dsi_write_reg(dsidev
, DSI_IRQSTATUS
, irqstatus
& ~DSI_IRQ_CHANNEL_MASK
);
746 /* flush posted write */
747 dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
749 for (i
= 0; i
< 4; ++i
) {
750 if ((irqstatus
& (1 << i
)) == 0) {
755 vcstatus
[i
] = dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
757 dsi_write_reg(dsidev
, DSI_VC_IRQSTATUS(i
), vcstatus
[i
]);
758 /* flush posted write */
759 dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
762 if (irqstatus
& DSI_IRQ_COMPLEXIO_ERR
) {
763 ciostatus
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
765 dsi_write_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
, ciostatus
);
766 /* flush posted write */
767 dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
772 #ifdef DSI_CATCH_MISSING_TE
773 if (irqstatus
& DSI_IRQ_TE_TRIGGER
)
774 del_timer(&dsi
->te_timer
);
777 /* make a copy and unlock, so that isrs can unregister
779 memcpy(&dsi
->isr_tables_copy
, &dsi
->isr_tables
,
780 sizeof(dsi
->isr_tables
));
782 spin_unlock(&dsi
->irq_lock
);
784 dsi_handle_isrs(&dsi
->isr_tables_copy
, irqstatus
, vcstatus
, ciostatus
);
786 dsi_handle_irq_errors(dsidev
, irqstatus
, vcstatus
, ciostatus
);
788 dsi_collect_irq_stats(dsidev
, irqstatus
, vcstatus
, ciostatus
);
793 /* dsi->irq_lock has to be locked by the caller */
794 static void _omap_dsi_configure_irqs(struct platform_device
*dsidev
,
795 struct dsi_isr_data
*isr_array
,
796 unsigned isr_array_size
, u32 default_mask
,
797 const struct dsi_reg enable_reg
,
798 const struct dsi_reg status_reg
)
800 struct dsi_isr_data
*isr_data
;
807 for (i
= 0; i
< isr_array_size
; i
++) {
808 isr_data
= &isr_array
[i
];
810 if (isr_data
->isr
== NULL
)
813 mask
|= isr_data
->mask
;
816 old_mask
= dsi_read_reg(dsidev
, enable_reg
);
817 /* clear the irqstatus for newly enabled irqs */
818 dsi_write_reg(dsidev
, status_reg
, (mask
^ old_mask
) & mask
);
819 dsi_write_reg(dsidev
, enable_reg
, mask
);
821 /* flush posted writes */
822 dsi_read_reg(dsidev
, enable_reg
);
823 dsi_read_reg(dsidev
, status_reg
);
826 /* dsi->irq_lock has to be locked by the caller */
827 static void _omap_dsi_set_irqs(struct platform_device
*dsidev
)
829 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
830 u32 mask
= DSI_IRQ_ERROR_MASK
;
831 #ifdef DSI_CATCH_MISSING_TE
832 mask
|= DSI_IRQ_TE_TRIGGER
;
834 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table
,
835 ARRAY_SIZE(dsi
->isr_tables
.isr_table
), mask
,
836 DSI_IRQENABLE
, DSI_IRQSTATUS
);
839 /* dsi->irq_lock has to be locked by the caller */
840 static void _omap_dsi_set_irqs_vc(struct platform_device
*dsidev
, int vc
)
842 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
844 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_vc
[vc
],
845 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[vc
]),
846 DSI_VC_IRQ_ERROR_MASK
,
847 DSI_VC_IRQENABLE(vc
), DSI_VC_IRQSTATUS(vc
));
850 /* dsi->irq_lock has to be locked by the caller */
851 static void _omap_dsi_set_irqs_cio(struct platform_device
*dsidev
)
853 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
855 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_cio
,
856 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
),
857 DSI_CIO_IRQ_ERROR_MASK
,
858 DSI_COMPLEXIO_IRQ_ENABLE
, DSI_COMPLEXIO_IRQ_STATUS
);
861 static void _dsi_initialize_irq(struct platform_device
*dsidev
)
863 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
867 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
869 memset(&dsi
->isr_tables
, 0, sizeof(dsi
->isr_tables
));
871 _omap_dsi_set_irqs(dsidev
);
872 for (vc
= 0; vc
< 4; ++vc
)
873 _omap_dsi_set_irqs_vc(dsidev
, vc
);
874 _omap_dsi_set_irqs_cio(dsidev
);
876 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
879 static int _dsi_register_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
880 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
882 struct dsi_isr_data
*isr_data
;
888 /* check for duplicate entry and find a free slot */
890 for (i
= 0; i
< isr_array_size
; i
++) {
891 isr_data
= &isr_array
[i
];
893 if (isr_data
->isr
== isr
&& isr_data
->arg
== arg
&&
894 isr_data
->mask
== mask
) {
898 if (isr_data
->isr
== NULL
&& free_idx
== -1)
905 isr_data
= &isr_array
[free_idx
];
908 isr_data
->mask
= mask
;
913 static int _dsi_unregister_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
914 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
916 struct dsi_isr_data
*isr_data
;
919 for (i
= 0; i
< isr_array_size
; i
++) {
920 isr_data
= &isr_array
[i
];
921 if (isr_data
->isr
!= isr
|| isr_data
->arg
!= arg
||
922 isr_data
->mask
!= mask
)
925 isr_data
->isr
= NULL
;
926 isr_data
->arg
= NULL
;
935 static int dsi_register_isr(struct platform_device
*dsidev
, omap_dsi_isr_t isr
,
938 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
942 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
944 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
945 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
948 _omap_dsi_set_irqs(dsidev
);
950 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
955 static int dsi_unregister_isr(struct platform_device
*dsidev
,
956 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
958 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
962 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
964 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
965 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
968 _omap_dsi_set_irqs(dsidev
);
970 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
975 static int dsi_register_isr_vc(struct platform_device
*dsidev
, int channel
,
976 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
978 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
982 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
984 r
= _dsi_register_isr(isr
, arg
, mask
,
985 dsi
->isr_tables
.isr_table_vc
[channel
],
986 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
989 _omap_dsi_set_irqs_vc(dsidev
, channel
);
991 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
996 static int dsi_unregister_isr_vc(struct platform_device
*dsidev
, int channel
,
997 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
999 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1000 unsigned long flags
;
1003 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1005 r
= _dsi_unregister_isr(isr
, arg
, mask
,
1006 dsi
->isr_tables
.isr_table_vc
[channel
],
1007 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
1010 _omap_dsi_set_irqs_vc(dsidev
, channel
);
1012 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1017 static int dsi_register_isr_cio(struct platform_device
*dsidev
,
1018 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1020 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1021 unsigned long flags
;
1024 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1026 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1027 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1030 _omap_dsi_set_irqs_cio(dsidev
);
1032 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1037 static int dsi_unregister_isr_cio(struct platform_device
*dsidev
,
1038 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1040 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1041 unsigned long flags
;
1044 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1046 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1047 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1050 _omap_dsi_set_irqs_cio(dsidev
);
1052 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1057 static u32
dsi_get_errors(struct platform_device
*dsidev
)
1059 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1060 unsigned long flags
;
1062 spin_lock_irqsave(&dsi
->errors_lock
, flags
);
1065 spin_unlock_irqrestore(&dsi
->errors_lock
, flags
);
1069 int dsi_runtime_get(struct platform_device
*dsidev
)
1072 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1074 DSSDBG("dsi_runtime_get\n");
1076 r
= pm_runtime_get_sync(&dsi
->pdev
->dev
);
1078 return r
< 0 ? r
: 0;
1081 void dsi_runtime_put(struct platform_device
*dsidev
)
1083 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1086 DSSDBG("dsi_runtime_put\n");
1088 r
= pm_runtime_put(&dsi
->pdev
->dev
);
1092 /* source clock for DSI PLL. this could also be PCLKFREE */
1093 static inline void dsi_enable_pll_clock(struct platform_device
*dsidev
,
1096 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1099 clk_enable(dsi
->sys_clk
);
1101 clk_disable(dsi
->sys_clk
);
1103 if (enable
&& dsi
->pll_locked
) {
1104 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1)
1105 DSSERR("cannot lock PLL when enabling clocks\n");
1110 static void _dsi_print_reset_status(struct platform_device
*dsidev
)
1118 /* A dummy read using the SCP interface to any DSIPHY register is
1119 * required after DSIPHY reset to complete the reset of the DSI complex
1121 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
1123 printk(KERN_DEBUG
"DSI resets: ");
1125 l
= dsi_read_reg(dsidev
, DSI_PLL_STATUS
);
1126 printk("PLL (%d) ", FLD_GET(l
, 0, 0));
1128 l
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
);
1129 printk("CIO (%d) ", FLD_GET(l
, 29, 29));
1131 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
)) {
1141 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
1142 printk("PHY (%x%x%x, %d, %d, %d)\n",
1148 FLD_GET(l
, 31, 31));
1151 #define _dsi_print_reset_status(x)
1154 static inline int dsi_if_enable(struct platform_device
*dsidev
, bool enable
)
1156 DSSDBG("dsi_if_enable(%d)\n", enable
);
1158 enable
= enable
? 1 : 0;
1159 REG_FLD_MOD(dsidev
, DSI_CTRL
, enable
, 0, 0); /* IF_EN */
1161 if (wait_for_bit_change(dsidev
, DSI_CTRL
, 0, enable
) != enable
) {
1162 DSSERR("Failed to set dsi_if_enable to %d\n", enable
);
1169 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device
*dsidev
)
1171 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1173 return dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
;
1176 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device
*dsidev
)
1178 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1180 return dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
;
1183 static unsigned long dsi_get_txbyteclkhs(struct platform_device
*dsidev
)
1185 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1187 return dsi
->current_cinfo
.clkin4ddr
/ 16;
1190 static unsigned long dsi_fclk_rate(struct platform_device
*dsidev
)
1193 int dsi_module
= dsi_get_dsidev_id(dsidev
);
1194 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1196 if (dss_get_dsi_clk_source(dsi_module
) == OMAP_DSS_CLK_SRC_FCK
) {
1197 /* DSI FCLK source is DSS_CLK_FCK */
1198 r
= clk_get_rate(dsi
->dss_clk
);
1200 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1201 r
= dsi_get_pll_hsdiv_dsi_rate(dsidev
);
1207 static int dsi_set_lp_clk_divisor(struct omap_dss_device
*dssdev
)
1209 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
1210 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1211 unsigned long dsi_fclk
;
1212 unsigned lp_clk_div
;
1213 unsigned long lp_clk
;
1215 lp_clk_div
= dssdev
->clocks
.dsi
.lp_clk_div
;
1217 if (lp_clk_div
== 0 || lp_clk_div
> dsi
->lpdiv_max
)
1220 dsi_fclk
= dsi_fclk_rate(dsidev
);
1222 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
1224 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div
, lp_clk
);
1225 dsi
->current_cinfo
.lp_clk
= lp_clk
;
1226 dsi
->current_cinfo
.lp_clk_div
= lp_clk_div
;
1228 /* LP_CLK_DIVISOR */
1229 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, lp_clk_div
, 12, 0);
1231 /* LP_RX_SYNCHRO_ENABLE */
1232 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, dsi_fclk
> 30000000 ? 1 : 0, 21, 21);
1237 static void dsi_enable_scp_clk(struct platform_device
*dsidev
)
1239 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1241 if (dsi
->scp_clk_refcount
++ == 0)
1242 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 14, 14); /* CIO_CLK_ICG */
1245 static void dsi_disable_scp_clk(struct platform_device
*dsidev
)
1247 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1249 WARN_ON(dsi
->scp_clk_refcount
== 0);
1250 if (--dsi
->scp_clk_refcount
== 0)
1251 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 14, 14); /* CIO_CLK_ICG */
1254 enum dsi_pll_power_state
{
1255 DSI_PLL_POWER_OFF
= 0x0,
1256 DSI_PLL_POWER_ON_HSCLK
= 0x1,
1257 DSI_PLL_POWER_ON_ALL
= 0x2,
1258 DSI_PLL_POWER_ON_DIV
= 0x3,
1261 static int dsi_pll_power(struct platform_device
*dsidev
,
1262 enum dsi_pll_power_state state
)
1266 /* DSI-PLL power command 0x3 is not working */
1267 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG
) &&
1268 state
== DSI_PLL_POWER_ON_DIV
)
1269 state
= DSI_PLL_POWER_ON_ALL
;
1272 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, state
, 31, 30);
1274 /* PLL_PWR_STATUS */
1275 while (FLD_GET(dsi_read_reg(dsidev
, DSI_CLK_CTRL
), 29, 28) != state
) {
1277 DSSERR("Failed to set DSI PLL power mode to %d\n",
1287 /* calculate clock rates using dividers in cinfo */
1288 static int dsi_calc_clock_rates(struct omap_dss_device
*dssdev
,
1289 struct dsi_clock_info
*cinfo
)
1291 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
1292 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1294 if (cinfo
->regn
== 0 || cinfo
->regn
> dsi
->regn_max
)
1297 if (cinfo
->regm
== 0 || cinfo
->regm
> dsi
->regm_max
)
1300 if (cinfo
->regm_dispc
> dsi
->regm_dispc_max
)
1303 if (cinfo
->regm_dsi
> dsi
->regm_dsi_max
)
1306 if (cinfo
->use_sys_clk
) {
1307 cinfo
->clkin
= clk_get_rate(dsi
->sys_clk
);
1308 /* XXX it is unclear if highfreq should be used
1309 * with DSS_SYS_CLK source also */
1310 cinfo
->highfreq
= 0;
1312 cinfo
->clkin
= dispc_mgr_pclk_rate(dssdev
->manager
->id
);
1314 if (cinfo
->clkin
< 32000000)
1315 cinfo
->highfreq
= 0;
1317 cinfo
->highfreq
= 1;
1320 cinfo
->fint
= cinfo
->clkin
/ (cinfo
->regn
* (cinfo
->highfreq
? 2 : 1));
1322 if (cinfo
->fint
> dsi
->fint_max
|| cinfo
->fint
< dsi
->fint_min
)
1325 cinfo
->clkin4ddr
= 2 * cinfo
->regm
* cinfo
->fint
;
1327 if (cinfo
->clkin4ddr
> 1800 * 1000 * 1000)
1330 if (cinfo
->regm_dispc
> 0)
1331 cinfo
->dsi_pll_hsdiv_dispc_clk
=
1332 cinfo
->clkin4ddr
/ cinfo
->regm_dispc
;
1334 cinfo
->dsi_pll_hsdiv_dispc_clk
= 0;
1336 if (cinfo
->regm_dsi
> 0)
1337 cinfo
->dsi_pll_hsdiv_dsi_clk
=
1338 cinfo
->clkin4ddr
/ cinfo
->regm_dsi
;
1340 cinfo
->dsi_pll_hsdiv_dsi_clk
= 0;
1345 int dsi_pll_calc_clock_div_pck(struct platform_device
*dsidev
, bool is_tft
,
1346 unsigned long req_pck
, struct dsi_clock_info
*dsi_cinfo
,
1347 struct dispc_clock_info
*dispc_cinfo
)
1349 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1350 struct dsi_clock_info cur
, best
;
1351 struct dispc_clock_info best_dispc
;
1352 int min_fck_per_pck
;
1354 unsigned long dss_sys_clk
, max_dss_fck
;
1356 dss_sys_clk
= clk_get_rate(dsi
->sys_clk
);
1358 max_dss_fck
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
1360 if (req_pck
== dsi
->cache_req_pck
&&
1361 dsi
->cache_cinfo
.clkin
== dss_sys_clk
) {
1362 DSSDBG("DSI clock info found from cache\n");
1363 *dsi_cinfo
= dsi
->cache_cinfo
;
1364 dispc_find_clk_divs(is_tft
, req_pck
,
1365 dsi_cinfo
->dsi_pll_hsdiv_dispc_clk
, dispc_cinfo
);
1369 min_fck_per_pck
= CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
;
1371 if (min_fck_per_pck
&&
1372 req_pck
* min_fck_per_pck
> max_dss_fck
) {
1373 DSSERR("Requested pixel clock not possible with the current "
1374 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1375 "the constraint off.\n");
1376 min_fck_per_pck
= 0;
1379 DSSDBG("dsi_pll_calc\n");
1382 memset(&best
, 0, sizeof(best
));
1383 memset(&best_dispc
, 0, sizeof(best_dispc
));
1385 memset(&cur
, 0, sizeof(cur
));
1386 cur
.clkin
= dss_sys_clk
;
1387 cur
.use_sys_clk
= 1;
1390 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1391 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1392 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1393 for (cur
.regn
= 1; cur
.regn
< dsi
->regn_max
; ++cur
.regn
) {
1394 if (cur
.highfreq
== 0)
1395 cur
.fint
= cur
.clkin
/ cur
.regn
;
1397 cur
.fint
= cur
.clkin
/ (2 * cur
.regn
);
1399 if (cur
.fint
> dsi
->fint_max
|| cur
.fint
< dsi
->fint_min
)
1402 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1403 for (cur
.regm
= 1; cur
.regm
< dsi
->regm_max
; ++cur
.regm
) {
1406 a
= 2 * cur
.regm
* (cur
.clkin
/1000);
1407 b
= cur
.regn
* (cur
.highfreq
+ 1);
1408 cur
.clkin4ddr
= a
/ b
* 1000;
1410 if (cur
.clkin4ddr
> 1800 * 1000 * 1000)
1413 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1414 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1415 for (cur
.regm_dispc
= 1; cur
.regm_dispc
<
1416 dsi
->regm_dispc_max
; ++cur
.regm_dispc
) {
1417 struct dispc_clock_info cur_dispc
;
1418 cur
.dsi_pll_hsdiv_dispc_clk
=
1419 cur
.clkin4ddr
/ cur
.regm_dispc
;
1421 /* this will narrow down the search a bit,
1422 * but still give pixclocks below what was
1424 if (cur
.dsi_pll_hsdiv_dispc_clk
< req_pck
)
1427 if (cur
.dsi_pll_hsdiv_dispc_clk
> max_dss_fck
)
1430 if (min_fck_per_pck
&&
1431 cur
.dsi_pll_hsdiv_dispc_clk
<
1432 req_pck
* min_fck_per_pck
)
1437 dispc_find_clk_divs(is_tft
, req_pck
,
1438 cur
.dsi_pll_hsdiv_dispc_clk
,
1441 if (abs(cur_dispc
.pck
- req_pck
) <
1442 abs(best_dispc
.pck
- req_pck
)) {
1444 best_dispc
= cur_dispc
;
1446 if (cur_dispc
.pck
== req_pck
)
1454 if (min_fck_per_pck
) {
1455 DSSERR("Could not find suitable clock settings.\n"
1456 "Turning FCK/PCK constraint off and"
1458 min_fck_per_pck
= 0;
1462 DSSERR("Could not find suitable clock settings.\n");
1467 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1469 best
.dsi_pll_hsdiv_dsi_clk
= 0;
1474 *dispc_cinfo
= best_dispc
;
1476 dsi
->cache_req_pck
= req_pck
;
1477 dsi
->cache_clk_freq
= 0;
1478 dsi
->cache_cinfo
= best
;
1483 int dsi_pll_set_clock_div(struct platform_device
*dsidev
,
1484 struct dsi_clock_info
*cinfo
)
1486 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1490 u8 regn_start
, regn_end
, regm_start
, regm_end
;
1491 u8 regm_dispc_start
, regm_dispc_end
, regm_dsi_start
, regm_dsi_end
;
1495 dsi
->current_cinfo
.use_sys_clk
= cinfo
->use_sys_clk
;
1496 dsi
->current_cinfo
.highfreq
= cinfo
->highfreq
;
1498 dsi
->current_cinfo
.fint
= cinfo
->fint
;
1499 dsi
->current_cinfo
.clkin4ddr
= cinfo
->clkin4ddr
;
1500 dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
=
1501 cinfo
->dsi_pll_hsdiv_dispc_clk
;
1502 dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
=
1503 cinfo
->dsi_pll_hsdiv_dsi_clk
;
1505 dsi
->current_cinfo
.regn
= cinfo
->regn
;
1506 dsi
->current_cinfo
.regm
= cinfo
->regm
;
1507 dsi
->current_cinfo
.regm_dispc
= cinfo
->regm_dispc
;
1508 dsi
->current_cinfo
.regm_dsi
= cinfo
->regm_dsi
;
1510 DSSDBG("DSI Fint %ld\n", cinfo
->fint
);
1512 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1513 cinfo
->use_sys_clk
? "dss_sys_clk" : "pclkfree",
1517 /* DSIPHY == CLKIN4DDR */
1518 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1522 cinfo
->highfreq
+ 1,
1525 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1526 cinfo
->clkin4ddr
/ 1000 / 1000 / 2);
1528 DSSDBG("Clock lane freq %ld Hz\n", cinfo
->clkin4ddr
/ 4);
1530 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo
->regm_dispc
,
1531 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1532 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1533 cinfo
->dsi_pll_hsdiv_dispc_clk
);
1534 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo
->regm_dsi
,
1535 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1536 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1537 cinfo
->dsi_pll_hsdiv_dsi_clk
);
1539 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN
, ®n_start
, ®n_end
);
1540 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM
, ®m_start
, ®m_end
);
1541 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC
, ®m_dispc_start
,
1543 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI
, ®m_dsi_start
,
1546 /* DSI_PLL_AUTOMODE = manual */
1547 REG_FLD_MOD(dsidev
, DSI_PLL_CONTROL
, 0, 0, 0);
1549 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION1
);
1550 l
= FLD_MOD(l
, 1, 0, 0); /* DSI_PLL_STOPMODE */
1552 l
= FLD_MOD(l
, cinfo
->regn
- 1, regn_start
, regn_end
);
1554 l
= FLD_MOD(l
, cinfo
->regm
, regm_start
, regm_end
);
1556 l
= FLD_MOD(l
, cinfo
->regm_dispc
> 0 ? cinfo
->regm_dispc
- 1 : 0,
1557 regm_dispc_start
, regm_dispc_end
);
1558 /* DSIPROTO_CLOCK_DIV */
1559 l
= FLD_MOD(l
, cinfo
->regm_dsi
> 0 ? cinfo
->regm_dsi
- 1 : 0,
1560 regm_dsi_start
, regm_dsi_end
);
1561 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION1
, l
);
1563 BUG_ON(cinfo
->fint
< dsi
->fint_min
|| cinfo
->fint
> dsi
->fint_max
);
1565 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL
)) {
1566 f
= cinfo
->fint
< 1000000 ? 0x3 :
1567 cinfo
->fint
< 1250000 ? 0x4 :
1568 cinfo
->fint
< 1500000 ? 0x5 :
1569 cinfo
->fint
< 1750000 ? 0x6 :
1573 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1575 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL
))
1576 l
= FLD_MOD(l
, f
, 4, 1); /* DSI_PLL_FREQSEL */
1577 l
= FLD_MOD(l
, cinfo
->use_sys_clk
? 0 : 1,
1578 11, 11); /* DSI_PLL_CLKSEL */
1579 l
= FLD_MOD(l
, cinfo
->highfreq
,
1580 12, 12); /* DSI_PLL_HIGHFREQ */
1581 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1582 l
= FLD_MOD(l
, 0, 14, 14); /* DSIPHY_CLKINEN */
1583 l
= FLD_MOD(l
, 1, 20, 20); /* DSI_HSDIVBYPASS */
1584 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1586 REG_FLD_MOD(dsidev
, DSI_PLL_GO
, 1, 0, 0); /* DSI_PLL_GO */
1588 if (wait_for_bit_change(dsidev
, DSI_PLL_GO
, 0, 0) != 0) {
1589 DSSERR("dsi pll go bit not going down.\n");
1594 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1) {
1595 DSSERR("cannot lock PLL\n");
1600 dsi
->pll_locked
= 1;
1602 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1603 l
= FLD_MOD(l
, 0, 0, 0); /* DSI_PLL_IDLE */
1604 l
= FLD_MOD(l
, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1605 l
= FLD_MOD(l
, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1606 l
= FLD_MOD(l
, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1607 l
= FLD_MOD(l
, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1608 l
= FLD_MOD(l
, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1609 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1610 l
= FLD_MOD(l
, 1, 14, 14); /* DSIPHY_CLKINEN */
1611 l
= FLD_MOD(l
, 0, 15, 15); /* DSI_BYPASSEN */
1612 l
= FLD_MOD(l
, 1, 16, 16); /* DSS_CLOCK_EN */
1613 l
= FLD_MOD(l
, 0, 17, 17); /* DSS_CLOCK_PWDN */
1614 l
= FLD_MOD(l
, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1615 l
= FLD_MOD(l
, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1616 l
= FLD_MOD(l
, 0, 20, 20); /* DSI_HSDIVBYPASS */
1617 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1619 DSSDBG("PLL config done\n");
1624 int dsi_pll_init(struct platform_device
*dsidev
, bool enable_hsclk
,
1627 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1629 enum dsi_pll_power_state pwstate
;
1631 DSSDBG("PLL init\n");
1633 if (dsi
->vdds_dsi_reg
== NULL
) {
1634 struct regulator
*vdds_dsi
;
1636 vdds_dsi
= regulator_get(&dsi
->pdev
->dev
, "vdds_dsi");
1638 if (IS_ERR(vdds_dsi
)) {
1639 DSSERR("can't get VDDS_DSI regulator\n");
1640 return PTR_ERR(vdds_dsi
);
1643 dsi
->vdds_dsi_reg
= vdds_dsi
;
1646 dsi_enable_pll_clock(dsidev
, 1);
1648 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1650 dsi_enable_scp_clk(dsidev
);
1652 if (!dsi
->vdds_dsi_enabled
) {
1653 r
= regulator_enable(dsi
->vdds_dsi_reg
);
1656 dsi
->vdds_dsi_enabled
= true;
1659 /* XXX PLL does not come out of reset without this... */
1660 dispc_pck_free_enable(1);
1662 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 0, 1) != 1) {
1663 DSSERR("PLL not coming out of reset.\n");
1665 dispc_pck_free_enable(0);
1669 /* XXX ... but if left on, we get problems when planes do not
1670 * fill the whole display. No idea about this */
1671 dispc_pck_free_enable(0);
1673 if (enable_hsclk
&& enable_hsdiv
)
1674 pwstate
= DSI_PLL_POWER_ON_ALL
;
1675 else if (enable_hsclk
)
1676 pwstate
= DSI_PLL_POWER_ON_HSCLK
;
1677 else if (enable_hsdiv
)
1678 pwstate
= DSI_PLL_POWER_ON_DIV
;
1680 pwstate
= DSI_PLL_POWER_OFF
;
1682 r
= dsi_pll_power(dsidev
, pwstate
);
1687 DSSDBG("PLL init done\n");
1691 if (dsi
->vdds_dsi_enabled
) {
1692 regulator_disable(dsi
->vdds_dsi_reg
);
1693 dsi
->vdds_dsi_enabled
= false;
1696 dsi_disable_scp_clk(dsidev
);
1697 dsi_enable_pll_clock(dsidev
, 0);
1701 void dsi_pll_uninit(struct platform_device
*dsidev
, bool disconnect_lanes
)
1703 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1705 dsi
->pll_locked
= 0;
1706 dsi_pll_power(dsidev
, DSI_PLL_POWER_OFF
);
1707 if (disconnect_lanes
) {
1708 WARN_ON(!dsi
->vdds_dsi_enabled
);
1709 regulator_disable(dsi
->vdds_dsi_reg
);
1710 dsi
->vdds_dsi_enabled
= false;
1713 dsi_disable_scp_clk(dsidev
);
1714 dsi_enable_pll_clock(dsidev
, 0);
1716 DSSDBG("PLL uninit done\n");
1719 static void dsi_dump_dsidev_clocks(struct platform_device
*dsidev
,
1722 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1723 struct dsi_clock_info
*cinfo
= &dsi
->current_cinfo
;
1724 enum omap_dss_clk_source dispc_clk_src
, dsi_clk_src
;
1725 int dsi_module
= dsi_get_dsidev_id(dsidev
);
1727 dispc_clk_src
= dss_get_dispc_clk_source();
1728 dsi_clk_src
= dss_get_dsi_clk_source(dsi_module
);
1730 if (dsi_runtime_get(dsidev
))
1733 seq_printf(s
, "- DSI%d PLL -\n", dsi_module
+ 1);
1735 seq_printf(s
, "dsi pll source = %s\n",
1736 cinfo
->use_sys_clk
? "dss_sys_clk" : "pclkfree");
1738 seq_printf(s
, "Fint\t\t%-16luregn %u\n", cinfo
->fint
, cinfo
->regn
);
1740 seq_printf(s
, "CLKIN4DDR\t%-16luregm %u\n",
1741 cinfo
->clkin4ddr
, cinfo
->regm
);
1743 seq_printf(s
, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1744 dss_get_generic_clk_source_name(dispc_clk_src
),
1745 dss_feat_get_clk_source_name(dispc_clk_src
),
1746 cinfo
->dsi_pll_hsdiv_dispc_clk
,
1748 dispc_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1751 seq_printf(s
, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1752 dss_get_generic_clk_source_name(dsi_clk_src
),
1753 dss_feat_get_clk_source_name(dsi_clk_src
),
1754 cinfo
->dsi_pll_hsdiv_dsi_clk
,
1756 dsi_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1759 seq_printf(s
, "- DSI%d -\n", dsi_module
+ 1);
1761 seq_printf(s
, "dsi fclk source = %s (%s)\n",
1762 dss_get_generic_clk_source_name(dsi_clk_src
),
1763 dss_feat_get_clk_source_name(dsi_clk_src
));
1765 seq_printf(s
, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev
));
1767 seq_printf(s
, "DDR_CLK\t\t%lu\n",
1768 cinfo
->clkin4ddr
/ 4);
1770 seq_printf(s
, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev
));
1772 seq_printf(s
, "LP_CLK\t\t%lu\n", cinfo
->lp_clk
);
1774 dsi_runtime_put(dsidev
);
1777 void dsi_dump_clocks(struct seq_file
*s
)
1779 struct platform_device
*dsidev
;
1782 for (i
= 0; i
< MAX_NUM_DSI
; i
++) {
1783 dsidev
= dsi_get_dsidev_from_id(i
);
1785 dsi_dump_dsidev_clocks(dsidev
, s
);
1789 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1790 static void dsi_dump_dsidev_irqs(struct platform_device
*dsidev
,
1793 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1794 unsigned long flags
;
1795 struct dsi_irq_stats stats
;
1796 int dsi_module
= dsi_get_dsidev_id(dsidev
);
1798 spin_lock_irqsave(&dsi
->irq_stats_lock
, flags
);
1800 stats
= dsi
->irq_stats
;
1801 memset(&dsi
->irq_stats
, 0, sizeof(dsi
->irq_stats
));
1802 dsi
->irq_stats
.last_reset
= jiffies
;
1804 spin_unlock_irqrestore(&dsi
->irq_stats_lock
, flags
);
1806 seq_printf(s
, "period %u ms\n",
1807 jiffies_to_msecs(jiffies
- stats
.last_reset
));
1809 seq_printf(s
, "irqs %d\n", stats
.irq_count
);
1811 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1813 seq_printf(s
, "-- DSI%d interrupts --\n", dsi_module
+ 1);
1829 PIS(LDO_POWER_GOOD
);
1834 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1835 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1836 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1837 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1838 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1840 seq_printf(s
, "-- VC interrupts --\n");
1849 PIS(PP_BUSY_CHANGE
);
1853 seq_printf(s, "%-20s %10d\n", #x, \
1854 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1856 seq_printf(s
, "-- CIO interrupts --\n");
1869 PIS(ERRCONTENTIONLP0_1
);
1870 PIS(ERRCONTENTIONLP1_1
);
1871 PIS(ERRCONTENTIONLP0_2
);
1872 PIS(ERRCONTENTIONLP1_2
);
1873 PIS(ERRCONTENTIONLP0_3
);
1874 PIS(ERRCONTENTIONLP1_3
);
1875 PIS(ULPSACTIVENOT_ALL0
);
1876 PIS(ULPSACTIVENOT_ALL1
);
1880 static void dsi1_dump_irqs(struct seq_file
*s
)
1882 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1884 dsi_dump_dsidev_irqs(dsidev
, s
);
1887 static void dsi2_dump_irqs(struct seq_file
*s
)
1889 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
1891 dsi_dump_dsidev_irqs(dsidev
, s
);
1894 void dsi_create_debugfs_files_irq(struct dentry
*debugfs_dir
,
1895 const struct file_operations
*debug_fops
)
1897 struct platform_device
*dsidev
;
1899 dsidev
= dsi_get_dsidev_from_id(0);
1901 debugfs_create_file("dsi1_irqs", S_IRUGO
, debugfs_dir
,
1902 &dsi1_dump_irqs
, debug_fops
);
1904 dsidev
= dsi_get_dsidev_from_id(1);
1906 debugfs_create_file("dsi2_irqs", S_IRUGO
, debugfs_dir
,
1907 &dsi2_dump_irqs
, debug_fops
);
1911 static void dsi_dump_dsidev_regs(struct platform_device
*dsidev
,
1914 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1916 if (dsi_runtime_get(dsidev
))
1918 dsi_enable_scp_clk(dsidev
);
1920 DUMPREG(DSI_REVISION
);
1921 DUMPREG(DSI_SYSCONFIG
);
1922 DUMPREG(DSI_SYSSTATUS
);
1923 DUMPREG(DSI_IRQSTATUS
);
1924 DUMPREG(DSI_IRQENABLE
);
1926 DUMPREG(DSI_COMPLEXIO_CFG1
);
1927 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS
);
1928 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE
);
1929 DUMPREG(DSI_CLK_CTRL
);
1930 DUMPREG(DSI_TIMING1
);
1931 DUMPREG(DSI_TIMING2
);
1932 DUMPREG(DSI_VM_TIMING1
);
1933 DUMPREG(DSI_VM_TIMING2
);
1934 DUMPREG(DSI_VM_TIMING3
);
1935 DUMPREG(DSI_CLK_TIMING
);
1936 DUMPREG(DSI_TX_FIFO_VC_SIZE
);
1937 DUMPREG(DSI_RX_FIFO_VC_SIZE
);
1938 DUMPREG(DSI_COMPLEXIO_CFG2
);
1939 DUMPREG(DSI_RX_FIFO_VC_FULLNESS
);
1940 DUMPREG(DSI_VM_TIMING4
);
1941 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS
);
1942 DUMPREG(DSI_VM_TIMING5
);
1943 DUMPREG(DSI_VM_TIMING6
);
1944 DUMPREG(DSI_VM_TIMING7
);
1945 DUMPREG(DSI_STOPCLK_TIMING
);
1947 DUMPREG(DSI_VC_CTRL(0));
1948 DUMPREG(DSI_VC_TE(0));
1949 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1950 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1951 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1952 DUMPREG(DSI_VC_IRQSTATUS(0));
1953 DUMPREG(DSI_VC_IRQENABLE(0));
1955 DUMPREG(DSI_VC_CTRL(1));
1956 DUMPREG(DSI_VC_TE(1));
1957 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1958 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1959 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1960 DUMPREG(DSI_VC_IRQSTATUS(1));
1961 DUMPREG(DSI_VC_IRQENABLE(1));
1963 DUMPREG(DSI_VC_CTRL(2));
1964 DUMPREG(DSI_VC_TE(2));
1965 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1966 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1967 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1968 DUMPREG(DSI_VC_IRQSTATUS(2));
1969 DUMPREG(DSI_VC_IRQENABLE(2));
1971 DUMPREG(DSI_VC_CTRL(3));
1972 DUMPREG(DSI_VC_TE(3));
1973 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1974 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1975 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1976 DUMPREG(DSI_VC_IRQSTATUS(3));
1977 DUMPREG(DSI_VC_IRQENABLE(3));
1979 DUMPREG(DSI_DSIPHY_CFG0
);
1980 DUMPREG(DSI_DSIPHY_CFG1
);
1981 DUMPREG(DSI_DSIPHY_CFG2
);
1982 DUMPREG(DSI_DSIPHY_CFG5
);
1984 DUMPREG(DSI_PLL_CONTROL
);
1985 DUMPREG(DSI_PLL_STATUS
);
1986 DUMPREG(DSI_PLL_GO
);
1987 DUMPREG(DSI_PLL_CONFIGURATION1
);
1988 DUMPREG(DSI_PLL_CONFIGURATION2
);
1990 dsi_disable_scp_clk(dsidev
);
1991 dsi_runtime_put(dsidev
);
1995 static void dsi1_dump_regs(struct seq_file
*s
)
1997 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1999 dsi_dump_dsidev_regs(dsidev
, s
);
2002 static void dsi2_dump_regs(struct seq_file
*s
)
2004 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
2006 dsi_dump_dsidev_regs(dsidev
, s
);
2009 void dsi_create_debugfs_files_reg(struct dentry
*debugfs_dir
,
2010 const struct file_operations
*debug_fops
)
2012 struct platform_device
*dsidev
;
2014 dsidev
= dsi_get_dsidev_from_id(0);
2016 debugfs_create_file("dsi1_regs", S_IRUGO
, debugfs_dir
,
2017 &dsi1_dump_regs
, debug_fops
);
2019 dsidev
= dsi_get_dsidev_from_id(1);
2021 debugfs_create_file("dsi2_regs", S_IRUGO
, debugfs_dir
,
2022 &dsi2_dump_regs
, debug_fops
);
2024 enum dsi_cio_power_state
{
2025 DSI_COMPLEXIO_POWER_OFF
= 0x0,
2026 DSI_COMPLEXIO_POWER_ON
= 0x1,
2027 DSI_COMPLEXIO_POWER_ULPS
= 0x2,
2030 static int dsi_cio_power(struct platform_device
*dsidev
,
2031 enum dsi_cio_power_state state
)
2036 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG1
, state
, 28, 27);
2039 while (FLD_GET(dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
),
2042 DSSERR("failed to set complexio power state to "
2052 static unsigned dsi_get_line_buf_size(struct platform_device
*dsidev
)
2056 /* line buffer on OMAP3 is 1024 x 24bits */
2057 /* XXX: for some reason using full buffer size causes
2058 * considerable TX slowdown with update sizes that fill the
2060 if (!dss_has_feature(FEAT_DSI_GNQ
))
2063 val
= REG_GET(dsidev
, DSI_GNQ
, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2067 return 512 * 3; /* 512x24 bits */
2069 return 682 * 3; /* 682x24 bits */
2071 return 853 * 3; /* 853x24 bits */
2073 return 1024 * 3; /* 1024x24 bits */
2075 return 1194 * 3; /* 1194x24 bits */
2077 return 1365 * 3; /* 1365x24 bits */
2083 static int dsi_parse_lane_config(struct omap_dss_device
*dssdev
)
2085 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2086 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2087 u8 lanes
[DSI_MAX_NR_LANES
];
2088 u8 polarities
[DSI_MAX_NR_LANES
];
2091 static const enum dsi_lane_function functions
[] = {
2099 lanes
[0] = dssdev
->phy
.dsi
.clk_lane
;
2100 lanes
[1] = dssdev
->phy
.dsi
.data1_lane
;
2101 lanes
[2] = dssdev
->phy
.dsi
.data2_lane
;
2102 lanes
[3] = dssdev
->phy
.dsi
.data3_lane
;
2103 lanes
[4] = dssdev
->phy
.dsi
.data4_lane
;
2104 polarities
[0] = dssdev
->phy
.dsi
.clk_pol
;
2105 polarities
[1] = dssdev
->phy
.dsi
.data1_pol
;
2106 polarities
[2] = dssdev
->phy
.dsi
.data2_pol
;
2107 polarities
[3] = dssdev
->phy
.dsi
.data3_pol
;
2108 polarities
[4] = dssdev
->phy
.dsi
.data4_pol
;
2112 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
)
2113 dsi
->lanes
[i
].function
= DSI_LANE_UNUSED
;
2115 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2118 if (lanes
[i
] == DSI_LANE_UNUSED
)
2123 if (num
>= dsi
->num_lanes_supported
)
2126 if (dsi
->lanes
[num
].function
!= DSI_LANE_UNUSED
)
2129 dsi
->lanes
[num
].function
= functions
[i
];
2130 dsi
->lanes
[num
].polarity
= polarities
[i
];
2134 if (num_lanes
< 2 || num_lanes
> dsi
->num_lanes_supported
)
2137 dsi
->num_lanes_used
= num_lanes
;
2142 static int dsi_set_lane_config(struct omap_dss_device
*dssdev
)
2144 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2145 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2146 static const u8 offsets
[] = { 0, 4, 8, 12, 16 };
2147 static const enum dsi_lane_function functions
[] = {
2157 r
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
);
2159 for (i
= 0; i
< dsi
->num_lanes_used
; ++i
) {
2160 unsigned offset
= offsets
[i
];
2161 unsigned polarity
, lane_number
;
2164 for (t
= 0; t
< dsi
->num_lanes_supported
; ++t
)
2165 if (dsi
->lanes
[t
].function
== functions
[i
])
2168 if (t
== dsi
->num_lanes_supported
)
2172 polarity
= dsi
->lanes
[t
].polarity
;
2174 r
= FLD_MOD(r
, lane_number
+ 1, offset
+ 2, offset
);
2175 r
= FLD_MOD(r
, polarity
, offset
+ 3, offset
+ 3);
2178 /* clear the unused lanes */
2179 for (; i
< dsi
->num_lanes_supported
; ++i
) {
2180 unsigned offset
= offsets
[i
];
2182 r
= FLD_MOD(r
, 0, offset
+ 2, offset
);
2183 r
= FLD_MOD(r
, 0, offset
+ 3, offset
+ 3);
2186 dsi_write_reg(dsidev
, DSI_COMPLEXIO_CFG1
, r
);
2191 static inline unsigned ns2ddr(struct platform_device
*dsidev
, unsigned ns
)
2193 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2195 /* convert time in ns to ddr ticks, rounding up */
2196 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2197 return (ns
* (ddr_clk
/ 1000 / 1000) + 999) / 1000;
2200 static inline unsigned ddr2ns(struct platform_device
*dsidev
, unsigned ddr
)
2202 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2204 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2205 return ddr
* 1000 * 1000 / (ddr_clk
/ 1000);
2208 static void dsi_cio_timings(struct platform_device
*dsidev
)
2211 u32 ths_prepare
, ths_prepare_ths_zero
, ths_trail
, ths_exit
;
2212 u32 tlpx_half
, tclk_trail
, tclk_zero
;
2215 /* calculate timings */
2217 /* 1 * DDR_CLK = 2 * UI */
2219 /* min 40ns + 4*UI max 85ns + 6*UI */
2220 ths_prepare
= ns2ddr(dsidev
, 70) + 2;
2222 /* min 145ns + 10*UI */
2223 ths_prepare_ths_zero
= ns2ddr(dsidev
, 175) + 2;
2225 /* min max(8*UI, 60ns+4*UI) */
2226 ths_trail
= ns2ddr(dsidev
, 60) + 5;
2229 ths_exit
= ns2ddr(dsidev
, 145);
2232 tlpx_half
= ns2ddr(dsidev
, 25);
2235 tclk_trail
= ns2ddr(dsidev
, 60) + 2;
2237 /* min 38ns, max 95ns */
2238 tclk_prepare
= ns2ddr(dsidev
, 65);
2240 /* min tclk-prepare + tclk-zero = 300ns */
2241 tclk_zero
= ns2ddr(dsidev
, 260);
2243 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2244 ths_prepare
, ddr2ns(dsidev
, ths_prepare
),
2245 ths_prepare_ths_zero
, ddr2ns(dsidev
, ths_prepare_ths_zero
));
2246 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2247 ths_trail
, ddr2ns(dsidev
, ths_trail
),
2248 ths_exit
, ddr2ns(dsidev
, ths_exit
));
2250 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2251 "tclk_zero %u (%uns)\n",
2252 tlpx_half
, ddr2ns(dsidev
, tlpx_half
),
2253 tclk_trail
, ddr2ns(dsidev
, tclk_trail
),
2254 tclk_zero
, ddr2ns(dsidev
, tclk_zero
));
2255 DSSDBG("tclk_prepare %u (%uns)\n",
2256 tclk_prepare
, ddr2ns(dsidev
, tclk_prepare
));
2258 /* program timings */
2260 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
2261 r
= FLD_MOD(r
, ths_prepare
, 31, 24);
2262 r
= FLD_MOD(r
, ths_prepare_ths_zero
, 23, 16);
2263 r
= FLD_MOD(r
, ths_trail
, 15, 8);
2264 r
= FLD_MOD(r
, ths_exit
, 7, 0);
2265 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG0
, r
);
2267 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
2268 r
= FLD_MOD(r
, tlpx_half
, 22, 16);
2269 r
= FLD_MOD(r
, tclk_trail
, 15, 8);
2270 r
= FLD_MOD(r
, tclk_zero
, 7, 0);
2271 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG1
, r
);
2273 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
2274 r
= FLD_MOD(r
, tclk_prepare
, 7, 0);
2275 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG2
, r
);
2278 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2279 static void dsi_cio_enable_lane_override(struct omap_dss_device
*dssdev
,
2280 unsigned mask_p
, unsigned mask_n
)
2282 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2283 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2286 u8 lptxscp_start
= dsi
->num_lanes_supported
== 3 ? 22 : 26;
2290 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2291 unsigned p
= dsi
->lanes
[i
].polarity
;
2293 if (mask_p
& (1 << i
))
2294 l
|= 1 << (i
* 2 + (p
? 0 : 1));
2296 if (mask_n
& (1 << i
))
2297 l
|= 1 << (i
* 2 + (p
? 1 : 0));
2301 * Bits in REGLPTXSCPDAT4TO0DXDY:
2309 /* Set the lane override configuration */
2311 /* REGLPTXSCPDAT4TO0DXDY */
2312 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, l
, lptxscp_start
, 17);
2314 /* Enable lane override */
2317 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 1, 27, 27);
2320 static void dsi_cio_disable_lane_override(struct platform_device
*dsidev
)
2322 /* Disable lane override */
2323 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 27, 27); /* ENLPTXSCPDAT */
2324 /* Reset the lane override configuration */
2325 /* REGLPTXSCPDAT4TO0DXDY */
2326 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 22, 17);
2329 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device
*dssdev
)
2331 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2332 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2334 bool in_use
[DSI_MAX_NR_LANES
];
2335 static const u8 offsets_old
[] = { 28, 27, 26 };
2336 static const u8 offsets_new
[] = { 24, 25, 26, 27, 28 };
2339 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
))
2340 offsets
= offsets_old
;
2342 offsets
= offsets_new
;
2344 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
)
2345 in_use
[i
] = dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
;
2352 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2355 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2356 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2360 if (ok
== dsi
->num_lanes_supported
)
2364 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2365 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2368 DSSERR("CIO TXCLKESC%d domain not coming " \
2369 "out of reset\n", i
);
2378 /* return bitmask of enabled lanes, lane0 being the lsb */
2379 static unsigned dsi_get_lane_mask(struct omap_dss_device
*dssdev
)
2381 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2382 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2386 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2387 if (dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
)
2394 static int dsi_cio_init(struct omap_dss_device
*dssdev
)
2396 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2397 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2403 r
= dsi
->enable_pads(dsidev
->id
, dsi_get_lane_mask(dssdev
));
2407 dsi_enable_scp_clk(dsidev
);
2409 /* A dummy read using the SCP interface to any DSIPHY register is
2410 * required after DSIPHY reset to complete the reset of the DSI complex
2412 dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2414 if (wait_for_bit_change(dsidev
, DSI_DSIPHY_CFG5
, 30, 1) != 1) {
2415 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2417 goto err_scp_clk_dom
;
2420 r
= dsi_set_lane_config(dssdev
);
2422 goto err_scp_clk_dom
;
2424 /* set TX STOP MODE timer to maximum for this operation */
2425 l
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2426 l
= FLD_MOD(l
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2427 l
= FLD_MOD(l
, 1, 14, 14); /* STOP_STATE_X16_IO */
2428 l
= FLD_MOD(l
, 1, 13, 13); /* STOP_STATE_X4_IO */
2429 l
= FLD_MOD(l
, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2430 dsi_write_reg(dsidev
, DSI_TIMING1
, l
);
2432 if (dsi
->ulps_enabled
) {
2436 DSSDBG("manual ulps exit\n");
2438 /* ULPS is exited by Mark-1 state for 1ms, followed by
2439 * stop state. DSS HW cannot do this via the normal
2440 * ULPS exit sequence, as after reset the DSS HW thinks
2441 * that we are not in ULPS mode, and refuses to send the
2442 * sequence. So we need to send the ULPS exit sequence
2443 * manually by setting positive lines high and negative lines
2449 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2450 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
2455 dsi_cio_enable_lane_override(dssdev
, mask_p
, 0);
2458 r
= dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ON
);
2462 if (wait_for_bit_change(dsidev
, DSI_COMPLEXIO_CFG1
, 29, 1) != 1) {
2463 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2465 goto err_cio_pwr_dom
;
2468 dsi_if_enable(dsidev
, true);
2469 dsi_if_enable(dsidev
, false);
2470 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 20, 20); /* LP_CLK_ENABLE */
2472 r
= dsi_cio_wait_tx_clk_esc_reset(dssdev
);
2474 goto err_tx_clk_esc_rst
;
2476 if (dsi
->ulps_enabled
) {
2477 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2478 ktime_t wait
= ns_to_ktime(1000 * 1000);
2479 set_current_state(TASK_UNINTERRUPTIBLE
);
2480 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
2482 /* Disable the override. The lanes should be set to Mark-11
2483 * state by the HW */
2484 dsi_cio_disable_lane_override(dsidev
);
2487 /* FORCE_TX_STOP_MODE_IO */
2488 REG_FLD_MOD(dsidev
, DSI_TIMING1
, 0, 15, 15);
2490 dsi_cio_timings(dsidev
);
2492 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
2493 /* DDR_CLK_ALWAYS_ON */
2494 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
,
2495 dssdev
->panel
.dsi_vm_data
.ddr_clk_always_on
, 13, 13);
2498 dsi
->ulps_enabled
= false;
2500 DSSDBG("CIO init done\n");
2505 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 20, 20); /* LP_CLK_ENABLE */
2507 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2509 if (dsi
->ulps_enabled
)
2510 dsi_cio_disable_lane_override(dsidev
);
2512 dsi_disable_scp_clk(dsidev
);
2513 dsi
->disable_pads(dsidev
->id
, dsi_get_lane_mask(dssdev
));
2517 static void dsi_cio_uninit(struct omap_dss_device
*dssdev
)
2519 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2520 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2522 /* DDR_CLK_ALWAYS_ON */
2523 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
2525 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2526 dsi_disable_scp_clk(dsidev
);
2527 dsi
->disable_pads(dsidev
->id
, dsi_get_lane_mask(dssdev
));
2530 static void dsi_config_tx_fifo(struct platform_device
*dsidev
,
2531 enum fifo_size size1
, enum fifo_size size2
,
2532 enum fifo_size size3
, enum fifo_size size4
)
2534 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2539 dsi
->vc
[0].fifo_size
= size1
;
2540 dsi
->vc
[1].fifo_size
= size2
;
2541 dsi
->vc
[2].fifo_size
= size3
;
2542 dsi
->vc
[3].fifo_size
= size4
;
2544 for (i
= 0; i
< 4; i
++) {
2546 int size
= dsi
->vc
[i
].fifo_size
;
2548 if (add
+ size
> 4) {
2549 DSSERR("Illegal FIFO configuration\n");
2553 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2555 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2559 dsi_write_reg(dsidev
, DSI_TX_FIFO_VC_SIZE
, r
);
2562 static void dsi_config_rx_fifo(struct platform_device
*dsidev
,
2563 enum fifo_size size1
, enum fifo_size size2
,
2564 enum fifo_size size3
, enum fifo_size size4
)
2566 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2571 dsi
->vc
[0].fifo_size
= size1
;
2572 dsi
->vc
[1].fifo_size
= size2
;
2573 dsi
->vc
[2].fifo_size
= size3
;
2574 dsi
->vc
[3].fifo_size
= size4
;
2576 for (i
= 0; i
< 4; i
++) {
2578 int size
= dsi
->vc
[i
].fifo_size
;
2580 if (add
+ size
> 4) {
2581 DSSERR("Illegal FIFO configuration\n");
2585 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2587 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2591 dsi_write_reg(dsidev
, DSI_RX_FIFO_VC_SIZE
, r
);
2594 static int dsi_force_tx_stop_mode_io(struct platform_device
*dsidev
)
2598 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2599 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2600 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
2602 if (wait_for_bit_change(dsidev
, DSI_TIMING1
, 15, 0) != 0) {
2603 DSSERR("TX_STOP bit not going down\n");
2610 static bool dsi_vc_is_enabled(struct platform_device
*dsidev
, int channel
)
2612 return REG_GET(dsidev
, DSI_VC_CTRL(channel
), 0, 0);
2615 static void dsi_packet_sent_handler_vp(void *data
, u32 mask
)
2617 struct dsi_packet_sent_handler_data
*vp_data
=
2618 (struct dsi_packet_sent_handler_data
*) data
;
2619 struct dsi_data
*dsi
= dsi_get_dsidrv_data(vp_data
->dsidev
);
2620 const int channel
= dsi
->update_channel
;
2621 u8 bit
= dsi
->te_enabled
? 30 : 31;
2623 if (REG_GET(vp_data
->dsidev
, DSI_VC_TE(channel
), bit
, bit
) == 0)
2624 complete(vp_data
->completion
);
2627 static int dsi_sync_vc_vp(struct platform_device
*dsidev
, int channel
)
2629 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2630 DECLARE_COMPLETION_ONSTACK(completion
);
2631 struct dsi_packet_sent_handler_data vp_data
= { dsidev
, &completion
};
2635 bit
= dsi
->te_enabled
? 30 : 31;
2637 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2638 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2642 /* Wait for completion only if TE_EN/TE_START is still set */
2643 if (REG_GET(dsidev
, DSI_VC_TE(channel
), bit
, bit
)) {
2644 if (wait_for_completion_timeout(&completion
,
2645 msecs_to_jiffies(10)) == 0) {
2646 DSSERR("Failed to complete previous frame transfer\n");
2652 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2653 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2657 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2658 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2663 static void dsi_packet_sent_handler_l4(void *data
, u32 mask
)
2665 struct dsi_packet_sent_handler_data
*l4_data
=
2666 (struct dsi_packet_sent_handler_data
*) data
;
2667 struct dsi_data
*dsi
= dsi_get_dsidrv_data(l4_data
->dsidev
);
2668 const int channel
= dsi
->update_channel
;
2670 if (REG_GET(l4_data
->dsidev
, DSI_VC_CTRL(channel
), 5, 5) == 0)
2671 complete(l4_data
->completion
);
2674 static int dsi_sync_vc_l4(struct platform_device
*dsidev
, int channel
)
2676 DECLARE_COMPLETION_ONSTACK(completion
);
2677 struct dsi_packet_sent_handler_data l4_data
= { dsidev
, &completion
};
2680 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2681 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2685 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2686 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 5, 5)) {
2687 if (wait_for_completion_timeout(&completion
,
2688 msecs_to_jiffies(10)) == 0) {
2689 DSSERR("Failed to complete previous l4 transfer\n");
2695 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2696 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2700 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2701 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2706 static int dsi_sync_vc(struct platform_device
*dsidev
, int channel
)
2708 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2710 WARN_ON(!dsi_bus_is_locked(dsidev
));
2712 WARN_ON(in_interrupt());
2714 if (!dsi_vc_is_enabled(dsidev
, channel
))
2717 switch (dsi
->vc
[channel
].source
) {
2718 case DSI_VC_SOURCE_VP
:
2719 return dsi_sync_vc_vp(dsidev
, channel
);
2720 case DSI_VC_SOURCE_L4
:
2721 return dsi_sync_vc_l4(dsidev
, channel
);
2727 static int dsi_vc_enable(struct platform_device
*dsidev
, int channel
,
2730 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2733 enable
= enable
? 1 : 0;
2735 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 0, 0);
2737 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
),
2738 0, enable
) != enable
) {
2739 DSSERR("Failed to set dsi_vc_enable to %d\n", enable
);
2746 static void dsi_vc_initial_config(struct platform_device
*dsidev
, int channel
)
2750 DSSDBGF("%d", channel
);
2752 r
= dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2754 if (FLD_GET(r
, 15, 15)) /* VC_BUSY */
2755 DSSERR("VC(%d) busy when trying to configure it!\n",
2758 r
= FLD_MOD(r
, 0, 1, 1); /* SOURCE, 0 = L4 */
2759 r
= FLD_MOD(r
, 0, 2, 2); /* BTA_SHORT_EN */
2760 r
= FLD_MOD(r
, 0, 3, 3); /* BTA_LONG_EN */
2761 r
= FLD_MOD(r
, 0, 4, 4); /* MODE, 0 = command */
2762 r
= FLD_MOD(r
, 1, 7, 7); /* CS_TX_EN */
2763 r
= FLD_MOD(r
, 1, 8, 8); /* ECC_TX_EN */
2764 r
= FLD_MOD(r
, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2765 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH
))
2766 r
= FLD_MOD(r
, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2768 r
= FLD_MOD(r
, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2769 r
= FLD_MOD(r
, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2771 dsi_write_reg(dsidev
, DSI_VC_CTRL(channel
), r
);
2774 static int dsi_vc_config_source(struct platform_device
*dsidev
, int channel
,
2775 enum dsi_vc_source source
)
2777 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2779 if (dsi
->vc
[channel
].source
== source
)
2782 DSSDBGF("%d", channel
);
2784 dsi_sync_vc(dsidev
, channel
);
2786 dsi_vc_enable(dsidev
, channel
, 0);
2789 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
), 15, 0) != 0) {
2790 DSSERR("vc(%d) busy when trying to config for VP\n", channel
);
2794 /* SOURCE, 0 = L4, 1 = video port */
2795 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), source
, 1, 1);
2797 /* DCS_CMD_ENABLE */
2798 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
2799 bool enable
= source
== DSI_VC_SOURCE_VP
;
2800 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 30, 30);
2803 dsi_vc_enable(dsidev
, channel
, 1);
2805 dsi
->vc
[channel
].source
= source
;
2810 void omapdss_dsi_vc_enable_hs(struct omap_dss_device
*dssdev
, int channel
,
2813 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2815 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel
, enable
);
2817 WARN_ON(!dsi_bus_is_locked(dsidev
));
2819 dsi_vc_enable(dsidev
, channel
, 0);
2820 dsi_if_enable(dsidev
, 0);
2822 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 9, 9);
2824 dsi_vc_enable(dsidev
, channel
, 1);
2825 dsi_if_enable(dsidev
, 1);
2827 dsi_force_tx_stop_mode_io(dsidev
);
2829 /* start the DDR clock by sending a NULL packet */
2830 if (dssdev
->panel
.dsi_vm_data
.ddr_clk_always_on
&& enable
)
2831 dsi_vc_send_null(dssdev
, channel
);
2833 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs
);
2835 static void dsi_vc_flush_long_data(struct platform_device
*dsidev
, int channel
)
2837 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2839 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2840 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2844 (val
>> 24) & 0xff);
2848 static void dsi_show_rx_ack_with_err(u16 err
)
2850 DSSERR("\tACK with ERROR (%#x):\n", err
);
2852 DSSERR("\t\tSoT Error\n");
2854 DSSERR("\t\tSoT Sync Error\n");
2856 DSSERR("\t\tEoT Sync Error\n");
2858 DSSERR("\t\tEscape Mode Entry Command Error\n");
2860 DSSERR("\t\tLP Transmit Sync Error\n");
2862 DSSERR("\t\tHS Receive Timeout Error\n");
2864 DSSERR("\t\tFalse Control Error\n");
2866 DSSERR("\t\t(reserved7)\n");
2868 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2870 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2871 if (err
& (1 << 10))
2872 DSSERR("\t\tChecksum Error\n");
2873 if (err
& (1 << 11))
2874 DSSERR("\t\tData type not recognized\n");
2875 if (err
& (1 << 12))
2876 DSSERR("\t\tInvalid VC ID\n");
2877 if (err
& (1 << 13))
2878 DSSERR("\t\tInvalid Transmission Length\n");
2879 if (err
& (1 << 14))
2880 DSSERR("\t\t(reserved14)\n");
2881 if (err
& (1 << 15))
2882 DSSERR("\t\tDSI Protocol Violation\n");
2885 static u16
dsi_vc_flush_receive_data(struct platform_device
*dsidev
,
2888 /* RX_FIFO_NOT_EMPTY */
2889 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2892 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2893 DSSERR("\trawval %#08x\n", val
);
2894 dt
= FLD_GET(val
, 5, 0);
2895 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
2896 u16 err
= FLD_GET(val
, 23, 8);
2897 dsi_show_rx_ack_with_err(err
);
2898 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
) {
2899 DSSERR("\tDCS short response, 1 byte: %#x\n",
2900 FLD_GET(val
, 23, 8));
2901 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
) {
2902 DSSERR("\tDCS short response, 2 byte: %#x\n",
2903 FLD_GET(val
, 23, 8));
2904 } else if (dt
== MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
) {
2905 DSSERR("\tDCS long response, len %d\n",
2906 FLD_GET(val
, 23, 8));
2907 dsi_vc_flush_long_data(dsidev
, channel
);
2909 DSSERR("\tunknown datatype 0x%02x\n", dt
);
2915 static int dsi_vc_send_bta(struct platform_device
*dsidev
, int channel
)
2917 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2919 if (dsi
->debug_write
|| dsi
->debug_read
)
2920 DSSDBG("dsi_vc_send_bta %d\n", channel
);
2922 WARN_ON(!dsi_bus_is_locked(dsidev
));
2924 /* RX_FIFO_NOT_EMPTY */
2925 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2926 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2927 dsi_vc_flush_receive_data(dsidev
, channel
);
2930 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 6, 6); /* BTA_EN */
2932 /* flush posted write */
2933 dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2938 int dsi_vc_send_bta_sync(struct omap_dss_device
*dssdev
, int channel
)
2940 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2941 DECLARE_COMPLETION_ONSTACK(completion
);
2945 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2946 &completion
, DSI_VC_IRQ_BTA
);
2950 r
= dsi_register_isr(dsidev
, dsi_completion_handler
, &completion
,
2951 DSI_IRQ_ERROR_MASK
);
2955 r
= dsi_vc_send_bta(dsidev
, channel
);
2959 if (wait_for_completion_timeout(&completion
,
2960 msecs_to_jiffies(500)) == 0) {
2961 DSSERR("Failed to receive BTA\n");
2966 err
= dsi_get_errors(dsidev
);
2968 DSSERR("Error while sending BTA: %x\n", err
);
2973 dsi_unregister_isr(dsidev
, dsi_completion_handler
, &completion
,
2974 DSI_IRQ_ERROR_MASK
);
2976 dsi_unregister_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2977 &completion
, DSI_VC_IRQ_BTA
);
2981 EXPORT_SYMBOL(dsi_vc_send_bta_sync
);
2983 static inline void dsi_vc_write_long_header(struct platform_device
*dsidev
,
2984 int channel
, u8 data_type
, u16 len
, u8 ecc
)
2986 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2990 WARN_ON(!dsi_bus_is_locked(dsidev
));
2992 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
2994 val
= FLD_VAL(data_id
, 7, 0) | FLD_VAL(len
, 23, 8) |
2995 FLD_VAL(ecc
, 31, 24);
2997 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_HEADER(channel
), val
);
3000 static inline void dsi_vc_write_long_payload(struct platform_device
*dsidev
,
3001 int channel
, u8 b1
, u8 b2
, u8 b3
, u8 b4
)
3005 val
= b4
<< 24 | b3
<< 16 | b2
<< 8 | b1
<< 0;
3007 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3008 b1, b2, b3, b4, val); */
3010 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_PAYLOAD(channel
), val
);
3013 static int dsi_vc_send_long(struct platform_device
*dsidev
, int channel
,
3014 u8 data_type
, u8
*data
, u16 len
, u8 ecc
)
3017 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3023 if (dsi
->debug_write
)
3024 DSSDBG("dsi_vc_send_long, %d bytes\n", len
);
3027 if (dsi
->vc
[channel
].fifo_size
* 32 * 4 < len
+ 4) {
3028 DSSERR("unable to send long packet: packet too long.\n");
3032 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
3034 dsi_vc_write_long_header(dsidev
, channel
, data_type
, len
, ecc
);
3037 for (i
= 0; i
< len
>> 2; i
++) {
3038 if (dsi
->debug_write
)
3039 DSSDBG("\tsending full packet %d\n", i
);
3046 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, b4
);
3051 b1
= 0; b2
= 0; b3
= 0;
3053 if (dsi
->debug_write
)
3054 DSSDBG("\tsending remainder bytes %d\n", i
);
3071 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, 0);
3077 static int dsi_vc_send_short(struct platform_device
*dsidev
, int channel
,
3078 u8 data_type
, u16 data
, u8 ecc
)
3080 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3084 WARN_ON(!dsi_bus_is_locked(dsidev
));
3086 if (dsi
->debug_write
)
3087 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3089 data_type
, data
& 0xff, (data
>> 8) & 0xff);
3091 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
3093 if (FLD_GET(dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
)), 16, 16)) {
3094 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3098 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
3100 r
= (data_id
<< 0) | (data
<< 8) | (ecc
<< 24);
3102 dsi_write_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
), r
);
3107 int dsi_vc_send_null(struct omap_dss_device
*dssdev
, int channel
)
3109 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3111 return dsi_vc_send_long(dsidev
, channel
, MIPI_DSI_NULL_PACKET
, NULL
,
3114 EXPORT_SYMBOL(dsi_vc_send_null
);
3116 static int dsi_vc_write_nosync_common(struct omap_dss_device
*dssdev
,
3117 int channel
, u8
*data
, int len
, enum dss_dsi_content_type type
)
3119 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3123 BUG_ON(type
== DSS_DSI_CONTENT_DCS
);
3124 r
= dsi_vc_send_short(dsidev
, channel
,
3125 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
, 0, 0);
3126 } else if (len
== 1) {
3127 r
= dsi_vc_send_short(dsidev
, channel
,
3128 type
== DSS_DSI_CONTENT_GENERIC
?
3129 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
3130 MIPI_DSI_DCS_SHORT_WRITE
, data
[0], 0);
3131 } else if (len
== 2) {
3132 r
= dsi_vc_send_short(dsidev
, channel
,
3133 type
== DSS_DSI_CONTENT_GENERIC
?
3134 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
3135 MIPI_DSI_DCS_SHORT_WRITE_PARAM
,
3136 data
[0] | (data
[1] << 8), 0);
3138 r
= dsi_vc_send_long(dsidev
, channel
,
3139 type
== DSS_DSI_CONTENT_GENERIC
?
3140 MIPI_DSI_GENERIC_LONG_WRITE
:
3141 MIPI_DSI_DCS_LONG_WRITE
, data
, len
, 0);
3147 int dsi_vc_dcs_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3150 return dsi_vc_write_nosync_common(dssdev
, channel
, data
, len
,
3151 DSS_DSI_CONTENT_DCS
);
3153 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync
);
3155 int dsi_vc_generic_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3158 return dsi_vc_write_nosync_common(dssdev
, channel
, data
, len
,
3159 DSS_DSI_CONTENT_GENERIC
);
3161 EXPORT_SYMBOL(dsi_vc_generic_write_nosync
);
3163 static int dsi_vc_write_common(struct omap_dss_device
*dssdev
, int channel
,
3164 u8
*data
, int len
, enum dss_dsi_content_type type
)
3166 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3169 r
= dsi_vc_write_nosync_common(dssdev
, channel
, data
, len
, type
);
3173 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3177 /* RX_FIFO_NOT_EMPTY */
3178 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
3179 DSSERR("rx fifo not empty after write, dumping data:\n");
3180 dsi_vc_flush_receive_data(dsidev
, channel
);
3187 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3188 channel
, data
[0], len
);
3192 int dsi_vc_dcs_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3195 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3196 DSS_DSI_CONTENT_DCS
);
3198 EXPORT_SYMBOL(dsi_vc_dcs_write
);
3200 int dsi_vc_generic_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3203 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3204 DSS_DSI_CONTENT_GENERIC
);
3206 EXPORT_SYMBOL(dsi_vc_generic_write
);
3208 int dsi_vc_dcs_write_0(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
)
3210 return dsi_vc_dcs_write(dssdev
, channel
, &dcs_cmd
, 1);
3212 EXPORT_SYMBOL(dsi_vc_dcs_write_0
);
3214 int dsi_vc_generic_write_0(struct omap_dss_device
*dssdev
, int channel
)
3216 return dsi_vc_generic_write(dssdev
, channel
, NULL
, 0);
3218 EXPORT_SYMBOL(dsi_vc_generic_write_0
);
3220 int dsi_vc_dcs_write_1(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3226 return dsi_vc_dcs_write(dssdev
, channel
, buf
, 2);
3228 EXPORT_SYMBOL(dsi_vc_dcs_write_1
);
3230 int dsi_vc_generic_write_1(struct omap_dss_device
*dssdev
, int channel
,
3233 return dsi_vc_generic_write(dssdev
, channel
, ¶m
, 1);
3235 EXPORT_SYMBOL(dsi_vc_generic_write_1
);
3237 int dsi_vc_generic_write_2(struct omap_dss_device
*dssdev
, int channel
,
3238 u8 param1
, u8 param2
)
3243 return dsi_vc_generic_write(dssdev
, channel
, buf
, 2);
3245 EXPORT_SYMBOL(dsi_vc_generic_write_2
);
3247 static int dsi_vc_dcs_send_read_request(struct omap_dss_device
*dssdev
,
3248 int channel
, u8 dcs_cmd
)
3250 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3251 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3254 if (dsi
->debug_read
)
3255 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3258 r
= dsi_vc_send_short(dsidev
, channel
, MIPI_DSI_DCS_READ
, dcs_cmd
, 0);
3260 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3261 " failed\n", channel
, dcs_cmd
);
3268 static int dsi_vc_generic_send_read_request(struct omap_dss_device
*dssdev
,
3269 int channel
, u8
*reqdata
, int reqlen
)
3271 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3272 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3277 if (dsi
->debug_read
)
3278 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3282 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
;
3284 } else if (reqlen
== 1) {
3285 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
;
3287 } else if (reqlen
== 2) {
3288 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
;
3289 data
= reqdata
[0] | (reqdata
[1] << 8);
3294 r
= dsi_vc_send_short(dsidev
, channel
, data_type
, data
, 0);
3296 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3297 " failed\n", channel
, reqlen
);
3304 static int dsi_vc_read_rx_fifo(struct platform_device
*dsidev
, int channel
,
3305 u8
*buf
, int buflen
, enum dss_dsi_content_type type
)
3307 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3312 /* RX_FIFO_NOT_EMPTY */
3313 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20) == 0) {
3314 DSSERR("RX fifo empty when trying to read.\n");
3319 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
3320 if (dsi
->debug_read
)
3321 DSSDBG("\theader: %08x\n", val
);
3322 dt
= FLD_GET(val
, 5, 0);
3323 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
3324 u16 err
= FLD_GET(val
, 23, 8);
3325 dsi_show_rx_ack_with_err(err
);
3329 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3330 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE
:
3331 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
)) {
3332 u8 data
= FLD_GET(val
, 15, 8);
3333 if (dsi
->debug_read
)
3334 DSSDBG("\t%s short response, 1 byte: %02x\n",
3335 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3346 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3347 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE
:
3348 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
)) {
3349 u16 data
= FLD_GET(val
, 23, 8);
3350 if (dsi
->debug_read
)
3351 DSSDBG("\t%s short response, 2 byte: %04x\n",
3352 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3360 buf
[0] = data
& 0xff;
3361 buf
[1] = (data
>> 8) & 0xff;
3364 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3365 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
3366 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
)) {
3368 int len
= FLD_GET(val
, 23, 8);
3369 if (dsi
->debug_read
)
3370 DSSDBG("\t%s long response, len %d\n",
3371 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3379 /* two byte checksum ends the packet, not included in len */
3380 for (w
= 0; w
< len
+ 2;) {
3382 val
= dsi_read_reg(dsidev
,
3383 DSI_VC_SHORT_PACKET_HEADER(channel
));
3384 if (dsi
->debug_read
)
3385 DSSDBG("\t\t%02x %02x %02x %02x\n",
3389 (val
>> 24) & 0xff);
3391 for (b
= 0; b
< 4; ++b
) {
3393 buf
[w
] = (val
>> (b
* 8)) & 0xff;
3394 /* we discard the 2 byte checksum */
3401 DSSERR("\tunknown datatype 0x%02x\n", dt
);
3408 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel
,
3409 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" : "DCS");
3414 int dsi_vc_dcs_read(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3415 u8
*buf
, int buflen
)
3417 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3420 r
= dsi_vc_dcs_send_read_request(dssdev
, channel
, dcs_cmd
);
3424 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3428 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3429 DSS_DSI_CONTENT_DCS
);
3440 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel
, dcs_cmd
);
3443 EXPORT_SYMBOL(dsi_vc_dcs_read
);
3445 static int dsi_vc_generic_read(struct omap_dss_device
*dssdev
, int channel
,
3446 u8
*reqdata
, int reqlen
, u8
*buf
, int buflen
)
3448 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3451 r
= dsi_vc_generic_send_read_request(dssdev
, channel
, reqdata
, reqlen
);
3455 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3459 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3460 DSS_DSI_CONTENT_GENERIC
);
3472 int dsi_vc_generic_read_0(struct omap_dss_device
*dssdev
, int channel
, u8
*buf
,
3477 r
= dsi_vc_generic_read(dssdev
, channel
, NULL
, 0, buf
, buflen
);
3479 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel
);
3485 EXPORT_SYMBOL(dsi_vc_generic_read_0
);
3487 int dsi_vc_generic_read_1(struct omap_dss_device
*dssdev
, int channel
, u8 param
,
3488 u8
*buf
, int buflen
)
3492 r
= dsi_vc_generic_read(dssdev
, channel
, ¶m
, 1, buf
, buflen
);
3494 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel
);
3500 EXPORT_SYMBOL(dsi_vc_generic_read_1
);
3502 int dsi_vc_generic_read_2(struct omap_dss_device
*dssdev
, int channel
,
3503 u8 param1
, u8 param2
, u8
*buf
, int buflen
)
3508 reqdata
[0] = param1
;
3509 reqdata
[1] = param2
;
3511 r
= dsi_vc_generic_read(dssdev
, channel
, reqdata
, 2, buf
, buflen
);
3513 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel
);
3519 EXPORT_SYMBOL(dsi_vc_generic_read_2
);
3521 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device
*dssdev
, int channel
,
3524 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3526 return dsi_vc_send_short(dsidev
, channel
,
3527 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
, len
, 0);
3529 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size
);
3531 static int dsi_enter_ulps(struct platform_device
*dsidev
)
3533 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3534 DECLARE_COMPLETION_ONSTACK(completion
);
3540 WARN_ON(!dsi_bus_is_locked(dsidev
));
3542 WARN_ON(dsi
->ulps_enabled
);
3544 if (dsi
->ulps_enabled
)
3547 /* DDR_CLK_ALWAYS_ON */
3548 if (REG_GET(dsidev
, DSI_CLK_CTRL
, 13, 13)) {
3549 dsi_if_enable(dsidev
, 0);
3550 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
3551 dsi_if_enable(dsidev
, 1);
3554 dsi_sync_vc(dsidev
, 0);
3555 dsi_sync_vc(dsidev
, 1);
3556 dsi_sync_vc(dsidev
, 2);
3557 dsi_sync_vc(dsidev
, 3);
3559 dsi_force_tx_stop_mode_io(dsidev
);
3561 dsi_vc_enable(dsidev
, 0, false);
3562 dsi_vc_enable(dsidev
, 1, false);
3563 dsi_vc_enable(dsidev
, 2, false);
3564 dsi_vc_enable(dsidev
, 3, false);
3566 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 16, 16)) { /* HS_BUSY */
3567 DSSERR("HS busy when enabling ULPS\n");
3571 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 17, 17)) { /* LP_BUSY */
3572 DSSERR("LP busy when enabling ULPS\n");
3576 r
= dsi_register_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3577 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3583 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
3584 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
3588 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3589 /* LANEx_ULPS_SIG2 */
3590 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, mask
, 9, 5);
3592 /* flush posted write and wait for SCP interface to finish the write */
3593 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3595 if (wait_for_completion_timeout(&completion
,
3596 msecs_to_jiffies(1000)) == 0) {
3597 DSSERR("ULPS enable timeout\n");
3602 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3603 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3605 /* Reset LANEx_ULPS_SIG2 */
3606 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, 0, 9, 5);
3608 /* flush posted write and wait for SCP interface to finish the write */
3609 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3611 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ULPS
);
3613 dsi_if_enable(dsidev
, false);
3615 dsi
->ulps_enabled
= true;
3620 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3621 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3625 static void dsi_set_lp_rx_timeout(struct platform_device
*dsidev
,
3626 unsigned ticks
, bool x4
, bool x16
)
3629 unsigned long total_ticks
;
3632 BUG_ON(ticks
> 0x1fff);
3634 /* ticks in DSI_FCK */
3635 fck
= dsi_fclk_rate(dsidev
);
3637 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3638 r
= FLD_MOD(r
, 1, 15, 15); /* LP_RX_TO */
3639 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3640 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3641 r
= FLD_MOD(r
, ticks
, 12, 0); /* LP_RX_COUNTER */
3642 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3644 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3646 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3648 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3649 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3652 static void dsi_set_ta_timeout(struct platform_device
*dsidev
, unsigned ticks
,
3656 unsigned long total_ticks
;
3659 BUG_ON(ticks
> 0x1fff);
3661 /* ticks in DSI_FCK */
3662 fck
= dsi_fclk_rate(dsidev
);
3664 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3665 r
= FLD_MOD(r
, 1, 31, 31); /* TA_TO */
3666 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* TA_TO_X16 */
3667 r
= FLD_MOD(r
, x8
? 1 : 0, 29, 29); /* TA_TO_X8 */
3668 r
= FLD_MOD(r
, ticks
, 28, 16); /* TA_TO_COUNTER */
3669 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3671 total_ticks
= ticks
* (x16
? 16 : 1) * (x8
? 8 : 1);
3673 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3675 ticks
, x8
? " x8" : "", x16
? " x16" : "",
3676 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3679 static void dsi_set_stop_state_counter(struct platform_device
*dsidev
,
3680 unsigned ticks
, bool x4
, bool x16
)
3683 unsigned long total_ticks
;
3686 BUG_ON(ticks
> 0x1fff);
3688 /* ticks in DSI_FCK */
3689 fck
= dsi_fclk_rate(dsidev
);
3691 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3692 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3693 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3694 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3695 r
= FLD_MOD(r
, ticks
, 12, 0); /* STOP_STATE_COUNTER_IO */
3696 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3698 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3700 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3702 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3703 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3706 static void dsi_set_hs_tx_timeout(struct platform_device
*dsidev
,
3707 unsigned ticks
, bool x4
, bool x16
)
3710 unsigned long total_ticks
;
3713 BUG_ON(ticks
> 0x1fff);
3715 /* ticks in TxByteClkHS */
3716 fck
= dsi_get_txbyteclkhs(dsidev
);
3718 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3719 r
= FLD_MOD(r
, 1, 31, 31); /* HS_TX_TO */
3720 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3721 r
= FLD_MOD(r
, x4
? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3722 r
= FLD_MOD(r
, ticks
, 28, 16); /* HS_TX_TO_COUNTER */
3723 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3725 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3727 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3729 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3730 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3733 static void dsi_config_vp_num_line_buffers(struct omap_dss_device
*dssdev
)
3735 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3736 int num_line_buffers
;
3738 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3739 int bpp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
);
3740 unsigned line_buf_size
= dsi_get_line_buf_size(dsidev
);
3741 struct omap_video_timings
*timings
= &dssdev
->panel
.timings
;
3743 * Don't use line buffers if width is greater than the video
3744 * port's line buffer size
3746 if (line_buf_size
<= timings
->x_res
* bpp
/ 8)
3747 num_line_buffers
= 0;
3749 num_line_buffers
= 2;
3751 /* Use maximum number of line buffers in command mode */
3752 num_line_buffers
= 2;
3756 REG_FLD_MOD(dsidev
, DSI_CTRL
, num_line_buffers
, 13, 12);
3759 static void dsi_config_vp_sync_events(struct omap_dss_device
*dssdev
)
3761 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3762 int de_pol
= dssdev
->panel
.dsi_vm_data
.vp_de_pol
;
3763 int hsync_pol
= dssdev
->panel
.dsi_vm_data
.vp_hsync_pol
;
3764 int vsync_pol
= dssdev
->panel
.dsi_vm_data
.vp_vsync_pol
;
3765 bool vsync_end
= dssdev
->panel
.dsi_vm_data
.vp_vsync_end
;
3766 bool hsync_end
= dssdev
->panel
.dsi_vm_data
.vp_hsync_end
;
3769 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3770 r
= FLD_MOD(r
, de_pol
, 9, 9); /* VP_DE_POL */
3771 r
= FLD_MOD(r
, hsync_pol
, 10, 10); /* VP_HSYNC_POL */
3772 r
= FLD_MOD(r
, vsync_pol
, 11, 11); /* VP_VSYNC_POL */
3773 r
= FLD_MOD(r
, 1, 15, 15); /* VP_VSYNC_START */
3774 r
= FLD_MOD(r
, vsync_end
, 16, 16); /* VP_VSYNC_END */
3775 r
= FLD_MOD(r
, 1, 17, 17); /* VP_HSYNC_START */
3776 r
= FLD_MOD(r
, hsync_end
, 18, 18); /* VP_HSYNC_END */
3777 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3780 static void dsi_config_blanking_modes(struct omap_dss_device
*dssdev
)
3782 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3783 int blanking_mode
= dssdev
->panel
.dsi_vm_data
.blanking_mode
;
3784 int hfp_blanking_mode
= dssdev
->panel
.dsi_vm_data
.hfp_blanking_mode
;
3785 int hbp_blanking_mode
= dssdev
->panel
.dsi_vm_data
.hbp_blanking_mode
;
3786 int hsa_blanking_mode
= dssdev
->panel
.dsi_vm_data
.hsa_blanking_mode
;
3790 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3791 * 1 = Long blanking packets are sent in corresponding blanking periods
3793 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3794 r
= FLD_MOD(r
, blanking_mode
, 20, 20); /* BLANKING_MODE */
3795 r
= FLD_MOD(r
, hfp_blanking_mode
, 21, 21); /* HFP_BLANKING */
3796 r
= FLD_MOD(r
, hbp_blanking_mode
, 22, 22); /* HBP_BLANKING */
3797 r
= FLD_MOD(r
, hsa_blanking_mode
, 23, 23); /* HSA_BLANKING */
3798 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3801 static int dsi_proto_config(struct omap_dss_device
*dssdev
)
3803 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3807 dsi_config_tx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3812 dsi_config_rx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3817 /* XXX what values for the timeouts? */
3818 dsi_set_stop_state_counter(dsidev
, 0x1000, false, false);
3819 dsi_set_ta_timeout(dsidev
, 0x1fff, true, true);
3820 dsi_set_lp_rx_timeout(dsidev
, 0x1fff, true, true);
3821 dsi_set_hs_tx_timeout(dsidev
, 0x1fff, true, true);
3823 switch (dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
)) {
3837 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3838 r
= FLD_MOD(r
, 1, 1, 1); /* CS_RX_EN */
3839 r
= FLD_MOD(r
, 1, 2, 2); /* ECC_RX_EN */
3840 r
= FLD_MOD(r
, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3841 r
= FLD_MOD(r
, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3842 r
= FLD_MOD(r
, buswidth
, 7, 6); /* VP_DATA_BUS_WIDTH */
3843 r
= FLD_MOD(r
, 0, 8, 8); /* VP_CLK_POL */
3844 r
= FLD_MOD(r
, 1, 14, 14); /* TRIGGER_RESET_MODE */
3845 r
= FLD_MOD(r
, 1, 19, 19); /* EOT_ENABLE */
3846 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
3847 r
= FLD_MOD(r
, 1, 24, 24); /* DCS_CMD_ENABLE */
3848 /* DCS_CMD_CODE, 1=start, 0=continue */
3849 r
= FLD_MOD(r
, 0, 25, 25);
3852 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3854 dsi_config_vp_num_line_buffers(dssdev
);
3856 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3857 dsi_config_vp_sync_events(dssdev
);
3858 dsi_config_blanking_modes(dssdev
);
3861 dsi_vc_initial_config(dsidev
, 0);
3862 dsi_vc_initial_config(dsidev
, 1);
3863 dsi_vc_initial_config(dsidev
, 2);
3864 dsi_vc_initial_config(dsidev
, 3);
3869 static void dsi_proto_timings(struct omap_dss_device
*dssdev
)
3871 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3872 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3873 unsigned tlpx
, tclk_zero
, tclk_prepare
, tclk_trail
;
3874 unsigned tclk_pre
, tclk_post
;
3875 unsigned ths_prepare
, ths_prepare_ths_zero
, ths_zero
;
3876 unsigned ths_trail
, ths_exit
;
3877 unsigned ddr_clk_pre
, ddr_clk_post
;
3878 unsigned enter_hs_mode_lat
, exit_hs_mode_lat
;
3880 int ndl
= dsi
->num_lanes_used
- 1;
3883 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
3884 ths_prepare
= FLD_GET(r
, 31, 24);
3885 ths_prepare_ths_zero
= FLD_GET(r
, 23, 16);
3886 ths_zero
= ths_prepare_ths_zero
- ths_prepare
;
3887 ths_trail
= FLD_GET(r
, 15, 8);
3888 ths_exit
= FLD_GET(r
, 7, 0);
3890 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
3891 tlpx
= FLD_GET(r
, 22, 16) * 2;
3892 tclk_trail
= FLD_GET(r
, 15, 8);
3893 tclk_zero
= FLD_GET(r
, 7, 0);
3895 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
3896 tclk_prepare
= FLD_GET(r
, 7, 0);
3900 /* min 60ns + 52*UI */
3901 tclk_post
= ns2ddr(dsidev
, 60) + 26;
3903 ths_eot
= DIV_ROUND_UP(4, ndl
);
3905 ddr_clk_pre
= DIV_ROUND_UP(tclk_pre
+ tlpx
+ tclk_zero
+ tclk_prepare
,
3907 ddr_clk_post
= DIV_ROUND_UP(tclk_post
+ ths_trail
, 4) + ths_eot
;
3909 BUG_ON(ddr_clk_pre
== 0 || ddr_clk_pre
> 255);
3910 BUG_ON(ddr_clk_post
== 0 || ddr_clk_post
> 255);
3912 r
= dsi_read_reg(dsidev
, DSI_CLK_TIMING
);
3913 r
= FLD_MOD(r
, ddr_clk_pre
, 15, 8);
3914 r
= FLD_MOD(r
, ddr_clk_post
, 7, 0);
3915 dsi_write_reg(dsidev
, DSI_CLK_TIMING
, r
);
3917 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3921 enter_hs_mode_lat
= 1 + DIV_ROUND_UP(tlpx
, 4) +
3922 DIV_ROUND_UP(ths_prepare
, 4) +
3923 DIV_ROUND_UP(ths_zero
+ 3, 4);
3925 exit_hs_mode_lat
= DIV_ROUND_UP(ths_trail
+ ths_exit
, 4) + 1 + ths_eot
;
3927 r
= FLD_VAL(enter_hs_mode_lat
, 31, 16) |
3928 FLD_VAL(exit_hs_mode_lat
, 15, 0);
3929 dsi_write_reg(dsidev
, DSI_VM_TIMING7
, r
);
3931 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3932 enter_hs_mode_lat
, exit_hs_mode_lat
);
3934 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3935 /* TODO: Implement a video mode check_timings function */
3936 int hsa
= dssdev
->panel
.dsi_vm_data
.hsa
;
3937 int hfp
= dssdev
->panel
.dsi_vm_data
.hfp
;
3938 int hbp
= dssdev
->panel
.dsi_vm_data
.hbp
;
3939 int vsa
= dssdev
->panel
.dsi_vm_data
.vsa
;
3940 int vfp
= dssdev
->panel
.dsi_vm_data
.vfp
;
3941 int vbp
= dssdev
->panel
.dsi_vm_data
.vbp
;
3942 int window_sync
= dssdev
->panel
.dsi_vm_data
.window_sync
;
3943 bool hsync_end
= dssdev
->panel
.dsi_vm_data
.vp_hsync_end
;
3944 struct omap_video_timings
*timings
= &dssdev
->panel
.timings
;
3945 int bpp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
);
3946 int tl
, t_he
, width_bytes
;
3949 ((hsa
== 0 && ndl
== 3) ? 1 : DIV_ROUND_UP(4, ndl
)) : 0;
3951 width_bytes
= DIV_ROUND_UP(timings
->x_res
* bpp
, 8);
3953 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3954 tl
= DIV_ROUND_UP(4, ndl
) + (hsync_end
? hsa
: 0) + t_he
+ hfp
+
3955 DIV_ROUND_UP(width_bytes
+ 6, ndl
) + hbp
;
3957 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp
,
3958 hfp
, hsync_end
? hsa
: 0, tl
);
3959 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp
, vfp
,
3960 vsa
, timings
->y_res
);
3962 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING1
);
3963 r
= FLD_MOD(r
, hbp
, 11, 0); /* HBP */
3964 r
= FLD_MOD(r
, hfp
, 23, 12); /* HFP */
3965 r
= FLD_MOD(r
, hsync_end
? hsa
: 0, 31, 24); /* HSA */
3966 dsi_write_reg(dsidev
, DSI_VM_TIMING1
, r
);
3968 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING2
);
3969 r
= FLD_MOD(r
, vbp
, 7, 0); /* VBP */
3970 r
= FLD_MOD(r
, vfp
, 15, 8); /* VFP */
3971 r
= FLD_MOD(r
, vsa
, 23, 16); /* VSA */
3972 r
= FLD_MOD(r
, window_sync
, 27, 24); /* WINDOW_SYNC */
3973 dsi_write_reg(dsidev
, DSI_VM_TIMING2
, r
);
3975 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING3
);
3976 r
= FLD_MOD(r
, timings
->y_res
, 14, 0); /* VACT */
3977 r
= FLD_MOD(r
, tl
, 31, 16); /* TL */
3978 dsi_write_reg(dsidev
, DSI_VM_TIMING3
, r
);
3982 int dsi_video_mode_enable(struct omap_dss_device
*dssdev
, int channel
)
3984 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3985 int bpp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
);
3989 switch (dssdev
->panel
.dsi_pix_fmt
) {
3990 case OMAP_DSS_DSI_FMT_RGB888
:
3991 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
3993 case OMAP_DSS_DSI_FMT_RGB666
:
3994 data_type
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
3996 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
3997 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
3999 case OMAP_DSS_DSI_FMT_RGB565
:
4000 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
4006 dsi_if_enable(dsidev
, false);
4007 dsi_vc_enable(dsidev
, channel
, false);
4009 /* MODE, 1 = video mode */
4010 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 4, 4);
4012 word_count
= DIV_ROUND_UP(dssdev
->panel
.timings
.x_res
* bpp
, 8);
4014 dsi_vc_write_long_header(dsidev
, channel
, data_type
, word_count
, 0);
4016 dsi_vc_enable(dsidev
, channel
, true);
4017 dsi_if_enable(dsidev
, true);
4019 dssdev
->manager
->enable(dssdev
->manager
);
4023 EXPORT_SYMBOL(dsi_video_mode_enable
);
4025 void dsi_video_mode_disable(struct omap_dss_device
*dssdev
, int channel
)
4027 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4029 dsi_if_enable(dsidev
, false);
4030 dsi_vc_enable(dsidev
, channel
, false);
4032 /* MODE, 0 = command mode */
4033 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 0, 4, 4);
4035 dsi_vc_enable(dsidev
, channel
, true);
4036 dsi_if_enable(dsidev
, true);
4038 dssdev
->manager
->disable(dssdev
->manager
);
4040 EXPORT_SYMBOL(dsi_video_mode_disable
);
4042 static void dsi_update_screen_dispc(struct omap_dss_device
*dssdev
,
4043 u16 x
, u16 y
, u16 w
, u16 h
)
4045 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4046 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4051 unsigned packet_payload
;
4052 unsigned packet_len
;
4055 const unsigned channel
= dsi
->update_channel
;
4056 const unsigned line_buf_size
= dsi_get_line_buf_size(dsidev
);
4058 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4061 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_VP
);
4063 bytespp
= dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
) / 8;
4064 bytespl
= w
* bytespp
;
4065 bytespf
= bytespl
* h
;
4067 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4068 * number of lines in a packet. See errata about VP_CLK_RATIO */
4070 if (bytespf
< line_buf_size
)
4071 packet_payload
= bytespf
;
4073 packet_payload
= (line_buf_size
) / bytespl
* bytespl
;
4075 packet_len
= packet_payload
+ 1; /* 1 byte for DCS cmd */
4076 total_len
= (bytespf
/ packet_payload
) * packet_len
;
4078 if (bytespf
% packet_payload
)
4079 total_len
+= (bytespf
% packet_payload
) + 1;
4081 l
= FLD_VAL(total_len
, 23, 0); /* TE_SIZE */
4082 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4084 dsi_vc_write_long_header(dsidev
, channel
, MIPI_DSI_DCS_LONG_WRITE
,
4087 if (dsi
->te_enabled
)
4088 l
= FLD_MOD(l
, 1, 30, 30); /* TE_EN */
4090 l
= FLD_MOD(l
, 1, 31, 31); /* TE_START */
4091 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4093 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4094 * because DSS interrupts are not capable of waking up the CPU and the
4095 * framedone interrupt could be delayed for quite a long time. I think
4096 * the same goes for any DSS interrupts, but for some reason I have not
4097 * seen the problem anywhere else than here.
4099 dispc_disable_sidle();
4101 dsi_perf_mark_start(dsidev
);
4103 r
= schedule_delayed_work(&dsi
->framedone_timeout_work
,
4104 msecs_to_jiffies(250));
4107 dss_start_update(dssdev
);
4109 if (dsi
->te_enabled
) {
4110 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4111 * for TE is longer than the timer allows */
4112 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 0, 15, 15); /* LP_RX_TO */
4114 dsi_vc_send_bta(dsidev
, channel
);
4116 #ifdef DSI_CATCH_MISSING_TE
4117 mod_timer(&dsi
->te_timer
, jiffies
+ msecs_to_jiffies(250));
4122 #ifdef DSI_CATCH_MISSING_TE
4123 static void dsi_te_timeout(unsigned long arg
)
4125 DSSERR("TE not received for 250ms!\n");
4129 static void dsi_handle_framedone(struct platform_device
*dsidev
, int error
)
4131 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4133 /* SIDLEMODE back to smart-idle */
4134 dispc_enable_sidle();
4136 if (dsi
->te_enabled
) {
4137 /* enable LP_RX_TO again after the TE */
4138 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
4141 dsi
->framedone_callback(error
, dsi
->framedone_data
);
4144 dsi_perf_show(dsidev
, "DISPC");
4147 static void dsi_framedone_timeout_work_callback(struct work_struct
*work
)
4149 struct dsi_data
*dsi
= container_of(work
, struct dsi_data
,
4150 framedone_timeout_work
.work
);
4151 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4152 * 250ms which would conflict with this timeout work. What should be
4153 * done is first cancel the transfer on the HW, and then cancel the
4154 * possibly scheduled framedone work. However, cancelling the transfer
4155 * on the HW is buggy, and would probably require resetting the whole
4158 DSSERR("Framedone not received for 250ms!\n");
4160 dsi_handle_framedone(dsi
->pdev
, -ETIMEDOUT
);
4163 static void dsi_framedone_irq_callback(void *data
, u32 mask
)
4165 struct omap_dss_device
*dssdev
= (struct omap_dss_device
*) data
;
4166 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4167 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4169 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4170 * turns itself off. However, DSI still has the pixels in its buffers,
4171 * and is sending the data.
4174 __cancel_delayed_work(&dsi
->framedone_timeout_work
);
4176 dsi_handle_framedone(dsidev
, 0);
4178 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4179 dispc_fake_vsync_irq();
4183 int omap_dsi_prepare_update(struct omap_dss_device
*dssdev
,
4184 u16
*x
, u16
*y
, u16
*w
, u16
*h
,
4185 bool enlarge_update_area
)
4187 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4190 dssdev
->driver
->get_resolution(dssdev
, &dw
, &dh
);
4192 if (*x
> dw
|| *y
> dh
)
4204 if (*w
== 0 || *h
== 0)
4207 dsi_perf_mark_setup(dsidev
);
4209 dss_setup_partial_planes(dssdev
, x
, y
, w
, h
,
4210 enlarge_update_area
);
4211 dispc_mgr_set_lcd_size(dssdev
->manager
->id
, *w
, *h
);
4215 EXPORT_SYMBOL(omap_dsi_prepare_update
);
4217 int omap_dsi_update(struct omap_dss_device
*dssdev
,
4219 u16 x
, u16 y
, u16 w
, u16 h
,
4220 void (*callback
)(int, void *), void *data
)
4222 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4223 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4225 dsi
->update_channel
= channel
;
4227 /* OMAP DSS cannot send updates of odd widths.
4228 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4229 * here to make sure we catch erroneous updates. Otherwise we'll only
4230 * see rather obscure HW error happening, as DSS halts. */
4233 dsi
->framedone_callback
= callback
;
4234 dsi
->framedone_data
= data
;
4236 dsi
->update_region
.x
= x
;
4237 dsi
->update_region
.y
= y
;
4238 dsi
->update_region
.w
= w
;
4239 dsi
->update_region
.h
= h
;
4240 dsi
->update_region
.device
= dssdev
;
4242 dsi_update_screen_dispc(dssdev
, x
, y
, w
, h
);
4246 EXPORT_SYMBOL(omap_dsi_update
);
4250 static int dsi_display_init_dispc(struct omap_dss_device
*dssdev
)
4254 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_CMD_MODE
) {
4256 struct omap_video_timings timings
= {
4265 irq
= dssdev
->manager
->id
== OMAP_DSS_CHANNEL_LCD
?
4266 DISPC_IRQ_FRAMEDONE
: DISPC_IRQ_FRAMEDONE2
;
4268 r
= omap_dispc_register_isr(dsi_framedone_irq_callback
,
4269 (void *) dssdev
, irq
);
4271 DSSERR("can't get FRAMEDONE irq\n");
4275 dispc_mgr_enable_stallmode(dssdev
->manager
->id
, true);
4276 dispc_mgr_enable_fifohandcheck(dssdev
->manager
->id
, 1);
4278 dispc_mgr_set_lcd_timings(dssdev
->manager
->id
, &timings
);
4280 dispc_mgr_enable_stallmode(dssdev
->manager
->id
, false);
4281 dispc_mgr_enable_fifohandcheck(dssdev
->manager
->id
, 0);
4283 dispc_mgr_set_lcd_timings(dssdev
->manager
->id
,
4284 &dssdev
->panel
.timings
);
4287 dispc_mgr_set_lcd_display_type(dssdev
->manager
->id
,
4288 OMAP_DSS_LCD_DISPLAY_TFT
);
4289 dispc_mgr_set_tft_data_lines(dssdev
->manager
->id
,
4290 dsi_get_pixel_size(dssdev
->panel
.dsi_pix_fmt
));
4294 static void dsi_display_uninit_dispc(struct omap_dss_device
*dssdev
)
4296 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_CMD_MODE
) {
4299 irq
= dssdev
->manager
->id
== OMAP_DSS_CHANNEL_LCD
?
4300 DISPC_IRQ_FRAMEDONE
: DISPC_IRQ_FRAMEDONE2
;
4302 omap_dispc_unregister_isr(dsi_framedone_irq_callback
,
4303 (void *) dssdev
, irq
);
4307 static int dsi_configure_dsi_clocks(struct omap_dss_device
*dssdev
)
4309 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4310 struct dsi_clock_info cinfo
;
4313 /* we always use DSS_CLK_SYSCK as input clock */
4314 cinfo
.use_sys_clk
= true;
4315 cinfo
.regn
= dssdev
->clocks
.dsi
.regn
;
4316 cinfo
.regm
= dssdev
->clocks
.dsi
.regm
;
4317 cinfo
.regm_dispc
= dssdev
->clocks
.dsi
.regm_dispc
;
4318 cinfo
.regm_dsi
= dssdev
->clocks
.dsi
.regm_dsi
;
4319 r
= dsi_calc_clock_rates(dssdev
, &cinfo
);
4321 DSSERR("Failed to calc dsi clocks\n");
4325 r
= dsi_pll_set_clock_div(dsidev
, &cinfo
);
4327 DSSERR("Failed to set dsi clocks\n");
4334 static int dsi_configure_dispc_clocks(struct omap_dss_device
*dssdev
)
4336 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4337 struct dispc_clock_info dispc_cinfo
;
4339 unsigned long long fck
;
4341 fck
= dsi_get_pll_hsdiv_dispc_rate(dsidev
);
4343 dispc_cinfo
.lck_div
= dssdev
->clocks
.dispc
.channel
.lck_div
;
4344 dispc_cinfo
.pck_div
= dssdev
->clocks
.dispc
.channel
.pck_div
;
4346 r
= dispc_calc_clock_rates(fck
, &dispc_cinfo
);
4348 DSSERR("Failed to calc dispc clocks\n");
4352 r
= dispc_mgr_set_clock_div(dssdev
->manager
->id
, &dispc_cinfo
);
4354 DSSERR("Failed to set dispc clocks\n");
4361 static int dsi_display_init_dsi(struct omap_dss_device
*dssdev
)
4363 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4364 int dsi_module
= dsi_get_dsidev_id(dsidev
);
4367 r
= dsi_parse_lane_config(dssdev
);
4369 DSSERR("illegal lane config");
4373 r
= dsi_pll_init(dsidev
, true, true);
4377 r
= dsi_configure_dsi_clocks(dssdev
);
4381 dss_select_dispc_clk_source(dssdev
->clocks
.dispc
.dispc_fclk_src
);
4382 dss_select_dsi_clk_source(dsi_module
, dssdev
->clocks
.dsi
.dsi_fclk_src
);
4383 dss_select_lcd_clk_source(dssdev
->manager
->id
,
4384 dssdev
->clocks
.dispc
.channel
.lcd_clk_src
);
4388 r
= dsi_configure_dispc_clocks(dssdev
);
4392 r
= dsi_cio_init(dssdev
);
4396 _dsi_print_reset_status(dsidev
);
4398 dsi_proto_timings(dssdev
);
4399 dsi_set_lp_clk_divisor(dssdev
);
4402 _dsi_print_reset_status(dsidev
);
4404 r
= dsi_proto_config(dssdev
);
4408 /* enable interface */
4409 dsi_vc_enable(dsidev
, 0, 1);
4410 dsi_vc_enable(dsidev
, 1, 1);
4411 dsi_vc_enable(dsidev
, 2, 1);
4412 dsi_vc_enable(dsidev
, 3, 1);
4413 dsi_if_enable(dsidev
, 1);
4414 dsi_force_tx_stop_mode_io(dsidev
);
4418 dsi_cio_uninit(dssdev
);
4420 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK
);
4421 dss_select_dsi_clk_source(dsi_module
, OMAP_DSS_CLK_SRC_FCK
);
4422 dss_select_lcd_clk_source(dssdev
->manager
->id
, OMAP_DSS_CLK_SRC_FCK
);
4425 dsi_pll_uninit(dsidev
, true);
4430 static void dsi_display_uninit_dsi(struct omap_dss_device
*dssdev
,
4431 bool disconnect_lanes
, bool enter_ulps
)
4433 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4434 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4435 int dsi_module
= dsi_get_dsidev_id(dsidev
);
4437 if (enter_ulps
&& !dsi
->ulps_enabled
)
4438 dsi_enter_ulps(dsidev
);
4440 /* disable interface */
4441 dsi_if_enable(dsidev
, 0);
4442 dsi_vc_enable(dsidev
, 0, 0);
4443 dsi_vc_enable(dsidev
, 1, 0);
4444 dsi_vc_enable(dsidev
, 2, 0);
4445 dsi_vc_enable(dsidev
, 3, 0);
4447 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK
);
4448 dss_select_dsi_clk_source(dsi_module
, OMAP_DSS_CLK_SRC_FCK
);
4449 dss_select_lcd_clk_source(dssdev
->manager
->id
, OMAP_DSS_CLK_SRC_FCK
);
4450 dsi_cio_uninit(dssdev
);
4451 dsi_pll_uninit(dsidev
, disconnect_lanes
);
4454 int omapdss_dsi_display_enable(struct omap_dss_device
*dssdev
)
4456 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4457 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4460 DSSDBG("dsi_display_enable\n");
4462 WARN_ON(!dsi_bus_is_locked(dsidev
));
4464 mutex_lock(&dsi
->lock
);
4466 if (dssdev
->manager
== NULL
) {
4467 DSSERR("failed to enable display: no manager\n");
4472 r
= omap_dss_start_device(dssdev
);
4474 DSSERR("failed to start device\n");
4478 r
= dsi_runtime_get(dsidev
);
4482 dsi_enable_pll_clock(dsidev
, 1);
4484 _dsi_initialize_irq(dsidev
);
4486 r
= dsi_display_init_dispc(dssdev
);
4488 goto err_init_dispc
;
4490 r
= dsi_display_init_dsi(dssdev
);
4494 mutex_unlock(&dsi
->lock
);
4499 dsi_display_uninit_dispc(dssdev
);
4501 dsi_enable_pll_clock(dsidev
, 0);
4502 dsi_runtime_put(dsidev
);
4504 omap_dss_stop_device(dssdev
);
4506 mutex_unlock(&dsi
->lock
);
4507 DSSDBG("dsi_display_enable FAILED\n");
4510 EXPORT_SYMBOL(omapdss_dsi_display_enable
);
4512 void omapdss_dsi_display_disable(struct omap_dss_device
*dssdev
,
4513 bool disconnect_lanes
, bool enter_ulps
)
4515 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4516 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4518 DSSDBG("dsi_display_disable\n");
4520 WARN_ON(!dsi_bus_is_locked(dsidev
));
4522 mutex_lock(&dsi
->lock
);
4524 dsi_sync_vc(dsidev
, 0);
4525 dsi_sync_vc(dsidev
, 1);
4526 dsi_sync_vc(dsidev
, 2);
4527 dsi_sync_vc(dsidev
, 3);
4529 dsi_display_uninit_dispc(dssdev
);
4531 dsi_display_uninit_dsi(dssdev
, disconnect_lanes
, enter_ulps
);
4533 dsi_runtime_put(dsidev
);
4534 dsi_enable_pll_clock(dsidev
, 0);
4536 omap_dss_stop_device(dssdev
);
4538 mutex_unlock(&dsi
->lock
);
4540 EXPORT_SYMBOL(omapdss_dsi_display_disable
);
4542 int omapdss_dsi_enable_te(struct omap_dss_device
*dssdev
, bool enable
)
4544 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4545 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4547 dsi
->te_enabled
= enable
;
4550 EXPORT_SYMBOL(omapdss_dsi_enable_te
);
4552 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane
,
4553 u32 fifo_size
, u32 burst_size
,
4554 u32
*fifo_low
, u32
*fifo_high
)
4556 *fifo_high
= fifo_size
- burst_size
;
4557 *fifo_low
= fifo_size
- burst_size
* 2;
4560 int dsi_init_display(struct omap_dss_device
*dssdev
)
4562 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4563 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4565 DSSDBG("DSI init\n");
4567 if (dssdev
->panel
.dsi_mode
== OMAP_DSS_DSI_CMD_MODE
) {
4568 dssdev
->caps
= OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE
|
4569 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM
;
4572 if (dsi
->vdds_dsi_reg
== NULL
) {
4573 struct regulator
*vdds_dsi
;
4575 vdds_dsi
= regulator_get(&dsi
->pdev
->dev
, "vdds_dsi");
4577 if (IS_ERR(vdds_dsi
)) {
4578 DSSERR("can't get VDDS_DSI regulator\n");
4579 return PTR_ERR(vdds_dsi
);
4582 dsi
->vdds_dsi_reg
= vdds_dsi
;
4588 int omap_dsi_request_vc(struct omap_dss_device
*dssdev
, int *channel
)
4590 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4591 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4594 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
4595 if (!dsi
->vc
[i
].dssdev
) {
4596 dsi
->vc
[i
].dssdev
= dssdev
;
4602 DSSERR("cannot get VC for display %s", dssdev
->name
);
4605 EXPORT_SYMBOL(omap_dsi_request_vc
);
4607 int omap_dsi_set_vc_id(struct omap_dss_device
*dssdev
, int channel
, int vc_id
)
4609 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4610 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4612 if (vc_id
< 0 || vc_id
> 3) {
4613 DSSERR("VC ID out of range\n");
4617 if (channel
< 0 || channel
> 3) {
4618 DSSERR("Virtual Channel out of range\n");
4622 if (dsi
->vc
[channel
].dssdev
!= dssdev
) {
4623 DSSERR("Virtual Channel not allocated to display %s\n",
4628 dsi
->vc
[channel
].vc_id
= vc_id
;
4632 EXPORT_SYMBOL(omap_dsi_set_vc_id
);
4634 void omap_dsi_release_vc(struct omap_dss_device
*dssdev
, int channel
)
4636 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4637 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4639 if ((channel
>= 0 && channel
<= 3) &&
4640 dsi
->vc
[channel
].dssdev
== dssdev
) {
4641 dsi
->vc
[channel
].dssdev
= NULL
;
4642 dsi
->vc
[channel
].vc_id
= 0;
4645 EXPORT_SYMBOL(omap_dsi_release_vc
);
4647 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device
*dsidev
)
4649 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 7, 1) != 1)
4650 DSSERR("%s (%s) not active\n",
4651 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
4652 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
));
4655 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device
*dsidev
)
4657 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 8, 1) != 1)
4658 DSSERR("%s (%s) not active\n",
4659 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
4660 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
));
4663 static void dsi_calc_clock_param_ranges(struct platform_device
*dsidev
)
4665 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4667 dsi
->regn_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN
);
4668 dsi
->regm_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM
);
4669 dsi
->regm_dispc_max
=
4670 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC
);
4671 dsi
->regm_dsi_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI
);
4672 dsi
->fint_min
= dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT
);
4673 dsi
->fint_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT
);
4674 dsi
->lpdiv_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV
);
4677 static int dsi_get_clocks(struct platform_device
*dsidev
)
4679 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4682 clk
= clk_get(&dsidev
->dev
, "fck");
4684 DSSERR("can't get fck\n");
4685 return PTR_ERR(clk
);
4690 clk
= clk_get(&dsidev
->dev
, "sys_clk");
4692 DSSERR("can't get sys_clk\n");
4693 clk_put(dsi
->dss_clk
);
4694 dsi
->dss_clk
= NULL
;
4695 return PTR_ERR(clk
);
4703 static void dsi_put_clocks(struct platform_device
*dsidev
)
4705 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4708 clk_put(dsi
->dss_clk
);
4710 clk_put(dsi
->sys_clk
);
4713 /* DSI1 HW IP initialisation */
4714 static int omap_dsihw_probe(struct platform_device
*dsidev
)
4716 struct omap_display_platform_data
*dss_plat_data
;
4717 struct omap_dss_board_info
*board_info
;
4719 int r
, i
, dsi_module
= dsi_get_dsidev_id(dsidev
);
4720 struct resource
*dsi_mem
;
4721 struct dsi_data
*dsi
;
4723 dsi
= kzalloc(sizeof(*dsi
), GFP_KERNEL
);
4730 dsi_pdev_map
[dsi_module
] = dsidev
;
4731 dev_set_drvdata(&dsidev
->dev
, dsi
);
4733 dss_plat_data
= dsidev
->dev
.platform_data
;
4734 board_info
= dss_plat_data
->board_data
;
4735 dsi
->enable_pads
= board_info
->dsi_enable_pads
;
4736 dsi
->disable_pads
= board_info
->dsi_disable_pads
;
4738 spin_lock_init(&dsi
->irq_lock
);
4739 spin_lock_init(&dsi
->errors_lock
);
4742 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4743 spin_lock_init(&dsi
->irq_stats_lock
);
4744 dsi
->irq_stats
.last_reset
= jiffies
;
4747 mutex_init(&dsi
->lock
);
4748 sema_init(&dsi
->bus_lock
, 1);
4750 r
= dsi_get_clocks(dsidev
);
4754 pm_runtime_enable(&dsidev
->dev
);
4756 INIT_DELAYED_WORK_DEFERRABLE(&dsi
->framedone_timeout_work
,
4757 dsi_framedone_timeout_work_callback
);
4759 #ifdef DSI_CATCH_MISSING_TE
4760 init_timer(&dsi
->te_timer
);
4761 dsi
->te_timer
.function
= dsi_te_timeout
;
4762 dsi
->te_timer
.data
= 0;
4764 dsi_mem
= platform_get_resource(dsi
->pdev
, IORESOURCE_MEM
, 0);
4766 DSSERR("can't get IORESOURCE_MEM DSI\n");
4770 dsi
->base
= ioremap(dsi_mem
->start
, resource_size(dsi_mem
));
4772 DSSERR("can't ioremap DSI\n");
4776 dsi
->irq
= platform_get_irq(dsi
->pdev
, 0);
4778 DSSERR("platform_get_irq failed\n");
4783 r
= request_irq(dsi
->irq
, omap_dsi_irq_handler
, IRQF_SHARED
,
4784 dev_name(&dsidev
->dev
), dsi
->pdev
);
4786 DSSERR("request_irq failed\n");
4790 /* DSI VCs initialization */
4791 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
4792 dsi
->vc
[i
].source
= DSI_VC_SOURCE_L4
;
4793 dsi
->vc
[i
].dssdev
= NULL
;
4794 dsi
->vc
[i
].vc_id
= 0;
4797 dsi_calc_clock_param_ranges(dsidev
);
4799 r
= dsi_runtime_get(dsidev
);
4803 rev
= dsi_read_reg(dsidev
, DSI_REVISION
);
4804 dev_dbg(&dsidev
->dev
, "OMAP DSI rev %d.%d\n",
4805 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
4807 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4808 * of data to 3 by default */
4809 if (dss_has_feature(FEAT_DSI_GNQ
))
4811 dsi
->num_lanes_supported
= 1 + REG_GET(dsidev
, DSI_GNQ
, 11, 9);
4813 dsi
->num_lanes_supported
= 3;
4815 dsi_runtime_put(dsidev
);
4820 free_irq(dsi
->irq
, dsi
->pdev
);
4824 pm_runtime_disable(&dsidev
->dev
);
4831 static int omap_dsihw_remove(struct platform_device
*dsidev
)
4833 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4835 WARN_ON(dsi
->scp_clk_refcount
> 0);
4837 pm_runtime_disable(&dsidev
->dev
);
4839 dsi_put_clocks(dsidev
);
4841 if (dsi
->vdds_dsi_reg
!= NULL
) {
4842 if (dsi
->vdds_dsi_enabled
) {
4843 regulator_disable(dsi
->vdds_dsi_reg
);
4844 dsi
->vdds_dsi_enabled
= false;
4847 regulator_put(dsi
->vdds_dsi_reg
);
4848 dsi
->vdds_dsi_reg
= NULL
;
4851 free_irq(dsi
->irq
, dsi
->pdev
);
4859 static int dsi_runtime_suspend(struct device
*dev
)
4861 dispc_runtime_put();
4867 static int dsi_runtime_resume(struct device
*dev
)
4871 r
= dss_runtime_get();
4875 r
= dispc_runtime_get();
4887 static const struct dev_pm_ops dsi_pm_ops
= {
4888 .runtime_suspend
= dsi_runtime_suspend
,
4889 .runtime_resume
= dsi_runtime_resume
,
4892 static struct platform_driver omap_dsihw_driver
= {
4893 .probe
= omap_dsihw_probe
,
4894 .remove
= omap_dsihw_remove
,
4896 .name
= "omapdss_dsi",
4897 .owner
= THIS_MODULE
,
4902 int dsi_init_platform_driver(void)
4904 return platform_driver_register(&omap_dsihw_driver
);
4907 void dsi_uninit_platform_driver(void)
4909 return platform_driver_unregister(&omap_dsihw_driver
);