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OMAP: DSS2: DSI: Add OMAP4 CIO irqs
[mirror_ubuntu-bionic-kernel.git] / drivers / video / omap2 / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
36 #include <linux/sched.h>
37
38 #include <video/omapdss.h>
39 #include <plat/clock.h>
40
41 #include "dss.h"
42 #include "dss_features.h"
43
44 /*#define VERBOSE_IRQ*/
45 #define DSI_CATCH_MISSING_TE
46
47 struct dsi_reg { u16 idx; };
48
49 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
50
51 #define DSI_SZ_REGS SZ_1K
52 /* DSI Protocol Engine */
53
54 #define DSI_REVISION DSI_REG(0x0000)
55 #define DSI_SYSCONFIG DSI_REG(0x0010)
56 #define DSI_SYSSTATUS DSI_REG(0x0014)
57 #define DSI_IRQSTATUS DSI_REG(0x0018)
58 #define DSI_IRQENABLE DSI_REG(0x001C)
59 #define DSI_CTRL DSI_REG(0x0040)
60 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63 #define DSI_CLK_CTRL DSI_REG(0x0054)
64 #define DSI_TIMING1 DSI_REG(0x0058)
65 #define DSI_TIMING2 DSI_REG(0x005C)
66 #define DSI_VM_TIMING1 DSI_REG(0x0060)
67 #define DSI_VM_TIMING2 DSI_REG(0x0064)
68 #define DSI_VM_TIMING3 DSI_REG(0x0068)
69 #define DSI_CLK_TIMING DSI_REG(0x006C)
70 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74 #define DSI_VM_TIMING4 DSI_REG(0x0080)
75 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76 #define DSI_VM_TIMING5 DSI_REG(0x0088)
77 #define DSI_VM_TIMING6 DSI_REG(0x008C)
78 #define DSI_VM_TIMING7 DSI_REG(0x0090)
79 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
87
88 /* DSIPHY_SCP */
89
90 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
95
96 /* DSI_PLL_CTRL_SCP */
97
98 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
99 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
100 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
101 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
102 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
103
104 #define REG_GET(idx, start, end) \
105 FLD_GET(dsi_read_reg(idx), start, end)
106
107 #define REG_FLD_MOD(idx, val, start, end) \
108 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
109
110 /* Global interrupts */
111 #define DSI_IRQ_VC0 (1 << 0)
112 #define DSI_IRQ_VC1 (1 << 1)
113 #define DSI_IRQ_VC2 (1 << 2)
114 #define DSI_IRQ_VC3 (1 << 3)
115 #define DSI_IRQ_WAKEUP (1 << 4)
116 #define DSI_IRQ_RESYNC (1 << 5)
117 #define DSI_IRQ_PLL_LOCK (1 << 7)
118 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
119 #define DSI_IRQ_PLL_RECALL (1 << 9)
120 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
121 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
122 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
123 #define DSI_IRQ_TE_TRIGGER (1 << 16)
124 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
125 #define DSI_IRQ_SYNC_LOST (1 << 18)
126 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
127 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
128 #define DSI_IRQ_ERROR_MASK \
129 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
130 DSI_IRQ_TA_TIMEOUT)
131 #define DSI_IRQ_CHANNEL_MASK 0xf
132
133 /* Virtual channel interrupts */
134 #define DSI_VC_IRQ_CS (1 << 0)
135 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
136 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
137 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
138 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
139 #define DSI_VC_IRQ_BTA (1 << 5)
140 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
141 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
142 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
143 #define DSI_VC_IRQ_ERROR_MASK \
144 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
145 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
146 DSI_VC_IRQ_FIFO_TX_UDF)
147
148 /* ComplexIO interrupts */
149 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
150 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
151 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
152 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
153 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
154 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
155 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
156 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
157 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
158 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
159 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
160 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
161 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
162 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
163 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
164 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
165 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
166 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
167 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
168 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
169 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
170 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
171 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
172 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
179 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
180 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
181 #define DSI_CIO_IRQ_ERROR_MASK \
182 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
183 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
184 DSI_CIO_IRQ_ERRSYNCESC5 | \
185 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
186 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
187 DSI_CIO_IRQ_ERRESC5 | \
188 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
189 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
190 DSI_CIO_IRQ_ERRCONTROL5 | \
191 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
192 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
193 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
194 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
195 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
196
197 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
198 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
199 #define DSI_DT_DCS_READ 0x06
200 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
201 #define DSI_DT_NULL_PACKET 0x09
202 #define DSI_DT_DCS_LONG_WRITE 0x39
203
204 #define DSI_DT_RX_ACK_WITH_ERR 0x02
205 #define DSI_DT_RX_DCS_LONG_READ 0x1c
206 #define DSI_DT_RX_SHORT_READ_1 0x21
207 #define DSI_DT_RX_SHORT_READ_2 0x22
208
209 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
210
211 #define DSI_MAX_NR_ISRS 2
212
213 struct dsi_isr_data {
214 omap_dsi_isr_t isr;
215 void *arg;
216 u32 mask;
217 };
218
219 enum fifo_size {
220 DSI_FIFO_SIZE_0 = 0,
221 DSI_FIFO_SIZE_32 = 1,
222 DSI_FIFO_SIZE_64 = 2,
223 DSI_FIFO_SIZE_96 = 3,
224 DSI_FIFO_SIZE_128 = 4,
225 };
226
227 enum dsi_vc_mode {
228 DSI_VC_MODE_L4 = 0,
229 DSI_VC_MODE_VP,
230 };
231
232 enum dsi_lane {
233 DSI_CLK_P = 1 << 0,
234 DSI_CLK_N = 1 << 1,
235 DSI_DATA1_P = 1 << 2,
236 DSI_DATA1_N = 1 << 3,
237 DSI_DATA2_P = 1 << 4,
238 DSI_DATA2_N = 1 << 5,
239 };
240
241 struct dsi_update_region {
242 u16 x, y, w, h;
243 struct omap_dss_device *device;
244 };
245
246 struct dsi_irq_stats {
247 unsigned long last_reset;
248 unsigned irq_count;
249 unsigned dsi_irqs[32];
250 unsigned vc_irqs[4][32];
251 unsigned cio_irqs[32];
252 };
253
254 struct dsi_isr_tables {
255 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
256 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
257 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
258 };
259
260 static struct
261 {
262 struct platform_device *pdev;
263 void __iomem *base;
264 int irq;
265
266 void (*dsi_mux_pads)(bool enable);
267
268 struct dsi_clock_info current_cinfo;
269
270 bool vdds_dsi_enabled;
271 struct regulator *vdds_dsi_reg;
272
273 struct {
274 enum dsi_vc_mode mode;
275 struct omap_dss_device *dssdev;
276 enum fifo_size fifo_size;
277 int vc_id;
278 } vc[4];
279
280 struct mutex lock;
281 struct semaphore bus_lock;
282
283 unsigned pll_locked;
284
285 spinlock_t irq_lock;
286 struct dsi_isr_tables isr_tables;
287 /* space for a copy used by the interrupt handler */
288 struct dsi_isr_tables isr_tables_copy;
289
290 int update_channel;
291 struct dsi_update_region update_region;
292
293 bool te_enabled;
294 bool ulps_enabled;
295
296 struct workqueue_struct *workqueue;
297
298 void (*framedone_callback)(int, void *);
299 void *framedone_data;
300
301 struct delayed_work framedone_timeout_work;
302
303 #ifdef DSI_CATCH_MISSING_TE
304 struct timer_list te_timer;
305 #endif
306
307 unsigned long cache_req_pck;
308 unsigned long cache_clk_freq;
309 struct dsi_clock_info cache_cinfo;
310
311 u32 errors;
312 spinlock_t errors_lock;
313 #ifdef DEBUG
314 ktime_t perf_setup_time;
315 ktime_t perf_start_time;
316 #endif
317 int debug_read;
318 int debug_write;
319
320 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
321 spinlock_t irq_stats_lock;
322 struct dsi_irq_stats irq_stats;
323 #endif
324 /* DSI PLL Parameter Ranges */
325 unsigned long regm_max, regn_max;
326 unsigned long regm_dispc_max, regm_dsi_max;
327 unsigned long fint_min, fint_max;
328 unsigned long lpdiv_max;
329
330 unsigned scp_clk_refcount;
331 } dsi;
332
333 #ifdef DEBUG
334 static unsigned int dsi_perf;
335 module_param_named(dsi_perf, dsi_perf, bool, 0644);
336 #endif
337
338 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
339 {
340 __raw_writel(val, dsi.base + idx.idx);
341 }
342
343 static inline u32 dsi_read_reg(const struct dsi_reg idx)
344 {
345 return __raw_readl(dsi.base + idx.idx);
346 }
347
348
349 void dsi_save_context(void)
350 {
351 }
352
353 void dsi_restore_context(void)
354 {
355 }
356
357 void dsi_bus_lock(void)
358 {
359 down(&dsi.bus_lock);
360 }
361 EXPORT_SYMBOL(dsi_bus_lock);
362
363 void dsi_bus_unlock(void)
364 {
365 up(&dsi.bus_lock);
366 }
367 EXPORT_SYMBOL(dsi_bus_unlock);
368
369 static bool dsi_bus_is_locked(void)
370 {
371 return dsi.bus_lock.count == 0;
372 }
373
374 static void dsi_completion_handler(void *data, u32 mask)
375 {
376 complete((struct completion *)data);
377 }
378
379 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
380 int value)
381 {
382 int t = 100000;
383
384 while (REG_GET(idx, bitnum, bitnum) != value) {
385 if (--t == 0)
386 return !value;
387 }
388
389 return value;
390 }
391
392 #ifdef DEBUG
393 static void dsi_perf_mark_setup(void)
394 {
395 dsi.perf_setup_time = ktime_get();
396 }
397
398 static void dsi_perf_mark_start(void)
399 {
400 dsi.perf_start_time = ktime_get();
401 }
402
403 static void dsi_perf_show(const char *name)
404 {
405 ktime_t t, setup_time, trans_time;
406 u32 total_bytes;
407 u32 setup_us, trans_us, total_us;
408
409 if (!dsi_perf)
410 return;
411
412 t = ktime_get();
413
414 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
415 setup_us = (u32)ktime_to_us(setup_time);
416 if (setup_us == 0)
417 setup_us = 1;
418
419 trans_time = ktime_sub(t, dsi.perf_start_time);
420 trans_us = (u32)ktime_to_us(trans_time);
421 if (trans_us == 0)
422 trans_us = 1;
423
424 total_us = setup_us + trans_us;
425
426 total_bytes = dsi.update_region.w *
427 dsi.update_region.h *
428 dsi.update_region.device->ctrl.pixel_size / 8;
429
430 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
431 "%u bytes, %u kbytes/sec\n",
432 name,
433 setup_us,
434 trans_us,
435 total_us,
436 1000*1000 / total_us,
437 total_bytes,
438 total_bytes * 1000 / total_us);
439 }
440 #else
441 #define dsi_perf_mark_setup()
442 #define dsi_perf_mark_start()
443 #define dsi_perf_show(x)
444 #endif
445
446 static void print_irq_status(u32 status)
447 {
448 if (status == 0)
449 return;
450
451 #ifndef VERBOSE_IRQ
452 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
453 return;
454 #endif
455 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
456
457 #define PIS(x) \
458 if (status & DSI_IRQ_##x) \
459 printk(#x " ");
460 #ifdef VERBOSE_IRQ
461 PIS(VC0);
462 PIS(VC1);
463 PIS(VC2);
464 PIS(VC3);
465 #endif
466 PIS(WAKEUP);
467 PIS(RESYNC);
468 PIS(PLL_LOCK);
469 PIS(PLL_UNLOCK);
470 PIS(PLL_RECALL);
471 PIS(COMPLEXIO_ERR);
472 PIS(HS_TX_TIMEOUT);
473 PIS(LP_RX_TIMEOUT);
474 PIS(TE_TRIGGER);
475 PIS(ACK_TRIGGER);
476 PIS(SYNC_LOST);
477 PIS(LDO_POWER_GOOD);
478 PIS(TA_TIMEOUT);
479 #undef PIS
480
481 printk("\n");
482 }
483
484 static void print_irq_status_vc(int channel, u32 status)
485 {
486 if (status == 0)
487 return;
488
489 #ifndef VERBOSE_IRQ
490 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
491 return;
492 #endif
493 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
494
495 #define PIS(x) \
496 if (status & DSI_VC_IRQ_##x) \
497 printk(#x " ");
498 PIS(CS);
499 PIS(ECC_CORR);
500 #ifdef VERBOSE_IRQ
501 PIS(PACKET_SENT);
502 #endif
503 PIS(FIFO_TX_OVF);
504 PIS(FIFO_RX_OVF);
505 PIS(BTA);
506 PIS(ECC_NO_CORR);
507 PIS(FIFO_TX_UDF);
508 PIS(PP_BUSY_CHANGE);
509 #undef PIS
510 printk("\n");
511 }
512
513 static void print_irq_status_cio(u32 status)
514 {
515 if (status == 0)
516 return;
517
518 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
519
520 #define PIS(x) \
521 if (status & DSI_CIO_IRQ_##x) \
522 printk(#x " ");
523 PIS(ERRSYNCESC1);
524 PIS(ERRSYNCESC2);
525 PIS(ERRSYNCESC3);
526 PIS(ERRESC1);
527 PIS(ERRESC2);
528 PIS(ERRESC3);
529 PIS(ERRCONTROL1);
530 PIS(ERRCONTROL2);
531 PIS(ERRCONTROL3);
532 PIS(STATEULPS1);
533 PIS(STATEULPS2);
534 PIS(STATEULPS3);
535 PIS(ERRCONTENTIONLP0_1);
536 PIS(ERRCONTENTIONLP1_1);
537 PIS(ERRCONTENTIONLP0_2);
538 PIS(ERRCONTENTIONLP1_2);
539 PIS(ERRCONTENTIONLP0_3);
540 PIS(ERRCONTENTIONLP1_3);
541 PIS(ULPSACTIVENOT_ALL0);
542 PIS(ULPSACTIVENOT_ALL1);
543 #undef PIS
544
545 printk("\n");
546 }
547
548 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
549 static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
550 {
551 int i;
552
553 spin_lock(&dsi.irq_stats_lock);
554
555 dsi.irq_stats.irq_count++;
556 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
557
558 for (i = 0; i < 4; ++i)
559 dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]);
560
561 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
562
563 spin_unlock(&dsi.irq_stats_lock);
564 }
565 #else
566 #define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus)
567 #endif
568
569 static int debug_irq;
570
571 static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
572 {
573 int i;
574
575 if (irqstatus & DSI_IRQ_ERROR_MASK) {
576 DSSERR("DSI error, irqstatus %x\n", irqstatus);
577 print_irq_status(irqstatus);
578 spin_lock(&dsi.errors_lock);
579 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
580 spin_unlock(&dsi.errors_lock);
581 } else if (debug_irq) {
582 print_irq_status(irqstatus);
583 }
584
585 for (i = 0; i < 4; ++i) {
586 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
587 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
588 i, vcstatus[i]);
589 print_irq_status_vc(i, vcstatus[i]);
590 } else if (debug_irq) {
591 print_irq_status_vc(i, vcstatus[i]);
592 }
593 }
594
595 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
596 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
597 print_irq_status_cio(ciostatus);
598 } else if (debug_irq) {
599 print_irq_status_cio(ciostatus);
600 }
601 }
602
603 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
604 unsigned isr_array_size, u32 irqstatus)
605 {
606 struct dsi_isr_data *isr_data;
607 int i;
608
609 for (i = 0; i < isr_array_size; i++) {
610 isr_data = &isr_array[i];
611 if (isr_data->isr && isr_data->mask & irqstatus)
612 isr_data->isr(isr_data->arg, irqstatus);
613 }
614 }
615
616 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
617 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
618 {
619 int i;
620
621 dsi_call_isrs(isr_tables->isr_table,
622 ARRAY_SIZE(isr_tables->isr_table),
623 irqstatus);
624
625 for (i = 0; i < 4; ++i) {
626 if (vcstatus[i] == 0)
627 continue;
628 dsi_call_isrs(isr_tables->isr_table_vc[i],
629 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
630 vcstatus[i]);
631 }
632
633 if (ciostatus != 0)
634 dsi_call_isrs(isr_tables->isr_table_cio,
635 ARRAY_SIZE(isr_tables->isr_table_cio),
636 ciostatus);
637 }
638
639 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
640 {
641 u32 irqstatus, vcstatus[4], ciostatus;
642 int i;
643
644 spin_lock(&dsi.irq_lock);
645
646 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
647
648 /* IRQ is not for us */
649 if (!irqstatus) {
650 spin_unlock(&dsi.irq_lock);
651 return IRQ_NONE;
652 }
653
654 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
655 /* flush posted write */
656 dsi_read_reg(DSI_IRQSTATUS);
657
658 for (i = 0; i < 4; ++i) {
659 if ((irqstatus & (1 << i)) == 0) {
660 vcstatus[i] = 0;
661 continue;
662 }
663
664 vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i));
665
666 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]);
667 /* flush posted write */
668 dsi_read_reg(DSI_VC_IRQSTATUS(i));
669 }
670
671 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
672 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
673
674 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
675 /* flush posted write */
676 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
677 } else {
678 ciostatus = 0;
679 }
680
681 #ifdef DSI_CATCH_MISSING_TE
682 if (irqstatus & DSI_IRQ_TE_TRIGGER)
683 del_timer(&dsi.te_timer);
684 #endif
685
686 /* make a copy and unlock, so that isrs can unregister
687 * themselves */
688 memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables));
689
690 spin_unlock(&dsi.irq_lock);
691
692 dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus);
693
694 dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus);
695
696 dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus);
697
698 return IRQ_HANDLED;
699 }
700
701 /* dsi.irq_lock has to be locked by the caller */
702 static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array,
703 unsigned isr_array_size, u32 default_mask,
704 const struct dsi_reg enable_reg,
705 const struct dsi_reg status_reg)
706 {
707 struct dsi_isr_data *isr_data;
708 u32 mask;
709 u32 old_mask;
710 int i;
711
712 mask = default_mask;
713
714 for (i = 0; i < isr_array_size; i++) {
715 isr_data = &isr_array[i];
716
717 if (isr_data->isr == NULL)
718 continue;
719
720 mask |= isr_data->mask;
721 }
722
723 old_mask = dsi_read_reg(enable_reg);
724 /* clear the irqstatus for newly enabled irqs */
725 dsi_write_reg(status_reg, (mask ^ old_mask) & mask);
726 dsi_write_reg(enable_reg, mask);
727
728 /* flush posted writes */
729 dsi_read_reg(enable_reg);
730 dsi_read_reg(status_reg);
731 }
732
733 /* dsi.irq_lock has to be locked by the caller */
734 static void _omap_dsi_set_irqs(void)
735 {
736 u32 mask = DSI_IRQ_ERROR_MASK;
737 #ifdef DSI_CATCH_MISSING_TE
738 mask |= DSI_IRQ_TE_TRIGGER;
739 #endif
740 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table,
741 ARRAY_SIZE(dsi.isr_tables.isr_table), mask,
742 DSI_IRQENABLE, DSI_IRQSTATUS);
743 }
744
745 /* dsi.irq_lock has to be locked by the caller */
746 static void _omap_dsi_set_irqs_vc(int vc)
747 {
748 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc],
749 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]),
750 DSI_VC_IRQ_ERROR_MASK,
751 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
752 }
753
754 /* dsi.irq_lock has to be locked by the caller */
755 static void _omap_dsi_set_irqs_cio(void)
756 {
757 _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio,
758 ARRAY_SIZE(dsi.isr_tables.isr_table_cio),
759 DSI_CIO_IRQ_ERROR_MASK,
760 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
761 }
762
763 static void _dsi_initialize_irq(void)
764 {
765 unsigned long flags;
766 int vc;
767
768 spin_lock_irqsave(&dsi.irq_lock, flags);
769
770 memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables));
771
772 _omap_dsi_set_irqs();
773 for (vc = 0; vc < 4; ++vc)
774 _omap_dsi_set_irqs_vc(vc);
775 _omap_dsi_set_irqs_cio();
776
777 spin_unlock_irqrestore(&dsi.irq_lock, flags);
778 }
779
780 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
781 struct dsi_isr_data *isr_array, unsigned isr_array_size)
782 {
783 struct dsi_isr_data *isr_data;
784 int free_idx;
785 int i;
786
787 BUG_ON(isr == NULL);
788
789 /* check for duplicate entry and find a free slot */
790 free_idx = -1;
791 for (i = 0; i < isr_array_size; i++) {
792 isr_data = &isr_array[i];
793
794 if (isr_data->isr == isr && isr_data->arg == arg &&
795 isr_data->mask == mask) {
796 return -EINVAL;
797 }
798
799 if (isr_data->isr == NULL && free_idx == -1)
800 free_idx = i;
801 }
802
803 if (free_idx == -1)
804 return -EBUSY;
805
806 isr_data = &isr_array[free_idx];
807 isr_data->isr = isr;
808 isr_data->arg = arg;
809 isr_data->mask = mask;
810
811 return 0;
812 }
813
814 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
815 struct dsi_isr_data *isr_array, unsigned isr_array_size)
816 {
817 struct dsi_isr_data *isr_data;
818 int i;
819
820 for (i = 0; i < isr_array_size; i++) {
821 isr_data = &isr_array[i];
822 if (isr_data->isr != isr || isr_data->arg != arg ||
823 isr_data->mask != mask)
824 continue;
825
826 isr_data->isr = NULL;
827 isr_data->arg = NULL;
828 isr_data->mask = 0;
829
830 return 0;
831 }
832
833 return -EINVAL;
834 }
835
836 static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
837 {
838 unsigned long flags;
839 int r;
840
841 spin_lock_irqsave(&dsi.irq_lock, flags);
842
843 r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table,
844 ARRAY_SIZE(dsi.isr_tables.isr_table));
845
846 if (r == 0)
847 _omap_dsi_set_irqs();
848
849 spin_unlock_irqrestore(&dsi.irq_lock, flags);
850
851 return r;
852 }
853
854 static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
855 {
856 unsigned long flags;
857 int r;
858
859 spin_lock_irqsave(&dsi.irq_lock, flags);
860
861 r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table,
862 ARRAY_SIZE(dsi.isr_tables.isr_table));
863
864 if (r == 0)
865 _omap_dsi_set_irqs();
866
867 spin_unlock_irqrestore(&dsi.irq_lock, flags);
868
869 return r;
870 }
871
872 static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
873 u32 mask)
874 {
875 unsigned long flags;
876 int r;
877
878 spin_lock_irqsave(&dsi.irq_lock, flags);
879
880 r = _dsi_register_isr(isr, arg, mask,
881 dsi.isr_tables.isr_table_vc[channel],
882 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
883
884 if (r == 0)
885 _omap_dsi_set_irqs_vc(channel);
886
887 spin_unlock_irqrestore(&dsi.irq_lock, flags);
888
889 return r;
890 }
891
892 static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
893 u32 mask)
894 {
895 unsigned long flags;
896 int r;
897
898 spin_lock_irqsave(&dsi.irq_lock, flags);
899
900 r = _dsi_unregister_isr(isr, arg, mask,
901 dsi.isr_tables.isr_table_vc[channel],
902 ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
903
904 if (r == 0)
905 _omap_dsi_set_irqs_vc(channel);
906
907 spin_unlock_irqrestore(&dsi.irq_lock, flags);
908
909 return r;
910 }
911
912 static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
913 {
914 unsigned long flags;
915 int r;
916
917 spin_lock_irqsave(&dsi.irq_lock, flags);
918
919 r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
920 ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
921
922 if (r == 0)
923 _omap_dsi_set_irqs_cio();
924
925 spin_unlock_irqrestore(&dsi.irq_lock, flags);
926
927 return r;
928 }
929
930 static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
931 {
932 unsigned long flags;
933 int r;
934
935 spin_lock_irqsave(&dsi.irq_lock, flags);
936
937 r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
938 ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
939
940 if (r == 0)
941 _omap_dsi_set_irqs_cio();
942
943 spin_unlock_irqrestore(&dsi.irq_lock, flags);
944
945 return r;
946 }
947
948 static u32 dsi_get_errors(void)
949 {
950 unsigned long flags;
951 u32 e;
952 spin_lock_irqsave(&dsi.errors_lock, flags);
953 e = dsi.errors;
954 dsi.errors = 0;
955 spin_unlock_irqrestore(&dsi.errors_lock, flags);
956 return e;
957 }
958
959 /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */
960 static inline void enable_clocks(bool enable)
961 {
962 if (enable)
963 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
964 else
965 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
966 }
967
968 /* source clock for DSI PLL. this could also be PCLKFREE */
969 static inline void dsi_enable_pll_clock(bool enable)
970 {
971 if (enable)
972 dss_clk_enable(DSS_CLK_SYSCK);
973 else
974 dss_clk_disable(DSS_CLK_SYSCK);
975
976 if (enable && dsi.pll_locked) {
977 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
978 DSSERR("cannot lock PLL when enabling clocks\n");
979 }
980 }
981
982 #ifdef DEBUG
983 static void _dsi_print_reset_status(void)
984 {
985 u32 l;
986 int b0, b1, b2;
987
988 if (!dss_debug)
989 return;
990
991 /* A dummy read using the SCP interface to any DSIPHY register is
992 * required after DSIPHY reset to complete the reset of the DSI complex
993 * I/O. */
994 l = dsi_read_reg(DSI_DSIPHY_CFG5);
995
996 printk(KERN_DEBUG "DSI resets: ");
997
998 l = dsi_read_reg(DSI_PLL_STATUS);
999 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1000
1001 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1002 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1003
1004 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1005 b0 = 28;
1006 b1 = 27;
1007 b2 = 26;
1008 } else {
1009 b0 = 24;
1010 b1 = 25;
1011 b2 = 26;
1012 }
1013
1014 l = dsi_read_reg(DSI_DSIPHY_CFG5);
1015 printk("PHY (%x%x%x, %d, %d, %d)\n",
1016 FLD_GET(l, b0, b0),
1017 FLD_GET(l, b1, b1),
1018 FLD_GET(l, b2, b2),
1019 FLD_GET(l, 29, 29),
1020 FLD_GET(l, 30, 30),
1021 FLD_GET(l, 31, 31));
1022 }
1023 #else
1024 #define _dsi_print_reset_status()
1025 #endif
1026
1027 static inline int dsi_if_enable(bool enable)
1028 {
1029 DSSDBG("dsi_if_enable(%d)\n", enable);
1030
1031 enable = enable ? 1 : 0;
1032 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
1033
1034 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
1035 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1036 return -EIO;
1037 }
1038
1039 return 0;
1040 }
1041
1042 unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
1043 {
1044 return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk;
1045 }
1046
1047 static unsigned long dsi_get_pll_hsdiv_dsi_rate(void)
1048 {
1049 return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk;
1050 }
1051
1052 static unsigned long dsi_get_txbyteclkhs(void)
1053 {
1054 return dsi.current_cinfo.clkin4ddr / 16;
1055 }
1056
1057 static unsigned long dsi_fclk_rate(void)
1058 {
1059 unsigned long r;
1060
1061 if (dss_get_dsi_clk_source() == OMAP_DSS_CLK_SRC_FCK) {
1062 /* DSI FCLK source is DSS_CLK_FCK */
1063 r = dss_clk_get_rate(DSS_CLK_FCK);
1064 } else {
1065 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1066 r = dsi_get_pll_hsdiv_dsi_rate();
1067 }
1068
1069 return r;
1070 }
1071
1072 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1073 {
1074 unsigned long dsi_fclk;
1075 unsigned lp_clk_div;
1076 unsigned long lp_clk;
1077
1078 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1079
1080 if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max)
1081 return -EINVAL;
1082
1083 dsi_fclk = dsi_fclk_rate();
1084
1085 lp_clk = dsi_fclk / 2 / lp_clk_div;
1086
1087 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1088 dsi.current_cinfo.lp_clk = lp_clk;
1089 dsi.current_cinfo.lp_clk_div = lp_clk_div;
1090
1091 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
1092
1093 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
1094 21, 21); /* LP_RX_SYNCHRO_ENABLE */
1095
1096 return 0;
1097 }
1098
1099 static void dsi_enable_scp_clk(void)
1100 {
1101 if (dsi.scp_clk_refcount++ == 0)
1102 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1103 }
1104
1105 static void dsi_disable_scp_clk(void)
1106 {
1107 WARN_ON(dsi.scp_clk_refcount == 0);
1108 if (--dsi.scp_clk_refcount == 0)
1109 REG_FLD_MOD(DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1110 }
1111
1112 enum dsi_pll_power_state {
1113 DSI_PLL_POWER_OFF = 0x0,
1114 DSI_PLL_POWER_ON_HSCLK = 0x1,
1115 DSI_PLL_POWER_ON_ALL = 0x2,
1116 DSI_PLL_POWER_ON_DIV = 0x3,
1117 };
1118
1119 static int dsi_pll_power(enum dsi_pll_power_state state)
1120 {
1121 int t = 0;
1122
1123 /* DSI-PLL power command 0x3 is not working */
1124 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1125 state == DSI_PLL_POWER_ON_DIV)
1126 state = DSI_PLL_POWER_ON_ALL;
1127
1128 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
1129
1130 /* PLL_PWR_STATUS */
1131 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
1132 if (++t > 1000) {
1133 DSSERR("Failed to set DSI PLL power mode to %d\n",
1134 state);
1135 return -ENODEV;
1136 }
1137 udelay(1);
1138 }
1139
1140 return 0;
1141 }
1142
1143 /* calculate clock rates using dividers in cinfo */
1144 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1145 struct dsi_clock_info *cinfo)
1146 {
1147 if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max)
1148 return -EINVAL;
1149
1150 if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max)
1151 return -EINVAL;
1152
1153 if (cinfo->regm_dispc > dsi.regm_dispc_max)
1154 return -EINVAL;
1155
1156 if (cinfo->regm_dsi > dsi.regm_dsi_max)
1157 return -EINVAL;
1158
1159 if (cinfo->use_sys_clk) {
1160 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
1161 /* XXX it is unclear if highfreq should be used
1162 * with DSS_SYS_CLK source also */
1163 cinfo->highfreq = 0;
1164 } else {
1165 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
1166
1167 if (cinfo->clkin < 32000000)
1168 cinfo->highfreq = 0;
1169 else
1170 cinfo->highfreq = 1;
1171 }
1172
1173 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1174
1175 if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min)
1176 return -EINVAL;
1177
1178 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1179
1180 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1181 return -EINVAL;
1182
1183 if (cinfo->regm_dispc > 0)
1184 cinfo->dsi_pll_hsdiv_dispc_clk =
1185 cinfo->clkin4ddr / cinfo->regm_dispc;
1186 else
1187 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1188
1189 if (cinfo->regm_dsi > 0)
1190 cinfo->dsi_pll_hsdiv_dsi_clk =
1191 cinfo->clkin4ddr / cinfo->regm_dsi;
1192 else
1193 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1194
1195 return 0;
1196 }
1197
1198 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
1199 struct dsi_clock_info *dsi_cinfo,
1200 struct dispc_clock_info *dispc_cinfo)
1201 {
1202 struct dsi_clock_info cur, best;
1203 struct dispc_clock_info best_dispc;
1204 int min_fck_per_pck;
1205 int match = 0;
1206 unsigned long dss_sys_clk, max_dss_fck;
1207
1208 dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK);
1209
1210 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1211
1212 if (req_pck == dsi.cache_req_pck &&
1213 dsi.cache_cinfo.clkin == dss_sys_clk) {
1214 DSSDBG("DSI clock info found from cache\n");
1215 *dsi_cinfo = dsi.cache_cinfo;
1216 dispc_find_clk_divs(is_tft, req_pck,
1217 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1218 return 0;
1219 }
1220
1221 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1222
1223 if (min_fck_per_pck &&
1224 req_pck * min_fck_per_pck > max_dss_fck) {
1225 DSSERR("Requested pixel clock not possible with the current "
1226 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1227 "the constraint off.\n");
1228 min_fck_per_pck = 0;
1229 }
1230
1231 DSSDBG("dsi_pll_calc\n");
1232
1233 retry:
1234 memset(&best, 0, sizeof(best));
1235 memset(&best_dispc, 0, sizeof(best_dispc));
1236
1237 memset(&cur, 0, sizeof(cur));
1238 cur.clkin = dss_sys_clk;
1239 cur.use_sys_clk = 1;
1240 cur.highfreq = 0;
1241
1242 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1243 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1244 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1245 for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) {
1246 if (cur.highfreq == 0)
1247 cur.fint = cur.clkin / cur.regn;
1248 else
1249 cur.fint = cur.clkin / (2 * cur.regn);
1250
1251 if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min)
1252 continue;
1253
1254 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1255 for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) {
1256 unsigned long a, b;
1257
1258 a = 2 * cur.regm * (cur.clkin/1000);
1259 b = cur.regn * (cur.highfreq + 1);
1260 cur.clkin4ddr = a / b * 1000;
1261
1262 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1263 break;
1264
1265 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1266 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1267 for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max;
1268 ++cur.regm_dispc) {
1269 struct dispc_clock_info cur_dispc;
1270 cur.dsi_pll_hsdiv_dispc_clk =
1271 cur.clkin4ddr / cur.regm_dispc;
1272
1273 /* this will narrow down the search a bit,
1274 * but still give pixclocks below what was
1275 * requested */
1276 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1277 break;
1278
1279 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1280 continue;
1281
1282 if (min_fck_per_pck &&
1283 cur.dsi_pll_hsdiv_dispc_clk <
1284 req_pck * min_fck_per_pck)
1285 continue;
1286
1287 match = 1;
1288
1289 dispc_find_clk_divs(is_tft, req_pck,
1290 cur.dsi_pll_hsdiv_dispc_clk,
1291 &cur_dispc);
1292
1293 if (abs(cur_dispc.pck - req_pck) <
1294 abs(best_dispc.pck - req_pck)) {
1295 best = cur;
1296 best_dispc = cur_dispc;
1297
1298 if (cur_dispc.pck == req_pck)
1299 goto found;
1300 }
1301 }
1302 }
1303 }
1304 found:
1305 if (!match) {
1306 if (min_fck_per_pck) {
1307 DSSERR("Could not find suitable clock settings.\n"
1308 "Turning FCK/PCK constraint off and"
1309 "trying again.\n");
1310 min_fck_per_pck = 0;
1311 goto retry;
1312 }
1313
1314 DSSERR("Could not find suitable clock settings.\n");
1315
1316 return -EINVAL;
1317 }
1318
1319 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1320 best.regm_dsi = 0;
1321 best.dsi_pll_hsdiv_dsi_clk = 0;
1322
1323 if (dsi_cinfo)
1324 *dsi_cinfo = best;
1325 if (dispc_cinfo)
1326 *dispc_cinfo = best_dispc;
1327
1328 dsi.cache_req_pck = req_pck;
1329 dsi.cache_clk_freq = 0;
1330 dsi.cache_cinfo = best;
1331
1332 return 0;
1333 }
1334
1335 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
1336 {
1337 int r = 0;
1338 u32 l;
1339 int f = 0;
1340 u8 regn_start, regn_end, regm_start, regm_end;
1341 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1342
1343 DSSDBGF();
1344
1345 dsi.current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1346 dsi.current_cinfo.highfreq = cinfo->highfreq;
1347
1348 dsi.current_cinfo.fint = cinfo->fint;
1349 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1350 dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk =
1351 cinfo->dsi_pll_hsdiv_dispc_clk;
1352 dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk =
1353 cinfo->dsi_pll_hsdiv_dsi_clk;
1354
1355 dsi.current_cinfo.regn = cinfo->regn;
1356 dsi.current_cinfo.regm = cinfo->regm;
1357 dsi.current_cinfo.regm_dispc = cinfo->regm_dispc;
1358 dsi.current_cinfo.regm_dsi = cinfo->regm_dsi;
1359
1360 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1361
1362 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1363 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1364 cinfo->clkin,
1365 cinfo->highfreq);
1366
1367 /* DSIPHY == CLKIN4DDR */
1368 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1369 cinfo->regm,
1370 cinfo->regn,
1371 cinfo->clkin,
1372 cinfo->highfreq + 1,
1373 cinfo->clkin4ddr);
1374
1375 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1376 cinfo->clkin4ddr / 1000 / 1000 / 2);
1377
1378 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1379
1380 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1381 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1382 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1383 cinfo->dsi_pll_hsdiv_dispc_clk);
1384 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1385 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1386 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1387 cinfo->dsi_pll_hsdiv_dsi_clk);
1388
1389 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1390 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1391 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1392 &regm_dispc_end);
1393 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1394 &regm_dsi_end);
1395
1396 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1397
1398 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1399 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1400 /* DSI_PLL_REGN */
1401 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1402 /* DSI_PLL_REGM */
1403 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1404 /* DSI_CLOCK_DIV */
1405 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1406 regm_dispc_start, regm_dispc_end);
1407 /* DSIPROTO_CLOCK_DIV */
1408 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1409 regm_dsi_start, regm_dsi_end);
1410 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1411
1412 BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
1413
1414 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1415 f = cinfo->fint < 1000000 ? 0x3 :
1416 cinfo->fint < 1250000 ? 0x4 :
1417 cinfo->fint < 1500000 ? 0x5 :
1418 cinfo->fint < 1750000 ? 0x6 :
1419 0x7;
1420 }
1421
1422 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1423
1424 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1425 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1426 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1427 11, 11); /* DSI_PLL_CLKSEL */
1428 l = FLD_MOD(l, cinfo->highfreq,
1429 12, 12); /* DSI_PLL_HIGHFREQ */
1430 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1431 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1432 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1433 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1434
1435 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1436
1437 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1438 DSSERR("dsi pll go bit not going down.\n");
1439 r = -EIO;
1440 goto err;
1441 }
1442
1443 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1444 DSSERR("cannot lock PLL\n");
1445 r = -EIO;
1446 goto err;
1447 }
1448
1449 dsi.pll_locked = 1;
1450
1451 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1452 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1453 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1454 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1455 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1456 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1457 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1458 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1459 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1460 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1461 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1462 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1463 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1464 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1465 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1466 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1467
1468 DSSDBG("PLL config done\n");
1469 err:
1470 return r;
1471 }
1472
1473 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1474 bool enable_hsdiv)
1475 {
1476 int r = 0;
1477 enum dsi_pll_power_state pwstate;
1478
1479 DSSDBG("PLL init\n");
1480
1481 if (dsi.vdds_dsi_reg == NULL) {
1482 struct regulator *vdds_dsi;
1483
1484 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
1485
1486 if (IS_ERR(vdds_dsi)) {
1487 DSSERR("can't get VDDS_DSI regulator\n");
1488 return PTR_ERR(vdds_dsi);
1489 }
1490
1491 dsi.vdds_dsi_reg = vdds_dsi;
1492 }
1493
1494 enable_clocks(1);
1495 dsi_enable_pll_clock(1);
1496 /*
1497 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1498 */
1499 dsi_enable_scp_clk();
1500
1501 if (!dsi.vdds_dsi_enabled) {
1502 r = regulator_enable(dsi.vdds_dsi_reg);
1503 if (r)
1504 goto err0;
1505 dsi.vdds_dsi_enabled = true;
1506 }
1507
1508 /* XXX PLL does not come out of reset without this... */
1509 dispc_pck_free_enable(1);
1510
1511 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1512 DSSERR("PLL not coming out of reset.\n");
1513 r = -ENODEV;
1514 dispc_pck_free_enable(0);
1515 goto err1;
1516 }
1517
1518 /* XXX ... but if left on, we get problems when planes do not
1519 * fill the whole display. No idea about this */
1520 dispc_pck_free_enable(0);
1521
1522 if (enable_hsclk && enable_hsdiv)
1523 pwstate = DSI_PLL_POWER_ON_ALL;
1524 else if (enable_hsclk)
1525 pwstate = DSI_PLL_POWER_ON_HSCLK;
1526 else if (enable_hsdiv)
1527 pwstate = DSI_PLL_POWER_ON_DIV;
1528 else
1529 pwstate = DSI_PLL_POWER_OFF;
1530
1531 r = dsi_pll_power(pwstate);
1532
1533 if (r)
1534 goto err1;
1535
1536 DSSDBG("PLL init done\n");
1537
1538 return 0;
1539 err1:
1540 if (dsi.vdds_dsi_enabled) {
1541 regulator_disable(dsi.vdds_dsi_reg);
1542 dsi.vdds_dsi_enabled = false;
1543 }
1544 err0:
1545 dsi_disable_scp_clk();
1546 enable_clocks(0);
1547 dsi_enable_pll_clock(0);
1548 return r;
1549 }
1550
1551 void dsi_pll_uninit(bool disconnect_lanes)
1552 {
1553 dsi.pll_locked = 0;
1554 dsi_pll_power(DSI_PLL_POWER_OFF);
1555 if (disconnect_lanes) {
1556 WARN_ON(!dsi.vdds_dsi_enabled);
1557 regulator_disable(dsi.vdds_dsi_reg);
1558 dsi.vdds_dsi_enabled = false;
1559 }
1560
1561 dsi_disable_scp_clk();
1562 enable_clocks(0);
1563 dsi_enable_pll_clock(0);
1564
1565 DSSDBG("PLL uninit done\n");
1566 }
1567
1568 void dsi_dump_clocks(struct seq_file *s)
1569 {
1570 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1571 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1572
1573 dispc_clk_src = dss_get_dispc_clk_source();
1574 dsi_clk_src = dss_get_dsi_clk_source();
1575
1576 enable_clocks(1);
1577
1578 seq_printf(s, "- DSI PLL -\n");
1579
1580 seq_printf(s, "dsi pll source = %s\n",
1581 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1582
1583 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1584
1585 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1586 cinfo->clkin4ddr, cinfo->regm);
1587
1588 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1589 dss_get_generic_clk_source_name(dispc_clk_src),
1590 dss_feat_get_clk_source_name(dispc_clk_src),
1591 cinfo->dsi_pll_hsdiv_dispc_clk,
1592 cinfo->regm_dispc,
1593 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1594 "off" : "on");
1595
1596 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1597 dss_get_generic_clk_source_name(dsi_clk_src),
1598 dss_feat_get_clk_source_name(dsi_clk_src),
1599 cinfo->dsi_pll_hsdiv_dsi_clk,
1600 cinfo->regm_dsi,
1601 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1602 "off" : "on");
1603
1604 seq_printf(s, "- DSI -\n");
1605
1606 seq_printf(s, "dsi fclk source = %s (%s)\n",
1607 dss_get_generic_clk_source_name(dsi_clk_src),
1608 dss_feat_get_clk_source_name(dsi_clk_src));
1609
1610 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1611
1612 seq_printf(s, "DDR_CLK\t\t%lu\n",
1613 cinfo->clkin4ddr / 4);
1614
1615 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1616
1617 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1618
1619 seq_printf(s, "VP_CLK\t\t%lu\n"
1620 "VP_PCLK\t\t%lu\n",
1621 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1622 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
1623
1624 enable_clocks(0);
1625 }
1626
1627 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1628 void dsi_dump_irqs(struct seq_file *s)
1629 {
1630 unsigned long flags;
1631 struct dsi_irq_stats stats;
1632
1633 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1634
1635 stats = dsi.irq_stats;
1636 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1637 dsi.irq_stats.last_reset = jiffies;
1638
1639 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1640
1641 seq_printf(s, "period %u ms\n",
1642 jiffies_to_msecs(jiffies - stats.last_reset));
1643
1644 seq_printf(s, "irqs %d\n", stats.irq_count);
1645 #define PIS(x) \
1646 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1647
1648 seq_printf(s, "-- DSI interrupts --\n");
1649 PIS(VC0);
1650 PIS(VC1);
1651 PIS(VC2);
1652 PIS(VC3);
1653 PIS(WAKEUP);
1654 PIS(RESYNC);
1655 PIS(PLL_LOCK);
1656 PIS(PLL_UNLOCK);
1657 PIS(PLL_RECALL);
1658 PIS(COMPLEXIO_ERR);
1659 PIS(HS_TX_TIMEOUT);
1660 PIS(LP_RX_TIMEOUT);
1661 PIS(TE_TRIGGER);
1662 PIS(ACK_TRIGGER);
1663 PIS(SYNC_LOST);
1664 PIS(LDO_POWER_GOOD);
1665 PIS(TA_TIMEOUT);
1666 #undef PIS
1667
1668 #define PIS(x) \
1669 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1670 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1671 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1672 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1673 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1674
1675 seq_printf(s, "-- VC interrupts --\n");
1676 PIS(CS);
1677 PIS(ECC_CORR);
1678 PIS(PACKET_SENT);
1679 PIS(FIFO_TX_OVF);
1680 PIS(FIFO_RX_OVF);
1681 PIS(BTA);
1682 PIS(ECC_NO_CORR);
1683 PIS(FIFO_TX_UDF);
1684 PIS(PP_BUSY_CHANGE);
1685 #undef PIS
1686
1687 #define PIS(x) \
1688 seq_printf(s, "%-20s %10d\n", #x, \
1689 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1690
1691 seq_printf(s, "-- CIO interrupts --\n");
1692 PIS(ERRSYNCESC1);
1693 PIS(ERRSYNCESC2);
1694 PIS(ERRSYNCESC3);
1695 PIS(ERRESC1);
1696 PIS(ERRESC2);
1697 PIS(ERRESC3);
1698 PIS(ERRCONTROL1);
1699 PIS(ERRCONTROL2);
1700 PIS(ERRCONTROL3);
1701 PIS(STATEULPS1);
1702 PIS(STATEULPS2);
1703 PIS(STATEULPS3);
1704 PIS(ERRCONTENTIONLP0_1);
1705 PIS(ERRCONTENTIONLP1_1);
1706 PIS(ERRCONTENTIONLP0_2);
1707 PIS(ERRCONTENTIONLP1_2);
1708 PIS(ERRCONTENTIONLP0_3);
1709 PIS(ERRCONTENTIONLP1_3);
1710 PIS(ULPSACTIVENOT_ALL0);
1711 PIS(ULPSACTIVENOT_ALL1);
1712 #undef PIS
1713 }
1714 #endif
1715
1716 void dsi_dump_regs(struct seq_file *s)
1717 {
1718 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1719
1720 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1721
1722 DUMPREG(DSI_REVISION);
1723 DUMPREG(DSI_SYSCONFIG);
1724 DUMPREG(DSI_SYSSTATUS);
1725 DUMPREG(DSI_IRQSTATUS);
1726 DUMPREG(DSI_IRQENABLE);
1727 DUMPREG(DSI_CTRL);
1728 DUMPREG(DSI_COMPLEXIO_CFG1);
1729 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1730 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1731 DUMPREG(DSI_CLK_CTRL);
1732 DUMPREG(DSI_TIMING1);
1733 DUMPREG(DSI_TIMING2);
1734 DUMPREG(DSI_VM_TIMING1);
1735 DUMPREG(DSI_VM_TIMING2);
1736 DUMPREG(DSI_VM_TIMING3);
1737 DUMPREG(DSI_CLK_TIMING);
1738 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1739 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1740 DUMPREG(DSI_COMPLEXIO_CFG2);
1741 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1742 DUMPREG(DSI_VM_TIMING4);
1743 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1744 DUMPREG(DSI_VM_TIMING5);
1745 DUMPREG(DSI_VM_TIMING6);
1746 DUMPREG(DSI_VM_TIMING7);
1747 DUMPREG(DSI_STOPCLK_TIMING);
1748
1749 DUMPREG(DSI_VC_CTRL(0));
1750 DUMPREG(DSI_VC_TE(0));
1751 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1752 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1753 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1754 DUMPREG(DSI_VC_IRQSTATUS(0));
1755 DUMPREG(DSI_VC_IRQENABLE(0));
1756
1757 DUMPREG(DSI_VC_CTRL(1));
1758 DUMPREG(DSI_VC_TE(1));
1759 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1760 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1761 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1762 DUMPREG(DSI_VC_IRQSTATUS(1));
1763 DUMPREG(DSI_VC_IRQENABLE(1));
1764
1765 DUMPREG(DSI_VC_CTRL(2));
1766 DUMPREG(DSI_VC_TE(2));
1767 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1768 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1769 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1770 DUMPREG(DSI_VC_IRQSTATUS(2));
1771 DUMPREG(DSI_VC_IRQENABLE(2));
1772
1773 DUMPREG(DSI_VC_CTRL(3));
1774 DUMPREG(DSI_VC_TE(3));
1775 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1776 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1777 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1778 DUMPREG(DSI_VC_IRQSTATUS(3));
1779 DUMPREG(DSI_VC_IRQENABLE(3));
1780
1781 DUMPREG(DSI_DSIPHY_CFG0);
1782 DUMPREG(DSI_DSIPHY_CFG1);
1783 DUMPREG(DSI_DSIPHY_CFG2);
1784 DUMPREG(DSI_DSIPHY_CFG5);
1785
1786 DUMPREG(DSI_PLL_CONTROL);
1787 DUMPREG(DSI_PLL_STATUS);
1788 DUMPREG(DSI_PLL_GO);
1789 DUMPREG(DSI_PLL_CONFIGURATION1);
1790 DUMPREG(DSI_PLL_CONFIGURATION2);
1791
1792 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1793 #undef DUMPREG
1794 }
1795
1796 enum dsi_cio_power_state {
1797 DSI_COMPLEXIO_POWER_OFF = 0x0,
1798 DSI_COMPLEXIO_POWER_ON = 0x1,
1799 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1800 };
1801
1802 static int dsi_cio_power(enum dsi_cio_power_state state)
1803 {
1804 int t = 0;
1805
1806 /* PWR_CMD */
1807 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1808
1809 /* PWR_STATUS */
1810 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1811 if (++t > 1000) {
1812 DSSERR("failed to set complexio power state to "
1813 "%d\n", state);
1814 return -ENODEV;
1815 }
1816 udelay(1);
1817 }
1818
1819 return 0;
1820 }
1821
1822 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
1823 {
1824 u32 r;
1825
1826 int clk_lane = dssdev->phy.dsi.clk_lane;
1827 int data1_lane = dssdev->phy.dsi.data1_lane;
1828 int data2_lane = dssdev->phy.dsi.data2_lane;
1829 int clk_pol = dssdev->phy.dsi.clk_pol;
1830 int data1_pol = dssdev->phy.dsi.data1_pol;
1831 int data2_pol = dssdev->phy.dsi.data2_pol;
1832
1833 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1834 r = FLD_MOD(r, clk_lane, 2, 0);
1835 r = FLD_MOD(r, clk_pol, 3, 3);
1836 r = FLD_MOD(r, data1_lane, 6, 4);
1837 r = FLD_MOD(r, data1_pol, 7, 7);
1838 r = FLD_MOD(r, data2_lane, 10, 8);
1839 r = FLD_MOD(r, data2_pol, 11, 11);
1840 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1841
1842 /* The configuration of the DSI complex I/O (number of data lanes,
1843 position, differential order) should not be changed while
1844 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1845 the hardware to take into account a new configuration of the complex
1846 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1847 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1848 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1849 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1850 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1851 DSI complex I/O configuration is unknown. */
1852
1853 /*
1854 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1855 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1856 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1857 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1858 */
1859 }
1860
1861 static inline unsigned ns2ddr(unsigned ns)
1862 {
1863 /* convert time in ns to ddr ticks, rounding up */
1864 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1865 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1866 }
1867
1868 static inline unsigned ddr2ns(unsigned ddr)
1869 {
1870 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1871 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1872 }
1873
1874 static void dsi_cio_timings(void)
1875 {
1876 u32 r;
1877 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1878 u32 tlpx_half, tclk_trail, tclk_zero;
1879 u32 tclk_prepare;
1880
1881 /* calculate timings */
1882
1883 /* 1 * DDR_CLK = 2 * UI */
1884
1885 /* min 40ns + 4*UI max 85ns + 6*UI */
1886 ths_prepare = ns2ddr(70) + 2;
1887
1888 /* min 145ns + 10*UI */
1889 ths_prepare_ths_zero = ns2ddr(175) + 2;
1890
1891 /* min max(8*UI, 60ns+4*UI) */
1892 ths_trail = ns2ddr(60) + 5;
1893
1894 /* min 100ns */
1895 ths_exit = ns2ddr(145);
1896
1897 /* tlpx min 50n */
1898 tlpx_half = ns2ddr(25);
1899
1900 /* min 60ns */
1901 tclk_trail = ns2ddr(60) + 2;
1902
1903 /* min 38ns, max 95ns */
1904 tclk_prepare = ns2ddr(65);
1905
1906 /* min tclk-prepare + tclk-zero = 300ns */
1907 tclk_zero = ns2ddr(260);
1908
1909 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1910 ths_prepare, ddr2ns(ths_prepare),
1911 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1912 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1913 ths_trail, ddr2ns(ths_trail),
1914 ths_exit, ddr2ns(ths_exit));
1915
1916 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1917 "tclk_zero %u (%uns)\n",
1918 tlpx_half, ddr2ns(tlpx_half),
1919 tclk_trail, ddr2ns(tclk_trail),
1920 tclk_zero, ddr2ns(tclk_zero));
1921 DSSDBG("tclk_prepare %u (%uns)\n",
1922 tclk_prepare, ddr2ns(tclk_prepare));
1923
1924 /* program timings */
1925
1926 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1927 r = FLD_MOD(r, ths_prepare, 31, 24);
1928 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1929 r = FLD_MOD(r, ths_trail, 15, 8);
1930 r = FLD_MOD(r, ths_exit, 7, 0);
1931 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1932
1933 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1934 r = FLD_MOD(r, tlpx_half, 22, 16);
1935 r = FLD_MOD(r, tclk_trail, 15, 8);
1936 r = FLD_MOD(r, tclk_zero, 7, 0);
1937 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1938
1939 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1940 r = FLD_MOD(r, tclk_prepare, 7, 0);
1941 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1942 }
1943
1944 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
1945 enum dsi_lane lanes)
1946 {
1947 int clk_lane = dssdev->phy.dsi.clk_lane;
1948 int data1_lane = dssdev->phy.dsi.data1_lane;
1949 int data2_lane = dssdev->phy.dsi.data2_lane;
1950 int clk_pol = dssdev->phy.dsi.clk_pol;
1951 int data1_pol = dssdev->phy.dsi.data1_pol;
1952 int data2_pol = dssdev->phy.dsi.data2_pol;
1953
1954 u32 l = 0;
1955
1956 if (lanes & DSI_CLK_P)
1957 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
1958 if (lanes & DSI_CLK_N)
1959 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
1960
1961 if (lanes & DSI_DATA1_P)
1962 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
1963 if (lanes & DSI_DATA1_N)
1964 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
1965
1966 if (lanes & DSI_DATA2_P)
1967 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
1968 if (lanes & DSI_DATA2_N)
1969 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
1970
1971 /*
1972 * Bits in REGLPTXSCPDAT4TO0DXDY:
1973 * 17: DY0 18: DX0
1974 * 19: DY1 20: DX1
1975 * 21: DY2 22: DX2
1976 */
1977
1978 /* Set the lane override configuration */
1979 REG_FLD_MOD(DSI_DSIPHY_CFG10, l, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */
1980
1981 /* Enable lane override */
1982 REG_FLD_MOD(DSI_DSIPHY_CFG10, 1, 27, 27); /* ENLPTXSCPDAT */
1983 }
1984
1985 static void dsi_cio_disable_lane_override(void)
1986 {
1987 /* Disable lane override */
1988 REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1989 /* Reset the lane override configuration */
1990 REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */
1991 }
1992
1993 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
1994 {
1995 int t;
1996 int bits[3];
1997 bool in_use[3];
1998
1999 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2000 bits[0] = 28;
2001 bits[1] = 27;
2002 bits[2] = 26;
2003 } else {
2004 bits[0] = 24;
2005 bits[1] = 25;
2006 bits[2] = 26;
2007 }
2008
2009 in_use[0] = false;
2010 in_use[1] = false;
2011 in_use[2] = false;
2012
2013 if (dssdev->phy.dsi.clk_lane != 0)
2014 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2015 if (dssdev->phy.dsi.data1_lane != 0)
2016 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2017 if (dssdev->phy.dsi.data2_lane != 0)
2018 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2019
2020 t = 100000;
2021 while (true) {
2022 u32 l;
2023 int i;
2024 int ok;
2025
2026 l = dsi_read_reg(DSI_DSIPHY_CFG5);
2027
2028 ok = 0;
2029 for (i = 0; i < 3; ++i) {
2030 if (!in_use[i] || (l & (1 << bits[i])))
2031 ok++;
2032 }
2033
2034 if (ok == 3)
2035 break;
2036
2037 if (--t == 0) {
2038 for (i = 0; i < 3; ++i) {
2039 if (!in_use[i] || (l & (1 << bits[i])))
2040 continue;
2041
2042 DSSERR("CIO TXCLKESC%d domain not coming " \
2043 "out of reset\n", i);
2044 }
2045 return -EIO;
2046 }
2047 }
2048
2049 return 0;
2050 }
2051
2052 static int dsi_cio_init(struct omap_dss_device *dssdev)
2053 {
2054 int r;
2055 u32 l;
2056
2057 DSSDBGF();
2058
2059 if (dsi.dsi_mux_pads)
2060 dsi.dsi_mux_pads(true);
2061
2062 dsi_enable_scp_clk();
2063
2064 /* A dummy read using the SCP interface to any DSIPHY register is
2065 * required after DSIPHY reset to complete the reset of the DSI complex
2066 * I/O. */
2067 dsi_read_reg(DSI_DSIPHY_CFG5);
2068
2069 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
2070 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2071 r = -EIO;
2072 goto err_scp_clk_dom;
2073 }
2074
2075 dsi_set_lane_config(dssdev);
2076
2077 /* set TX STOP MODE timer to maximum for this operation */
2078 l = dsi_read_reg(DSI_TIMING1);
2079 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2080 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2081 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2082 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2083 dsi_write_reg(DSI_TIMING1, l);
2084
2085 if (dsi.ulps_enabled) {
2086 DSSDBG("manual ulps exit\n");
2087
2088 /* ULPS is exited by Mark-1 state for 1ms, followed by
2089 * stop state. DSS HW cannot do this via the normal
2090 * ULPS exit sequence, as after reset the DSS HW thinks
2091 * that we are not in ULPS mode, and refuses to send the
2092 * sequence. So we need to send the ULPS exit sequence
2093 * manually.
2094 */
2095
2096 dsi_cio_enable_lane_override(dssdev,
2097 DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P);
2098 }
2099
2100 r = dsi_cio_power(DSI_COMPLEXIO_POWER_ON);
2101 if (r)
2102 goto err_cio_pwr;
2103
2104 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2105 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2106 r = -ENODEV;
2107 goto err_cio_pwr_dom;
2108 }
2109
2110 dsi_if_enable(true);
2111 dsi_if_enable(false);
2112 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2113
2114 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2115 if (r)
2116 goto err_tx_clk_esc_rst;
2117
2118 if (dsi.ulps_enabled) {
2119 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2120 ktime_t wait = ns_to_ktime(1000 * 1000);
2121 set_current_state(TASK_UNINTERRUPTIBLE);
2122 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2123
2124 /* Disable the override. The lanes should be set to Mark-11
2125 * state by the HW */
2126 dsi_cio_disable_lane_override();
2127 }
2128
2129 /* FORCE_TX_STOP_MODE_IO */
2130 REG_FLD_MOD(DSI_TIMING1, 0, 15, 15);
2131
2132 dsi_cio_timings();
2133
2134 dsi.ulps_enabled = false;
2135
2136 DSSDBG("CIO init done\n");
2137
2138 return 0;
2139
2140 err_tx_clk_esc_rst:
2141 REG_FLD_MOD(DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2142 err_cio_pwr_dom:
2143 dsi_cio_power(DSI_COMPLEXIO_POWER_OFF);
2144 err_cio_pwr:
2145 if (dsi.ulps_enabled)
2146 dsi_cio_disable_lane_override();
2147 err_scp_clk_dom:
2148 dsi_disable_scp_clk();
2149 if (dsi.dsi_mux_pads)
2150 dsi.dsi_mux_pads(false);
2151 return r;
2152 }
2153
2154 static void dsi_cio_uninit(void)
2155 {
2156 dsi_cio_power(DSI_COMPLEXIO_POWER_OFF);
2157 dsi_disable_scp_clk();
2158 if (dsi.dsi_mux_pads)
2159 dsi.dsi_mux_pads(false);
2160 }
2161
2162 static int _dsi_wait_reset(void)
2163 {
2164 int t = 0;
2165
2166 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
2167 if (++t > 5) {
2168 DSSERR("soft reset failed\n");
2169 return -ENODEV;
2170 }
2171 udelay(1);
2172 }
2173
2174 return 0;
2175 }
2176
2177 static int _dsi_reset(void)
2178 {
2179 /* Soft reset */
2180 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
2181 return _dsi_wait_reset();
2182 }
2183
2184 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
2185 enum fifo_size size3, enum fifo_size size4)
2186 {
2187 u32 r = 0;
2188 int add = 0;
2189 int i;
2190
2191 dsi.vc[0].fifo_size = size1;
2192 dsi.vc[1].fifo_size = size2;
2193 dsi.vc[2].fifo_size = size3;
2194 dsi.vc[3].fifo_size = size4;
2195
2196 for (i = 0; i < 4; i++) {
2197 u8 v;
2198 int size = dsi.vc[i].fifo_size;
2199
2200 if (add + size > 4) {
2201 DSSERR("Illegal FIFO configuration\n");
2202 BUG();
2203 }
2204
2205 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2206 r |= v << (8 * i);
2207 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2208 add += size;
2209 }
2210
2211 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
2212 }
2213
2214 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
2215 enum fifo_size size3, enum fifo_size size4)
2216 {
2217 u32 r = 0;
2218 int add = 0;
2219 int i;
2220
2221 dsi.vc[0].fifo_size = size1;
2222 dsi.vc[1].fifo_size = size2;
2223 dsi.vc[2].fifo_size = size3;
2224 dsi.vc[3].fifo_size = size4;
2225
2226 for (i = 0; i < 4; i++) {
2227 u8 v;
2228 int size = dsi.vc[i].fifo_size;
2229
2230 if (add + size > 4) {
2231 DSSERR("Illegal FIFO configuration\n");
2232 BUG();
2233 }
2234
2235 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2236 r |= v << (8 * i);
2237 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2238 add += size;
2239 }
2240
2241 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
2242 }
2243
2244 static int dsi_force_tx_stop_mode_io(void)
2245 {
2246 u32 r;
2247
2248 r = dsi_read_reg(DSI_TIMING1);
2249 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2250 dsi_write_reg(DSI_TIMING1, r);
2251
2252 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
2253 DSSERR("TX_STOP bit not going down\n");
2254 return -EIO;
2255 }
2256
2257 return 0;
2258 }
2259
2260 static bool dsi_vc_is_enabled(int channel)
2261 {
2262 return REG_GET(DSI_VC_CTRL(channel), 0, 0);
2263 }
2264
2265 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2266 {
2267 const int channel = dsi.update_channel;
2268 u8 bit = dsi.te_enabled ? 30 : 31;
2269
2270 if (REG_GET(DSI_VC_TE(channel), bit, bit) == 0)
2271 complete((struct completion *)data);
2272 }
2273
2274 static int dsi_sync_vc_vp(int channel)
2275 {
2276 int r = 0;
2277 u8 bit;
2278
2279 DECLARE_COMPLETION_ONSTACK(completion);
2280
2281 bit = dsi.te_enabled ? 30 : 31;
2282
2283 r = dsi_register_isr_vc(channel, dsi_packet_sent_handler_vp,
2284 &completion, DSI_VC_IRQ_PACKET_SENT);
2285 if (r)
2286 goto err0;
2287
2288 /* Wait for completion only if TE_EN/TE_START is still set */
2289 if (REG_GET(DSI_VC_TE(channel), bit, bit)) {
2290 if (wait_for_completion_timeout(&completion,
2291 msecs_to_jiffies(10)) == 0) {
2292 DSSERR("Failed to complete previous frame transfer\n");
2293 r = -EIO;
2294 goto err1;
2295 }
2296 }
2297
2298 dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_vp,
2299 &completion, DSI_VC_IRQ_PACKET_SENT);
2300
2301 return 0;
2302 err1:
2303 dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_vp, &completion,
2304 DSI_VC_IRQ_PACKET_SENT);
2305 err0:
2306 return r;
2307 }
2308
2309 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2310 {
2311 const int channel = dsi.update_channel;
2312
2313 if (REG_GET(DSI_VC_CTRL(channel), 5, 5) == 0)
2314 complete((struct completion *)data);
2315 }
2316
2317 static int dsi_sync_vc_l4(int channel)
2318 {
2319 int r = 0;
2320
2321 DECLARE_COMPLETION_ONSTACK(completion);
2322
2323 r = dsi_register_isr_vc(channel, dsi_packet_sent_handler_l4,
2324 &completion, DSI_VC_IRQ_PACKET_SENT);
2325 if (r)
2326 goto err0;
2327
2328 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2329 if (REG_GET(DSI_VC_CTRL(channel), 5, 5)) {
2330 if (wait_for_completion_timeout(&completion,
2331 msecs_to_jiffies(10)) == 0) {
2332 DSSERR("Failed to complete previous l4 transfer\n");
2333 r = -EIO;
2334 goto err1;
2335 }
2336 }
2337
2338 dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_l4,
2339 &completion, DSI_VC_IRQ_PACKET_SENT);
2340
2341 return 0;
2342 err1:
2343 dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_l4,
2344 &completion, DSI_VC_IRQ_PACKET_SENT);
2345 err0:
2346 return r;
2347 }
2348
2349 static int dsi_sync_vc(int channel)
2350 {
2351 WARN_ON(!dsi_bus_is_locked());
2352
2353 WARN_ON(in_interrupt());
2354
2355 if (!dsi_vc_is_enabled(channel))
2356 return 0;
2357
2358 switch (dsi.vc[channel].mode) {
2359 case DSI_VC_MODE_VP:
2360 return dsi_sync_vc_vp(channel);
2361 case DSI_VC_MODE_L4:
2362 return dsi_sync_vc_l4(channel);
2363 default:
2364 BUG();
2365 }
2366 }
2367
2368 static int dsi_vc_enable(int channel, bool enable)
2369 {
2370 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2371 channel, enable);
2372
2373 enable = enable ? 1 : 0;
2374
2375 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
2376
2377 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
2378 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2379 return -EIO;
2380 }
2381
2382 return 0;
2383 }
2384
2385 static void dsi_vc_initial_config(int channel)
2386 {
2387 u32 r;
2388
2389 DSSDBGF("%d", channel);
2390
2391 r = dsi_read_reg(DSI_VC_CTRL(channel));
2392
2393 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2394 DSSERR("VC(%d) busy when trying to configure it!\n",
2395 channel);
2396
2397 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2398 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2399 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2400 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2401 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2402 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2403 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2404 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2405 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2406
2407 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2408 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2409
2410 dsi_write_reg(DSI_VC_CTRL(channel), r);
2411 }
2412
2413 static int dsi_vc_config_l4(int channel)
2414 {
2415 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
2416 return 0;
2417
2418 DSSDBGF("%d", channel);
2419
2420 dsi_sync_vc(channel);
2421
2422 dsi_vc_enable(channel, 0);
2423
2424 /* VC_BUSY */
2425 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
2426 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
2427 return -EIO;
2428 }
2429
2430 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
2431
2432 /* DCS_CMD_ENABLE */
2433 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
2434 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 30, 30);
2435
2436 dsi_vc_enable(channel, 1);
2437
2438 dsi.vc[channel].mode = DSI_VC_MODE_L4;
2439
2440 return 0;
2441 }
2442
2443 static int dsi_vc_config_vp(int channel)
2444 {
2445 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
2446 return 0;
2447
2448 DSSDBGF("%d", channel);
2449
2450 dsi_sync_vc(channel);
2451
2452 dsi_vc_enable(channel, 0);
2453
2454 /* VC_BUSY */
2455 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
2456 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2457 return -EIO;
2458 }
2459
2460 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
2461
2462 /* DCS_CMD_ENABLE */
2463 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
2464 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 30, 30);
2465
2466 dsi_vc_enable(channel, 1);
2467
2468 dsi.vc[channel].mode = DSI_VC_MODE_VP;
2469
2470 return 0;
2471 }
2472
2473
2474 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
2475 {
2476 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2477
2478 WARN_ON(!dsi_bus_is_locked());
2479
2480 dsi_vc_enable(channel, 0);
2481 dsi_if_enable(0);
2482
2483 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
2484
2485 dsi_vc_enable(channel, 1);
2486 dsi_if_enable(1);
2487
2488 dsi_force_tx_stop_mode_io();
2489 }
2490 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2491
2492 static void dsi_vc_flush_long_data(int channel)
2493 {
2494 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2495 u32 val;
2496 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2497 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2498 (val >> 0) & 0xff,
2499 (val >> 8) & 0xff,
2500 (val >> 16) & 0xff,
2501 (val >> 24) & 0xff);
2502 }
2503 }
2504
2505 static void dsi_show_rx_ack_with_err(u16 err)
2506 {
2507 DSSERR("\tACK with ERROR (%#x):\n", err);
2508 if (err & (1 << 0))
2509 DSSERR("\t\tSoT Error\n");
2510 if (err & (1 << 1))
2511 DSSERR("\t\tSoT Sync Error\n");
2512 if (err & (1 << 2))
2513 DSSERR("\t\tEoT Sync Error\n");
2514 if (err & (1 << 3))
2515 DSSERR("\t\tEscape Mode Entry Command Error\n");
2516 if (err & (1 << 4))
2517 DSSERR("\t\tLP Transmit Sync Error\n");
2518 if (err & (1 << 5))
2519 DSSERR("\t\tHS Receive Timeout Error\n");
2520 if (err & (1 << 6))
2521 DSSERR("\t\tFalse Control Error\n");
2522 if (err & (1 << 7))
2523 DSSERR("\t\t(reserved7)\n");
2524 if (err & (1 << 8))
2525 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2526 if (err & (1 << 9))
2527 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2528 if (err & (1 << 10))
2529 DSSERR("\t\tChecksum Error\n");
2530 if (err & (1 << 11))
2531 DSSERR("\t\tData type not recognized\n");
2532 if (err & (1 << 12))
2533 DSSERR("\t\tInvalid VC ID\n");
2534 if (err & (1 << 13))
2535 DSSERR("\t\tInvalid Transmission Length\n");
2536 if (err & (1 << 14))
2537 DSSERR("\t\t(reserved14)\n");
2538 if (err & (1 << 15))
2539 DSSERR("\t\tDSI Protocol Violation\n");
2540 }
2541
2542 static u16 dsi_vc_flush_receive_data(int channel)
2543 {
2544 /* RX_FIFO_NOT_EMPTY */
2545 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2546 u32 val;
2547 u8 dt;
2548 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2549 DSSERR("\trawval %#08x\n", val);
2550 dt = FLD_GET(val, 5, 0);
2551 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2552 u16 err = FLD_GET(val, 23, 8);
2553 dsi_show_rx_ack_with_err(err);
2554 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2555 DSSERR("\tDCS short response, 1 byte: %#x\n",
2556 FLD_GET(val, 23, 8));
2557 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2558 DSSERR("\tDCS short response, 2 byte: %#x\n",
2559 FLD_GET(val, 23, 8));
2560 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2561 DSSERR("\tDCS long response, len %d\n",
2562 FLD_GET(val, 23, 8));
2563 dsi_vc_flush_long_data(channel);
2564 } else {
2565 DSSERR("\tunknown datatype 0x%02x\n", dt);
2566 }
2567 }
2568 return 0;
2569 }
2570
2571 static int dsi_vc_send_bta(int channel)
2572 {
2573 if (dsi.debug_write || dsi.debug_read)
2574 DSSDBG("dsi_vc_send_bta %d\n", channel);
2575
2576 WARN_ON(!dsi_bus_is_locked());
2577
2578 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2579 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2580 dsi_vc_flush_receive_data(channel);
2581 }
2582
2583 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2584
2585 return 0;
2586 }
2587
2588 int dsi_vc_send_bta_sync(int channel)
2589 {
2590 DECLARE_COMPLETION_ONSTACK(completion);
2591 int r = 0;
2592 u32 err;
2593
2594 r = dsi_register_isr_vc(channel, dsi_completion_handler,
2595 &completion, DSI_VC_IRQ_BTA);
2596 if (r)
2597 goto err0;
2598
2599 r = dsi_register_isr(dsi_completion_handler, &completion,
2600 DSI_IRQ_ERROR_MASK);
2601 if (r)
2602 goto err1;
2603
2604 r = dsi_vc_send_bta(channel);
2605 if (r)
2606 goto err2;
2607
2608 if (wait_for_completion_timeout(&completion,
2609 msecs_to_jiffies(500)) == 0) {
2610 DSSERR("Failed to receive BTA\n");
2611 r = -EIO;
2612 goto err2;
2613 }
2614
2615 err = dsi_get_errors();
2616 if (err) {
2617 DSSERR("Error while sending BTA: %x\n", err);
2618 r = -EIO;
2619 goto err2;
2620 }
2621 err2:
2622 dsi_unregister_isr(dsi_completion_handler, &completion,
2623 DSI_IRQ_ERROR_MASK);
2624 err1:
2625 dsi_unregister_isr_vc(channel, dsi_completion_handler,
2626 &completion, DSI_VC_IRQ_BTA);
2627 err0:
2628 return r;
2629 }
2630 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2631
2632 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
2633 u16 len, u8 ecc)
2634 {
2635 u32 val;
2636 u8 data_id;
2637
2638 WARN_ON(!dsi_bus_is_locked());
2639
2640 data_id = data_type | dsi.vc[channel].vc_id << 6;
2641
2642 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2643 FLD_VAL(ecc, 31, 24);
2644
2645 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
2646 }
2647
2648 static inline void dsi_vc_write_long_payload(int channel,
2649 u8 b1, u8 b2, u8 b3, u8 b4)
2650 {
2651 u32 val;
2652
2653 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2654
2655 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2656 b1, b2, b3, b4, val); */
2657
2658 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2659 }
2660
2661 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
2662 u8 ecc)
2663 {
2664 /*u32 val; */
2665 int i;
2666 u8 *p;
2667 int r = 0;
2668 u8 b1, b2, b3, b4;
2669
2670 if (dsi.debug_write)
2671 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2672
2673 /* len + header */
2674 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
2675 DSSERR("unable to send long packet: packet too long.\n");
2676 return -EINVAL;
2677 }
2678
2679 dsi_vc_config_l4(channel);
2680
2681 dsi_vc_write_long_header(channel, data_type, len, ecc);
2682
2683 p = data;
2684 for (i = 0; i < len >> 2; i++) {
2685 if (dsi.debug_write)
2686 DSSDBG("\tsending full packet %d\n", i);
2687
2688 b1 = *p++;
2689 b2 = *p++;
2690 b3 = *p++;
2691 b4 = *p++;
2692
2693 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2694 }
2695
2696 i = len % 4;
2697 if (i) {
2698 b1 = 0; b2 = 0; b3 = 0;
2699
2700 if (dsi.debug_write)
2701 DSSDBG("\tsending remainder bytes %d\n", i);
2702
2703 switch (i) {
2704 case 3:
2705 b1 = *p++;
2706 b2 = *p++;
2707 b3 = *p++;
2708 break;
2709 case 2:
2710 b1 = *p++;
2711 b2 = *p++;
2712 break;
2713 case 1:
2714 b1 = *p++;
2715 break;
2716 }
2717
2718 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2719 }
2720
2721 return r;
2722 }
2723
2724 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2725 {
2726 u32 r;
2727 u8 data_id;
2728
2729 WARN_ON(!dsi_bus_is_locked());
2730
2731 if (dsi.debug_write)
2732 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2733 channel,
2734 data_type, data & 0xff, (data >> 8) & 0xff);
2735
2736 dsi_vc_config_l4(channel);
2737
2738 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2739 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2740 return -EINVAL;
2741 }
2742
2743 data_id = data_type | dsi.vc[channel].vc_id << 6;
2744
2745 r = (data_id << 0) | (data << 8) | (ecc << 24);
2746
2747 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2748
2749 return 0;
2750 }
2751
2752 int dsi_vc_send_null(int channel)
2753 {
2754 u8 nullpkg[] = {0, 0, 0, 0};
2755 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2756 }
2757 EXPORT_SYMBOL(dsi_vc_send_null);
2758
2759 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2760 {
2761 int r;
2762
2763 BUG_ON(len == 0);
2764
2765 if (len == 1) {
2766 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2767 data[0], 0);
2768 } else if (len == 2) {
2769 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2770 data[0] | (data[1] << 8), 0);
2771 } else {
2772 /* 0x39 = DCS Long Write */
2773 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2774 data, len, 0);
2775 }
2776
2777 return r;
2778 }
2779 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2780
2781 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2782 {
2783 int r;
2784
2785 r = dsi_vc_dcs_write_nosync(channel, data, len);
2786 if (r)
2787 goto err;
2788
2789 r = dsi_vc_send_bta_sync(channel);
2790 if (r)
2791 goto err;
2792
2793 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2794 DSSERR("rx fifo not empty after write, dumping data:\n");
2795 dsi_vc_flush_receive_data(channel);
2796 r = -EIO;
2797 goto err;
2798 }
2799
2800 return 0;
2801 err:
2802 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2803 channel, data[0], len);
2804 return r;
2805 }
2806 EXPORT_SYMBOL(dsi_vc_dcs_write);
2807
2808 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2809 {
2810 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2811 }
2812 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2813
2814 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2815 {
2816 u8 buf[2];
2817 buf[0] = dcs_cmd;
2818 buf[1] = param;
2819 return dsi_vc_dcs_write(channel, buf, 2);
2820 }
2821 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2822
2823 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2824 {
2825 u32 val;
2826 u8 dt;
2827 int r;
2828
2829 if (dsi.debug_read)
2830 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2831
2832 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2833 if (r)
2834 goto err;
2835
2836 r = dsi_vc_send_bta_sync(channel);
2837 if (r)
2838 goto err;
2839
2840 /* RX_FIFO_NOT_EMPTY */
2841 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2842 DSSERR("RX fifo empty when trying to read.\n");
2843 r = -EIO;
2844 goto err;
2845 }
2846
2847 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2848 if (dsi.debug_read)
2849 DSSDBG("\theader: %08x\n", val);
2850 dt = FLD_GET(val, 5, 0);
2851 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2852 u16 err = FLD_GET(val, 23, 8);
2853 dsi_show_rx_ack_with_err(err);
2854 r = -EIO;
2855 goto err;
2856
2857 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2858 u8 data = FLD_GET(val, 15, 8);
2859 if (dsi.debug_read)
2860 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2861
2862 if (buflen < 1) {
2863 r = -EIO;
2864 goto err;
2865 }
2866
2867 buf[0] = data;
2868
2869 return 1;
2870 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2871 u16 data = FLD_GET(val, 23, 8);
2872 if (dsi.debug_read)
2873 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2874
2875 if (buflen < 2) {
2876 r = -EIO;
2877 goto err;
2878 }
2879
2880 buf[0] = data & 0xff;
2881 buf[1] = (data >> 8) & 0xff;
2882
2883 return 2;
2884 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2885 int w;
2886 int len = FLD_GET(val, 23, 8);
2887 if (dsi.debug_read)
2888 DSSDBG("\tDCS long response, len %d\n", len);
2889
2890 if (len > buflen) {
2891 r = -EIO;
2892 goto err;
2893 }
2894
2895 /* two byte checksum ends the packet, not included in len */
2896 for (w = 0; w < len + 2;) {
2897 int b;
2898 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2899 if (dsi.debug_read)
2900 DSSDBG("\t\t%02x %02x %02x %02x\n",
2901 (val >> 0) & 0xff,
2902 (val >> 8) & 0xff,
2903 (val >> 16) & 0xff,
2904 (val >> 24) & 0xff);
2905
2906 for (b = 0; b < 4; ++b) {
2907 if (w < len)
2908 buf[w] = (val >> (b * 8)) & 0xff;
2909 /* we discard the 2 byte checksum */
2910 ++w;
2911 }
2912 }
2913
2914 return len;
2915 } else {
2916 DSSERR("\tunknown datatype 0x%02x\n", dt);
2917 r = -EIO;
2918 goto err;
2919 }
2920
2921 BUG();
2922 err:
2923 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2924 channel, dcs_cmd);
2925 return r;
2926
2927 }
2928 EXPORT_SYMBOL(dsi_vc_dcs_read);
2929
2930 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2931 {
2932 int r;
2933
2934 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2935
2936 if (r < 0)
2937 return r;
2938
2939 if (r != 1)
2940 return -EIO;
2941
2942 return 0;
2943 }
2944 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2945
2946 int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
2947 {
2948 u8 buf[2];
2949 int r;
2950
2951 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
2952
2953 if (r < 0)
2954 return r;
2955
2956 if (r != 2)
2957 return -EIO;
2958
2959 *data1 = buf[0];
2960 *data2 = buf[1];
2961
2962 return 0;
2963 }
2964 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2965
2966 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2967 {
2968 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2969 len, 0);
2970 }
2971 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2972
2973 static int dsi_enter_ulps(void)
2974 {
2975 DECLARE_COMPLETION_ONSTACK(completion);
2976 int r;
2977
2978 DSSDBGF();
2979
2980 WARN_ON(!dsi_bus_is_locked());
2981
2982 WARN_ON(dsi.ulps_enabled);
2983
2984 if (dsi.ulps_enabled)
2985 return 0;
2986
2987 if (REG_GET(DSI_CLK_CTRL, 13, 13)) {
2988 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
2989 return -EIO;
2990 }
2991
2992 dsi_sync_vc(0);
2993 dsi_sync_vc(1);
2994 dsi_sync_vc(2);
2995 dsi_sync_vc(3);
2996
2997 dsi_force_tx_stop_mode_io();
2998
2999 dsi_vc_enable(0, false);
3000 dsi_vc_enable(1, false);
3001 dsi_vc_enable(2, false);
3002 dsi_vc_enable(3, false);
3003
3004 if (REG_GET(DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3005 DSSERR("HS busy when enabling ULPS\n");
3006 return -EIO;
3007 }
3008
3009 if (REG_GET(DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3010 DSSERR("LP busy when enabling ULPS\n");
3011 return -EIO;
3012 }
3013
3014 r = dsi_register_isr_cio(dsi_completion_handler, &completion,
3015 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3016 if (r)
3017 return r;
3018
3019 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3020 /* LANEx_ULPS_SIG2 */
3021 REG_FLD_MOD(DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2), 7, 5);
3022
3023 if (wait_for_completion_timeout(&completion,
3024 msecs_to_jiffies(1000)) == 0) {
3025 DSSERR("ULPS enable timeout\n");
3026 r = -EIO;
3027 goto err;
3028 }
3029
3030 dsi_unregister_isr_cio(dsi_completion_handler, &completion,
3031 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3032
3033 dsi_cio_power(DSI_COMPLEXIO_POWER_ULPS);
3034
3035 dsi_if_enable(false);
3036
3037 dsi.ulps_enabled = true;
3038
3039 return 0;
3040
3041 err:
3042 dsi_unregister_isr_cio(dsi_completion_handler, &completion,
3043 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3044 return r;
3045 }
3046
3047 static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
3048 {
3049 unsigned long fck;
3050 unsigned long total_ticks;
3051 u32 r;
3052
3053 BUG_ON(ticks > 0x1fff);
3054
3055 /* ticks in DSI_FCK */
3056 fck = dsi_fclk_rate();
3057
3058 r = dsi_read_reg(DSI_TIMING2);
3059 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3060 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3061 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3062 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3063 dsi_write_reg(DSI_TIMING2, r);
3064
3065 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3066
3067 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3068 total_ticks,
3069 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3070 (total_ticks * 1000) / (fck / 1000 / 1000));
3071 }
3072
3073 static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
3074 {
3075 unsigned long fck;
3076 unsigned long total_ticks;
3077 u32 r;
3078
3079 BUG_ON(ticks > 0x1fff);
3080
3081 /* ticks in DSI_FCK */
3082 fck = dsi_fclk_rate();
3083
3084 r = dsi_read_reg(DSI_TIMING1);
3085 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3086 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3087 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3088 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3089 dsi_write_reg(DSI_TIMING1, r);
3090
3091 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3092
3093 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3094 total_ticks,
3095 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3096 (total_ticks * 1000) / (fck / 1000 / 1000));
3097 }
3098
3099 static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
3100 {
3101 unsigned long fck;
3102 unsigned long total_ticks;
3103 u32 r;
3104
3105 BUG_ON(ticks > 0x1fff);
3106
3107 /* ticks in DSI_FCK */
3108 fck = dsi_fclk_rate();
3109
3110 r = dsi_read_reg(DSI_TIMING1);
3111 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3112 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3113 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3114 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3115 dsi_write_reg(DSI_TIMING1, r);
3116
3117 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3118
3119 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3120 total_ticks,
3121 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3122 (total_ticks * 1000) / (fck / 1000 / 1000));
3123 }
3124
3125 static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
3126 {
3127 unsigned long fck;
3128 unsigned long total_ticks;
3129 u32 r;
3130
3131 BUG_ON(ticks > 0x1fff);
3132
3133 /* ticks in TxByteClkHS */
3134 fck = dsi_get_txbyteclkhs();
3135
3136 r = dsi_read_reg(DSI_TIMING2);
3137 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3138 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3139 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3140 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3141 dsi_write_reg(DSI_TIMING2, r);
3142
3143 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3144
3145 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3146 total_ticks,
3147 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3148 (total_ticks * 1000) / (fck / 1000 / 1000));
3149 }
3150 static int dsi_proto_config(struct omap_dss_device *dssdev)
3151 {
3152 u32 r;
3153 int buswidth = 0;
3154
3155 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
3156 DSI_FIFO_SIZE_32,
3157 DSI_FIFO_SIZE_32,
3158 DSI_FIFO_SIZE_32);
3159
3160 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
3161 DSI_FIFO_SIZE_32,
3162 DSI_FIFO_SIZE_32,
3163 DSI_FIFO_SIZE_32);
3164
3165 /* XXX what values for the timeouts? */
3166 dsi_set_stop_state_counter(0x1000, false, false);
3167 dsi_set_ta_timeout(0x1fff, true, true);
3168 dsi_set_lp_rx_timeout(0x1fff, true, true);
3169 dsi_set_hs_tx_timeout(0x1fff, true, true);
3170
3171 switch (dssdev->ctrl.pixel_size) {
3172 case 16:
3173 buswidth = 0;
3174 break;
3175 case 18:
3176 buswidth = 1;
3177 break;
3178 case 24:
3179 buswidth = 2;
3180 break;
3181 default:
3182 BUG();
3183 }
3184
3185 r = dsi_read_reg(DSI_CTRL);
3186 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3187 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3188 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3189 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3190 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3191 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3192 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
3193 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3194 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3195 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3196 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3197 /* DCS_CMD_CODE, 1=start, 0=continue */
3198 r = FLD_MOD(r, 0, 25, 25);
3199 }
3200
3201 dsi_write_reg(DSI_CTRL, r);
3202
3203 dsi_vc_initial_config(0);
3204 dsi_vc_initial_config(1);
3205 dsi_vc_initial_config(2);
3206 dsi_vc_initial_config(3);
3207
3208 return 0;
3209 }
3210
3211 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3212 {
3213 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3214 unsigned tclk_pre, tclk_post;
3215 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3216 unsigned ths_trail, ths_exit;
3217 unsigned ddr_clk_pre, ddr_clk_post;
3218 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3219 unsigned ths_eot;
3220 u32 r;
3221
3222 r = dsi_read_reg(DSI_DSIPHY_CFG0);
3223 ths_prepare = FLD_GET(r, 31, 24);
3224 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3225 ths_zero = ths_prepare_ths_zero - ths_prepare;
3226 ths_trail = FLD_GET(r, 15, 8);
3227 ths_exit = FLD_GET(r, 7, 0);
3228
3229 r = dsi_read_reg(DSI_DSIPHY_CFG1);
3230 tlpx = FLD_GET(r, 22, 16) * 2;
3231 tclk_trail = FLD_GET(r, 15, 8);
3232 tclk_zero = FLD_GET(r, 7, 0);
3233
3234 r = dsi_read_reg(DSI_DSIPHY_CFG2);
3235 tclk_prepare = FLD_GET(r, 7, 0);
3236
3237 /* min 8*UI */
3238 tclk_pre = 20;
3239 /* min 60ns + 52*UI */
3240 tclk_post = ns2ddr(60) + 26;
3241
3242 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
3243 if (dssdev->phy.dsi.data1_lane != 0 &&
3244 dssdev->phy.dsi.data2_lane != 0)
3245 ths_eot = 2;
3246 else
3247 ths_eot = 4;
3248
3249 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3250 4);
3251 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3252
3253 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3254 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3255
3256 r = dsi_read_reg(DSI_CLK_TIMING);
3257 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3258 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3259 dsi_write_reg(DSI_CLK_TIMING, r);
3260
3261 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3262 ddr_clk_pre,
3263 ddr_clk_post);
3264
3265 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3266 DIV_ROUND_UP(ths_prepare, 4) +
3267 DIV_ROUND_UP(ths_zero + 3, 4);
3268
3269 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3270
3271 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3272 FLD_VAL(exit_hs_mode_lat, 15, 0);
3273 dsi_write_reg(DSI_VM_TIMING7, r);
3274
3275 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3276 enter_hs_mode_lat, exit_hs_mode_lat);
3277 }
3278
3279
3280 #define DSI_DECL_VARS \
3281 int __dsi_cb = 0; u32 __dsi_cv = 0;
3282
3283 #define DSI_FLUSH(ch) \
3284 if (__dsi_cb > 0) { \
3285 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
3286 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
3287 __dsi_cb = __dsi_cv = 0; \
3288 }
3289
3290 #define DSI_PUSH(ch, data) \
3291 do { \
3292 __dsi_cv |= (data) << (__dsi_cb * 8); \
3293 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
3294 if (++__dsi_cb > 3) \
3295 DSI_FLUSH(ch); \
3296 } while (0)
3297
3298 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
3299 int x, int y, int w, int h)
3300 {
3301 /* Note: supports only 24bit colors in 32bit container */
3302 int first = 1;
3303 int fifo_stalls = 0;
3304 int max_dsi_packet_size;
3305 int max_data_per_packet;
3306 int max_pixels_per_packet;
3307 int pixels_left;
3308 int bytespp = dssdev->ctrl.pixel_size / 8;
3309 int scr_width;
3310 u32 __iomem *data;
3311 int start_offset;
3312 int horiz_inc;
3313 int current_x;
3314 struct omap_overlay *ovl;
3315
3316 debug_irq = 0;
3317
3318 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
3319 x, y, w, h);
3320
3321 ovl = dssdev->manager->overlays[0];
3322
3323 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
3324 return -EINVAL;
3325
3326 if (dssdev->ctrl.pixel_size != 24)
3327 return -EINVAL;
3328
3329 scr_width = ovl->info.screen_width;
3330 data = ovl->info.vaddr;
3331
3332 start_offset = scr_width * y + x;
3333 horiz_inc = scr_width - w;
3334 current_x = x;
3335
3336 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
3337 * in fifo */
3338
3339 /* When using CPU, max long packet size is TX buffer size */
3340 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
3341
3342 /* we seem to get better perf if we divide the tx fifo to half,
3343 and while the other half is being sent, we fill the other half
3344 max_dsi_packet_size /= 2; */
3345
3346 max_data_per_packet = max_dsi_packet_size - 4 - 1;
3347
3348 max_pixels_per_packet = max_data_per_packet / bytespp;
3349
3350 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
3351
3352 pixels_left = w * h;
3353
3354 DSSDBG("total pixels %d\n", pixels_left);
3355
3356 data += start_offset;
3357
3358 while (pixels_left > 0) {
3359 /* 0x2c = write_memory_start */
3360 /* 0x3c = write_memory_continue */
3361 u8 dcs_cmd = first ? 0x2c : 0x3c;
3362 int pixels;
3363 DSI_DECL_VARS;
3364 first = 0;
3365
3366 #if 1
3367 /* using fifo not empty */
3368 /* TX_FIFO_NOT_EMPTY */
3369 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
3370 fifo_stalls++;
3371 if (fifo_stalls > 0xfffff) {
3372 DSSERR("fifo stalls overflow, pixels left %d\n",
3373 pixels_left);
3374 dsi_if_enable(0);
3375 return -EIO;
3376 }
3377 udelay(1);
3378 }
3379 #elif 1
3380 /* using fifo emptiness */
3381 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
3382 max_dsi_packet_size) {
3383 fifo_stalls++;
3384 if (fifo_stalls > 0xfffff) {
3385 DSSERR("fifo stalls overflow, pixels left %d\n",
3386 pixels_left);
3387 dsi_if_enable(0);
3388 return -EIO;
3389 }
3390 }
3391 #else
3392 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
3393 fifo_stalls++;
3394 if (fifo_stalls > 0xfffff) {
3395 DSSERR("fifo stalls overflow, pixels left %d\n",
3396 pixels_left);
3397 dsi_if_enable(0);
3398 return -EIO;
3399 }
3400 }
3401 #endif
3402 pixels = min(max_pixels_per_packet, pixels_left);
3403
3404 pixels_left -= pixels;
3405
3406 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
3407 1 + pixels * bytespp, 0);
3408
3409 DSI_PUSH(0, dcs_cmd);
3410
3411 while (pixels-- > 0) {
3412 u32 pix = __raw_readl(data++);
3413
3414 DSI_PUSH(0, (pix >> 16) & 0xff);
3415 DSI_PUSH(0, (pix >> 8) & 0xff);
3416 DSI_PUSH(0, (pix >> 0) & 0xff);
3417
3418 current_x++;
3419 if (current_x == x+w) {
3420 current_x = x;
3421 data += horiz_inc;
3422 }
3423 }
3424
3425 DSI_FLUSH(0);
3426 }
3427
3428 return 0;
3429 }
3430
3431 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3432 u16 x, u16 y, u16 w, u16 h)
3433 {
3434 unsigned bytespp;
3435 unsigned bytespl;
3436 unsigned bytespf;
3437 unsigned total_len;
3438 unsigned packet_payload;
3439 unsigned packet_len;
3440 u32 l;
3441 int r;
3442 const unsigned channel = dsi.update_channel;
3443 /* line buffer is 1024 x 24bits */
3444 /* XXX: for some reason using full buffer size causes considerable TX
3445 * slowdown with update sizes that fill the whole buffer */
3446 const unsigned line_buf_size = 1023 * 3;
3447
3448 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
3449 x, y, w, h);
3450
3451 dsi_vc_config_vp(channel);
3452
3453 bytespp = dssdev->ctrl.pixel_size / 8;
3454 bytespl = w * bytespp;
3455 bytespf = bytespl * h;
3456
3457 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3458 * number of lines in a packet. See errata about VP_CLK_RATIO */
3459
3460 if (bytespf < line_buf_size)
3461 packet_payload = bytespf;
3462 else
3463 packet_payload = (line_buf_size) / bytespl * bytespl;
3464
3465 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3466 total_len = (bytespf / packet_payload) * packet_len;
3467
3468 if (bytespf % packet_payload)
3469 total_len += (bytespf % packet_payload) + 1;
3470
3471 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3472 dsi_write_reg(DSI_VC_TE(channel), l);
3473
3474 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
3475
3476 if (dsi.te_enabled)
3477 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3478 else
3479 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3480 dsi_write_reg(DSI_VC_TE(channel), l);
3481
3482 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3483 * because DSS interrupts are not capable of waking up the CPU and the
3484 * framedone interrupt could be delayed for quite a long time. I think
3485 * the same goes for any DSS interrupts, but for some reason I have not
3486 * seen the problem anywhere else than here.
3487 */
3488 dispc_disable_sidle();
3489
3490 dsi_perf_mark_start();
3491
3492 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
3493 msecs_to_jiffies(250));
3494 BUG_ON(r == 0);
3495
3496 dss_start_update(dssdev);
3497
3498 if (dsi.te_enabled) {
3499 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3500 * for TE is longer than the timer allows */
3501 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3502
3503 dsi_vc_send_bta(channel);
3504
3505 #ifdef DSI_CATCH_MISSING_TE
3506 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
3507 #endif
3508 }
3509 }
3510
3511 #ifdef DSI_CATCH_MISSING_TE
3512 static void dsi_te_timeout(unsigned long arg)
3513 {
3514 DSSERR("TE not received for 250ms!\n");
3515 }
3516 #endif
3517
3518 static void dsi_handle_framedone(int error)
3519 {
3520 /* SIDLEMODE back to smart-idle */
3521 dispc_enable_sidle();
3522
3523 if (dsi.te_enabled) {
3524 /* enable LP_RX_TO again after the TE */
3525 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3526 }
3527
3528 dsi.framedone_callback(error, dsi.framedone_data);
3529
3530 if (!error)
3531 dsi_perf_show("DISPC");
3532 }
3533
3534 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3535 {
3536 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3537 * 250ms which would conflict with this timeout work. What should be
3538 * done is first cancel the transfer on the HW, and then cancel the
3539 * possibly scheduled framedone work. However, cancelling the transfer
3540 * on the HW is buggy, and would probably require resetting the whole
3541 * DSI */
3542
3543 DSSERR("Framedone not received for 250ms!\n");
3544
3545 dsi_handle_framedone(-ETIMEDOUT);
3546 }
3547
3548 static void dsi_framedone_irq_callback(void *data, u32 mask)
3549 {
3550 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3551 * turns itself off. However, DSI still has the pixels in its buffers,
3552 * and is sending the data.
3553 */
3554
3555 __cancel_delayed_work(&dsi.framedone_timeout_work);
3556
3557 dsi_handle_framedone(0);
3558
3559 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3560 dispc_fake_vsync_irq();
3561 #endif
3562 }
3563
3564 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3565 u16 *x, u16 *y, u16 *w, u16 *h,
3566 bool enlarge_update_area)
3567 {
3568 u16 dw, dh;
3569
3570 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3571
3572 if (*x > dw || *y > dh)
3573 return -EINVAL;
3574
3575 if (*x + *w > dw)
3576 return -EINVAL;
3577
3578 if (*y + *h > dh)
3579 return -EINVAL;
3580
3581 if (*w == 1)
3582 return -EINVAL;
3583
3584 if (*w == 0 || *h == 0)
3585 return -EINVAL;
3586
3587 dsi_perf_mark_setup();
3588
3589 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3590 dss_setup_partial_planes(dssdev, x, y, w, h,
3591 enlarge_update_area);
3592 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
3593 }
3594
3595 return 0;
3596 }
3597 EXPORT_SYMBOL(omap_dsi_prepare_update);
3598
3599 int omap_dsi_update(struct omap_dss_device *dssdev,
3600 int channel,
3601 u16 x, u16 y, u16 w, u16 h,
3602 void (*callback)(int, void *), void *data)
3603 {
3604 dsi.update_channel = channel;
3605
3606 /* OMAP DSS cannot send updates of odd widths.
3607 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
3608 * here to make sure we catch erroneous updates. Otherwise we'll only
3609 * see rather obscure HW error happening, as DSS halts. */
3610 BUG_ON(x % 2 == 1);
3611
3612 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
3613 dsi.framedone_callback = callback;
3614 dsi.framedone_data = data;
3615
3616 dsi.update_region.x = x;
3617 dsi.update_region.y = y;
3618 dsi.update_region.w = w;
3619 dsi.update_region.h = h;
3620 dsi.update_region.device = dssdev;
3621
3622 dsi_update_screen_dispc(dssdev, x, y, w, h);
3623 } else {
3624 int r;
3625
3626 r = dsi_update_screen_l4(dssdev, x, y, w, h);
3627 if (r)
3628 return r;
3629
3630 dsi_perf_show("L4");
3631 callback(0, data);
3632 }
3633
3634 return 0;
3635 }
3636 EXPORT_SYMBOL(omap_dsi_update);
3637
3638 /* Display funcs */
3639
3640 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
3641 {
3642 int r;
3643
3644 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
3645 DISPC_IRQ_FRAMEDONE);
3646 if (r) {
3647 DSSERR("can't get FRAMEDONE irq\n");
3648 return r;
3649 }
3650
3651 dispc_set_lcd_display_type(dssdev->manager->id,
3652 OMAP_DSS_LCD_DISPLAY_TFT);
3653
3654 dispc_set_parallel_interface_mode(dssdev->manager->id,
3655 OMAP_DSS_PARALLELMODE_DSI);
3656 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
3657
3658 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
3659
3660 {
3661 struct omap_video_timings timings = {
3662 .hsw = 1,
3663 .hfp = 1,
3664 .hbp = 1,
3665 .vsw = 1,
3666 .vfp = 0,
3667 .vbp = 0,
3668 };
3669
3670 dispc_set_lcd_timings(dssdev->manager->id, &timings);
3671 }
3672
3673 return 0;
3674 }
3675
3676 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3677 {
3678 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3679 DISPC_IRQ_FRAMEDONE);
3680 }
3681
3682 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3683 {
3684 struct dsi_clock_info cinfo;
3685 int r;
3686
3687 /* we always use DSS_CLK_SYSCK as input clock */
3688 cinfo.use_sys_clk = true;
3689 cinfo.regn = dssdev->clocks.dsi.regn;
3690 cinfo.regm = dssdev->clocks.dsi.regm;
3691 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
3692 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
3693 r = dsi_calc_clock_rates(dssdev, &cinfo);
3694 if (r) {
3695 DSSERR("Failed to calc dsi clocks\n");
3696 return r;
3697 }
3698
3699 r = dsi_pll_set_clock_div(&cinfo);
3700 if (r) {
3701 DSSERR("Failed to set dsi clocks\n");
3702 return r;
3703 }
3704
3705 return 0;
3706 }
3707
3708 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3709 {
3710 struct dispc_clock_info dispc_cinfo;
3711 int r;
3712 unsigned long long fck;
3713
3714 fck = dsi_get_pll_hsdiv_dispc_rate();
3715
3716 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
3717 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
3718
3719 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3720 if (r) {
3721 DSSERR("Failed to calc dispc clocks\n");
3722 return r;
3723 }
3724
3725 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3726 if (r) {
3727 DSSERR("Failed to set dispc clocks\n");
3728 return r;
3729 }
3730
3731 return 0;
3732 }
3733
3734 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3735 {
3736 int r;
3737
3738 r = dsi_pll_init(dssdev, true, true);
3739 if (r)
3740 goto err0;
3741
3742 r = dsi_configure_dsi_clocks(dssdev);
3743 if (r)
3744 goto err1;
3745
3746 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
3747 dss_select_dsi_clk_source(dssdev->clocks.dsi.dsi_fclk_src);
3748 dss_select_lcd_clk_source(dssdev->manager->id,
3749 dssdev->clocks.dispc.channel.lcd_clk_src);
3750
3751 DSSDBG("PLL OK\n");
3752
3753 r = dsi_configure_dispc_clocks(dssdev);
3754 if (r)
3755 goto err2;
3756
3757 r = dsi_cio_init(dssdev);
3758 if (r)
3759 goto err2;
3760
3761 _dsi_print_reset_status();
3762
3763 dsi_proto_timings(dssdev);
3764 dsi_set_lp_clk_divisor(dssdev);
3765
3766 if (1)
3767 _dsi_print_reset_status();
3768
3769 r = dsi_proto_config(dssdev);
3770 if (r)
3771 goto err3;
3772
3773 /* enable interface */
3774 dsi_vc_enable(0, 1);
3775 dsi_vc_enable(1, 1);
3776 dsi_vc_enable(2, 1);
3777 dsi_vc_enable(3, 1);
3778 dsi_if_enable(1);
3779 dsi_force_tx_stop_mode_io();
3780
3781 return 0;
3782 err3:
3783 dsi_cio_uninit();
3784 err2:
3785 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
3786 dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK);
3787 err1:
3788 dsi_pll_uninit(true);
3789 err0:
3790 return r;
3791 }
3792
3793 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
3794 bool disconnect_lanes, bool enter_ulps)
3795 {
3796 if (enter_ulps && !dsi.ulps_enabled)
3797 dsi_enter_ulps();
3798
3799 /* disable interface */
3800 dsi_if_enable(0);
3801 dsi_vc_enable(0, 0);
3802 dsi_vc_enable(1, 0);
3803 dsi_vc_enable(2, 0);
3804 dsi_vc_enable(3, 0);
3805
3806 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
3807 dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK);
3808 dsi_cio_uninit();
3809 dsi_pll_uninit(disconnect_lanes);
3810 }
3811
3812 static int dsi_core_init(void)
3813 {
3814 /* Autoidle */
3815 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3816
3817 /* ENWAKEUP */
3818 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3819
3820 /* SIDLEMODE smart-idle */
3821 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3822
3823 _dsi_initialize_irq();
3824
3825 return 0;
3826 }
3827
3828 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3829 {
3830 int r = 0;
3831
3832 DSSDBG("dsi_display_enable\n");
3833
3834 WARN_ON(!dsi_bus_is_locked());
3835
3836 mutex_lock(&dsi.lock);
3837
3838 r = omap_dss_start_device(dssdev);
3839 if (r) {
3840 DSSERR("failed to start device\n");
3841 goto err0;
3842 }
3843
3844 enable_clocks(1);
3845 dsi_enable_pll_clock(1);
3846
3847 r = _dsi_reset();
3848 if (r)
3849 goto err1;
3850
3851 dsi_core_init();
3852
3853 r = dsi_display_init_dispc(dssdev);
3854 if (r)
3855 goto err1;
3856
3857 r = dsi_display_init_dsi(dssdev);
3858 if (r)
3859 goto err2;
3860
3861 mutex_unlock(&dsi.lock);
3862
3863 return 0;
3864
3865 err2:
3866 dsi_display_uninit_dispc(dssdev);
3867 err1:
3868 enable_clocks(0);
3869 dsi_enable_pll_clock(0);
3870 omap_dss_stop_device(dssdev);
3871 err0:
3872 mutex_unlock(&dsi.lock);
3873 DSSDBG("dsi_display_enable FAILED\n");
3874 return r;
3875 }
3876 EXPORT_SYMBOL(omapdss_dsi_display_enable);
3877
3878 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
3879 bool disconnect_lanes, bool enter_ulps)
3880 {
3881 DSSDBG("dsi_display_disable\n");
3882
3883 WARN_ON(!dsi_bus_is_locked());
3884
3885 mutex_lock(&dsi.lock);
3886
3887 dsi_display_uninit_dispc(dssdev);
3888
3889 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
3890
3891 enable_clocks(0);
3892 dsi_enable_pll_clock(0);
3893
3894 omap_dss_stop_device(dssdev);
3895
3896 mutex_unlock(&dsi.lock);
3897 }
3898 EXPORT_SYMBOL(omapdss_dsi_display_disable);
3899
3900 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3901 {
3902 dsi.te_enabled = enable;
3903 return 0;
3904 }
3905 EXPORT_SYMBOL(omapdss_dsi_enable_te);
3906
3907 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3908 u32 fifo_size, enum omap_burst_size *burst_size,
3909 u32 *fifo_low, u32 *fifo_high)
3910 {
3911 unsigned burst_size_bytes;
3912
3913 *burst_size = OMAP_DSS_BURST_16x32;
3914 burst_size_bytes = 16 * 32 / 8;
3915
3916 *fifo_high = fifo_size - burst_size_bytes;
3917 *fifo_low = fifo_size - burst_size_bytes * 2;
3918 }
3919
3920 int dsi_init_display(struct omap_dss_device *dssdev)
3921 {
3922 DSSDBG("DSI init\n");
3923
3924 /* XXX these should be figured out dynamically */
3925 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3926 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3927
3928 if (dsi.vdds_dsi_reg == NULL) {
3929 struct regulator *vdds_dsi;
3930
3931 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3932
3933 if (IS_ERR(vdds_dsi)) {
3934 DSSERR("can't get VDDS_DSI regulator\n");
3935 return PTR_ERR(vdds_dsi);
3936 }
3937
3938 dsi.vdds_dsi_reg = vdds_dsi;
3939 }
3940
3941 return 0;
3942 }
3943
3944 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
3945 {
3946 int i;
3947
3948 for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
3949 if (!dsi.vc[i].dssdev) {
3950 dsi.vc[i].dssdev = dssdev;
3951 *channel = i;
3952 return 0;
3953 }
3954 }
3955
3956 DSSERR("cannot get VC for display %s", dssdev->name);
3957 return -ENOSPC;
3958 }
3959 EXPORT_SYMBOL(omap_dsi_request_vc);
3960
3961 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
3962 {
3963 if (vc_id < 0 || vc_id > 3) {
3964 DSSERR("VC ID out of range\n");
3965 return -EINVAL;
3966 }
3967
3968 if (channel < 0 || channel > 3) {
3969 DSSERR("Virtual Channel out of range\n");
3970 return -EINVAL;
3971 }
3972
3973 if (dsi.vc[channel].dssdev != dssdev) {
3974 DSSERR("Virtual Channel not allocated to display %s\n",
3975 dssdev->name);
3976 return -EINVAL;
3977 }
3978
3979 dsi.vc[channel].vc_id = vc_id;
3980
3981 return 0;
3982 }
3983 EXPORT_SYMBOL(omap_dsi_set_vc_id);
3984
3985 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
3986 {
3987 if ((channel >= 0 && channel <= 3) &&
3988 dsi.vc[channel].dssdev == dssdev) {
3989 dsi.vc[channel].dssdev = NULL;
3990 dsi.vc[channel].vc_id = 0;
3991 }
3992 }
3993 EXPORT_SYMBOL(omap_dsi_release_vc);
3994
3995 void dsi_wait_pll_hsdiv_dispc_active(void)
3996 {
3997 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3998 DSSERR("%s (%s) not active\n",
3999 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4000 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4001 }
4002
4003 void dsi_wait_pll_hsdiv_dsi_active(void)
4004 {
4005 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
4006 DSSERR("%s (%s) not active\n",
4007 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4008 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4009 }
4010
4011 static void dsi_calc_clock_param_ranges(void)
4012 {
4013 dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4014 dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4015 dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4016 dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4017 dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4018 dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4019 dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4020 }
4021
4022 static int dsi_init(struct platform_device *pdev)
4023 {
4024 struct omap_display_platform_data *dss_plat_data;
4025 struct omap_dss_board_info *board_info;
4026 u32 rev;
4027 int r, i;
4028 struct resource *dsi_mem;
4029
4030 dss_plat_data = pdev->dev.platform_data;
4031 board_info = dss_plat_data->board_data;
4032 dsi.dsi_mux_pads = board_info->dsi_mux_pads;
4033
4034 spin_lock_init(&dsi.irq_lock);
4035 spin_lock_init(&dsi.errors_lock);
4036 dsi.errors = 0;
4037
4038 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4039 spin_lock_init(&dsi.irq_stats_lock);
4040 dsi.irq_stats.last_reset = jiffies;
4041 #endif
4042
4043 mutex_init(&dsi.lock);
4044 sema_init(&dsi.bus_lock, 1);
4045
4046 dsi.workqueue = create_singlethread_workqueue("dsi");
4047 if (dsi.workqueue == NULL)
4048 return -ENOMEM;
4049
4050 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
4051 dsi_framedone_timeout_work_callback);
4052
4053 #ifdef DSI_CATCH_MISSING_TE
4054 init_timer(&dsi.te_timer);
4055 dsi.te_timer.function = dsi_te_timeout;
4056 dsi.te_timer.data = 0;
4057 #endif
4058 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
4059 if (!dsi_mem) {
4060 DSSERR("can't get IORESOURCE_MEM DSI\n");
4061 r = -EINVAL;
4062 goto err1;
4063 }
4064 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4065 if (!dsi.base) {
4066 DSSERR("can't ioremap DSI\n");
4067 r = -ENOMEM;
4068 goto err1;
4069 }
4070 dsi.irq = platform_get_irq(dsi.pdev, 0);
4071 if (dsi.irq < 0) {
4072 DSSERR("platform_get_irq failed\n");
4073 r = -ENODEV;
4074 goto err2;
4075 }
4076
4077 r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
4078 "OMAP DSI1", dsi.pdev);
4079 if (r < 0) {
4080 DSSERR("request_irq failed\n");
4081 goto err2;
4082 }
4083
4084 /* DSI VCs initialization */
4085 for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
4086 dsi.vc[i].mode = DSI_VC_MODE_L4;
4087 dsi.vc[i].dssdev = NULL;
4088 dsi.vc[i].vc_id = 0;
4089 }
4090
4091 dsi_calc_clock_param_ranges();
4092
4093 enable_clocks(1);
4094
4095 rev = dsi_read_reg(DSI_REVISION);
4096 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
4097 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4098
4099 enable_clocks(0);
4100
4101 return 0;
4102 err2:
4103 iounmap(dsi.base);
4104 err1:
4105 destroy_workqueue(dsi.workqueue);
4106 return r;
4107 }
4108
4109 static void dsi_exit(void)
4110 {
4111 if (dsi.vdds_dsi_reg != NULL) {
4112 if (dsi.vdds_dsi_enabled) {
4113 regulator_disable(dsi.vdds_dsi_reg);
4114 dsi.vdds_dsi_enabled = false;
4115 }
4116
4117 regulator_put(dsi.vdds_dsi_reg);
4118 dsi.vdds_dsi_reg = NULL;
4119 }
4120
4121 free_irq(dsi.irq, dsi.pdev);
4122 iounmap(dsi.base);
4123
4124 destroy_workqueue(dsi.workqueue);
4125
4126 DSSDBG("omap_dsi_exit\n");
4127 }
4128
4129 /* DSI1 HW IP initialisation */
4130 static int omap_dsi1hw_probe(struct platform_device *pdev)
4131 {
4132 int r;
4133 dsi.pdev = pdev;
4134 r = dsi_init(pdev);
4135 if (r) {
4136 DSSERR("Failed to initialize DSI\n");
4137 goto err_dsi;
4138 }
4139 err_dsi:
4140 return r;
4141 }
4142
4143 static int omap_dsi1hw_remove(struct platform_device *pdev)
4144 {
4145 dsi_exit();
4146 WARN_ON(dsi.scp_clk_refcount > 0);
4147 return 0;
4148 }
4149
4150 static struct platform_driver omap_dsi1hw_driver = {
4151 .probe = omap_dsi1hw_probe,
4152 .remove = omap_dsi1hw_remove,
4153 .driver = {
4154 .name = "omapdss_dsi1",
4155 .owner = THIS_MODULE,
4156 },
4157 };
4158
4159 int dsi_init_platform_driver(void)
4160 {
4161 return platform_driver_register(&omap_dsi1hw_driver);
4162 }
4163
4164 void dsi_uninit_platform_driver(void)
4165 {
4166 return platform_driver_unregister(&omap_dsi1hw_driver);
4167 }
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