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[mirror_ubuntu-artful-kernel.git] / drivers / video / omap2 / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
45
46 #include "dss.h"
47 #include "dss_features.h"
48
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
51
52 struct dsi_reg { u16 idx; };
53
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
55
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
58
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
93
94 /* DSIPHY_SCP */
95
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
101
102 /* DSI_PLL_CTRL_SCP */
103
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
109
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
138
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
153
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204
205 #define DSI_MAX_NR_ISRS 2
206 #define DSI_MAX_NR_LANES 5
207
208 enum dsi_lane_function {
209 DSI_LANE_UNUSED = 0,
210 DSI_LANE_CLK,
211 DSI_LANE_DATA1,
212 DSI_LANE_DATA2,
213 DSI_LANE_DATA3,
214 DSI_LANE_DATA4,
215 };
216
217 struct dsi_lane_config {
218 enum dsi_lane_function function;
219 u8 polarity;
220 };
221
222 struct dsi_isr_data {
223 omap_dsi_isr_t isr;
224 void *arg;
225 u32 mask;
226 };
227
228 enum fifo_size {
229 DSI_FIFO_SIZE_0 = 0,
230 DSI_FIFO_SIZE_32 = 1,
231 DSI_FIFO_SIZE_64 = 2,
232 DSI_FIFO_SIZE_96 = 3,
233 DSI_FIFO_SIZE_128 = 4,
234 };
235
236 enum dsi_vc_source {
237 DSI_VC_SOURCE_L4 = 0,
238 DSI_VC_SOURCE_VP,
239 };
240
241 struct dsi_update_region {
242 u16 x, y, w, h;
243 struct omap_dss_device *device;
244 };
245
246 struct dsi_irq_stats {
247 unsigned long last_reset;
248 unsigned irq_count;
249 unsigned dsi_irqs[32];
250 unsigned vc_irqs[4][32];
251 unsigned cio_irqs[32];
252 };
253
254 struct dsi_isr_tables {
255 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
256 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
257 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
258 };
259
260 struct dsi_data {
261 struct platform_device *pdev;
262 void __iomem *base;
263
264 int irq;
265
266 struct clk *dss_clk;
267 struct clk *sys_clk;
268
269 int (*enable_pads)(int dsi_id, unsigned lane_mask);
270 void (*disable_pads)(int dsi_id, unsigned lane_mask);
271
272 struct dsi_clock_info current_cinfo;
273
274 bool vdds_dsi_enabled;
275 struct regulator *vdds_dsi_reg;
276
277 struct {
278 enum dsi_vc_source source;
279 struct omap_dss_device *dssdev;
280 enum fifo_size fifo_size;
281 int vc_id;
282 } vc[4];
283
284 struct mutex lock;
285 struct semaphore bus_lock;
286
287 unsigned pll_locked;
288
289 spinlock_t irq_lock;
290 struct dsi_isr_tables isr_tables;
291 /* space for a copy used by the interrupt handler */
292 struct dsi_isr_tables isr_tables_copy;
293
294 int update_channel;
295 struct dsi_update_region update_region;
296
297 bool te_enabled;
298 bool ulps_enabled;
299
300 void (*framedone_callback)(int, void *);
301 void *framedone_data;
302
303 struct delayed_work framedone_timeout_work;
304
305 #ifdef DSI_CATCH_MISSING_TE
306 struct timer_list te_timer;
307 #endif
308
309 unsigned long cache_req_pck;
310 unsigned long cache_clk_freq;
311 struct dsi_clock_info cache_cinfo;
312
313 u32 errors;
314 spinlock_t errors_lock;
315 #ifdef DEBUG
316 ktime_t perf_setup_time;
317 ktime_t perf_start_time;
318 #endif
319 int debug_read;
320 int debug_write;
321
322 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
323 spinlock_t irq_stats_lock;
324 struct dsi_irq_stats irq_stats;
325 #endif
326 /* DSI PLL Parameter Ranges */
327 unsigned long regm_max, regn_max;
328 unsigned long regm_dispc_max, regm_dsi_max;
329 unsigned long fint_min, fint_max;
330 unsigned long lpdiv_max;
331
332 unsigned num_lanes_supported;
333
334 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
335 unsigned num_lanes_used;
336
337 unsigned scp_clk_refcount;
338 };
339
340 struct dsi_packet_sent_handler_data {
341 struct platform_device *dsidev;
342 struct completion *completion;
343 };
344
345 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
346
347 #ifdef DEBUG
348 static unsigned int dsi_perf;
349 module_param_named(dsi_perf, dsi_perf, bool, 0644);
350 #endif
351
352 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
353 {
354 return dev_get_drvdata(&dsidev->dev);
355 }
356
357 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
358 {
359 return dsi_pdev_map[dssdev->phy.dsi.module];
360 }
361
362 struct platform_device *dsi_get_dsidev_from_id(int module)
363 {
364 return dsi_pdev_map[module];
365 }
366
367 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
368 {
369 return dsidev->id;
370 }
371
372 static inline void dsi_write_reg(struct platform_device *dsidev,
373 const struct dsi_reg idx, u32 val)
374 {
375 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
376
377 __raw_writel(val, dsi->base + idx.idx);
378 }
379
380 static inline u32 dsi_read_reg(struct platform_device *dsidev,
381 const struct dsi_reg idx)
382 {
383 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
384
385 return __raw_readl(dsi->base + idx.idx);
386 }
387
388 void dsi_bus_lock(struct omap_dss_device *dssdev)
389 {
390 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
391 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
392
393 down(&dsi->bus_lock);
394 }
395 EXPORT_SYMBOL(dsi_bus_lock);
396
397 void dsi_bus_unlock(struct omap_dss_device *dssdev)
398 {
399 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
400 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
401
402 up(&dsi->bus_lock);
403 }
404 EXPORT_SYMBOL(dsi_bus_unlock);
405
406 static bool dsi_bus_is_locked(struct platform_device *dsidev)
407 {
408 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
409
410 return dsi->bus_lock.count == 0;
411 }
412
413 static void dsi_completion_handler(void *data, u32 mask)
414 {
415 complete((struct completion *)data);
416 }
417
418 static inline int wait_for_bit_change(struct platform_device *dsidev,
419 const struct dsi_reg idx, int bitnum, int value)
420 {
421 int t = 100000;
422
423 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
424 if (--t == 0)
425 return !value;
426 }
427
428 return value;
429 }
430
431 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
432 {
433 switch (fmt) {
434 case OMAP_DSS_DSI_FMT_RGB888:
435 case OMAP_DSS_DSI_FMT_RGB666:
436 return 24;
437 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
438 return 18;
439 case OMAP_DSS_DSI_FMT_RGB565:
440 return 16;
441 default:
442 BUG();
443 }
444 }
445
446 #ifdef DEBUG
447 static void dsi_perf_mark_setup(struct platform_device *dsidev)
448 {
449 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
450 dsi->perf_setup_time = ktime_get();
451 }
452
453 static void dsi_perf_mark_start(struct platform_device *dsidev)
454 {
455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
456 dsi->perf_start_time = ktime_get();
457 }
458
459 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
460 {
461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
462 struct omap_dss_device *dssdev = dsi->update_region.device;
463 ktime_t t, setup_time, trans_time;
464 u32 total_bytes;
465 u32 setup_us, trans_us, total_us;
466
467 if (!dsi_perf)
468 return;
469
470 t = ktime_get();
471
472 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
473 setup_us = (u32)ktime_to_us(setup_time);
474 if (setup_us == 0)
475 setup_us = 1;
476
477 trans_time = ktime_sub(t, dsi->perf_start_time);
478 trans_us = (u32)ktime_to_us(trans_time);
479 if (trans_us == 0)
480 trans_us = 1;
481
482 total_us = setup_us + trans_us;
483
484 total_bytes = dsi->update_region.w *
485 dsi->update_region.h *
486 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
487
488 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
489 "%u bytes, %u kbytes/sec\n",
490 name,
491 setup_us,
492 trans_us,
493 total_us,
494 1000*1000 / total_us,
495 total_bytes,
496 total_bytes * 1000 / total_us);
497 }
498 #else
499 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
500 {
501 }
502
503 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
504 {
505 }
506
507 static inline void dsi_perf_show(struct platform_device *dsidev,
508 const char *name)
509 {
510 }
511 #endif
512
513 static void print_irq_status(u32 status)
514 {
515 if (status == 0)
516 return;
517
518 #ifndef VERBOSE_IRQ
519 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
520 return;
521 #endif
522 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
523
524 #define PIS(x) \
525 if (status & DSI_IRQ_##x) \
526 printk(#x " ");
527 #ifdef VERBOSE_IRQ
528 PIS(VC0);
529 PIS(VC1);
530 PIS(VC2);
531 PIS(VC3);
532 #endif
533 PIS(WAKEUP);
534 PIS(RESYNC);
535 PIS(PLL_LOCK);
536 PIS(PLL_UNLOCK);
537 PIS(PLL_RECALL);
538 PIS(COMPLEXIO_ERR);
539 PIS(HS_TX_TIMEOUT);
540 PIS(LP_RX_TIMEOUT);
541 PIS(TE_TRIGGER);
542 PIS(ACK_TRIGGER);
543 PIS(SYNC_LOST);
544 PIS(LDO_POWER_GOOD);
545 PIS(TA_TIMEOUT);
546 #undef PIS
547
548 printk("\n");
549 }
550
551 static void print_irq_status_vc(int channel, u32 status)
552 {
553 if (status == 0)
554 return;
555
556 #ifndef VERBOSE_IRQ
557 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
558 return;
559 #endif
560 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
561
562 #define PIS(x) \
563 if (status & DSI_VC_IRQ_##x) \
564 printk(#x " ");
565 PIS(CS);
566 PIS(ECC_CORR);
567 #ifdef VERBOSE_IRQ
568 PIS(PACKET_SENT);
569 #endif
570 PIS(FIFO_TX_OVF);
571 PIS(FIFO_RX_OVF);
572 PIS(BTA);
573 PIS(ECC_NO_CORR);
574 PIS(FIFO_TX_UDF);
575 PIS(PP_BUSY_CHANGE);
576 #undef PIS
577 printk("\n");
578 }
579
580 static void print_irq_status_cio(u32 status)
581 {
582 if (status == 0)
583 return;
584
585 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
586
587 #define PIS(x) \
588 if (status & DSI_CIO_IRQ_##x) \
589 printk(#x " ");
590 PIS(ERRSYNCESC1);
591 PIS(ERRSYNCESC2);
592 PIS(ERRSYNCESC3);
593 PIS(ERRESC1);
594 PIS(ERRESC2);
595 PIS(ERRESC3);
596 PIS(ERRCONTROL1);
597 PIS(ERRCONTROL2);
598 PIS(ERRCONTROL3);
599 PIS(STATEULPS1);
600 PIS(STATEULPS2);
601 PIS(STATEULPS3);
602 PIS(ERRCONTENTIONLP0_1);
603 PIS(ERRCONTENTIONLP1_1);
604 PIS(ERRCONTENTIONLP0_2);
605 PIS(ERRCONTENTIONLP1_2);
606 PIS(ERRCONTENTIONLP0_3);
607 PIS(ERRCONTENTIONLP1_3);
608 PIS(ULPSACTIVENOT_ALL0);
609 PIS(ULPSACTIVENOT_ALL1);
610 #undef PIS
611
612 printk("\n");
613 }
614
615 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
616 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
617 u32 *vcstatus, u32 ciostatus)
618 {
619 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
620 int i;
621
622 spin_lock(&dsi->irq_stats_lock);
623
624 dsi->irq_stats.irq_count++;
625 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
626
627 for (i = 0; i < 4; ++i)
628 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
629
630 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
631
632 spin_unlock(&dsi->irq_stats_lock);
633 }
634 #else
635 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
636 #endif
637
638 static int debug_irq;
639
640 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
641 u32 *vcstatus, u32 ciostatus)
642 {
643 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
644 int i;
645
646 if (irqstatus & DSI_IRQ_ERROR_MASK) {
647 DSSERR("DSI error, irqstatus %x\n", irqstatus);
648 print_irq_status(irqstatus);
649 spin_lock(&dsi->errors_lock);
650 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
651 spin_unlock(&dsi->errors_lock);
652 } else if (debug_irq) {
653 print_irq_status(irqstatus);
654 }
655
656 for (i = 0; i < 4; ++i) {
657 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
658 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
659 i, vcstatus[i]);
660 print_irq_status_vc(i, vcstatus[i]);
661 } else if (debug_irq) {
662 print_irq_status_vc(i, vcstatus[i]);
663 }
664 }
665
666 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
667 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
668 print_irq_status_cio(ciostatus);
669 } else if (debug_irq) {
670 print_irq_status_cio(ciostatus);
671 }
672 }
673
674 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
675 unsigned isr_array_size, u32 irqstatus)
676 {
677 struct dsi_isr_data *isr_data;
678 int i;
679
680 for (i = 0; i < isr_array_size; i++) {
681 isr_data = &isr_array[i];
682 if (isr_data->isr && isr_data->mask & irqstatus)
683 isr_data->isr(isr_data->arg, irqstatus);
684 }
685 }
686
687 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
688 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
689 {
690 int i;
691
692 dsi_call_isrs(isr_tables->isr_table,
693 ARRAY_SIZE(isr_tables->isr_table),
694 irqstatus);
695
696 for (i = 0; i < 4; ++i) {
697 if (vcstatus[i] == 0)
698 continue;
699 dsi_call_isrs(isr_tables->isr_table_vc[i],
700 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
701 vcstatus[i]);
702 }
703
704 if (ciostatus != 0)
705 dsi_call_isrs(isr_tables->isr_table_cio,
706 ARRAY_SIZE(isr_tables->isr_table_cio),
707 ciostatus);
708 }
709
710 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
711 {
712 struct platform_device *dsidev;
713 struct dsi_data *dsi;
714 u32 irqstatus, vcstatus[4], ciostatus;
715 int i;
716
717 dsidev = (struct platform_device *) arg;
718 dsi = dsi_get_dsidrv_data(dsidev);
719
720 spin_lock(&dsi->irq_lock);
721
722 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
723
724 /* IRQ is not for us */
725 if (!irqstatus) {
726 spin_unlock(&dsi->irq_lock);
727 return IRQ_NONE;
728 }
729
730 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
731 /* flush posted write */
732 dsi_read_reg(dsidev, DSI_IRQSTATUS);
733
734 for (i = 0; i < 4; ++i) {
735 if ((irqstatus & (1 << i)) == 0) {
736 vcstatus[i] = 0;
737 continue;
738 }
739
740 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
741
742 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
743 /* flush posted write */
744 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
745 }
746
747 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
748 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
749
750 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
751 /* flush posted write */
752 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
753 } else {
754 ciostatus = 0;
755 }
756
757 #ifdef DSI_CATCH_MISSING_TE
758 if (irqstatus & DSI_IRQ_TE_TRIGGER)
759 del_timer(&dsi->te_timer);
760 #endif
761
762 /* make a copy and unlock, so that isrs can unregister
763 * themselves */
764 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
765 sizeof(dsi->isr_tables));
766
767 spin_unlock(&dsi->irq_lock);
768
769 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
770
771 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
772
773 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
774
775 return IRQ_HANDLED;
776 }
777
778 /* dsi->irq_lock has to be locked by the caller */
779 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
780 struct dsi_isr_data *isr_array,
781 unsigned isr_array_size, u32 default_mask,
782 const struct dsi_reg enable_reg,
783 const struct dsi_reg status_reg)
784 {
785 struct dsi_isr_data *isr_data;
786 u32 mask;
787 u32 old_mask;
788 int i;
789
790 mask = default_mask;
791
792 for (i = 0; i < isr_array_size; i++) {
793 isr_data = &isr_array[i];
794
795 if (isr_data->isr == NULL)
796 continue;
797
798 mask |= isr_data->mask;
799 }
800
801 old_mask = dsi_read_reg(dsidev, enable_reg);
802 /* clear the irqstatus for newly enabled irqs */
803 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
804 dsi_write_reg(dsidev, enable_reg, mask);
805
806 /* flush posted writes */
807 dsi_read_reg(dsidev, enable_reg);
808 dsi_read_reg(dsidev, status_reg);
809 }
810
811 /* dsi->irq_lock has to be locked by the caller */
812 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
813 {
814 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
815 u32 mask = DSI_IRQ_ERROR_MASK;
816 #ifdef DSI_CATCH_MISSING_TE
817 mask |= DSI_IRQ_TE_TRIGGER;
818 #endif
819 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
820 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
821 DSI_IRQENABLE, DSI_IRQSTATUS);
822 }
823
824 /* dsi->irq_lock has to be locked by the caller */
825 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
826 {
827 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
828
829 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
830 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
831 DSI_VC_IRQ_ERROR_MASK,
832 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
833 }
834
835 /* dsi->irq_lock has to be locked by the caller */
836 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
837 {
838 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
839
840 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
841 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
842 DSI_CIO_IRQ_ERROR_MASK,
843 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
844 }
845
846 static void _dsi_initialize_irq(struct platform_device *dsidev)
847 {
848 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
849 unsigned long flags;
850 int vc;
851
852 spin_lock_irqsave(&dsi->irq_lock, flags);
853
854 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
855
856 _omap_dsi_set_irqs(dsidev);
857 for (vc = 0; vc < 4; ++vc)
858 _omap_dsi_set_irqs_vc(dsidev, vc);
859 _omap_dsi_set_irqs_cio(dsidev);
860
861 spin_unlock_irqrestore(&dsi->irq_lock, flags);
862 }
863
864 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
865 struct dsi_isr_data *isr_array, unsigned isr_array_size)
866 {
867 struct dsi_isr_data *isr_data;
868 int free_idx;
869 int i;
870
871 BUG_ON(isr == NULL);
872
873 /* check for duplicate entry and find a free slot */
874 free_idx = -1;
875 for (i = 0; i < isr_array_size; i++) {
876 isr_data = &isr_array[i];
877
878 if (isr_data->isr == isr && isr_data->arg == arg &&
879 isr_data->mask == mask) {
880 return -EINVAL;
881 }
882
883 if (isr_data->isr == NULL && free_idx == -1)
884 free_idx = i;
885 }
886
887 if (free_idx == -1)
888 return -EBUSY;
889
890 isr_data = &isr_array[free_idx];
891 isr_data->isr = isr;
892 isr_data->arg = arg;
893 isr_data->mask = mask;
894
895 return 0;
896 }
897
898 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
899 struct dsi_isr_data *isr_array, unsigned isr_array_size)
900 {
901 struct dsi_isr_data *isr_data;
902 int i;
903
904 for (i = 0; i < isr_array_size; i++) {
905 isr_data = &isr_array[i];
906 if (isr_data->isr != isr || isr_data->arg != arg ||
907 isr_data->mask != mask)
908 continue;
909
910 isr_data->isr = NULL;
911 isr_data->arg = NULL;
912 isr_data->mask = 0;
913
914 return 0;
915 }
916
917 return -EINVAL;
918 }
919
920 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
921 void *arg, u32 mask)
922 {
923 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
924 unsigned long flags;
925 int r;
926
927 spin_lock_irqsave(&dsi->irq_lock, flags);
928
929 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
930 ARRAY_SIZE(dsi->isr_tables.isr_table));
931
932 if (r == 0)
933 _omap_dsi_set_irqs(dsidev);
934
935 spin_unlock_irqrestore(&dsi->irq_lock, flags);
936
937 return r;
938 }
939
940 static int dsi_unregister_isr(struct platform_device *dsidev,
941 omap_dsi_isr_t isr, void *arg, u32 mask)
942 {
943 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
944 unsigned long flags;
945 int r;
946
947 spin_lock_irqsave(&dsi->irq_lock, flags);
948
949 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
950 ARRAY_SIZE(dsi->isr_tables.isr_table));
951
952 if (r == 0)
953 _omap_dsi_set_irqs(dsidev);
954
955 spin_unlock_irqrestore(&dsi->irq_lock, flags);
956
957 return r;
958 }
959
960 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
961 omap_dsi_isr_t isr, void *arg, u32 mask)
962 {
963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
964 unsigned long flags;
965 int r;
966
967 spin_lock_irqsave(&dsi->irq_lock, flags);
968
969 r = _dsi_register_isr(isr, arg, mask,
970 dsi->isr_tables.isr_table_vc[channel],
971 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
972
973 if (r == 0)
974 _omap_dsi_set_irqs_vc(dsidev, channel);
975
976 spin_unlock_irqrestore(&dsi->irq_lock, flags);
977
978 return r;
979 }
980
981 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
982 omap_dsi_isr_t isr, void *arg, u32 mask)
983 {
984 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
985 unsigned long flags;
986 int r;
987
988 spin_lock_irqsave(&dsi->irq_lock, flags);
989
990 r = _dsi_unregister_isr(isr, arg, mask,
991 dsi->isr_tables.isr_table_vc[channel],
992 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
993
994 if (r == 0)
995 _omap_dsi_set_irqs_vc(dsidev, channel);
996
997 spin_unlock_irqrestore(&dsi->irq_lock, flags);
998
999 return r;
1000 }
1001
1002 static int dsi_register_isr_cio(struct platform_device *dsidev,
1003 omap_dsi_isr_t isr, void *arg, u32 mask)
1004 {
1005 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1006 unsigned long flags;
1007 int r;
1008
1009 spin_lock_irqsave(&dsi->irq_lock, flags);
1010
1011 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1012 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1013
1014 if (r == 0)
1015 _omap_dsi_set_irqs_cio(dsidev);
1016
1017 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1018
1019 return r;
1020 }
1021
1022 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1023 omap_dsi_isr_t isr, void *arg, u32 mask)
1024 {
1025 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1026 unsigned long flags;
1027 int r;
1028
1029 spin_lock_irqsave(&dsi->irq_lock, flags);
1030
1031 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1032 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1033
1034 if (r == 0)
1035 _omap_dsi_set_irqs_cio(dsidev);
1036
1037 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1038
1039 return r;
1040 }
1041
1042 static u32 dsi_get_errors(struct platform_device *dsidev)
1043 {
1044 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1045 unsigned long flags;
1046 u32 e;
1047 spin_lock_irqsave(&dsi->errors_lock, flags);
1048 e = dsi->errors;
1049 dsi->errors = 0;
1050 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1051 return e;
1052 }
1053
1054 int dsi_runtime_get(struct platform_device *dsidev)
1055 {
1056 int r;
1057 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1058
1059 DSSDBG("dsi_runtime_get\n");
1060
1061 r = pm_runtime_get_sync(&dsi->pdev->dev);
1062 WARN_ON(r < 0);
1063 return r < 0 ? r : 0;
1064 }
1065
1066 void dsi_runtime_put(struct platform_device *dsidev)
1067 {
1068 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1069 int r;
1070
1071 DSSDBG("dsi_runtime_put\n");
1072
1073 r = pm_runtime_put(&dsi->pdev->dev);
1074 WARN_ON(r < 0);
1075 }
1076
1077 /* source clock for DSI PLL. this could also be PCLKFREE */
1078 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1079 bool enable)
1080 {
1081 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1082
1083 if (enable)
1084 clk_enable(dsi->sys_clk);
1085 else
1086 clk_disable(dsi->sys_clk);
1087
1088 if (enable && dsi->pll_locked) {
1089 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1090 DSSERR("cannot lock PLL when enabling clocks\n");
1091 }
1092 }
1093
1094 #ifdef DEBUG
1095 static void _dsi_print_reset_status(struct platform_device *dsidev)
1096 {
1097 u32 l;
1098 int b0, b1, b2;
1099
1100 if (!dss_debug)
1101 return;
1102
1103 /* A dummy read using the SCP interface to any DSIPHY register is
1104 * required after DSIPHY reset to complete the reset of the DSI complex
1105 * I/O. */
1106 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1107
1108 printk(KERN_DEBUG "DSI resets: ");
1109
1110 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1111 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1112
1113 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1114 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1115
1116 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1117 b0 = 28;
1118 b1 = 27;
1119 b2 = 26;
1120 } else {
1121 b0 = 24;
1122 b1 = 25;
1123 b2 = 26;
1124 }
1125
1126 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1127 printk("PHY (%x%x%x, %d, %d, %d)\n",
1128 FLD_GET(l, b0, b0),
1129 FLD_GET(l, b1, b1),
1130 FLD_GET(l, b2, b2),
1131 FLD_GET(l, 29, 29),
1132 FLD_GET(l, 30, 30),
1133 FLD_GET(l, 31, 31));
1134 }
1135 #else
1136 #define _dsi_print_reset_status(x)
1137 #endif
1138
1139 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1140 {
1141 DSSDBG("dsi_if_enable(%d)\n", enable);
1142
1143 enable = enable ? 1 : 0;
1144 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1145
1146 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1147 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1148 return -EIO;
1149 }
1150
1151 return 0;
1152 }
1153
1154 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1155 {
1156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1157
1158 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1159 }
1160
1161 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1162 {
1163 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1164
1165 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1166 }
1167
1168 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1169 {
1170 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1171
1172 return dsi->current_cinfo.clkin4ddr / 16;
1173 }
1174
1175 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1176 {
1177 unsigned long r;
1178 int dsi_module = dsi_get_dsidev_id(dsidev);
1179 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1180
1181 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1182 /* DSI FCLK source is DSS_CLK_FCK */
1183 r = clk_get_rate(dsi->dss_clk);
1184 } else {
1185 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1186 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1187 }
1188
1189 return r;
1190 }
1191
1192 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1193 {
1194 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1195 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1196 unsigned long dsi_fclk;
1197 unsigned lp_clk_div;
1198 unsigned long lp_clk;
1199
1200 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1201
1202 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1203 return -EINVAL;
1204
1205 dsi_fclk = dsi_fclk_rate(dsidev);
1206
1207 lp_clk = dsi_fclk / 2 / lp_clk_div;
1208
1209 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1210 dsi->current_cinfo.lp_clk = lp_clk;
1211 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1212
1213 /* LP_CLK_DIVISOR */
1214 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1215
1216 /* LP_RX_SYNCHRO_ENABLE */
1217 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1218
1219 return 0;
1220 }
1221
1222 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1223 {
1224 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1225
1226 if (dsi->scp_clk_refcount++ == 0)
1227 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1228 }
1229
1230 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1231 {
1232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1233
1234 WARN_ON(dsi->scp_clk_refcount == 0);
1235 if (--dsi->scp_clk_refcount == 0)
1236 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1237 }
1238
1239 enum dsi_pll_power_state {
1240 DSI_PLL_POWER_OFF = 0x0,
1241 DSI_PLL_POWER_ON_HSCLK = 0x1,
1242 DSI_PLL_POWER_ON_ALL = 0x2,
1243 DSI_PLL_POWER_ON_DIV = 0x3,
1244 };
1245
1246 static int dsi_pll_power(struct platform_device *dsidev,
1247 enum dsi_pll_power_state state)
1248 {
1249 int t = 0;
1250
1251 /* DSI-PLL power command 0x3 is not working */
1252 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1253 state == DSI_PLL_POWER_ON_DIV)
1254 state = DSI_PLL_POWER_ON_ALL;
1255
1256 /* PLL_PWR_CMD */
1257 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1258
1259 /* PLL_PWR_STATUS */
1260 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1261 if (++t > 1000) {
1262 DSSERR("Failed to set DSI PLL power mode to %d\n",
1263 state);
1264 return -ENODEV;
1265 }
1266 udelay(1);
1267 }
1268
1269 return 0;
1270 }
1271
1272 /* calculate clock rates using dividers in cinfo */
1273 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1274 struct dsi_clock_info *cinfo)
1275 {
1276 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1277 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1278
1279 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1280 return -EINVAL;
1281
1282 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1283 return -EINVAL;
1284
1285 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1286 return -EINVAL;
1287
1288 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1289 return -EINVAL;
1290
1291 if (cinfo->use_sys_clk) {
1292 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1293 /* XXX it is unclear if highfreq should be used
1294 * with DSS_SYS_CLK source also */
1295 cinfo->highfreq = 0;
1296 } else {
1297 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1298
1299 if (cinfo->clkin < 32000000)
1300 cinfo->highfreq = 0;
1301 else
1302 cinfo->highfreq = 1;
1303 }
1304
1305 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1306
1307 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1308 return -EINVAL;
1309
1310 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1311
1312 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1313 return -EINVAL;
1314
1315 if (cinfo->regm_dispc > 0)
1316 cinfo->dsi_pll_hsdiv_dispc_clk =
1317 cinfo->clkin4ddr / cinfo->regm_dispc;
1318 else
1319 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1320
1321 if (cinfo->regm_dsi > 0)
1322 cinfo->dsi_pll_hsdiv_dsi_clk =
1323 cinfo->clkin4ddr / cinfo->regm_dsi;
1324 else
1325 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1326
1327 return 0;
1328 }
1329
1330 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1331 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1332 struct dispc_clock_info *dispc_cinfo)
1333 {
1334 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1335 struct dsi_clock_info cur, best;
1336 struct dispc_clock_info best_dispc;
1337 int min_fck_per_pck;
1338 int match = 0;
1339 unsigned long dss_sys_clk, max_dss_fck;
1340
1341 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1342
1343 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1344
1345 if (req_pck == dsi->cache_req_pck &&
1346 dsi->cache_cinfo.clkin == dss_sys_clk) {
1347 DSSDBG("DSI clock info found from cache\n");
1348 *dsi_cinfo = dsi->cache_cinfo;
1349 dispc_find_clk_divs(is_tft, req_pck,
1350 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1351 return 0;
1352 }
1353
1354 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1355
1356 if (min_fck_per_pck &&
1357 req_pck * min_fck_per_pck > max_dss_fck) {
1358 DSSERR("Requested pixel clock not possible with the current "
1359 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1360 "the constraint off.\n");
1361 min_fck_per_pck = 0;
1362 }
1363
1364 DSSDBG("dsi_pll_calc\n");
1365
1366 retry:
1367 memset(&best, 0, sizeof(best));
1368 memset(&best_dispc, 0, sizeof(best_dispc));
1369
1370 memset(&cur, 0, sizeof(cur));
1371 cur.clkin = dss_sys_clk;
1372 cur.use_sys_clk = 1;
1373 cur.highfreq = 0;
1374
1375 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1376 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1377 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1378 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1379 if (cur.highfreq == 0)
1380 cur.fint = cur.clkin / cur.regn;
1381 else
1382 cur.fint = cur.clkin / (2 * cur.regn);
1383
1384 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1385 continue;
1386
1387 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1388 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1389 unsigned long a, b;
1390
1391 a = 2 * cur.regm * (cur.clkin/1000);
1392 b = cur.regn * (cur.highfreq + 1);
1393 cur.clkin4ddr = a / b * 1000;
1394
1395 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1396 break;
1397
1398 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1399 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1400 for (cur.regm_dispc = 1; cur.regm_dispc <
1401 dsi->regm_dispc_max; ++cur.regm_dispc) {
1402 struct dispc_clock_info cur_dispc;
1403 cur.dsi_pll_hsdiv_dispc_clk =
1404 cur.clkin4ddr / cur.regm_dispc;
1405
1406 /* this will narrow down the search a bit,
1407 * but still give pixclocks below what was
1408 * requested */
1409 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1410 break;
1411
1412 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1413 continue;
1414
1415 if (min_fck_per_pck &&
1416 cur.dsi_pll_hsdiv_dispc_clk <
1417 req_pck * min_fck_per_pck)
1418 continue;
1419
1420 match = 1;
1421
1422 dispc_find_clk_divs(is_tft, req_pck,
1423 cur.dsi_pll_hsdiv_dispc_clk,
1424 &cur_dispc);
1425
1426 if (abs(cur_dispc.pck - req_pck) <
1427 abs(best_dispc.pck - req_pck)) {
1428 best = cur;
1429 best_dispc = cur_dispc;
1430
1431 if (cur_dispc.pck == req_pck)
1432 goto found;
1433 }
1434 }
1435 }
1436 }
1437 found:
1438 if (!match) {
1439 if (min_fck_per_pck) {
1440 DSSERR("Could not find suitable clock settings.\n"
1441 "Turning FCK/PCK constraint off and"
1442 "trying again.\n");
1443 min_fck_per_pck = 0;
1444 goto retry;
1445 }
1446
1447 DSSERR("Could not find suitable clock settings.\n");
1448
1449 return -EINVAL;
1450 }
1451
1452 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1453 best.regm_dsi = 0;
1454 best.dsi_pll_hsdiv_dsi_clk = 0;
1455
1456 if (dsi_cinfo)
1457 *dsi_cinfo = best;
1458 if (dispc_cinfo)
1459 *dispc_cinfo = best_dispc;
1460
1461 dsi->cache_req_pck = req_pck;
1462 dsi->cache_clk_freq = 0;
1463 dsi->cache_cinfo = best;
1464
1465 return 0;
1466 }
1467
1468 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1469 struct dsi_clock_info *cinfo)
1470 {
1471 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1472 int r = 0;
1473 u32 l;
1474 int f = 0;
1475 u8 regn_start, regn_end, regm_start, regm_end;
1476 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1477
1478 DSSDBGF();
1479
1480 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1481 dsi->current_cinfo.highfreq = cinfo->highfreq;
1482
1483 dsi->current_cinfo.fint = cinfo->fint;
1484 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1485 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1486 cinfo->dsi_pll_hsdiv_dispc_clk;
1487 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1488 cinfo->dsi_pll_hsdiv_dsi_clk;
1489
1490 dsi->current_cinfo.regn = cinfo->regn;
1491 dsi->current_cinfo.regm = cinfo->regm;
1492 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1493 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1494
1495 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1496
1497 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1498 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1499 cinfo->clkin,
1500 cinfo->highfreq);
1501
1502 /* DSIPHY == CLKIN4DDR */
1503 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1504 cinfo->regm,
1505 cinfo->regn,
1506 cinfo->clkin,
1507 cinfo->highfreq + 1,
1508 cinfo->clkin4ddr);
1509
1510 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1511 cinfo->clkin4ddr / 1000 / 1000 / 2);
1512
1513 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1514
1515 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1516 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1517 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1518 cinfo->dsi_pll_hsdiv_dispc_clk);
1519 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1520 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1521 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1522 cinfo->dsi_pll_hsdiv_dsi_clk);
1523
1524 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1525 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1526 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1527 &regm_dispc_end);
1528 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1529 &regm_dsi_end);
1530
1531 /* DSI_PLL_AUTOMODE = manual */
1532 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1533
1534 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1535 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1536 /* DSI_PLL_REGN */
1537 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1538 /* DSI_PLL_REGM */
1539 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1540 /* DSI_CLOCK_DIV */
1541 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1542 regm_dispc_start, regm_dispc_end);
1543 /* DSIPROTO_CLOCK_DIV */
1544 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1545 regm_dsi_start, regm_dsi_end);
1546 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1547
1548 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1549
1550 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1551 f = cinfo->fint < 1000000 ? 0x3 :
1552 cinfo->fint < 1250000 ? 0x4 :
1553 cinfo->fint < 1500000 ? 0x5 :
1554 cinfo->fint < 1750000 ? 0x6 :
1555 0x7;
1556 }
1557
1558 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1559
1560 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1561 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1562 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1563 11, 11); /* DSI_PLL_CLKSEL */
1564 l = FLD_MOD(l, cinfo->highfreq,
1565 12, 12); /* DSI_PLL_HIGHFREQ */
1566 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1567 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1568 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1569 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1570
1571 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1572
1573 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1574 DSSERR("dsi pll go bit not going down.\n");
1575 r = -EIO;
1576 goto err;
1577 }
1578
1579 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1580 DSSERR("cannot lock PLL\n");
1581 r = -EIO;
1582 goto err;
1583 }
1584
1585 dsi->pll_locked = 1;
1586
1587 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1588 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1589 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1590 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1591 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1592 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1593 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1594 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1595 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1596 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1597 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1598 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1599 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1600 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1601 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1602 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1603
1604 DSSDBG("PLL config done\n");
1605 err:
1606 return r;
1607 }
1608
1609 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1610 bool enable_hsdiv)
1611 {
1612 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1613 int r = 0;
1614 enum dsi_pll_power_state pwstate;
1615
1616 DSSDBG("PLL init\n");
1617
1618 if (dsi->vdds_dsi_reg == NULL) {
1619 struct regulator *vdds_dsi;
1620
1621 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1622
1623 if (IS_ERR(vdds_dsi)) {
1624 DSSERR("can't get VDDS_DSI regulator\n");
1625 return PTR_ERR(vdds_dsi);
1626 }
1627
1628 dsi->vdds_dsi_reg = vdds_dsi;
1629 }
1630
1631 dsi_enable_pll_clock(dsidev, 1);
1632 /*
1633 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1634 */
1635 dsi_enable_scp_clk(dsidev);
1636
1637 if (!dsi->vdds_dsi_enabled) {
1638 r = regulator_enable(dsi->vdds_dsi_reg);
1639 if (r)
1640 goto err0;
1641 dsi->vdds_dsi_enabled = true;
1642 }
1643
1644 /* XXX PLL does not come out of reset without this... */
1645 dispc_pck_free_enable(1);
1646
1647 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1648 DSSERR("PLL not coming out of reset.\n");
1649 r = -ENODEV;
1650 dispc_pck_free_enable(0);
1651 goto err1;
1652 }
1653
1654 /* XXX ... but if left on, we get problems when planes do not
1655 * fill the whole display. No idea about this */
1656 dispc_pck_free_enable(0);
1657
1658 if (enable_hsclk && enable_hsdiv)
1659 pwstate = DSI_PLL_POWER_ON_ALL;
1660 else if (enable_hsclk)
1661 pwstate = DSI_PLL_POWER_ON_HSCLK;
1662 else if (enable_hsdiv)
1663 pwstate = DSI_PLL_POWER_ON_DIV;
1664 else
1665 pwstate = DSI_PLL_POWER_OFF;
1666
1667 r = dsi_pll_power(dsidev, pwstate);
1668
1669 if (r)
1670 goto err1;
1671
1672 DSSDBG("PLL init done\n");
1673
1674 return 0;
1675 err1:
1676 if (dsi->vdds_dsi_enabled) {
1677 regulator_disable(dsi->vdds_dsi_reg);
1678 dsi->vdds_dsi_enabled = false;
1679 }
1680 err0:
1681 dsi_disable_scp_clk(dsidev);
1682 dsi_enable_pll_clock(dsidev, 0);
1683 return r;
1684 }
1685
1686 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1687 {
1688 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1689
1690 dsi->pll_locked = 0;
1691 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1692 if (disconnect_lanes) {
1693 WARN_ON(!dsi->vdds_dsi_enabled);
1694 regulator_disable(dsi->vdds_dsi_reg);
1695 dsi->vdds_dsi_enabled = false;
1696 }
1697
1698 dsi_disable_scp_clk(dsidev);
1699 dsi_enable_pll_clock(dsidev, 0);
1700
1701 DSSDBG("PLL uninit done\n");
1702 }
1703
1704 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1705 struct seq_file *s)
1706 {
1707 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1708 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1709 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1710 int dsi_module = dsi_get_dsidev_id(dsidev);
1711
1712 dispc_clk_src = dss_get_dispc_clk_source();
1713 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1714
1715 if (dsi_runtime_get(dsidev))
1716 return;
1717
1718 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1719
1720 seq_printf(s, "dsi pll source = %s\n",
1721 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1722
1723 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1724
1725 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1726 cinfo->clkin4ddr, cinfo->regm);
1727
1728 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1729 dss_get_generic_clk_source_name(dispc_clk_src),
1730 dss_feat_get_clk_source_name(dispc_clk_src),
1731 cinfo->dsi_pll_hsdiv_dispc_clk,
1732 cinfo->regm_dispc,
1733 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1734 "off" : "on");
1735
1736 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1737 dss_get_generic_clk_source_name(dsi_clk_src),
1738 dss_feat_get_clk_source_name(dsi_clk_src),
1739 cinfo->dsi_pll_hsdiv_dsi_clk,
1740 cinfo->regm_dsi,
1741 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1742 "off" : "on");
1743
1744 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1745
1746 seq_printf(s, "dsi fclk source = %s (%s)\n",
1747 dss_get_generic_clk_source_name(dsi_clk_src),
1748 dss_feat_get_clk_source_name(dsi_clk_src));
1749
1750 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1751
1752 seq_printf(s, "DDR_CLK\t\t%lu\n",
1753 cinfo->clkin4ddr / 4);
1754
1755 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1756
1757 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1758
1759 dsi_runtime_put(dsidev);
1760 }
1761
1762 void dsi_dump_clocks(struct seq_file *s)
1763 {
1764 struct platform_device *dsidev;
1765 int i;
1766
1767 for (i = 0; i < MAX_NUM_DSI; i++) {
1768 dsidev = dsi_get_dsidev_from_id(i);
1769 if (dsidev)
1770 dsi_dump_dsidev_clocks(dsidev, s);
1771 }
1772 }
1773
1774 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1775 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1776 struct seq_file *s)
1777 {
1778 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1779 unsigned long flags;
1780 struct dsi_irq_stats stats;
1781 int dsi_module = dsi_get_dsidev_id(dsidev);
1782
1783 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1784
1785 stats = dsi->irq_stats;
1786 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1787 dsi->irq_stats.last_reset = jiffies;
1788
1789 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1790
1791 seq_printf(s, "period %u ms\n",
1792 jiffies_to_msecs(jiffies - stats.last_reset));
1793
1794 seq_printf(s, "irqs %d\n", stats.irq_count);
1795 #define PIS(x) \
1796 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1797
1798 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1799 PIS(VC0);
1800 PIS(VC1);
1801 PIS(VC2);
1802 PIS(VC3);
1803 PIS(WAKEUP);
1804 PIS(RESYNC);
1805 PIS(PLL_LOCK);
1806 PIS(PLL_UNLOCK);
1807 PIS(PLL_RECALL);
1808 PIS(COMPLEXIO_ERR);
1809 PIS(HS_TX_TIMEOUT);
1810 PIS(LP_RX_TIMEOUT);
1811 PIS(TE_TRIGGER);
1812 PIS(ACK_TRIGGER);
1813 PIS(SYNC_LOST);
1814 PIS(LDO_POWER_GOOD);
1815 PIS(TA_TIMEOUT);
1816 #undef PIS
1817
1818 #define PIS(x) \
1819 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1820 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1821 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1822 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1823 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1824
1825 seq_printf(s, "-- VC interrupts --\n");
1826 PIS(CS);
1827 PIS(ECC_CORR);
1828 PIS(PACKET_SENT);
1829 PIS(FIFO_TX_OVF);
1830 PIS(FIFO_RX_OVF);
1831 PIS(BTA);
1832 PIS(ECC_NO_CORR);
1833 PIS(FIFO_TX_UDF);
1834 PIS(PP_BUSY_CHANGE);
1835 #undef PIS
1836
1837 #define PIS(x) \
1838 seq_printf(s, "%-20s %10d\n", #x, \
1839 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1840
1841 seq_printf(s, "-- CIO interrupts --\n");
1842 PIS(ERRSYNCESC1);
1843 PIS(ERRSYNCESC2);
1844 PIS(ERRSYNCESC3);
1845 PIS(ERRESC1);
1846 PIS(ERRESC2);
1847 PIS(ERRESC3);
1848 PIS(ERRCONTROL1);
1849 PIS(ERRCONTROL2);
1850 PIS(ERRCONTROL3);
1851 PIS(STATEULPS1);
1852 PIS(STATEULPS2);
1853 PIS(STATEULPS3);
1854 PIS(ERRCONTENTIONLP0_1);
1855 PIS(ERRCONTENTIONLP1_1);
1856 PIS(ERRCONTENTIONLP0_2);
1857 PIS(ERRCONTENTIONLP1_2);
1858 PIS(ERRCONTENTIONLP0_3);
1859 PIS(ERRCONTENTIONLP1_3);
1860 PIS(ULPSACTIVENOT_ALL0);
1861 PIS(ULPSACTIVENOT_ALL1);
1862 #undef PIS
1863 }
1864
1865 static void dsi1_dump_irqs(struct seq_file *s)
1866 {
1867 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1868
1869 dsi_dump_dsidev_irqs(dsidev, s);
1870 }
1871
1872 static void dsi2_dump_irqs(struct seq_file *s)
1873 {
1874 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1875
1876 dsi_dump_dsidev_irqs(dsidev, s);
1877 }
1878
1879 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1880 const struct file_operations *debug_fops)
1881 {
1882 struct platform_device *dsidev;
1883
1884 dsidev = dsi_get_dsidev_from_id(0);
1885 if (dsidev)
1886 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1887 &dsi1_dump_irqs, debug_fops);
1888
1889 dsidev = dsi_get_dsidev_from_id(1);
1890 if (dsidev)
1891 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1892 &dsi2_dump_irqs, debug_fops);
1893 }
1894 #endif
1895
1896 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1897 struct seq_file *s)
1898 {
1899 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1900
1901 if (dsi_runtime_get(dsidev))
1902 return;
1903 dsi_enable_scp_clk(dsidev);
1904
1905 DUMPREG(DSI_REVISION);
1906 DUMPREG(DSI_SYSCONFIG);
1907 DUMPREG(DSI_SYSSTATUS);
1908 DUMPREG(DSI_IRQSTATUS);
1909 DUMPREG(DSI_IRQENABLE);
1910 DUMPREG(DSI_CTRL);
1911 DUMPREG(DSI_COMPLEXIO_CFG1);
1912 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1913 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1914 DUMPREG(DSI_CLK_CTRL);
1915 DUMPREG(DSI_TIMING1);
1916 DUMPREG(DSI_TIMING2);
1917 DUMPREG(DSI_VM_TIMING1);
1918 DUMPREG(DSI_VM_TIMING2);
1919 DUMPREG(DSI_VM_TIMING3);
1920 DUMPREG(DSI_CLK_TIMING);
1921 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1922 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1923 DUMPREG(DSI_COMPLEXIO_CFG2);
1924 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1925 DUMPREG(DSI_VM_TIMING4);
1926 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1927 DUMPREG(DSI_VM_TIMING5);
1928 DUMPREG(DSI_VM_TIMING6);
1929 DUMPREG(DSI_VM_TIMING7);
1930 DUMPREG(DSI_STOPCLK_TIMING);
1931
1932 DUMPREG(DSI_VC_CTRL(0));
1933 DUMPREG(DSI_VC_TE(0));
1934 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1935 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1936 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1937 DUMPREG(DSI_VC_IRQSTATUS(0));
1938 DUMPREG(DSI_VC_IRQENABLE(0));
1939
1940 DUMPREG(DSI_VC_CTRL(1));
1941 DUMPREG(DSI_VC_TE(1));
1942 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1943 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1944 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1945 DUMPREG(DSI_VC_IRQSTATUS(1));
1946 DUMPREG(DSI_VC_IRQENABLE(1));
1947
1948 DUMPREG(DSI_VC_CTRL(2));
1949 DUMPREG(DSI_VC_TE(2));
1950 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1951 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1952 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1953 DUMPREG(DSI_VC_IRQSTATUS(2));
1954 DUMPREG(DSI_VC_IRQENABLE(2));
1955
1956 DUMPREG(DSI_VC_CTRL(3));
1957 DUMPREG(DSI_VC_TE(3));
1958 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1959 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1960 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1961 DUMPREG(DSI_VC_IRQSTATUS(3));
1962 DUMPREG(DSI_VC_IRQENABLE(3));
1963
1964 DUMPREG(DSI_DSIPHY_CFG0);
1965 DUMPREG(DSI_DSIPHY_CFG1);
1966 DUMPREG(DSI_DSIPHY_CFG2);
1967 DUMPREG(DSI_DSIPHY_CFG5);
1968
1969 DUMPREG(DSI_PLL_CONTROL);
1970 DUMPREG(DSI_PLL_STATUS);
1971 DUMPREG(DSI_PLL_GO);
1972 DUMPREG(DSI_PLL_CONFIGURATION1);
1973 DUMPREG(DSI_PLL_CONFIGURATION2);
1974
1975 dsi_disable_scp_clk(dsidev);
1976 dsi_runtime_put(dsidev);
1977 #undef DUMPREG
1978 }
1979
1980 static void dsi1_dump_regs(struct seq_file *s)
1981 {
1982 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1983
1984 dsi_dump_dsidev_regs(dsidev, s);
1985 }
1986
1987 static void dsi2_dump_regs(struct seq_file *s)
1988 {
1989 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1990
1991 dsi_dump_dsidev_regs(dsidev, s);
1992 }
1993
1994 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1995 const struct file_operations *debug_fops)
1996 {
1997 struct platform_device *dsidev;
1998
1999 dsidev = dsi_get_dsidev_from_id(0);
2000 if (dsidev)
2001 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
2002 &dsi1_dump_regs, debug_fops);
2003
2004 dsidev = dsi_get_dsidev_from_id(1);
2005 if (dsidev)
2006 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
2007 &dsi2_dump_regs, debug_fops);
2008 }
2009 enum dsi_cio_power_state {
2010 DSI_COMPLEXIO_POWER_OFF = 0x0,
2011 DSI_COMPLEXIO_POWER_ON = 0x1,
2012 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2013 };
2014
2015 static int dsi_cio_power(struct platform_device *dsidev,
2016 enum dsi_cio_power_state state)
2017 {
2018 int t = 0;
2019
2020 /* PWR_CMD */
2021 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2022
2023 /* PWR_STATUS */
2024 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2025 26, 25) != state) {
2026 if (++t > 1000) {
2027 DSSERR("failed to set complexio power state to "
2028 "%d\n", state);
2029 return -ENODEV;
2030 }
2031 udelay(1);
2032 }
2033
2034 return 0;
2035 }
2036
2037 /* Number of lanes used by the dss device */
2038 static inline int dsi_get_num_lanes_used(struct omap_dss_device *dssdev)
2039 {
2040 int num_data_lanes = 0;
2041
2042 if (dssdev->phy.dsi.data1_lane != 0)
2043 num_data_lanes++;
2044 if (dssdev->phy.dsi.data2_lane != 0)
2045 num_data_lanes++;
2046 if (dssdev->phy.dsi.data3_lane != 0)
2047 num_data_lanes++;
2048 if (dssdev->phy.dsi.data4_lane != 0)
2049 num_data_lanes++;
2050
2051 return num_data_lanes + 1;
2052 }
2053
2054 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2055 {
2056 int val;
2057
2058 /* line buffer on OMAP3 is 1024 x 24bits */
2059 /* XXX: for some reason using full buffer size causes
2060 * considerable TX slowdown with update sizes that fill the
2061 * whole buffer */
2062 if (!dss_has_feature(FEAT_DSI_GNQ))
2063 return 1023 * 3;
2064
2065 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2066
2067 switch (val) {
2068 case 1:
2069 return 512 * 3; /* 512x24 bits */
2070 case 2:
2071 return 682 * 3; /* 682x24 bits */
2072 case 3:
2073 return 853 * 3; /* 853x24 bits */
2074 case 4:
2075 return 1024 * 3; /* 1024x24 bits */
2076 case 5:
2077 return 1194 * 3; /* 1194x24 bits */
2078 case 6:
2079 return 1365 * 3; /* 1365x24 bits */
2080 default:
2081 BUG();
2082 }
2083 }
2084
2085 static int dsi_parse_lane_config(struct omap_dss_device *dssdev)
2086 {
2087 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2088 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2089 u8 lanes[DSI_MAX_NR_LANES];
2090 u8 polarities[DSI_MAX_NR_LANES];
2091 int num_lanes, i;
2092
2093 static const enum dsi_lane_function functions[] = {
2094 DSI_LANE_CLK,
2095 DSI_LANE_DATA1,
2096 DSI_LANE_DATA2,
2097 DSI_LANE_DATA3,
2098 DSI_LANE_DATA4,
2099 };
2100
2101 lanes[0] = dssdev->phy.dsi.clk_lane;
2102 lanes[1] = dssdev->phy.dsi.data1_lane;
2103 lanes[2] = dssdev->phy.dsi.data2_lane;
2104 lanes[3] = dssdev->phy.dsi.data3_lane;
2105 lanes[4] = dssdev->phy.dsi.data4_lane;
2106 polarities[0] = dssdev->phy.dsi.clk_pol;
2107 polarities[1] = dssdev->phy.dsi.data1_pol;
2108 polarities[2] = dssdev->phy.dsi.data2_pol;
2109 polarities[3] = dssdev->phy.dsi.data3_pol;
2110 polarities[4] = dssdev->phy.dsi.data4_pol;
2111
2112 num_lanes = 0;
2113
2114 for (i = 0; i < dsi->num_lanes_supported; ++i)
2115 dsi->lanes[i].function = DSI_LANE_UNUSED;
2116
2117 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2118 int num;
2119
2120 if (lanes[i] == DSI_LANE_UNUSED)
2121 break;
2122
2123 num = lanes[i] - 1;
2124
2125 if (num >= dsi->num_lanes_supported)
2126 return -EINVAL;
2127
2128 if (dsi->lanes[num].function != DSI_LANE_UNUSED)
2129 return -EINVAL;
2130
2131 dsi->lanes[num].function = functions[i];
2132 dsi->lanes[num].polarity = polarities[i];
2133 num_lanes++;
2134 }
2135
2136 if (num_lanes < 2 || num_lanes > dsi->num_lanes_supported)
2137 return -EINVAL;
2138
2139 dsi->num_lanes_used = num_lanes;
2140
2141 return 0;
2142 }
2143
2144 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2145 {
2146 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2147 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2148 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2149 static const enum dsi_lane_function functions[] = {
2150 DSI_LANE_CLK,
2151 DSI_LANE_DATA1,
2152 DSI_LANE_DATA2,
2153 DSI_LANE_DATA3,
2154 DSI_LANE_DATA4,
2155 };
2156 u32 r;
2157 int i;
2158
2159 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2160
2161 for (i = 0; i < dsi->num_lanes_used; ++i) {
2162 unsigned offset = offsets[i];
2163 unsigned polarity, lane_number;
2164 unsigned t;
2165
2166 for (t = 0; t < dsi->num_lanes_supported; ++t)
2167 if (dsi->lanes[t].function == functions[i])
2168 break;
2169
2170 if (t == dsi->num_lanes_supported)
2171 return -EINVAL;
2172
2173 lane_number = t;
2174 polarity = dsi->lanes[t].polarity;
2175
2176 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2177 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2178 }
2179
2180 /* clear the unused lanes */
2181 for (; i < dsi->num_lanes_supported; ++i) {
2182 unsigned offset = offsets[i];
2183
2184 r = FLD_MOD(r, 0, offset + 2, offset);
2185 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2186 }
2187
2188 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2189
2190 return 0;
2191 }
2192
2193 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2194 {
2195 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2196
2197 /* convert time in ns to ddr ticks, rounding up */
2198 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2199 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2200 }
2201
2202 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2203 {
2204 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2205
2206 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2207 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2208 }
2209
2210 static void dsi_cio_timings(struct platform_device *dsidev)
2211 {
2212 u32 r;
2213 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2214 u32 tlpx_half, tclk_trail, tclk_zero;
2215 u32 tclk_prepare;
2216
2217 /* calculate timings */
2218
2219 /* 1 * DDR_CLK = 2 * UI */
2220
2221 /* min 40ns + 4*UI max 85ns + 6*UI */
2222 ths_prepare = ns2ddr(dsidev, 70) + 2;
2223
2224 /* min 145ns + 10*UI */
2225 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2226
2227 /* min max(8*UI, 60ns+4*UI) */
2228 ths_trail = ns2ddr(dsidev, 60) + 5;
2229
2230 /* min 100ns */
2231 ths_exit = ns2ddr(dsidev, 145);
2232
2233 /* tlpx min 50n */
2234 tlpx_half = ns2ddr(dsidev, 25);
2235
2236 /* min 60ns */
2237 tclk_trail = ns2ddr(dsidev, 60) + 2;
2238
2239 /* min 38ns, max 95ns */
2240 tclk_prepare = ns2ddr(dsidev, 65);
2241
2242 /* min tclk-prepare + tclk-zero = 300ns */
2243 tclk_zero = ns2ddr(dsidev, 260);
2244
2245 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2246 ths_prepare, ddr2ns(dsidev, ths_prepare),
2247 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2248 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2249 ths_trail, ddr2ns(dsidev, ths_trail),
2250 ths_exit, ddr2ns(dsidev, ths_exit));
2251
2252 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2253 "tclk_zero %u (%uns)\n",
2254 tlpx_half, ddr2ns(dsidev, tlpx_half),
2255 tclk_trail, ddr2ns(dsidev, tclk_trail),
2256 tclk_zero, ddr2ns(dsidev, tclk_zero));
2257 DSSDBG("tclk_prepare %u (%uns)\n",
2258 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2259
2260 /* program timings */
2261
2262 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2263 r = FLD_MOD(r, ths_prepare, 31, 24);
2264 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2265 r = FLD_MOD(r, ths_trail, 15, 8);
2266 r = FLD_MOD(r, ths_exit, 7, 0);
2267 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2268
2269 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2270 r = FLD_MOD(r, tlpx_half, 22, 16);
2271 r = FLD_MOD(r, tclk_trail, 15, 8);
2272 r = FLD_MOD(r, tclk_zero, 7, 0);
2273 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2274
2275 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2276 r = FLD_MOD(r, tclk_prepare, 7, 0);
2277 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2278 }
2279
2280 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2281 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2282 unsigned mask_p, unsigned mask_n)
2283 {
2284 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2285 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2286 int i;
2287 u32 l;
2288 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2289
2290 l = 0;
2291
2292 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2293 unsigned p = dsi->lanes[i].polarity;
2294
2295 if (mask_p & (1 << i))
2296 l |= 1 << (i * 2 + (p ? 0 : 1));
2297
2298 if (mask_n & (1 << i))
2299 l |= 1 << (i * 2 + (p ? 1 : 0));
2300 }
2301
2302 /*
2303 * Bits in REGLPTXSCPDAT4TO0DXDY:
2304 * 17: DY0 18: DX0
2305 * 19: DY1 20: DX1
2306 * 21: DY2 22: DX2
2307 * 23: DY3 24: DX3
2308 * 25: DY4 26: DX4
2309 */
2310
2311 /* Set the lane override configuration */
2312
2313 /* REGLPTXSCPDAT4TO0DXDY */
2314 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2315
2316 /* Enable lane override */
2317
2318 /* ENLPTXSCPDAT */
2319 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2320 }
2321
2322 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2323 {
2324 /* Disable lane override */
2325 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2326 /* Reset the lane override configuration */
2327 /* REGLPTXSCPDAT4TO0DXDY */
2328 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2329 }
2330
2331 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2332 {
2333 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2334 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2335 int t, i;
2336 bool in_use[DSI_MAX_NR_LANES];
2337 static const u8 offsets_old[] = { 28, 27, 26 };
2338 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2339 const u8 *offsets;
2340
2341 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2342 offsets = offsets_old;
2343 else
2344 offsets = offsets_new;
2345
2346 for (i = 0; i < dsi->num_lanes_supported; ++i)
2347 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2348
2349 t = 100000;
2350 while (true) {
2351 u32 l;
2352 int ok;
2353
2354 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2355
2356 ok = 0;
2357 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2358 if (!in_use[i] || (l & (1 << offsets[i])))
2359 ok++;
2360 }
2361
2362 if (ok == dsi->num_lanes_supported)
2363 break;
2364
2365 if (--t == 0) {
2366 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2367 if (!in_use[i] || (l & (1 << offsets[i])))
2368 continue;
2369
2370 DSSERR("CIO TXCLKESC%d domain not coming " \
2371 "out of reset\n", i);
2372 }
2373 return -EIO;
2374 }
2375 }
2376
2377 return 0;
2378 }
2379
2380 /* return bitmask of enabled lanes, lane0 being the lsb */
2381 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2382 {
2383 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2384 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2385 unsigned mask = 0;
2386 int i;
2387
2388 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2389 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2390 mask |= 1 << i;
2391 }
2392
2393 return mask;
2394 }
2395
2396 static int dsi_cio_init(struct omap_dss_device *dssdev)
2397 {
2398 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2399 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2400 int r;
2401 u32 l;
2402
2403 DSSDBGF();
2404
2405 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2406 if (r)
2407 return r;
2408
2409 dsi_enable_scp_clk(dsidev);
2410
2411 /* A dummy read using the SCP interface to any DSIPHY register is
2412 * required after DSIPHY reset to complete the reset of the DSI complex
2413 * I/O. */
2414 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2415
2416 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2417 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2418 r = -EIO;
2419 goto err_scp_clk_dom;
2420 }
2421
2422 r = dsi_set_lane_config(dssdev);
2423 if (r)
2424 goto err_scp_clk_dom;
2425
2426 /* set TX STOP MODE timer to maximum for this operation */
2427 l = dsi_read_reg(dsidev, DSI_TIMING1);
2428 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2429 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2430 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2431 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2432 dsi_write_reg(dsidev, DSI_TIMING1, l);
2433
2434 if (dsi->ulps_enabled) {
2435 unsigned mask_p;
2436 int i;
2437
2438 DSSDBG("manual ulps exit\n");
2439
2440 /* ULPS is exited by Mark-1 state for 1ms, followed by
2441 * stop state. DSS HW cannot do this via the normal
2442 * ULPS exit sequence, as after reset the DSS HW thinks
2443 * that we are not in ULPS mode, and refuses to send the
2444 * sequence. So we need to send the ULPS exit sequence
2445 * manually by setting positive lines high and negative lines
2446 * low for 1ms.
2447 */
2448
2449 mask_p = 0;
2450
2451 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2452 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2453 continue;
2454 mask_p |= 1 << i;
2455 }
2456
2457 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2458 }
2459
2460 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2461 if (r)
2462 goto err_cio_pwr;
2463
2464 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2465 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2466 r = -ENODEV;
2467 goto err_cio_pwr_dom;
2468 }
2469
2470 dsi_if_enable(dsidev, true);
2471 dsi_if_enable(dsidev, false);
2472 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2473
2474 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2475 if (r)
2476 goto err_tx_clk_esc_rst;
2477
2478 if (dsi->ulps_enabled) {
2479 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2480 ktime_t wait = ns_to_ktime(1000 * 1000);
2481 set_current_state(TASK_UNINTERRUPTIBLE);
2482 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2483
2484 /* Disable the override. The lanes should be set to Mark-11
2485 * state by the HW */
2486 dsi_cio_disable_lane_override(dsidev);
2487 }
2488
2489 /* FORCE_TX_STOP_MODE_IO */
2490 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2491
2492 dsi_cio_timings(dsidev);
2493
2494 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2495 /* DDR_CLK_ALWAYS_ON */
2496 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2497 dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2498 }
2499
2500 dsi->ulps_enabled = false;
2501
2502 DSSDBG("CIO init done\n");
2503
2504 return 0;
2505
2506 err_tx_clk_esc_rst:
2507 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2508 err_cio_pwr_dom:
2509 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2510 err_cio_pwr:
2511 if (dsi->ulps_enabled)
2512 dsi_cio_disable_lane_override(dsidev);
2513 err_scp_clk_dom:
2514 dsi_disable_scp_clk(dsidev);
2515 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2516 return r;
2517 }
2518
2519 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2520 {
2521 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2522 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2523
2524 /* DDR_CLK_ALWAYS_ON */
2525 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2526
2527 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2528 dsi_disable_scp_clk(dsidev);
2529 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2530 }
2531
2532 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2533 enum fifo_size size1, enum fifo_size size2,
2534 enum fifo_size size3, enum fifo_size size4)
2535 {
2536 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2537 u32 r = 0;
2538 int add = 0;
2539 int i;
2540
2541 dsi->vc[0].fifo_size = size1;
2542 dsi->vc[1].fifo_size = size2;
2543 dsi->vc[2].fifo_size = size3;
2544 dsi->vc[3].fifo_size = size4;
2545
2546 for (i = 0; i < 4; i++) {
2547 u8 v;
2548 int size = dsi->vc[i].fifo_size;
2549
2550 if (add + size > 4) {
2551 DSSERR("Illegal FIFO configuration\n");
2552 BUG();
2553 }
2554
2555 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2556 r |= v << (8 * i);
2557 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2558 add += size;
2559 }
2560
2561 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2562 }
2563
2564 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2565 enum fifo_size size1, enum fifo_size size2,
2566 enum fifo_size size3, enum fifo_size size4)
2567 {
2568 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2569 u32 r = 0;
2570 int add = 0;
2571 int i;
2572
2573 dsi->vc[0].fifo_size = size1;
2574 dsi->vc[1].fifo_size = size2;
2575 dsi->vc[2].fifo_size = size3;
2576 dsi->vc[3].fifo_size = size4;
2577
2578 for (i = 0; i < 4; i++) {
2579 u8 v;
2580 int size = dsi->vc[i].fifo_size;
2581
2582 if (add + size > 4) {
2583 DSSERR("Illegal FIFO configuration\n");
2584 BUG();
2585 }
2586
2587 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2588 r |= v << (8 * i);
2589 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2590 add += size;
2591 }
2592
2593 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2594 }
2595
2596 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2597 {
2598 u32 r;
2599
2600 r = dsi_read_reg(dsidev, DSI_TIMING1);
2601 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2602 dsi_write_reg(dsidev, DSI_TIMING1, r);
2603
2604 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2605 DSSERR("TX_STOP bit not going down\n");
2606 return -EIO;
2607 }
2608
2609 return 0;
2610 }
2611
2612 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2613 {
2614 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2615 }
2616
2617 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2618 {
2619 struct dsi_packet_sent_handler_data *vp_data =
2620 (struct dsi_packet_sent_handler_data *) data;
2621 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2622 const int channel = dsi->update_channel;
2623 u8 bit = dsi->te_enabled ? 30 : 31;
2624
2625 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2626 complete(vp_data->completion);
2627 }
2628
2629 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2630 {
2631 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2632 DECLARE_COMPLETION_ONSTACK(completion);
2633 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2634 int r = 0;
2635 u8 bit;
2636
2637 bit = dsi->te_enabled ? 30 : 31;
2638
2639 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2640 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2641 if (r)
2642 goto err0;
2643
2644 /* Wait for completion only if TE_EN/TE_START is still set */
2645 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2646 if (wait_for_completion_timeout(&completion,
2647 msecs_to_jiffies(10)) == 0) {
2648 DSSERR("Failed to complete previous frame transfer\n");
2649 r = -EIO;
2650 goto err1;
2651 }
2652 }
2653
2654 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2655 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2656
2657 return 0;
2658 err1:
2659 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2660 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2661 err0:
2662 return r;
2663 }
2664
2665 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2666 {
2667 struct dsi_packet_sent_handler_data *l4_data =
2668 (struct dsi_packet_sent_handler_data *) data;
2669 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2670 const int channel = dsi->update_channel;
2671
2672 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2673 complete(l4_data->completion);
2674 }
2675
2676 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2677 {
2678 DECLARE_COMPLETION_ONSTACK(completion);
2679 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2680 int r = 0;
2681
2682 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2683 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2684 if (r)
2685 goto err0;
2686
2687 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2688 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2689 if (wait_for_completion_timeout(&completion,
2690 msecs_to_jiffies(10)) == 0) {
2691 DSSERR("Failed to complete previous l4 transfer\n");
2692 r = -EIO;
2693 goto err1;
2694 }
2695 }
2696
2697 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2698 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2699
2700 return 0;
2701 err1:
2702 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2703 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2704 err0:
2705 return r;
2706 }
2707
2708 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2709 {
2710 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2711
2712 WARN_ON(!dsi_bus_is_locked(dsidev));
2713
2714 WARN_ON(in_interrupt());
2715
2716 if (!dsi_vc_is_enabled(dsidev, channel))
2717 return 0;
2718
2719 switch (dsi->vc[channel].source) {
2720 case DSI_VC_SOURCE_VP:
2721 return dsi_sync_vc_vp(dsidev, channel);
2722 case DSI_VC_SOURCE_L4:
2723 return dsi_sync_vc_l4(dsidev, channel);
2724 default:
2725 BUG();
2726 }
2727 }
2728
2729 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2730 bool enable)
2731 {
2732 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2733 channel, enable);
2734
2735 enable = enable ? 1 : 0;
2736
2737 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2738
2739 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2740 0, enable) != enable) {
2741 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2742 return -EIO;
2743 }
2744
2745 return 0;
2746 }
2747
2748 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2749 {
2750 u32 r;
2751
2752 DSSDBGF("%d", channel);
2753
2754 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2755
2756 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2757 DSSERR("VC(%d) busy when trying to configure it!\n",
2758 channel);
2759
2760 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2761 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2762 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2763 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2764 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2765 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2766 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2767 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2768 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2769
2770 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2771 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2772
2773 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2774 }
2775
2776 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2777 enum dsi_vc_source source)
2778 {
2779 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2780
2781 if (dsi->vc[channel].source == source)
2782 return 0;
2783
2784 DSSDBGF("%d", channel);
2785
2786 dsi_sync_vc(dsidev, channel);
2787
2788 dsi_vc_enable(dsidev, channel, 0);
2789
2790 /* VC_BUSY */
2791 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2792 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2793 return -EIO;
2794 }
2795
2796 /* SOURCE, 0 = L4, 1 = video port */
2797 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2798
2799 /* DCS_CMD_ENABLE */
2800 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2801 bool enable = source == DSI_VC_SOURCE_VP;
2802 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2803 }
2804
2805 dsi_vc_enable(dsidev, channel, 1);
2806
2807 dsi->vc[channel].source = source;
2808
2809 return 0;
2810 }
2811
2812 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2813 bool enable)
2814 {
2815 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2816
2817 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2818
2819 WARN_ON(!dsi_bus_is_locked(dsidev));
2820
2821 dsi_vc_enable(dsidev, channel, 0);
2822 dsi_if_enable(dsidev, 0);
2823
2824 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2825
2826 dsi_vc_enable(dsidev, channel, 1);
2827 dsi_if_enable(dsidev, 1);
2828
2829 dsi_force_tx_stop_mode_io(dsidev);
2830
2831 /* start the DDR clock by sending a NULL packet */
2832 if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2833 dsi_vc_send_null(dssdev, channel);
2834 }
2835 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2836
2837 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2838 {
2839 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2840 u32 val;
2841 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2842 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2843 (val >> 0) & 0xff,
2844 (val >> 8) & 0xff,
2845 (val >> 16) & 0xff,
2846 (val >> 24) & 0xff);
2847 }
2848 }
2849
2850 static void dsi_show_rx_ack_with_err(u16 err)
2851 {
2852 DSSERR("\tACK with ERROR (%#x):\n", err);
2853 if (err & (1 << 0))
2854 DSSERR("\t\tSoT Error\n");
2855 if (err & (1 << 1))
2856 DSSERR("\t\tSoT Sync Error\n");
2857 if (err & (1 << 2))
2858 DSSERR("\t\tEoT Sync Error\n");
2859 if (err & (1 << 3))
2860 DSSERR("\t\tEscape Mode Entry Command Error\n");
2861 if (err & (1 << 4))
2862 DSSERR("\t\tLP Transmit Sync Error\n");
2863 if (err & (1 << 5))
2864 DSSERR("\t\tHS Receive Timeout Error\n");
2865 if (err & (1 << 6))
2866 DSSERR("\t\tFalse Control Error\n");
2867 if (err & (1 << 7))
2868 DSSERR("\t\t(reserved7)\n");
2869 if (err & (1 << 8))
2870 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2871 if (err & (1 << 9))
2872 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2873 if (err & (1 << 10))
2874 DSSERR("\t\tChecksum Error\n");
2875 if (err & (1 << 11))
2876 DSSERR("\t\tData type not recognized\n");
2877 if (err & (1 << 12))
2878 DSSERR("\t\tInvalid VC ID\n");
2879 if (err & (1 << 13))
2880 DSSERR("\t\tInvalid Transmission Length\n");
2881 if (err & (1 << 14))
2882 DSSERR("\t\t(reserved14)\n");
2883 if (err & (1 << 15))
2884 DSSERR("\t\tDSI Protocol Violation\n");
2885 }
2886
2887 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2888 int channel)
2889 {
2890 /* RX_FIFO_NOT_EMPTY */
2891 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2892 u32 val;
2893 u8 dt;
2894 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2895 DSSERR("\trawval %#08x\n", val);
2896 dt = FLD_GET(val, 5, 0);
2897 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2898 u16 err = FLD_GET(val, 23, 8);
2899 dsi_show_rx_ack_with_err(err);
2900 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2901 DSSERR("\tDCS short response, 1 byte: %#x\n",
2902 FLD_GET(val, 23, 8));
2903 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2904 DSSERR("\tDCS short response, 2 byte: %#x\n",
2905 FLD_GET(val, 23, 8));
2906 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2907 DSSERR("\tDCS long response, len %d\n",
2908 FLD_GET(val, 23, 8));
2909 dsi_vc_flush_long_data(dsidev, channel);
2910 } else {
2911 DSSERR("\tunknown datatype 0x%02x\n", dt);
2912 }
2913 }
2914 return 0;
2915 }
2916
2917 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2918 {
2919 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2920
2921 if (dsi->debug_write || dsi->debug_read)
2922 DSSDBG("dsi_vc_send_bta %d\n", channel);
2923
2924 WARN_ON(!dsi_bus_is_locked(dsidev));
2925
2926 /* RX_FIFO_NOT_EMPTY */
2927 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2928 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2929 dsi_vc_flush_receive_data(dsidev, channel);
2930 }
2931
2932 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2933
2934 /* flush posted write */
2935 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2936
2937 return 0;
2938 }
2939
2940 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2941 {
2942 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2943 DECLARE_COMPLETION_ONSTACK(completion);
2944 int r = 0;
2945 u32 err;
2946
2947 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2948 &completion, DSI_VC_IRQ_BTA);
2949 if (r)
2950 goto err0;
2951
2952 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2953 DSI_IRQ_ERROR_MASK);
2954 if (r)
2955 goto err1;
2956
2957 r = dsi_vc_send_bta(dsidev, channel);
2958 if (r)
2959 goto err2;
2960
2961 if (wait_for_completion_timeout(&completion,
2962 msecs_to_jiffies(500)) == 0) {
2963 DSSERR("Failed to receive BTA\n");
2964 r = -EIO;
2965 goto err2;
2966 }
2967
2968 err = dsi_get_errors(dsidev);
2969 if (err) {
2970 DSSERR("Error while sending BTA: %x\n", err);
2971 r = -EIO;
2972 goto err2;
2973 }
2974 err2:
2975 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2976 DSI_IRQ_ERROR_MASK);
2977 err1:
2978 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2979 &completion, DSI_VC_IRQ_BTA);
2980 err0:
2981 return r;
2982 }
2983 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2984
2985 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2986 int channel, u8 data_type, u16 len, u8 ecc)
2987 {
2988 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2989 u32 val;
2990 u8 data_id;
2991
2992 WARN_ON(!dsi_bus_is_locked(dsidev));
2993
2994 data_id = data_type | dsi->vc[channel].vc_id << 6;
2995
2996 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2997 FLD_VAL(ecc, 31, 24);
2998
2999 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
3000 }
3001
3002 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
3003 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
3004 {
3005 u32 val;
3006
3007 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
3008
3009 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
3010 b1, b2, b3, b4, val); */
3011
3012 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
3013 }
3014
3015 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
3016 u8 data_type, u8 *data, u16 len, u8 ecc)
3017 {
3018 /*u32 val; */
3019 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3020 int i;
3021 u8 *p;
3022 int r = 0;
3023 u8 b1, b2, b3, b4;
3024
3025 if (dsi->debug_write)
3026 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
3027
3028 /* len + header */
3029 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
3030 DSSERR("unable to send long packet: packet too long.\n");
3031 return -EINVAL;
3032 }
3033
3034 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3035
3036 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3037
3038 p = data;
3039 for (i = 0; i < len >> 2; i++) {
3040 if (dsi->debug_write)
3041 DSSDBG("\tsending full packet %d\n", i);
3042
3043 b1 = *p++;
3044 b2 = *p++;
3045 b3 = *p++;
3046 b4 = *p++;
3047
3048 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3049 }
3050
3051 i = len % 4;
3052 if (i) {
3053 b1 = 0; b2 = 0; b3 = 0;
3054
3055 if (dsi->debug_write)
3056 DSSDBG("\tsending remainder bytes %d\n", i);
3057
3058 switch (i) {
3059 case 3:
3060 b1 = *p++;
3061 b2 = *p++;
3062 b3 = *p++;
3063 break;
3064 case 2:
3065 b1 = *p++;
3066 b2 = *p++;
3067 break;
3068 case 1:
3069 b1 = *p++;
3070 break;
3071 }
3072
3073 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3074 }
3075
3076 return r;
3077 }
3078
3079 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3080 u8 data_type, u16 data, u8 ecc)
3081 {
3082 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3083 u32 r;
3084 u8 data_id;
3085
3086 WARN_ON(!dsi_bus_is_locked(dsidev));
3087
3088 if (dsi->debug_write)
3089 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3090 channel,
3091 data_type, data & 0xff, (data >> 8) & 0xff);
3092
3093 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3094
3095 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3096 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3097 return -EINVAL;
3098 }
3099
3100 data_id = data_type | dsi->vc[channel].vc_id << 6;
3101
3102 r = (data_id << 0) | (data << 8) | (ecc << 24);
3103
3104 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3105
3106 return 0;
3107 }
3108
3109 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3110 {
3111 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3112
3113 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3114 0, 0);
3115 }
3116 EXPORT_SYMBOL(dsi_vc_send_null);
3117
3118 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3119 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3120 {
3121 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3122 int r;
3123
3124 if (len == 0) {
3125 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3126 r = dsi_vc_send_short(dsidev, channel,
3127 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3128 } else if (len == 1) {
3129 r = dsi_vc_send_short(dsidev, channel,
3130 type == DSS_DSI_CONTENT_GENERIC ?
3131 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3132 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3133 } else if (len == 2) {
3134 r = dsi_vc_send_short(dsidev, channel,
3135 type == DSS_DSI_CONTENT_GENERIC ?
3136 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3137 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3138 data[0] | (data[1] << 8), 0);
3139 } else {
3140 r = dsi_vc_send_long(dsidev, channel,
3141 type == DSS_DSI_CONTENT_GENERIC ?
3142 MIPI_DSI_GENERIC_LONG_WRITE :
3143 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3144 }
3145
3146 return r;
3147 }
3148
3149 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3150 u8 *data, int len)
3151 {
3152 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3153 DSS_DSI_CONTENT_DCS);
3154 }
3155 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3156
3157 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3158 u8 *data, int len)
3159 {
3160 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3161 DSS_DSI_CONTENT_GENERIC);
3162 }
3163 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3164
3165 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3166 u8 *data, int len, enum dss_dsi_content_type type)
3167 {
3168 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3169 int r;
3170
3171 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3172 if (r)
3173 goto err;
3174
3175 r = dsi_vc_send_bta_sync(dssdev, channel);
3176 if (r)
3177 goto err;
3178
3179 /* RX_FIFO_NOT_EMPTY */
3180 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3181 DSSERR("rx fifo not empty after write, dumping data:\n");
3182 dsi_vc_flush_receive_data(dsidev, channel);
3183 r = -EIO;
3184 goto err;
3185 }
3186
3187 return 0;
3188 err:
3189 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3190 channel, data[0], len);
3191 return r;
3192 }
3193
3194 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3195 int len)
3196 {
3197 return dsi_vc_write_common(dssdev, channel, data, len,
3198 DSS_DSI_CONTENT_DCS);
3199 }
3200 EXPORT_SYMBOL(dsi_vc_dcs_write);
3201
3202 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3203 int len)
3204 {
3205 return dsi_vc_write_common(dssdev, channel, data, len,
3206 DSS_DSI_CONTENT_GENERIC);
3207 }
3208 EXPORT_SYMBOL(dsi_vc_generic_write);
3209
3210 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3211 {
3212 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3213 }
3214 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3215
3216 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3217 {
3218 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3219 }
3220 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3221
3222 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3223 u8 param)
3224 {
3225 u8 buf[2];
3226 buf[0] = dcs_cmd;
3227 buf[1] = param;
3228 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3229 }
3230 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3231
3232 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3233 u8 param)
3234 {
3235 return dsi_vc_generic_write(dssdev, channel, &param, 1);
3236 }
3237 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3238
3239 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3240 u8 param1, u8 param2)
3241 {
3242 u8 buf[2];
3243 buf[0] = param1;
3244 buf[1] = param2;
3245 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3246 }
3247 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3248
3249 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3250 int channel, u8 dcs_cmd)
3251 {
3252 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3253 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3254 int r;
3255
3256 if (dsi->debug_read)
3257 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3258 channel, dcs_cmd);
3259
3260 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3261 if (r) {
3262 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3263 " failed\n", channel, dcs_cmd);
3264 return r;
3265 }
3266
3267 return 0;
3268 }
3269
3270 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3271 int channel, u8 *reqdata, int reqlen)
3272 {
3273 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3274 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3275 u16 data;
3276 u8 data_type;
3277 int r;
3278
3279 if (dsi->debug_read)
3280 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3281 channel, reqlen);
3282
3283 if (reqlen == 0) {
3284 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3285 data = 0;
3286 } else if (reqlen == 1) {
3287 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3288 data = reqdata[0];
3289 } else if (reqlen == 2) {
3290 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3291 data = reqdata[0] | (reqdata[1] << 8);
3292 } else {
3293 BUG();
3294 }
3295
3296 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3297 if (r) {
3298 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3299 " failed\n", channel, reqlen);
3300 return r;
3301 }
3302
3303 return 0;
3304 }
3305
3306 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3307 u8 *buf, int buflen, enum dss_dsi_content_type type)
3308 {
3309 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3310 u32 val;
3311 u8 dt;
3312 int r;
3313
3314 /* RX_FIFO_NOT_EMPTY */
3315 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3316 DSSERR("RX fifo empty when trying to read.\n");
3317 r = -EIO;
3318 goto err;
3319 }
3320
3321 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3322 if (dsi->debug_read)
3323 DSSDBG("\theader: %08x\n", val);
3324 dt = FLD_GET(val, 5, 0);
3325 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3326 u16 err = FLD_GET(val, 23, 8);
3327 dsi_show_rx_ack_with_err(err);
3328 r = -EIO;
3329 goto err;
3330
3331 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3332 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3333 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3334 u8 data = FLD_GET(val, 15, 8);
3335 if (dsi->debug_read)
3336 DSSDBG("\t%s short response, 1 byte: %02x\n",
3337 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3338 "DCS", data);
3339
3340 if (buflen < 1) {
3341 r = -EIO;
3342 goto err;
3343 }
3344
3345 buf[0] = data;
3346
3347 return 1;
3348 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3349 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3350 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3351 u16 data = FLD_GET(val, 23, 8);
3352 if (dsi->debug_read)
3353 DSSDBG("\t%s short response, 2 byte: %04x\n",
3354 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3355 "DCS", data);
3356
3357 if (buflen < 2) {
3358 r = -EIO;
3359 goto err;
3360 }
3361
3362 buf[0] = data & 0xff;
3363 buf[1] = (data >> 8) & 0xff;
3364
3365 return 2;
3366 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3367 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3368 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3369 int w;
3370 int len = FLD_GET(val, 23, 8);
3371 if (dsi->debug_read)
3372 DSSDBG("\t%s long response, len %d\n",
3373 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3374 "DCS", len);
3375
3376 if (len > buflen) {
3377 r = -EIO;
3378 goto err;
3379 }
3380
3381 /* two byte checksum ends the packet, not included in len */
3382 for (w = 0; w < len + 2;) {
3383 int b;
3384 val = dsi_read_reg(dsidev,
3385 DSI_VC_SHORT_PACKET_HEADER(channel));
3386 if (dsi->debug_read)
3387 DSSDBG("\t\t%02x %02x %02x %02x\n",
3388 (val >> 0) & 0xff,
3389 (val >> 8) & 0xff,
3390 (val >> 16) & 0xff,
3391 (val >> 24) & 0xff);
3392
3393 for (b = 0; b < 4; ++b) {
3394 if (w < len)
3395 buf[w] = (val >> (b * 8)) & 0xff;
3396 /* we discard the 2 byte checksum */
3397 ++w;
3398 }
3399 }
3400
3401 return len;
3402 } else {
3403 DSSERR("\tunknown datatype 0x%02x\n", dt);
3404 r = -EIO;
3405 goto err;
3406 }
3407
3408 BUG();
3409 err:
3410 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3411 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3412
3413 return r;
3414 }
3415
3416 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3417 u8 *buf, int buflen)
3418 {
3419 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3420 int r;
3421
3422 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3423 if (r)
3424 goto err;
3425
3426 r = dsi_vc_send_bta_sync(dssdev, channel);
3427 if (r)
3428 goto err;
3429
3430 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3431 DSS_DSI_CONTENT_DCS);
3432 if (r < 0)
3433 goto err;
3434
3435 if (r != buflen) {
3436 r = -EIO;
3437 goto err;
3438 }
3439
3440 return 0;
3441 err:
3442 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3443 return r;
3444 }
3445 EXPORT_SYMBOL(dsi_vc_dcs_read);
3446
3447 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3448 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3449 {
3450 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3451 int r;
3452
3453 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3454 if (r)
3455 return r;
3456
3457 r = dsi_vc_send_bta_sync(dssdev, channel);
3458 if (r)
3459 return r;
3460
3461 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3462 DSS_DSI_CONTENT_GENERIC);
3463 if (r < 0)
3464 return r;
3465
3466 if (r != buflen) {
3467 r = -EIO;
3468 return r;
3469 }
3470
3471 return 0;
3472 }
3473
3474 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3475 int buflen)
3476 {
3477 int r;
3478
3479 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3480 if (r) {
3481 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3482 return r;
3483 }
3484
3485 return 0;
3486 }
3487 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3488
3489 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3490 u8 *buf, int buflen)
3491 {
3492 int r;
3493
3494 r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3495 if (r) {
3496 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3497 return r;
3498 }
3499
3500 return 0;
3501 }
3502 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3503
3504 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3505 u8 param1, u8 param2, u8 *buf, int buflen)
3506 {
3507 int r;
3508 u8 reqdata[2];
3509
3510 reqdata[0] = param1;
3511 reqdata[1] = param2;
3512
3513 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3514 if (r) {
3515 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3516 return r;
3517 }
3518
3519 return 0;
3520 }
3521 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3522
3523 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3524 u16 len)
3525 {
3526 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3527
3528 return dsi_vc_send_short(dsidev, channel,
3529 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3530 }
3531 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3532
3533 static int dsi_enter_ulps(struct platform_device *dsidev)
3534 {
3535 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3536 DECLARE_COMPLETION_ONSTACK(completion);
3537 int r;
3538
3539 DSSDBGF();
3540
3541 WARN_ON(!dsi_bus_is_locked(dsidev));
3542
3543 WARN_ON(dsi->ulps_enabled);
3544
3545 if (dsi->ulps_enabled)
3546 return 0;
3547
3548 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3549 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3550 return -EIO;
3551 }
3552
3553 dsi_sync_vc(dsidev, 0);
3554 dsi_sync_vc(dsidev, 1);
3555 dsi_sync_vc(dsidev, 2);
3556 dsi_sync_vc(dsidev, 3);
3557
3558 dsi_force_tx_stop_mode_io(dsidev);
3559
3560 dsi_vc_enable(dsidev, 0, false);
3561 dsi_vc_enable(dsidev, 1, false);
3562 dsi_vc_enable(dsidev, 2, false);
3563 dsi_vc_enable(dsidev, 3, false);
3564
3565 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3566 DSSERR("HS busy when enabling ULPS\n");
3567 return -EIO;
3568 }
3569
3570 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3571 DSSERR("LP busy when enabling ULPS\n");
3572 return -EIO;
3573 }
3574
3575 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3576 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3577 if (r)
3578 return r;
3579
3580 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3581 /* LANEx_ULPS_SIG2 */
3582 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3583 7, 5);
3584
3585 /* flush posted write and wait for SCP interface to finish the write */
3586 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3587
3588 if (wait_for_completion_timeout(&completion,
3589 msecs_to_jiffies(1000)) == 0) {
3590 DSSERR("ULPS enable timeout\n");
3591 r = -EIO;
3592 goto err;
3593 }
3594
3595 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3596 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3597
3598 /* Reset LANEx_ULPS_SIG2 */
3599 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3600 7, 5);
3601
3602 /* flush posted write and wait for SCP interface to finish the write */
3603 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3604
3605 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3606
3607 dsi_if_enable(dsidev, false);
3608
3609 dsi->ulps_enabled = true;
3610
3611 return 0;
3612
3613 err:
3614 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3615 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3616 return r;
3617 }
3618
3619 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3620 unsigned ticks, bool x4, bool x16)
3621 {
3622 unsigned long fck;
3623 unsigned long total_ticks;
3624 u32 r;
3625
3626 BUG_ON(ticks > 0x1fff);
3627
3628 /* ticks in DSI_FCK */
3629 fck = dsi_fclk_rate(dsidev);
3630
3631 r = dsi_read_reg(dsidev, DSI_TIMING2);
3632 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3633 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3634 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3635 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3636 dsi_write_reg(dsidev, DSI_TIMING2, r);
3637
3638 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3639
3640 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3641 total_ticks,
3642 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3643 (total_ticks * 1000) / (fck / 1000 / 1000));
3644 }
3645
3646 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3647 bool x8, bool x16)
3648 {
3649 unsigned long fck;
3650 unsigned long total_ticks;
3651 u32 r;
3652
3653 BUG_ON(ticks > 0x1fff);
3654
3655 /* ticks in DSI_FCK */
3656 fck = dsi_fclk_rate(dsidev);
3657
3658 r = dsi_read_reg(dsidev, DSI_TIMING1);
3659 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3660 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3661 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3662 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3663 dsi_write_reg(dsidev, DSI_TIMING1, r);
3664
3665 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3666
3667 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3668 total_ticks,
3669 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3670 (total_ticks * 1000) / (fck / 1000 / 1000));
3671 }
3672
3673 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3674 unsigned ticks, bool x4, bool x16)
3675 {
3676 unsigned long fck;
3677 unsigned long total_ticks;
3678 u32 r;
3679
3680 BUG_ON(ticks > 0x1fff);
3681
3682 /* ticks in DSI_FCK */
3683 fck = dsi_fclk_rate(dsidev);
3684
3685 r = dsi_read_reg(dsidev, DSI_TIMING1);
3686 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3687 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3688 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3689 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3690 dsi_write_reg(dsidev, DSI_TIMING1, r);
3691
3692 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3693
3694 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3695 total_ticks,
3696 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3697 (total_ticks * 1000) / (fck / 1000 / 1000));
3698 }
3699
3700 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3701 unsigned ticks, bool x4, bool x16)
3702 {
3703 unsigned long fck;
3704 unsigned long total_ticks;
3705 u32 r;
3706
3707 BUG_ON(ticks > 0x1fff);
3708
3709 /* ticks in TxByteClkHS */
3710 fck = dsi_get_txbyteclkhs(dsidev);
3711
3712 r = dsi_read_reg(dsidev, DSI_TIMING2);
3713 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3714 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3715 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3716 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3717 dsi_write_reg(dsidev, DSI_TIMING2, r);
3718
3719 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3720
3721 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3722 total_ticks,
3723 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3724 (total_ticks * 1000) / (fck / 1000 / 1000));
3725 }
3726
3727 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3728 {
3729 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3730 int num_line_buffers;
3731
3732 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3733 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3734 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3735 struct omap_video_timings *timings = &dssdev->panel.timings;
3736 /*
3737 * Don't use line buffers if width is greater than the video
3738 * port's line buffer size
3739 */
3740 if (line_buf_size <= timings->x_res * bpp / 8)
3741 num_line_buffers = 0;
3742 else
3743 num_line_buffers = 2;
3744 } else {
3745 /* Use maximum number of line buffers in command mode */
3746 num_line_buffers = 2;
3747 }
3748
3749 /* LINE_BUFFER */
3750 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3751 }
3752
3753 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3754 {
3755 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3756 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3757 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3758 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3759 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3760 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3761 u32 r;
3762
3763 r = dsi_read_reg(dsidev, DSI_CTRL);
3764 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
3765 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
3766 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
3767 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3768 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3769 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3770 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3771 dsi_write_reg(dsidev, DSI_CTRL, r);
3772 }
3773
3774 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3775 {
3776 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3777 int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3778 int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3779 int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3780 int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3781 u32 r;
3782
3783 /*
3784 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3785 * 1 = Long blanking packets are sent in corresponding blanking periods
3786 */
3787 r = dsi_read_reg(dsidev, DSI_CTRL);
3788 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3789 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3790 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3791 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3792 dsi_write_reg(dsidev, DSI_CTRL, r);
3793 }
3794
3795 static int dsi_proto_config(struct omap_dss_device *dssdev)
3796 {
3797 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3798 u32 r;
3799 int buswidth = 0;
3800
3801 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3802 DSI_FIFO_SIZE_32,
3803 DSI_FIFO_SIZE_32,
3804 DSI_FIFO_SIZE_32);
3805
3806 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3807 DSI_FIFO_SIZE_32,
3808 DSI_FIFO_SIZE_32,
3809 DSI_FIFO_SIZE_32);
3810
3811 /* XXX what values for the timeouts? */
3812 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3813 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3814 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3815 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3816
3817 switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3818 case 16:
3819 buswidth = 0;
3820 break;
3821 case 18:
3822 buswidth = 1;
3823 break;
3824 case 24:
3825 buswidth = 2;
3826 break;
3827 default:
3828 BUG();
3829 }
3830
3831 r = dsi_read_reg(dsidev, DSI_CTRL);
3832 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3833 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3834 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3835 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3836 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3837 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3838 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3839 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3840 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3841 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3842 /* DCS_CMD_CODE, 1=start, 0=continue */
3843 r = FLD_MOD(r, 0, 25, 25);
3844 }
3845
3846 dsi_write_reg(dsidev, DSI_CTRL, r);
3847
3848 dsi_config_vp_num_line_buffers(dssdev);
3849
3850 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3851 dsi_config_vp_sync_events(dssdev);
3852 dsi_config_blanking_modes(dssdev);
3853 }
3854
3855 dsi_vc_initial_config(dsidev, 0);
3856 dsi_vc_initial_config(dsidev, 1);
3857 dsi_vc_initial_config(dsidev, 2);
3858 dsi_vc_initial_config(dsidev, 3);
3859
3860 return 0;
3861 }
3862
3863 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3864 {
3865 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3866 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3867 unsigned tclk_pre, tclk_post;
3868 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3869 unsigned ths_trail, ths_exit;
3870 unsigned ddr_clk_pre, ddr_clk_post;
3871 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3872 unsigned ths_eot;
3873 int ndl = dsi_get_num_lanes_used(dssdev) - 1;
3874 u32 r;
3875
3876 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3877 ths_prepare = FLD_GET(r, 31, 24);
3878 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3879 ths_zero = ths_prepare_ths_zero - ths_prepare;
3880 ths_trail = FLD_GET(r, 15, 8);
3881 ths_exit = FLD_GET(r, 7, 0);
3882
3883 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3884 tlpx = FLD_GET(r, 22, 16) * 2;
3885 tclk_trail = FLD_GET(r, 15, 8);
3886 tclk_zero = FLD_GET(r, 7, 0);
3887
3888 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3889 tclk_prepare = FLD_GET(r, 7, 0);
3890
3891 /* min 8*UI */
3892 tclk_pre = 20;
3893 /* min 60ns + 52*UI */
3894 tclk_post = ns2ddr(dsidev, 60) + 26;
3895
3896 ths_eot = DIV_ROUND_UP(4, ndl);
3897
3898 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3899 4);
3900 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3901
3902 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3903 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3904
3905 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3906 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3907 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3908 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3909
3910 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3911 ddr_clk_pre,
3912 ddr_clk_post);
3913
3914 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3915 DIV_ROUND_UP(ths_prepare, 4) +
3916 DIV_ROUND_UP(ths_zero + 3, 4);
3917
3918 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3919
3920 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3921 FLD_VAL(exit_hs_mode_lat, 15, 0);
3922 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3923
3924 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3925 enter_hs_mode_lat, exit_hs_mode_lat);
3926
3927 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3928 /* TODO: Implement a video mode check_timings function */
3929 int hsa = dssdev->panel.dsi_vm_data.hsa;
3930 int hfp = dssdev->panel.dsi_vm_data.hfp;
3931 int hbp = dssdev->panel.dsi_vm_data.hbp;
3932 int vsa = dssdev->panel.dsi_vm_data.vsa;
3933 int vfp = dssdev->panel.dsi_vm_data.vfp;
3934 int vbp = dssdev->panel.dsi_vm_data.vbp;
3935 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3936 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3937 struct omap_video_timings *timings = &dssdev->panel.timings;
3938 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3939 int tl, t_he, width_bytes;
3940
3941 t_he = hsync_end ?
3942 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3943
3944 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3945
3946 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3947 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3948 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3949
3950 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3951 hfp, hsync_end ? hsa : 0, tl);
3952 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3953 vsa, timings->y_res);
3954
3955 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3956 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3957 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3958 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3959 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3960
3961 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3962 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3963 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3964 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3965 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3966 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3967
3968 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3969 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3970 r = FLD_MOD(r, tl, 31, 16); /* TL */
3971 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3972 }
3973 }
3974
3975 int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
3976 {
3977 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3978 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3979 u8 data_type;
3980 u16 word_count;
3981
3982 switch (dssdev->panel.dsi_pix_fmt) {
3983 case OMAP_DSS_DSI_FMT_RGB888:
3984 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3985 break;
3986 case OMAP_DSS_DSI_FMT_RGB666:
3987 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3988 break;
3989 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3990 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3991 break;
3992 case OMAP_DSS_DSI_FMT_RGB565:
3993 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3994 break;
3995 default:
3996 BUG();
3997 };
3998
3999 dsi_if_enable(dsidev, false);
4000 dsi_vc_enable(dsidev, channel, false);
4001
4002 /* MODE, 1 = video mode */
4003 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4004
4005 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
4006
4007 dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);
4008
4009 dsi_vc_enable(dsidev, channel, true);
4010 dsi_if_enable(dsidev, true);
4011
4012 dssdev->manager->enable(dssdev->manager);
4013
4014 return 0;
4015 }
4016 EXPORT_SYMBOL(dsi_video_mode_enable);
4017
4018 void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
4019 {
4020 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4021
4022 dsi_if_enable(dsidev, false);
4023 dsi_vc_enable(dsidev, channel, false);
4024
4025 /* MODE, 0 = command mode */
4026 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4027
4028 dsi_vc_enable(dsidev, channel, true);
4029 dsi_if_enable(dsidev, true);
4030
4031 dssdev->manager->disable(dssdev->manager);
4032 }
4033 EXPORT_SYMBOL(dsi_video_mode_disable);
4034
4035 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4036 u16 x, u16 y, u16 w, u16 h)
4037 {
4038 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4039 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4040 unsigned bytespp;
4041 unsigned bytespl;
4042 unsigned bytespf;
4043 unsigned total_len;
4044 unsigned packet_payload;
4045 unsigned packet_len;
4046 u32 l;
4047 int r;
4048 const unsigned channel = dsi->update_channel;
4049 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4050
4051 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
4052 x, y, w, h);
4053
4054 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4055
4056 bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4057 bytespl = w * bytespp;
4058 bytespf = bytespl * h;
4059
4060 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4061 * number of lines in a packet. See errata about VP_CLK_RATIO */
4062
4063 if (bytespf < line_buf_size)
4064 packet_payload = bytespf;
4065 else
4066 packet_payload = (line_buf_size) / bytespl * bytespl;
4067
4068 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4069 total_len = (bytespf / packet_payload) * packet_len;
4070
4071 if (bytespf % packet_payload)
4072 total_len += (bytespf % packet_payload) + 1;
4073
4074 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4075 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4076
4077 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4078 packet_len, 0);
4079
4080 if (dsi->te_enabled)
4081 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4082 else
4083 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4084 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4085
4086 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4087 * because DSS interrupts are not capable of waking up the CPU and the
4088 * framedone interrupt could be delayed for quite a long time. I think
4089 * the same goes for any DSS interrupts, but for some reason I have not
4090 * seen the problem anywhere else than here.
4091 */
4092 dispc_disable_sidle();
4093
4094 dsi_perf_mark_start(dsidev);
4095
4096 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4097 msecs_to_jiffies(250));
4098 BUG_ON(r == 0);
4099
4100 dss_start_update(dssdev);
4101
4102 if (dsi->te_enabled) {
4103 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4104 * for TE is longer than the timer allows */
4105 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4106
4107 dsi_vc_send_bta(dsidev, channel);
4108
4109 #ifdef DSI_CATCH_MISSING_TE
4110 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4111 #endif
4112 }
4113 }
4114
4115 #ifdef DSI_CATCH_MISSING_TE
4116 static void dsi_te_timeout(unsigned long arg)
4117 {
4118 DSSERR("TE not received for 250ms!\n");
4119 }
4120 #endif
4121
4122 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4123 {
4124 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4125
4126 /* SIDLEMODE back to smart-idle */
4127 dispc_enable_sidle();
4128
4129 if (dsi->te_enabled) {
4130 /* enable LP_RX_TO again after the TE */
4131 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4132 }
4133
4134 dsi->framedone_callback(error, dsi->framedone_data);
4135
4136 if (!error)
4137 dsi_perf_show(dsidev, "DISPC");
4138 }
4139
4140 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4141 {
4142 struct dsi_data *dsi = container_of(work, struct dsi_data,
4143 framedone_timeout_work.work);
4144 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4145 * 250ms which would conflict with this timeout work. What should be
4146 * done is first cancel the transfer on the HW, and then cancel the
4147 * possibly scheduled framedone work. However, cancelling the transfer
4148 * on the HW is buggy, and would probably require resetting the whole
4149 * DSI */
4150
4151 DSSERR("Framedone not received for 250ms!\n");
4152
4153 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4154 }
4155
4156 static void dsi_framedone_irq_callback(void *data, u32 mask)
4157 {
4158 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4159 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4161
4162 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4163 * turns itself off. However, DSI still has the pixels in its buffers,
4164 * and is sending the data.
4165 */
4166
4167 __cancel_delayed_work(&dsi->framedone_timeout_work);
4168
4169 dsi_handle_framedone(dsidev, 0);
4170
4171 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4172 dispc_fake_vsync_irq();
4173 #endif
4174 }
4175
4176 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
4177 u16 *x, u16 *y, u16 *w, u16 *h,
4178 bool enlarge_update_area)
4179 {
4180 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4181 u16 dw, dh;
4182
4183 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4184
4185 if (*x > dw || *y > dh)
4186 return -EINVAL;
4187
4188 if (*x + *w > dw)
4189 return -EINVAL;
4190
4191 if (*y + *h > dh)
4192 return -EINVAL;
4193
4194 if (*w == 1)
4195 return -EINVAL;
4196
4197 if (*w == 0 || *h == 0)
4198 return -EINVAL;
4199
4200 dsi_perf_mark_setup(dsidev);
4201
4202 dss_setup_partial_planes(dssdev, x, y, w, h,
4203 enlarge_update_area);
4204 dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
4205
4206 return 0;
4207 }
4208 EXPORT_SYMBOL(omap_dsi_prepare_update);
4209
4210 int omap_dsi_update(struct omap_dss_device *dssdev,
4211 int channel,
4212 u16 x, u16 y, u16 w, u16 h,
4213 void (*callback)(int, void *), void *data)
4214 {
4215 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4216 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4217
4218 dsi->update_channel = channel;
4219
4220 /* OMAP DSS cannot send updates of odd widths.
4221 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
4222 * here to make sure we catch erroneous updates. Otherwise we'll only
4223 * see rather obscure HW error happening, as DSS halts. */
4224 BUG_ON(x % 2 == 1);
4225
4226 dsi->framedone_callback = callback;
4227 dsi->framedone_data = data;
4228
4229 dsi->update_region.x = x;
4230 dsi->update_region.y = y;
4231 dsi->update_region.w = w;
4232 dsi->update_region.h = h;
4233 dsi->update_region.device = dssdev;
4234
4235 dsi_update_screen_dispc(dssdev, x, y, w, h);
4236
4237 return 0;
4238 }
4239 EXPORT_SYMBOL(omap_dsi_update);
4240
4241 /* Display funcs */
4242
4243 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4244 {
4245 int r;
4246
4247 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4248 u32 irq;
4249 struct omap_video_timings timings = {
4250 .hsw = 1,
4251 .hfp = 1,
4252 .hbp = 1,
4253 .vsw = 1,
4254 .vfp = 0,
4255 .vbp = 0,
4256 };
4257
4258 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4259 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4260
4261 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4262 (void *) dssdev, irq);
4263 if (r) {
4264 DSSERR("can't get FRAMEDONE irq\n");
4265 return r;
4266 }
4267
4268 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4269 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4270
4271 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4272 } else {
4273 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4274 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4275
4276 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4277 &dssdev->panel.timings);
4278 }
4279
4280 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4281 OMAP_DSS_LCD_DISPLAY_TFT);
4282 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4283 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4284 return 0;
4285 }
4286
4287 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4288 {
4289 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4290 u32 irq;
4291
4292 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4293 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4294
4295 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4296 (void *) dssdev, irq);
4297 }
4298 }
4299
4300 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4301 {
4302 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4303 struct dsi_clock_info cinfo;
4304 int r;
4305
4306 /* we always use DSS_CLK_SYSCK as input clock */
4307 cinfo.use_sys_clk = true;
4308 cinfo.regn = dssdev->clocks.dsi.regn;
4309 cinfo.regm = dssdev->clocks.dsi.regm;
4310 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4311 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4312 r = dsi_calc_clock_rates(dssdev, &cinfo);
4313 if (r) {
4314 DSSERR("Failed to calc dsi clocks\n");
4315 return r;
4316 }
4317
4318 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4319 if (r) {
4320 DSSERR("Failed to set dsi clocks\n");
4321 return r;
4322 }
4323
4324 return 0;
4325 }
4326
4327 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4328 {
4329 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4330 struct dispc_clock_info dispc_cinfo;
4331 int r;
4332 unsigned long long fck;
4333
4334 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4335
4336 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4337 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4338
4339 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4340 if (r) {
4341 DSSERR("Failed to calc dispc clocks\n");
4342 return r;
4343 }
4344
4345 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4346 if (r) {
4347 DSSERR("Failed to set dispc clocks\n");
4348 return r;
4349 }
4350
4351 return 0;
4352 }
4353
4354 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4355 {
4356 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4357 int dsi_module = dsi_get_dsidev_id(dsidev);
4358 int r;
4359
4360 r = dsi_parse_lane_config(dssdev);
4361 if (r) {
4362 DSSERR("illegal lane config");
4363 goto err0;
4364 }
4365
4366 r = dsi_pll_init(dsidev, true, true);
4367 if (r)
4368 goto err0;
4369
4370 r = dsi_configure_dsi_clocks(dssdev);
4371 if (r)
4372 goto err1;
4373
4374 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4375 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4376 dss_select_lcd_clk_source(dssdev->manager->id,
4377 dssdev->clocks.dispc.channel.lcd_clk_src);
4378
4379 DSSDBG("PLL OK\n");
4380
4381 r = dsi_configure_dispc_clocks(dssdev);
4382 if (r)
4383 goto err2;
4384
4385 r = dsi_cio_init(dssdev);
4386 if (r)
4387 goto err2;
4388
4389 _dsi_print_reset_status(dsidev);
4390
4391 dsi_proto_timings(dssdev);
4392 dsi_set_lp_clk_divisor(dssdev);
4393
4394 if (1)
4395 _dsi_print_reset_status(dsidev);
4396
4397 r = dsi_proto_config(dssdev);
4398 if (r)
4399 goto err3;
4400
4401 /* enable interface */
4402 dsi_vc_enable(dsidev, 0, 1);
4403 dsi_vc_enable(dsidev, 1, 1);
4404 dsi_vc_enable(dsidev, 2, 1);
4405 dsi_vc_enable(dsidev, 3, 1);
4406 dsi_if_enable(dsidev, 1);
4407 dsi_force_tx_stop_mode_io(dsidev);
4408
4409 return 0;
4410 err3:
4411 dsi_cio_uninit(dssdev);
4412 err2:
4413 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4414 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4415 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4416
4417 err1:
4418 dsi_pll_uninit(dsidev, true);
4419 err0:
4420 return r;
4421 }
4422
4423 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4424 bool disconnect_lanes, bool enter_ulps)
4425 {
4426 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4427 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4428 int dsi_module = dsi_get_dsidev_id(dsidev);
4429
4430 if (enter_ulps && !dsi->ulps_enabled)
4431 dsi_enter_ulps(dsidev);
4432
4433 /* disable interface */
4434 dsi_if_enable(dsidev, 0);
4435 dsi_vc_enable(dsidev, 0, 0);
4436 dsi_vc_enable(dsidev, 1, 0);
4437 dsi_vc_enable(dsidev, 2, 0);
4438 dsi_vc_enable(dsidev, 3, 0);
4439
4440 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4441 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4442 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4443 dsi_cio_uninit(dssdev);
4444 dsi_pll_uninit(dsidev, disconnect_lanes);
4445 }
4446
4447 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4448 {
4449 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4451 int r = 0;
4452
4453 DSSDBG("dsi_display_enable\n");
4454
4455 WARN_ON(!dsi_bus_is_locked(dsidev));
4456
4457 mutex_lock(&dsi->lock);
4458
4459 if (dssdev->manager == NULL) {
4460 DSSERR("failed to enable display: no manager\n");
4461 r = -ENODEV;
4462 goto err_start_dev;
4463 }
4464
4465 r = omap_dss_start_device(dssdev);
4466 if (r) {
4467 DSSERR("failed to start device\n");
4468 goto err_start_dev;
4469 }
4470
4471 r = dsi_runtime_get(dsidev);
4472 if (r)
4473 goto err_get_dsi;
4474
4475 dsi_enable_pll_clock(dsidev, 1);
4476
4477 _dsi_initialize_irq(dsidev);
4478
4479 r = dsi_display_init_dispc(dssdev);
4480 if (r)
4481 goto err_init_dispc;
4482
4483 r = dsi_display_init_dsi(dssdev);
4484 if (r)
4485 goto err_init_dsi;
4486
4487 mutex_unlock(&dsi->lock);
4488
4489 return 0;
4490
4491 err_init_dsi:
4492 dsi_display_uninit_dispc(dssdev);
4493 err_init_dispc:
4494 dsi_enable_pll_clock(dsidev, 0);
4495 dsi_runtime_put(dsidev);
4496 err_get_dsi:
4497 omap_dss_stop_device(dssdev);
4498 err_start_dev:
4499 mutex_unlock(&dsi->lock);
4500 DSSDBG("dsi_display_enable FAILED\n");
4501 return r;
4502 }
4503 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4504
4505 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4506 bool disconnect_lanes, bool enter_ulps)
4507 {
4508 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4509 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4510
4511 DSSDBG("dsi_display_disable\n");
4512
4513 WARN_ON(!dsi_bus_is_locked(dsidev));
4514
4515 mutex_lock(&dsi->lock);
4516
4517 dsi_sync_vc(dsidev, 0);
4518 dsi_sync_vc(dsidev, 1);
4519 dsi_sync_vc(dsidev, 2);
4520 dsi_sync_vc(dsidev, 3);
4521
4522 dsi_display_uninit_dispc(dssdev);
4523
4524 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4525
4526 dsi_runtime_put(dsidev);
4527 dsi_enable_pll_clock(dsidev, 0);
4528
4529 omap_dss_stop_device(dssdev);
4530
4531 mutex_unlock(&dsi->lock);
4532 }
4533 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4534
4535 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4536 {
4537 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4538 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4539
4540 dsi->te_enabled = enable;
4541 return 0;
4542 }
4543 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4544
4545 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4546 u32 fifo_size, u32 burst_size,
4547 u32 *fifo_low, u32 *fifo_high)
4548 {
4549 *fifo_high = fifo_size - burst_size;
4550 *fifo_low = fifo_size - burst_size * 2;
4551 }
4552
4553 int dsi_init_display(struct omap_dss_device *dssdev)
4554 {
4555 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4556 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4557 int dsi_module = dsi_get_dsidev_id(dsidev);
4558
4559 DSSDBG("DSI init\n");
4560
4561 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4562 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4563 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4564 }
4565
4566 if (dsi->vdds_dsi_reg == NULL) {
4567 struct regulator *vdds_dsi;
4568
4569 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4570
4571 if (IS_ERR(vdds_dsi)) {
4572 DSSERR("can't get VDDS_DSI regulator\n");
4573 return PTR_ERR(vdds_dsi);
4574 }
4575
4576 dsi->vdds_dsi_reg = vdds_dsi;
4577 }
4578
4579 if (dsi_get_num_lanes_used(dssdev) > dsi->num_lanes_supported) {
4580 DSSERR("DSI%d can't support more than %d lanes\n",
4581 dsi_module + 1, dsi->num_lanes_supported);
4582 return -EINVAL;
4583 }
4584
4585 return 0;
4586 }
4587
4588 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4589 {
4590 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4591 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4592 int i;
4593
4594 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4595 if (!dsi->vc[i].dssdev) {
4596 dsi->vc[i].dssdev = dssdev;
4597 *channel = i;
4598 return 0;
4599 }
4600 }
4601
4602 DSSERR("cannot get VC for display %s", dssdev->name);
4603 return -ENOSPC;
4604 }
4605 EXPORT_SYMBOL(omap_dsi_request_vc);
4606
4607 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4608 {
4609 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4610 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4611
4612 if (vc_id < 0 || vc_id > 3) {
4613 DSSERR("VC ID out of range\n");
4614 return -EINVAL;
4615 }
4616
4617 if (channel < 0 || channel > 3) {
4618 DSSERR("Virtual Channel out of range\n");
4619 return -EINVAL;
4620 }
4621
4622 if (dsi->vc[channel].dssdev != dssdev) {
4623 DSSERR("Virtual Channel not allocated to display %s\n",
4624 dssdev->name);
4625 return -EINVAL;
4626 }
4627
4628 dsi->vc[channel].vc_id = vc_id;
4629
4630 return 0;
4631 }
4632 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4633
4634 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4635 {
4636 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4637 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4638
4639 if ((channel >= 0 && channel <= 3) &&
4640 dsi->vc[channel].dssdev == dssdev) {
4641 dsi->vc[channel].dssdev = NULL;
4642 dsi->vc[channel].vc_id = 0;
4643 }
4644 }
4645 EXPORT_SYMBOL(omap_dsi_release_vc);
4646
4647 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4648 {
4649 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4650 DSSERR("%s (%s) not active\n",
4651 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4652 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4653 }
4654
4655 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4656 {
4657 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4658 DSSERR("%s (%s) not active\n",
4659 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4660 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4661 }
4662
4663 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4664 {
4665 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4666
4667 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4668 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4669 dsi->regm_dispc_max =
4670 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4671 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4672 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4673 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4674 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4675 }
4676
4677 static int dsi_get_clocks(struct platform_device *dsidev)
4678 {
4679 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4680 struct clk *clk;
4681
4682 clk = clk_get(&dsidev->dev, "fck");
4683 if (IS_ERR(clk)) {
4684 DSSERR("can't get fck\n");
4685 return PTR_ERR(clk);
4686 }
4687
4688 dsi->dss_clk = clk;
4689
4690 clk = clk_get(&dsidev->dev, "sys_clk");
4691 if (IS_ERR(clk)) {
4692 DSSERR("can't get sys_clk\n");
4693 clk_put(dsi->dss_clk);
4694 dsi->dss_clk = NULL;
4695 return PTR_ERR(clk);
4696 }
4697
4698 dsi->sys_clk = clk;
4699
4700 return 0;
4701 }
4702
4703 static void dsi_put_clocks(struct platform_device *dsidev)
4704 {
4705 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4706
4707 if (dsi->dss_clk)
4708 clk_put(dsi->dss_clk);
4709 if (dsi->sys_clk)
4710 clk_put(dsi->sys_clk);
4711 }
4712
4713 /* DSI1 HW IP initialisation */
4714 static int omap_dsihw_probe(struct platform_device *dsidev)
4715 {
4716 struct omap_display_platform_data *dss_plat_data;
4717 struct omap_dss_board_info *board_info;
4718 u32 rev;
4719 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4720 struct resource *dsi_mem;
4721 struct dsi_data *dsi;
4722
4723 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4724 if (!dsi) {
4725 r = -ENOMEM;
4726 goto err_alloc;
4727 }
4728
4729 dsi->pdev = dsidev;
4730 dsi_pdev_map[dsi_module] = dsidev;
4731 dev_set_drvdata(&dsidev->dev, dsi);
4732
4733 dss_plat_data = dsidev->dev.platform_data;
4734 board_info = dss_plat_data->board_data;
4735 dsi->enable_pads = board_info->dsi_enable_pads;
4736 dsi->disable_pads = board_info->dsi_disable_pads;
4737
4738 spin_lock_init(&dsi->irq_lock);
4739 spin_lock_init(&dsi->errors_lock);
4740 dsi->errors = 0;
4741
4742 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4743 spin_lock_init(&dsi->irq_stats_lock);
4744 dsi->irq_stats.last_reset = jiffies;
4745 #endif
4746
4747 mutex_init(&dsi->lock);
4748 sema_init(&dsi->bus_lock, 1);
4749
4750 r = dsi_get_clocks(dsidev);
4751 if (r)
4752 goto err_get_clk;
4753
4754 pm_runtime_enable(&dsidev->dev);
4755
4756 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4757 dsi_framedone_timeout_work_callback);
4758
4759 #ifdef DSI_CATCH_MISSING_TE
4760 init_timer(&dsi->te_timer);
4761 dsi->te_timer.function = dsi_te_timeout;
4762 dsi->te_timer.data = 0;
4763 #endif
4764 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4765 if (!dsi_mem) {
4766 DSSERR("can't get IORESOURCE_MEM DSI\n");
4767 r = -EINVAL;
4768 goto err_ioremap;
4769 }
4770 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4771 if (!dsi->base) {
4772 DSSERR("can't ioremap DSI\n");
4773 r = -ENOMEM;
4774 goto err_ioremap;
4775 }
4776 dsi->irq = platform_get_irq(dsi->pdev, 0);
4777 if (dsi->irq < 0) {
4778 DSSERR("platform_get_irq failed\n");
4779 r = -ENODEV;
4780 goto err_get_irq;
4781 }
4782
4783 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4784 dev_name(&dsidev->dev), dsi->pdev);
4785 if (r < 0) {
4786 DSSERR("request_irq failed\n");
4787 goto err_get_irq;
4788 }
4789
4790 /* DSI VCs initialization */
4791 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4792 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4793 dsi->vc[i].dssdev = NULL;
4794 dsi->vc[i].vc_id = 0;
4795 }
4796
4797 dsi_calc_clock_param_ranges(dsidev);
4798
4799 r = dsi_runtime_get(dsidev);
4800 if (r)
4801 goto err_get_dsi;
4802
4803 rev = dsi_read_reg(dsidev, DSI_REVISION);
4804 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4805 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4806
4807 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4808 * of data to 3 by default */
4809 if (dss_has_feature(FEAT_DSI_GNQ))
4810 /* NB_DATA_LANES */
4811 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4812 else
4813 dsi->num_lanes_supported = 3;
4814
4815 dsi_runtime_put(dsidev);
4816
4817 return 0;
4818
4819 err_get_dsi:
4820 free_irq(dsi->irq, dsi->pdev);
4821 err_get_irq:
4822 iounmap(dsi->base);
4823 err_ioremap:
4824 pm_runtime_disable(&dsidev->dev);
4825 err_get_clk:
4826 kfree(dsi);
4827 err_alloc:
4828 return r;
4829 }
4830
4831 static int omap_dsihw_remove(struct platform_device *dsidev)
4832 {
4833 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4834
4835 WARN_ON(dsi->scp_clk_refcount > 0);
4836
4837 pm_runtime_disable(&dsidev->dev);
4838
4839 dsi_put_clocks(dsidev);
4840
4841 if (dsi->vdds_dsi_reg != NULL) {
4842 if (dsi->vdds_dsi_enabled) {
4843 regulator_disable(dsi->vdds_dsi_reg);
4844 dsi->vdds_dsi_enabled = false;
4845 }
4846
4847 regulator_put(dsi->vdds_dsi_reg);
4848 dsi->vdds_dsi_reg = NULL;
4849 }
4850
4851 free_irq(dsi->irq, dsi->pdev);
4852 iounmap(dsi->base);
4853
4854 kfree(dsi);
4855
4856 return 0;
4857 }
4858
4859 static int dsi_runtime_suspend(struct device *dev)
4860 {
4861 dispc_runtime_put();
4862 dss_runtime_put();
4863
4864 return 0;
4865 }
4866
4867 static int dsi_runtime_resume(struct device *dev)
4868 {
4869 int r;
4870
4871 r = dss_runtime_get();
4872 if (r)
4873 goto err_get_dss;
4874
4875 r = dispc_runtime_get();
4876 if (r)
4877 goto err_get_dispc;
4878
4879 return 0;
4880
4881 err_get_dispc:
4882 dss_runtime_put();
4883 err_get_dss:
4884 return r;
4885 }
4886
4887 static const struct dev_pm_ops dsi_pm_ops = {
4888 .runtime_suspend = dsi_runtime_suspend,
4889 .runtime_resume = dsi_runtime_resume,
4890 };
4891
4892 static struct platform_driver omap_dsihw_driver = {
4893 .probe = omap_dsihw_probe,
4894 .remove = omap_dsihw_remove,
4895 .driver = {
4896 .name = "omapdss_dsi",
4897 .owner = THIS_MODULE,
4898 .pm = &dsi_pm_ops,
4899 },
4900 };
4901
4902 int dsi_init_platform_driver(void)
4903 {
4904 return platform_driver_register(&omap_dsihw_driver);
4905 }
4906
4907 void dsi_uninit_platform_driver(void)
4908 {
4909 return platform_driver_unregister(&omap_dsihw_driver);
4910 }
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