2 * linux/drivers/video/omap2/dss/venc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * VENC settings from TI's DSS driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "VENC"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <video/omapdss.h>
42 #include "dss_features.h"
45 #define VENC_REV_ID 0x00
46 #define VENC_STATUS 0x04
47 #define VENC_F_CONTROL 0x08
48 #define VENC_VIDOUT_CTRL 0x10
49 #define VENC_SYNC_CTRL 0x14
50 #define VENC_LLEN 0x1C
51 #define VENC_FLENS 0x20
52 #define VENC_HFLTR_CTRL 0x24
53 #define VENC_CC_CARR_WSS_CARR 0x28
54 #define VENC_C_PHASE 0x2C
55 #define VENC_GAIN_U 0x30
56 #define VENC_GAIN_V 0x34
57 #define VENC_GAIN_Y 0x38
58 #define VENC_BLACK_LEVEL 0x3C
59 #define VENC_BLANK_LEVEL 0x40
60 #define VENC_X_COLOR 0x44
61 #define VENC_M_CONTROL 0x48
62 #define VENC_BSTAMP_WSS_DATA 0x4C
63 #define VENC_S_CARR 0x50
64 #define VENC_LINE21 0x54
65 #define VENC_LN_SEL 0x58
66 #define VENC_L21__WC_CTL 0x5C
67 #define VENC_HTRIGGER_VTRIGGER 0x60
68 #define VENC_SAVID__EAVID 0x64
69 #define VENC_FLEN__FAL 0x68
70 #define VENC_LAL__PHASE_RESET 0x6C
71 #define VENC_HS_INT_START_STOP_X 0x70
72 #define VENC_HS_EXT_START_STOP_X 0x74
73 #define VENC_VS_INT_START_X 0x78
74 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77 #define VENC_VS_EXT_STOP_Y 0x88
78 #define VENC_AVID_START_STOP_X 0x90
79 #define VENC_AVID_START_STOP_Y 0x94
80 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
84 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85 #define VENC_GEN_CTRL 0xB8
86 #define VENC_OUTPUT_CONTROL 0xC4
87 #define VENC_OUTPUT_TEST 0xC8
88 #define VENC_DAC_B__DAC_C 0xC8
111 u32 htrigger_vtrigger
;
114 u32 lal__phase_reset
;
115 u32 hs_int_start_stop_x
;
116 u32 hs_ext_start_stop_x
;
118 u32 vs_int_stop_x__vs_int_start_y
;
119 u32 vs_int_stop_y__vs_ext_start_x
;
120 u32 vs_ext_stop_x__vs_ext_start_y
;
122 u32 avid_start_stop_x
;
123 u32 avid_start_stop_y
;
124 u32 fid_int_start_x__fid_int_start_y
;
125 u32 fid_int_offset_y__fid_ext_start_x
;
126 u32 fid_ext_start_y__fid_ext_offset_y
;
127 u32 tvdetgp_int_start_stop_x
;
128 u32 tvdetgp_int_start_stop_y
;
133 static const struct venc_config venc_config_pal_trm
= {
137 .llen
= 0x35F, /* 863 */
138 .flens
= 0x270, /* 624 */
140 .cc_carr_wss_carr
= 0x2F7225ED,
149 .bstamp_wss_data
= 0x3F,
150 .s_carr
= 0x2A098ACB,
152 .ln_sel
= 0x01290015,
153 .l21__wc_ctl
= 0x0000F603,
154 .htrigger_vtrigger
= 0,
156 .savid__eavid
= 0x06A70108,
157 .flen__fal
= 0x00180270,
158 .lal__phase_reset
= 0x00040135,
159 .hs_int_start_stop_x
= 0x00880358,
160 .hs_ext_start_stop_x
= 0x000F035F,
161 .vs_int_start_x
= 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y
= 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x
= 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y
= 0x000101AF,
165 .vs_ext_stop_y
= 0x00000025,
166 .avid_start_stop_x
= 0x03530083,
167 .avid_start_stop_y
= 0x026C002E,
168 .fid_int_start_x__fid_int_start_y
= 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x
= 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y
= 0x01380001,
172 .tvdetgp_int_start_stop_x
= 0x00140001,
173 .tvdetgp_int_start_stop_y
= 0x00010001,
174 .gen_ctrl
= 0x00FF0000,
178 static const struct venc_config venc_config_ntsc_trm
= {
185 .cc_carr_wss_carr
= 0x043F2631,
194 .bstamp_wss_data
= 0x38,
195 .s_carr
= 0x21F07C1F,
197 .ln_sel
= 0x01310011,
198 .l21__wc_ctl
= 0x0000F003,
199 .htrigger_vtrigger
= 0,
201 .savid__eavid
= 0x069300F4,
202 .flen__fal
= 0x0016020C,
203 .lal__phase_reset
= 0x00060107,
204 .hs_int_start_stop_x
= 0x008E0350,
205 .hs_ext_start_stop_x
= 0x000F0359,
206 .vs_int_start_x
= 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y
= 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x
= 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y
= 0x020D01AC,
210 .vs_ext_stop_y
= 0x00000006,
211 .avid_start_stop_x
= 0x03480078,
212 .avid_start_stop_y
= 0x02060024,
213 .fid_int_start_x__fid_int_start_y
= 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x
= 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y
= 0x01060006,
217 .tvdetgp_int_start_stop_x
= 0x00140001,
218 .tvdetgp_int_start_stop_y
= 0x00010001,
219 .gen_ctrl
= 0x00F90000,
222 static const struct venc_config venc_config_pal_bdghi
= {
230 .htrigger_vtrigger
= 0,
231 .tvdetgp_int_start_stop_x
= 0x00140001,
232 .tvdetgp_int_start_stop_y
= 0x00010001,
233 .gen_ctrl
= 0x00FB0000,
237 .cc_carr_wss_carr
= 0x2F7625ED,
244 .m_control
= 0<<2 | 1<<1,
245 .bstamp_wss_data
= 0x42,
246 .s_carr
= 0x2a098acb,
247 .l21__wc_ctl
= 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid
= 0x06A70108,
249 .flen__fal
= 23<<16 | 624<<0,
250 .lal__phase_reset
= 2<<17 | 310<<0,
251 .hs_int_start_stop_x
= 0x00920358,
252 .hs_ext_start_stop_x
= 0x000F035F,
253 .vs_int_start_x
= 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y
= 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x
= 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y
= 0x27101af,
257 .vs_ext_stop_y
= 0x05,
258 .avid_start_stop_x
= 0x03530082,
259 .avid_start_stop_y
= 0x0270002E,
260 .fid_int_start_x__fid_int_start_y
= 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x
= 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y
= 0x01380005,
265 const struct omap_video_timings omap_dss_pal_timings
= {
268 .pixel_clock
= 13500,
276 EXPORT_SYMBOL(omap_dss_pal_timings
);
278 const struct omap_video_timings omap_dss_ntsc_timings
= {
281 .pixel_clock
= 13500,
289 EXPORT_SYMBOL(omap_dss_ntsc_timings
);
292 struct platform_device
*pdev
;
294 struct mutex venc_lock
;
296 struct regulator
*vdda_dac_reg
;
298 struct clk
*tv_dac_clk
;
301 static inline void venc_write_reg(int idx
, u32 val
)
303 __raw_writel(val
, venc
.base
+ idx
);
306 static inline u32
venc_read_reg(int idx
)
308 u32 l
= __raw_readl(venc
.base
+ idx
);
312 static void venc_write_config(const struct venc_config
*config
)
314 DSSDBG("write venc conf\n");
316 venc_write_reg(VENC_LLEN
, config
->llen
);
317 venc_write_reg(VENC_FLENS
, config
->flens
);
318 venc_write_reg(VENC_CC_CARR_WSS_CARR
, config
->cc_carr_wss_carr
);
319 venc_write_reg(VENC_C_PHASE
, config
->c_phase
);
320 venc_write_reg(VENC_GAIN_U
, config
->gain_u
);
321 venc_write_reg(VENC_GAIN_V
, config
->gain_v
);
322 venc_write_reg(VENC_GAIN_Y
, config
->gain_y
);
323 venc_write_reg(VENC_BLACK_LEVEL
, config
->black_level
);
324 venc_write_reg(VENC_BLANK_LEVEL
, config
->blank_level
);
325 venc_write_reg(VENC_M_CONTROL
, config
->m_control
);
326 venc_write_reg(VENC_BSTAMP_WSS_DATA
, config
->bstamp_wss_data
|
328 venc_write_reg(VENC_S_CARR
, config
->s_carr
);
329 venc_write_reg(VENC_L21__WC_CTL
, config
->l21__wc_ctl
);
330 venc_write_reg(VENC_SAVID__EAVID
, config
->savid__eavid
);
331 venc_write_reg(VENC_FLEN__FAL
, config
->flen__fal
);
332 venc_write_reg(VENC_LAL__PHASE_RESET
, config
->lal__phase_reset
);
333 venc_write_reg(VENC_HS_INT_START_STOP_X
, config
->hs_int_start_stop_x
);
334 venc_write_reg(VENC_HS_EXT_START_STOP_X
, config
->hs_ext_start_stop_x
);
335 venc_write_reg(VENC_VS_INT_START_X
, config
->vs_int_start_x
);
336 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y
,
337 config
->vs_int_stop_x__vs_int_start_y
);
338 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X
,
339 config
->vs_int_stop_y__vs_ext_start_x
);
340 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y
,
341 config
->vs_ext_stop_x__vs_ext_start_y
);
342 venc_write_reg(VENC_VS_EXT_STOP_Y
, config
->vs_ext_stop_y
);
343 venc_write_reg(VENC_AVID_START_STOP_X
, config
->avid_start_stop_x
);
344 venc_write_reg(VENC_AVID_START_STOP_Y
, config
->avid_start_stop_y
);
345 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y
,
346 config
->fid_int_start_x__fid_int_start_y
);
347 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X
,
348 config
->fid_int_offset_y__fid_ext_start_x
);
349 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y
,
350 config
->fid_ext_start_y__fid_ext_offset_y
);
352 venc_write_reg(VENC_DAC_B__DAC_C
, venc_read_reg(VENC_DAC_B__DAC_C
));
353 venc_write_reg(VENC_VIDOUT_CTRL
, config
->vidout_ctrl
);
354 venc_write_reg(VENC_HFLTR_CTRL
, config
->hfltr_ctrl
);
355 venc_write_reg(VENC_X_COLOR
, config
->x_color
);
356 venc_write_reg(VENC_LINE21
, config
->line21
);
357 venc_write_reg(VENC_LN_SEL
, config
->ln_sel
);
358 venc_write_reg(VENC_HTRIGGER_VTRIGGER
, config
->htrigger_vtrigger
);
359 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X
,
360 config
->tvdetgp_int_start_stop_x
);
361 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y
,
362 config
->tvdetgp_int_start_stop_y
);
363 venc_write_reg(VENC_GEN_CTRL
, config
->gen_ctrl
);
364 venc_write_reg(VENC_F_CONTROL
, config
->f_control
);
365 venc_write_reg(VENC_SYNC_CTRL
, config
->sync_ctrl
);
368 static void venc_reset(void)
372 venc_write_reg(VENC_F_CONTROL
, 1<<8);
373 while (venc_read_reg(VENC_F_CONTROL
) & (1<<8)) {
375 DSSERR("Failed to reset venc\n");
380 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
381 /* the magical sleep that makes things work */
382 /* XXX more info? What bug this circumvents? */
387 static int venc_runtime_get(void)
391 DSSDBG("venc_runtime_get\n");
393 r
= pm_runtime_get_sync(&venc
.pdev
->dev
);
395 return r
< 0 ? r
: 0;
398 static void venc_runtime_put(void)
402 DSSDBG("venc_runtime_put\n");
404 r
= pm_runtime_put_sync(&venc
.pdev
->dev
);
408 static const struct venc_config
*venc_timings_to_config(
409 struct omap_video_timings
*timings
)
411 if (memcmp(&omap_dss_pal_timings
, timings
, sizeof(*timings
)) == 0)
412 return &venc_config_pal_trm
;
414 if (memcmp(&omap_dss_ntsc_timings
, timings
, sizeof(*timings
)) == 0)
415 return &venc_config_ntsc_trm
;
421 static int venc_power_on(struct omap_dss_device
*dssdev
)
427 venc_write_config(venc_timings_to_config(&dssdev
->panel
.timings
));
429 dss_set_venc_output(dssdev
->phy
.venc
.type
);
430 dss_set_dac_pwrdn_bgz(1);
434 if (dssdev
->phy
.venc
.type
== OMAP_DSS_VENC_TYPE_COMPOSITE
)
437 l
|= (1 << 0) | (1 << 2);
439 if (dssdev
->phy
.venc
.invert_polarity
== false)
442 venc_write_reg(VENC_OUTPUT_CONTROL
, l
);
444 dss_mgr_set_timings(dssdev
->manager
, &dssdev
->panel
.timings
);
446 r
= regulator_enable(venc
.vdda_dac_reg
);
450 if (dssdev
->platform_enable
)
451 dssdev
->platform_enable(dssdev
);
453 r
= dss_mgr_enable(dssdev
->manager
);
460 venc_write_reg(VENC_OUTPUT_CONTROL
, 0);
461 dss_set_dac_pwrdn_bgz(0);
463 if (dssdev
->platform_disable
)
464 dssdev
->platform_disable(dssdev
);
466 regulator_disable(venc
.vdda_dac_reg
);
471 static void venc_power_off(struct omap_dss_device
*dssdev
)
473 venc_write_reg(VENC_OUTPUT_CONTROL
, 0);
474 dss_set_dac_pwrdn_bgz(0);
476 dss_mgr_disable(dssdev
->manager
);
478 if (dssdev
->platform_disable
)
479 dssdev
->platform_disable(dssdev
);
481 regulator_disable(venc
.vdda_dac_reg
);
484 unsigned long venc_get_pixel_clock(void)
486 /* VENC Pixel Clock in Mhz */
490 static ssize_t
display_output_type_show(struct device
*dev
,
491 struct device_attribute
*attr
, char *buf
)
493 struct omap_dss_device
*dssdev
= to_dss_device(dev
);
496 switch (dssdev
->phy
.venc
.type
) {
497 case OMAP_DSS_VENC_TYPE_COMPOSITE
:
500 case OMAP_DSS_VENC_TYPE_SVIDEO
:
507 return snprintf(buf
, PAGE_SIZE
, "%s\n", ret
);
510 static ssize_t
display_output_type_store(struct device
*dev
,
511 struct device_attribute
*attr
, const char *buf
, size_t size
)
513 struct omap_dss_device
*dssdev
= to_dss_device(dev
);
514 enum omap_dss_venc_type new_type
;
516 if (sysfs_streq("composite", buf
))
517 new_type
= OMAP_DSS_VENC_TYPE_COMPOSITE
;
518 else if (sysfs_streq("svideo", buf
))
519 new_type
= OMAP_DSS_VENC_TYPE_SVIDEO
;
523 mutex_lock(&venc
.venc_lock
);
525 if (dssdev
->phy
.venc
.type
!= new_type
) {
526 dssdev
->phy
.venc
.type
= new_type
;
527 if (dssdev
->state
== OMAP_DSS_DISPLAY_ACTIVE
) {
528 venc_power_off(dssdev
);
529 venc_power_on(dssdev
);
533 mutex_unlock(&venc
.venc_lock
);
538 static DEVICE_ATTR(output_type
, S_IRUGO
| S_IWUSR
,
539 display_output_type_show
, display_output_type_store
);
542 static int venc_panel_probe(struct omap_dss_device
*dssdev
)
544 dssdev
->panel
.timings
= omap_dss_pal_timings
;
546 return device_create_file(&dssdev
->dev
, &dev_attr_output_type
);
549 static void venc_panel_remove(struct omap_dss_device
*dssdev
)
551 device_remove_file(&dssdev
->dev
, &dev_attr_output_type
);
554 static int venc_panel_enable(struct omap_dss_device
*dssdev
)
558 DSSDBG("venc_enable_display\n");
560 mutex_lock(&venc
.venc_lock
);
562 r
= omap_dss_start_device(dssdev
);
564 DSSERR("failed to start device\n");
568 if (dssdev
->state
!= OMAP_DSS_DISPLAY_DISABLED
) {
573 r
= venc_runtime_get();
577 r
= venc_power_on(dssdev
);
583 dssdev
->state
= OMAP_DSS_DISPLAY_ACTIVE
;
585 mutex_unlock(&venc
.venc_lock
);
590 omap_dss_stop_device(dssdev
);
592 mutex_unlock(&venc
.venc_lock
);
597 static void venc_panel_disable(struct omap_dss_device
*dssdev
)
599 DSSDBG("venc_disable_display\n");
601 mutex_lock(&venc
.venc_lock
);
603 if (dssdev
->state
== OMAP_DSS_DISPLAY_DISABLED
)
606 if (dssdev
->state
== OMAP_DSS_DISPLAY_SUSPENDED
) {
607 /* suspended is the same as disabled with venc */
608 dssdev
->state
= OMAP_DSS_DISPLAY_DISABLED
;
612 venc_power_off(dssdev
);
616 dssdev
->state
= OMAP_DSS_DISPLAY_DISABLED
;
618 omap_dss_stop_device(dssdev
);
620 mutex_unlock(&venc
.venc_lock
);
623 static int venc_panel_suspend(struct omap_dss_device
*dssdev
)
625 venc_panel_disable(dssdev
);
629 static int venc_panel_resume(struct omap_dss_device
*dssdev
)
631 return venc_panel_enable(dssdev
);
634 static void venc_set_timings(struct omap_dss_device
*dssdev
,
635 struct omap_video_timings
*timings
)
637 DSSDBG("venc_set_timings\n");
639 /* Reset WSS data when the TV standard changes. */
640 if (memcmp(&dssdev
->panel
.timings
, timings
, sizeof(*timings
)))
643 dssdev
->panel
.timings
= *timings
;
644 if (dssdev
->state
== OMAP_DSS_DISPLAY_ACTIVE
) {
645 /* turn the venc off and on to get new timings to use */
646 venc_panel_disable(dssdev
);
647 venc_panel_enable(dssdev
);
649 dss_mgr_set_timings(dssdev
->manager
, timings
);
653 static int venc_check_timings(struct omap_dss_device
*dssdev
,
654 struct omap_video_timings
*timings
)
656 DSSDBG("venc_check_timings\n");
658 if (memcmp(&omap_dss_pal_timings
, timings
, sizeof(*timings
)) == 0)
661 if (memcmp(&omap_dss_ntsc_timings
, timings
, sizeof(*timings
)) == 0)
667 static u32
venc_get_wss(struct omap_dss_device
*dssdev
)
669 /* Invert due to VENC_L21_WC_CTL:INV=1 */
670 return (venc
.wss_data
>> 8) ^ 0xfffff;
673 static int venc_set_wss(struct omap_dss_device
*dssdev
, u32 wss
)
675 const struct venc_config
*config
;
678 DSSDBG("venc_set_wss\n");
680 mutex_lock(&venc
.venc_lock
);
682 config
= venc_timings_to_config(&dssdev
->panel
.timings
);
684 /* Invert due to VENC_L21_WC_CTL:INV=1 */
685 venc
.wss_data
= (wss
^ 0xfffff) << 8;
687 r
= venc_runtime_get();
691 venc_write_reg(VENC_BSTAMP_WSS_DATA
, config
->bstamp_wss_data
|
697 mutex_unlock(&venc
.venc_lock
);
702 static struct omap_dss_driver venc_driver
= {
703 .probe
= venc_panel_probe
,
704 .remove
= venc_panel_remove
,
706 .enable
= venc_panel_enable
,
707 .disable
= venc_panel_disable
,
708 .suspend
= venc_panel_suspend
,
709 .resume
= venc_panel_resume
,
711 .get_resolution
= omapdss_default_get_resolution
,
712 .get_recommended_bpp
= omapdss_default_get_recommended_bpp
,
714 .set_timings
= venc_set_timings
,
715 .check_timings
= venc_check_timings
,
717 .get_wss
= venc_get_wss
,
718 .set_wss
= venc_set_wss
,
722 .owner
= THIS_MODULE
,
727 static int __init
venc_init_display(struct omap_dss_device
*dssdev
)
729 DSSDBG("init_display\n");
731 if (venc
.vdda_dac_reg
== NULL
) {
732 struct regulator
*vdda_dac
;
734 vdda_dac
= regulator_get(&venc
.pdev
->dev
, "vdda_dac");
736 if (IS_ERR(vdda_dac
)) {
737 DSSERR("can't get VDDA_DAC regulator\n");
738 return PTR_ERR(vdda_dac
);
741 venc
.vdda_dac_reg
= vdda_dac
;
747 static void venc_dump_regs(struct seq_file
*s
)
749 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
751 if (cpu_is_omap44xx()) {
752 seq_printf(s
, "VENC currently disabled on OMAP44xx\n");
756 if (venc_runtime_get())
759 DUMPREG(VENC_F_CONTROL
);
760 DUMPREG(VENC_VIDOUT_CTRL
);
761 DUMPREG(VENC_SYNC_CTRL
);
764 DUMPREG(VENC_HFLTR_CTRL
);
765 DUMPREG(VENC_CC_CARR_WSS_CARR
);
766 DUMPREG(VENC_C_PHASE
);
767 DUMPREG(VENC_GAIN_U
);
768 DUMPREG(VENC_GAIN_V
);
769 DUMPREG(VENC_GAIN_Y
);
770 DUMPREG(VENC_BLACK_LEVEL
);
771 DUMPREG(VENC_BLANK_LEVEL
);
772 DUMPREG(VENC_X_COLOR
);
773 DUMPREG(VENC_M_CONTROL
);
774 DUMPREG(VENC_BSTAMP_WSS_DATA
);
775 DUMPREG(VENC_S_CARR
);
776 DUMPREG(VENC_LINE21
);
777 DUMPREG(VENC_LN_SEL
);
778 DUMPREG(VENC_L21__WC_CTL
);
779 DUMPREG(VENC_HTRIGGER_VTRIGGER
);
780 DUMPREG(VENC_SAVID__EAVID
);
781 DUMPREG(VENC_FLEN__FAL
);
782 DUMPREG(VENC_LAL__PHASE_RESET
);
783 DUMPREG(VENC_HS_INT_START_STOP_X
);
784 DUMPREG(VENC_HS_EXT_START_STOP_X
);
785 DUMPREG(VENC_VS_INT_START_X
);
786 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y
);
787 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X
);
788 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y
);
789 DUMPREG(VENC_VS_EXT_STOP_Y
);
790 DUMPREG(VENC_AVID_START_STOP_X
);
791 DUMPREG(VENC_AVID_START_STOP_Y
);
792 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y
);
793 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X
);
794 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y
);
795 DUMPREG(VENC_TVDETGP_INT_START_STOP_X
);
796 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y
);
797 DUMPREG(VENC_GEN_CTRL
);
798 DUMPREG(VENC_OUTPUT_CONTROL
);
799 DUMPREG(VENC_OUTPUT_TEST
);
806 static int venc_get_clocks(struct platform_device
*pdev
)
810 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK
)) {
811 clk
= clk_get(&pdev
->dev
, "tv_dac_clk");
813 DSSERR("can't get tv_dac_clk\n");
820 venc
.tv_dac_clk
= clk
;
825 static void venc_put_clocks(void)
828 clk_put(venc
.tv_dac_clk
);
831 static void __init
venc_probe_pdata(struct platform_device
*pdev
)
833 struct omap_dss_board_info
*pdata
= pdev
->dev
.platform_data
;
836 for (i
= 0; i
< pdata
->num_devices
; ++i
) {
837 struct omap_dss_device
*dssdev
= pdata
->devices
[i
];
839 if (dssdev
->type
!= OMAP_DISPLAY_TYPE_VENC
)
842 r
= venc_init_display(dssdev
);
844 DSSERR("device %s init failed: %d\n", dssdev
->name
, r
);
848 r
= omap_dss_register_device(dssdev
, &pdev
->dev
, i
);
850 DSSERR("device %s register failed: %d\n",
855 /* VENC HW IP initialisation */
856 static int __init
omap_venchw_probe(struct platform_device
*pdev
)
859 struct resource
*venc_mem
;
864 mutex_init(&venc
.venc_lock
);
868 venc_mem
= platform_get_resource(venc
.pdev
, IORESOURCE_MEM
, 0);
870 DSSERR("can't get IORESOURCE_MEM VENC\n");
874 venc
.base
= devm_ioremap(&pdev
->dev
, venc_mem
->start
,
875 resource_size(venc_mem
));
877 DSSERR("can't ioremap VENC\n");
881 r
= venc_get_clocks(pdev
);
885 pm_runtime_enable(&pdev
->dev
);
887 r
= venc_runtime_get();
889 goto err_runtime_get
;
891 rev_id
= (u8
)(venc_read_reg(VENC_REV_ID
) & 0xff);
892 dev_dbg(&pdev
->dev
, "OMAP VENC rev %d\n", rev_id
);
896 r
= omap_dss_register_driver(&venc_driver
);
898 goto err_reg_panel_driver
;
900 dss_debugfs_create_file("venc", venc_dump_regs
);
902 venc_probe_pdata(pdev
);
906 err_reg_panel_driver
:
908 pm_runtime_disable(&pdev
->dev
);
913 static int __exit
omap_venchw_remove(struct platform_device
*pdev
)
915 omap_dss_unregister_child_devices(&pdev
->dev
);
917 if (venc
.vdda_dac_reg
!= NULL
) {
918 regulator_put(venc
.vdda_dac_reg
);
919 venc
.vdda_dac_reg
= NULL
;
922 omap_dss_unregister_driver(&venc_driver
);
924 pm_runtime_disable(&pdev
->dev
);
930 static int venc_runtime_suspend(struct device
*dev
)
933 clk_disable(venc
.tv_dac_clk
);
940 static int venc_runtime_resume(struct device
*dev
)
944 r
= dispc_runtime_get();
949 clk_enable(venc
.tv_dac_clk
);
954 static const struct dev_pm_ops venc_pm_ops
= {
955 .runtime_suspend
= venc_runtime_suspend
,
956 .runtime_resume
= venc_runtime_resume
,
959 static struct platform_driver omap_venchw_driver
= {
960 .remove
= __exit_p(omap_venchw_remove
),
962 .name
= "omapdss_venc",
963 .owner
= THIS_MODULE
,
968 int __init
venc_init_platform_driver(void)
970 if (cpu_is_omap44xx())
973 return platform_driver_probe(&omap_venchw_driver
, omap_venchw_probe
);
976 void __exit
venc_uninit_platform_driver(void)
978 if (cpu_is_omap44xx())
981 platform_driver_unregister(&omap_venchw_driver
);