2 * Permedia2 framebuffer driver.
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
45 #include <video/permedia2.h>
46 #include <video/cvisionppc.h>
48 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
49 #error "The endianness of the target host has not been defined."
52 #if !defined(CONFIG_PCI)
53 #error "Only generic PCI cards supported."
56 #undef PM2FB_MASTER_DEBUG
57 #ifdef PM2FB_MASTER_DEBUG
58 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
60 #define DPRINTK(a,b...)
66 static char *mode __devinitdata
= NULL
;
69 * The XFree GLINT driver will (I think to implement hardware cursor
70 * support on TVP4010 and similar where there is no RAMDAC - see
71 * comment in set_video) always request +ve sync regardless of what
72 * the mode requires. This screws me because I have a Sun
73 * fixed-frequency monitor which absolutely has to have -ve sync. So
74 * these flags allow the user to specify that requests for +ve sync
75 * should be silently turned in -ve sync.
79 static int noaccel __devinitdata
;
82 static int nomtrr __devinitdata
;
86 * The hardware state of the graphics card that isn't part of the
91 pm2type_t type
; /* Board type */
92 unsigned char __iomem
*v_regs
;/* virtual address of p_regs */
93 u32 memclock
; /* memclock */
94 u32 video
; /* video flags before blanking */
95 u32 mem_config
; /* MemConfig reg at probe */
96 u32 mem_control
; /* MemControl reg at probe */
97 u32 boot_address
; /* BootAddress reg at probe */
103 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
104 * if we don't use modedb.
106 static struct fb_fix_screeninfo pm2fb_fix __devinitdata
= {
108 .type
= FB_TYPE_PACKED_PIXELS
,
109 .visual
= FB_VISUAL_PSEUDOCOLOR
,
113 .accel
= FB_ACCEL_3DLABS_PERMEDIA2
,
117 * Default video mode. In case the modedb doesn't work.
119 static struct fb_var_screeninfo pm2fb_var __devinitdata
= {
120 /* "640x480, 8 bpp @ 60 Hz */
129 .activate
= FB_ACTIVATE_NOW
,
140 .vmode
= FB_VMODE_NONINTERLACED
147 static inline u32
RD32(unsigned char __iomem
*base
, s32 off
)
149 return fb_readl(base
+ off
);
152 static inline void WR32(unsigned char __iomem
*base
, s32 off
, u32 v
)
154 fb_writel(v
, base
+ off
);
157 static inline u32
pm2_RD(struct pm2fb_par
* p
, s32 off
)
159 return RD32(p
->v_regs
, off
);
162 static inline void pm2_WR(struct pm2fb_par
* p
, s32 off
, u32 v
)
164 WR32(p
->v_regs
, off
, v
);
167 static inline u32
pm2_RDAC_RD(struct pm2fb_par
* p
, s32 idx
)
169 int index
= PM2R_RD_INDEXED_DATA
;
171 case PM2_TYPE_PERMEDIA2
:
172 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, idx
);
174 case PM2_TYPE_PERMEDIA2V
:
175 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
176 index
= PM2VR_RD_INDEXED_DATA
;
180 return pm2_RD(p
, index
);
183 static inline void pm2_RDAC_WR(struct pm2fb_par
* p
, s32 idx
, u32 v
)
185 int index
= PM2R_RD_INDEXED_DATA
;
187 case PM2_TYPE_PERMEDIA2
:
188 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, idx
);
190 case PM2_TYPE_PERMEDIA2V
:
191 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
192 index
= PM2VR_RD_INDEXED_DATA
;
200 static inline void pm2v_RDAC_WR(struct pm2fb_par
* p
, s32 idx
, u32 v
)
202 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
204 pm2_WR(p
, PM2VR_RD_INDEXED_DATA
, v
);
208 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
209 #define WAIT_FIFO(p, a)
211 static inline void WAIT_FIFO(struct pm2fb_par
* p
, u32 a
)
213 while( pm2_RD(p
, PM2R_IN_FIFO_SPACE
) < a
);
219 * partial products for the supported horizontal resolutions.
221 #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
222 static const struct {
226 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
227 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
228 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
229 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
230 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
231 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
232 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
233 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
234 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
235 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
236 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
237 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
238 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
239 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
240 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
241 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
244 static u32
partprod(u32 xres
)
248 for (i
= 0; pp_table
[i
].width
&& pp_table
[i
].width
!= xres
; i
++)
250 if ( pp_table
[i
].width
== 0 )
251 DPRINTK("invalid width %u\n", xres
);
252 return pp_table
[i
].pp
;
255 static u32
to3264(u32 timing
, int bpp
, int is64
)
265 timing
= (timing
* 3) >> (2 + is64
);
275 static void pm2_mnp(u32 clk
, unsigned char* mm
, unsigned char* nn
,
286 for (n
= 2; n
< 15; n
++) {
287 for (m
= 2; m
; m
++) {
288 f
= PM2_REFERENCE_CLOCK
* m
/ n
;
289 if (f
>= 150000 && f
<= 300000) {
290 for ( p
= 0; p
< 5; p
++, f
>>= 1) {
291 curr
= ( clk
> f
) ? clk
- f
: f
- clk
;
292 if ( curr
< delta
) {
304 static void pm2v_mnp(u32 clk
, unsigned char* mm
, unsigned char* nn
,
314 for ( m
= 1; m
< 128; m
++) {
315 for (n
= 2 * m
+ 1; n
; n
++) {
316 for ( p
= 0; p
< 2; p
++) {
317 f
= ( PM2_REFERENCE_CLOCK
>> ( p
+ 1 )) * n
/ m
;
318 if ( clk
> f
- delta
&& clk
< f
+ delta
) {
319 delta
= ( clk
> f
) ? clk
- f
: f
- clk
;
329 static void clear_palette(struct pm2fb_par
* p
) {
333 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, 0);
337 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
338 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
339 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
343 static void reset_card(struct pm2fb_par
* p
)
345 if (p
->type
== PM2_TYPE_PERMEDIA2V
)
346 pm2_WR(p
, PM2VR_RD_INDEX_HIGH
, 0);
347 pm2_WR(p
, PM2R_RESET_STATUS
, 0);
349 while (pm2_RD(p
, PM2R_RESET_STATUS
) & PM2F_BEING_RESET
)
352 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
353 DPRINTK("FIFO disconnect enabled\n");
354 pm2_WR(p
, PM2R_FIFO_DISCON
, 1);
358 /* Restore stashed memory config information from probe */
360 pm2_WR(p
, PM2R_MEM_CONTROL
, p
->mem_control
);
361 pm2_WR(p
, PM2R_BOOT_ADDRESS
, p
->boot_address
);
363 pm2_WR(p
, PM2R_MEM_CONFIG
, p
->mem_config
);
366 static void reset_config(struct pm2fb_par
* p
)
369 pm2_WR(p
, PM2R_CHIP_CONFIG
, pm2_RD(p
, PM2R_CHIP_CONFIG
) &
370 ~(PM2F_VGA_ENABLE
|PM2F_VGA_FIXED
));
371 pm2_WR(p
, PM2R_BYPASS_WRITE_MASK
, ~(0L));
372 pm2_WR(p
, PM2R_FRAMEBUFFER_WRITE_MASK
, ~(0L));
373 pm2_WR(p
, PM2R_FIFO_CONTROL
, 0);
374 pm2_WR(p
, PM2R_APERTURE_ONE
, 0);
375 pm2_WR(p
, PM2R_APERTURE_TWO
, 0);
376 pm2_WR(p
, PM2R_RASTERIZER_MODE
, 0);
377 pm2_WR(p
, PM2R_DELTA_MODE
, PM2F_DELTA_ORDER_RGB
);
378 pm2_WR(p
, PM2R_LB_READ_FORMAT
, 0);
379 pm2_WR(p
, PM2R_LB_WRITE_FORMAT
, 0);
380 pm2_WR(p
, PM2R_LB_READ_MODE
, 0);
381 pm2_WR(p
, PM2R_LB_SOURCE_OFFSET
, 0);
382 pm2_WR(p
, PM2R_FB_SOURCE_OFFSET
, 0);
383 pm2_WR(p
, PM2R_FB_PIXEL_OFFSET
, 0);
384 pm2_WR(p
, PM2R_FB_WINDOW_BASE
, 0);
385 pm2_WR(p
, PM2R_LB_WINDOW_BASE
, 0);
386 pm2_WR(p
, PM2R_FB_SOFT_WRITE_MASK
, ~(0L));
387 pm2_WR(p
, PM2R_FB_HARD_WRITE_MASK
, ~(0L));
388 pm2_WR(p
, PM2R_FB_READ_PIXEL
, 0);
389 pm2_WR(p
, PM2R_DITHER_MODE
, 0);
390 pm2_WR(p
, PM2R_AREA_STIPPLE_MODE
, 0);
391 pm2_WR(p
, PM2R_DEPTH_MODE
, 0);
392 pm2_WR(p
, PM2R_STENCIL_MODE
, 0);
393 pm2_WR(p
, PM2R_TEXTURE_ADDRESS_MODE
, 0);
394 pm2_WR(p
, PM2R_TEXTURE_READ_MODE
, 0);
395 pm2_WR(p
, PM2R_TEXEL_LUT_MODE
, 0);
396 pm2_WR(p
, PM2R_YUV_MODE
, 0);
397 pm2_WR(p
, PM2R_COLOR_DDA_MODE
, 0);
398 pm2_WR(p
, PM2R_TEXTURE_COLOR_MODE
, 0);
399 pm2_WR(p
, PM2R_FOG_MODE
, 0);
400 pm2_WR(p
, PM2R_ALPHA_BLEND_MODE
, 0);
401 pm2_WR(p
, PM2R_LOGICAL_OP_MODE
, 0);
402 pm2_WR(p
, PM2R_STATISTICS_MODE
, 0);
403 pm2_WR(p
, PM2R_SCISSOR_MODE
, 0);
404 pm2_WR(p
, PM2R_FILTER_MODE
, PM2F_SYNCHRONIZATION
);
406 case PM2_TYPE_PERMEDIA2
:
407 pm2_RDAC_WR(p
, PM2I_RD_MODE_CONTROL
, 0); /* no overlay */
408 pm2_RDAC_WR(p
, PM2I_RD_CURSOR_CONTROL
, 0);
409 pm2_RDAC_WR(p
, PM2I_RD_MISC_CONTROL
, PM2F_RD_PALETTE_WIDTH_8
);
411 case PM2_TYPE_PERMEDIA2V
:
412 pm2v_RDAC_WR(p
, PM2VI_RD_MISC_CONTROL
, 1); /* 8bit */
415 pm2_RDAC_WR(p
, PM2I_RD_COLOR_KEY_CONTROL
, 0);
416 pm2_RDAC_WR(p
, PM2I_RD_OVERLAY_KEY
, 0);
417 pm2_RDAC_WR(p
, PM2I_RD_RED_KEY
, 0);
418 pm2_RDAC_WR(p
, PM2I_RD_GREEN_KEY
, 0);
419 pm2_RDAC_WR(p
, PM2I_RD_BLUE_KEY
, 0);
422 static void set_aperture(struct pm2fb_par
* p
, u32 depth
)
425 * The hardware is little-endian. When used in big-endian
426 * hosts, the on-chip aperture settings are used where
427 * possible to translate from host to card byte order.
430 #ifdef __LITTLE_ENDIAN
431 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_STANDARD
);
434 case 24: /* RGB->BGR */
436 * We can't use the aperture to translate host to
437 * card byte order here, so we switch to BGR mode
438 * in pm2fb_set_par().
441 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_STANDARD
);
443 case 16: /* HL->LH */
444 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_HALFWORDSWAP
);
446 case 32: /* RGBA->ABGR */
447 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_BYTESWAP
);
452 // We don't use aperture two, so this may be superflous
453 pm2_WR(p
, PM2R_APERTURE_TWO
, PM2F_APERTURE_STANDARD
);
456 static void set_color(struct pm2fb_par
* p
, unsigned char regno
,
457 unsigned char r
, unsigned char g
, unsigned char b
)
460 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, regno
);
462 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, r
);
464 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, g
);
466 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, b
);
469 static void set_memclock(struct pm2fb_par
* par
, u32 clk
)
472 unsigned char m
, n
, p
;
475 case PM2_TYPE_PERMEDIA2V
:
476 pm2v_mnp(clk
/2, &m
, &n
, &p
);
478 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, PM2VI_RD_MCLK_CONTROL
>> 8);
479 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_CONTROL
, 0);
480 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_PRESCALE
, m
);
481 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_FEEDBACK
, n
);
482 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_POSTSCALE
, p
);
483 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_CONTROL
, 1);
486 i
&& !(pm2_RDAC_RD(par
, PM2VI_RD_MCLK_CONTROL
) & 2);
489 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
491 case PM2_TYPE_PERMEDIA2
:
492 pm2_mnp(clk
, &m
, &n
, &p
);
494 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_3
, 6);
495 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_1
, m
);
496 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_2
, n
);
497 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_3
, 8|p
);
498 pm2_RDAC_RD(par
, PM2I_RD_MEMORY_CLOCK_STATUS
);
501 i
&& !(pm2_RD(par
, PM2R_RD_INDEXED_DATA
) & PM2F_PLL_LOCKED
);
508 static void set_pixclock(struct pm2fb_par
* par
, u32 clk
)
511 unsigned char m
, n
, p
;
514 case PM2_TYPE_PERMEDIA2
:
515 pm2_mnp(clk
, &m
, &n
, &p
);
517 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A3
, 0);
518 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A1
, m
);
519 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A2
, n
);
520 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A3
, 8|p
);
521 pm2_RDAC_RD(par
, PM2I_RD_PIXEL_CLOCK_STATUS
);
524 i
&& !(pm2_RD(par
, PM2R_RD_INDEXED_DATA
) & PM2F_PLL_LOCKED
);
528 case PM2_TYPE_PERMEDIA2V
:
529 pm2v_mnp(clk
/2, &m
, &n
, &p
);
531 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, PM2VI_RD_CLK0_PRESCALE
>> 8);
532 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_PRESCALE
, m
);
533 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_FEEDBACK
, n
);
534 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_POSTSCALE
, p
);
535 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
540 static void set_video(struct pm2fb_par
* p
, u32 video
) {
546 DPRINTK("video = 0x%x\n", video
);
549 * The hardware cursor needs +vsync to recognise vert retrace.
550 * We may not be using the hardware cursor, but the X Glint
551 * driver may well. So always set +hsync/+vsync and then set
552 * the RAMDAC to invert the sync if necessary.
554 vsync
&= ~(PM2F_HSYNC_MASK
|PM2F_VSYNC_MASK
);
555 vsync
|= PM2F_HSYNC_ACT_HIGH
|PM2F_VSYNC_ACT_HIGH
;
558 pm2_WR(p
, PM2R_VIDEO_CONTROL
, vsync
);
561 case PM2_TYPE_PERMEDIA2
:
562 tmp
= PM2F_RD_PALETTE_WIDTH_8
;
563 if ((video
& PM2F_HSYNC_MASK
) == PM2F_HSYNC_ACT_LOW
)
564 tmp
|= 4; /* invert hsync */
565 if ((video
& PM2F_VSYNC_MASK
) == PM2F_VSYNC_ACT_LOW
)
566 tmp
|= 8; /* invert vsync */
567 pm2_RDAC_WR(p
, PM2I_RD_MISC_CONTROL
, tmp
);
569 case PM2_TYPE_PERMEDIA2V
:
571 if ((video
& PM2F_HSYNC_MASK
) == PM2F_HSYNC_ACT_LOW
)
572 tmp
|= 1; /* invert hsync */
573 if ((video
& PM2F_VSYNC_MASK
) == PM2F_VSYNC_ACT_LOW
)
574 tmp
|= 4; /* invert vsync */
575 pm2v_RDAC_WR(p
, PM2VI_RD_SYNC_CONTROL
, tmp
);
576 pm2v_RDAC_WR(p
, PM2VI_RD_MISC_CONTROL
, 1);
586 * pm2fb_check_var - Optional function. Validates a var passed in.
587 * @var: frame buffer variable screen structure
588 * @info: frame buffer structure that represents a single frame buffer
590 * Checks to see if the hardware supports the state requested by
593 * Returns negative errno on error, or zero on success.
595 static int pm2fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
599 if (var
->bits_per_pixel
!= 8 && var
->bits_per_pixel
!= 16 &&
600 var
->bits_per_pixel
!= 24 && var
->bits_per_pixel
!= 32) {
601 DPRINTK("depth not supported: %u\n", var
->bits_per_pixel
);
605 if (var
->xres
!= var
->xres_virtual
) {
606 DPRINTK("virtual x resolution != physical x resolution not supported\n");
610 if (var
->yres
> var
->yres_virtual
) {
611 DPRINTK("virtual y resolution < physical y resolution not possible\n");
616 DPRINTK("xoffset not supported\n");
620 if ((var
->vmode
& FB_VMODE_MASK
) == FB_VMODE_INTERLACED
) {
621 DPRINTK("interlace not supported\n");
625 var
->xres
= (var
->xres
+ 15) & ~15; /* could sometimes be 8 */
626 lpitch
= var
->xres
* ((var
->bits_per_pixel
+ 7)>>3);
628 if (var
->xres
< 320 || var
->xres
> 1600) {
629 DPRINTK("width not supported: %u\n", var
->xres
);
633 if (var
->yres
< 200 || var
->yres
> 1200) {
634 DPRINTK("height not supported: %u\n", var
->yres
);
638 if (lpitch
* var
->yres_virtual
> info
->fix
.smem_len
) {
639 DPRINTK("no memory for screen (%ux%ux%u)\n",
640 var
->xres
, var
->yres_virtual
, var
->bits_per_pixel
);
644 if (PICOS2KHZ(var
->pixclock
) > PM2_MAX_PIXCLOCK
) {
645 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var
->pixclock
));
649 var
->transp
.offset
= 0;
650 var
->transp
.length
= 0;
651 switch(var
->bits_per_pixel
) {
653 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
656 var
->red
.offset
= 11;
658 var
->green
.offset
= 5;
659 var
->green
.length
= 6;
660 var
->blue
.offset
= 0;
661 var
->blue
.length
= 5;
664 var
->transp
.offset
= 24;
665 var
->transp
.length
= 8;
666 var
->red
.offset
= 16;
667 var
->green
.offset
= 8;
668 var
->blue
.offset
= 0;
669 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
674 var
->blue
.offset
= 16;
676 var
->red
.offset
= 16;
677 var
->blue
.offset
= 0;
679 var
->green
.offset
= 8;
680 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
683 var
->height
= var
->width
= -1;
685 var
->accel_flags
= 0; /* Can't mmap if this is on */
687 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
688 var
->xres
, var
->yres
, var
->bits_per_pixel
);
693 * pm2fb_set_par - Alters the hardware state.
694 * @info: frame buffer structure that represents a single frame buffer
696 * Using the fb_var_screeninfo in fb_info we set the resolution of the
697 * this particular framebuffer.
699 static int pm2fb_set_par(struct fb_info
*info
)
701 struct pm2fb_par
*par
= info
->par
;
703 u32 width
, height
, depth
;
704 u32 hsstart
, hsend
, hbend
, htotal
;
705 u32 vsstart
, vsend
, vbend
, vtotal
;
709 u32 clrmode
= PM2F_RD_COLOR_MODE_RGB
| PM2F_RD_GUI_ACTIVE
;
720 set_memclock(par
, par
->memclock
);
722 width
= (info
->var
.xres_virtual
+ 7) & ~7;
723 height
= info
->var
.yres_virtual
;
724 depth
= (info
->var
.bits_per_pixel
+ 7) & ~7;
725 depth
= (depth
> 32) ? 32 : depth
;
726 data64
= depth
> 8 || par
->type
== PM2_TYPE_PERMEDIA2V
;
728 xres
= (info
->var
.xres
+ 31) & ~31;
729 pixclock
= PICOS2KHZ(info
->var
.pixclock
);
730 if (pixclock
> PM2_MAX_PIXCLOCK
) {
731 DPRINTK("pixclock too high (%uKHz)\n", pixclock
);
735 hsstart
= to3264(info
->var
.right_margin
, depth
, data64
);
736 hsend
= hsstart
+ to3264(info
->var
.hsync_len
, depth
, data64
);
737 hbend
= hsend
+ to3264(info
->var
.left_margin
, depth
, data64
);
738 htotal
= to3264(xres
, depth
, data64
) + hbend
- 1;
739 vsstart
= (info
->var
.lower_margin
)
740 ? info
->var
.lower_margin
- 1
742 vsend
= info
->var
.lower_margin
+ info
->var
.vsync_len
- 1;
743 vbend
= info
->var
.lower_margin
+ info
->var
.vsync_len
+ info
->var
.upper_margin
;
744 vtotal
= info
->var
.yres
+ vbend
- 1;
745 stride
= to3264(width
, depth
, 1);
746 base
= to3264(info
->var
.yoffset
* xres
+ info
->var
.xoffset
, depth
, 1);
748 video
|= PM2F_DATA_64_ENABLE
;
750 if (info
->var
.sync
& FB_SYNC_HOR_HIGH_ACT
) {
752 DPRINTK("ignoring +hsync, using -hsync.\n");
753 video
|= PM2F_HSYNC_ACT_LOW
;
755 video
|= PM2F_HSYNC_ACT_HIGH
;
758 video
|= PM2F_HSYNC_ACT_LOW
;
759 if (info
->var
.sync
& FB_SYNC_VERT_HIGH_ACT
) {
761 DPRINTK("ignoring +vsync, using -vsync.\n");
762 video
|= PM2F_VSYNC_ACT_LOW
;
764 video
|= PM2F_VSYNC_ACT_HIGH
;
767 video
|= PM2F_VSYNC_ACT_LOW
;
768 if ((info
->var
.vmode
& FB_VMODE_MASK
)==FB_VMODE_INTERLACED
) {
769 DPRINTK("interlaced not supported\n");
772 if ((info
->var
.vmode
& FB_VMODE_MASK
)==FB_VMODE_DOUBLE
)
773 video
|= PM2F_LINE_DOUBLE
;
774 if ((info
->var
.activate
& FB_ACTIVATE_MASK
)==FB_ACTIVATE_NOW
)
775 video
|= PM2F_VIDEO_ENABLE
;
779 (depth
== 8) ? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR
;
780 info
->fix
.line_length
= info
->var
.xres
* depth
/ 8;
781 info
->cmap
.len
= 256;
784 * Settings calculated. Now write them out.
786 if (par
->type
== PM2_TYPE_PERMEDIA2V
) {
788 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
791 set_aperture(par
, depth
);
795 pm2_RDAC_WR(par
, PM2I_RD_COLOR_KEY_CONTROL
,
796 ( depth
== 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF
);
799 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 0);
803 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 1);
804 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGB565
;
805 txtmap
= PM2F_TEXTEL_SIZE_16
;
810 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 2);
811 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGBA8888
;
812 txtmap
= PM2F_TEXTEL_SIZE_32
;
817 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 4);
818 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGB888
;
819 txtmap
= PM2F_TEXTEL_SIZE_24
;
824 pm2_WR(par
, PM2R_FB_WRITE_MODE
, PM2F_FB_WRITE_ENABLE
);
825 pm2_WR(par
, PM2R_FB_READ_MODE
, partprod(xres
));
826 pm2_WR(par
, PM2R_LB_READ_MODE
, partprod(xres
));
827 pm2_WR(par
, PM2R_TEXTURE_MAP_FORMAT
, txtmap
| partprod(xres
));
828 pm2_WR(par
, PM2R_H_TOTAL
, htotal
);
829 pm2_WR(par
, PM2R_HS_START
, hsstart
);
830 pm2_WR(par
, PM2R_HS_END
, hsend
);
831 pm2_WR(par
, PM2R_HG_END
, hbend
);
832 pm2_WR(par
, PM2R_HB_END
, hbend
);
833 pm2_WR(par
, PM2R_V_TOTAL
, vtotal
);
834 pm2_WR(par
, PM2R_VS_START
, vsstart
);
835 pm2_WR(par
, PM2R_VS_END
, vsend
);
836 pm2_WR(par
, PM2R_VB_END
, vbend
);
837 pm2_WR(par
, PM2R_SCREEN_STRIDE
, stride
);
839 pm2_WR(par
, PM2R_WINDOW_ORIGIN
, 0);
840 pm2_WR(par
, PM2R_SCREEN_SIZE
, (height
<< 16) | width
);
841 pm2_WR(par
, PM2R_SCISSOR_MODE
, PM2F_SCREEN_SCISSOR_ENABLE
);
843 pm2_WR(par
, PM2R_SCREEN_BASE
, base
);
845 set_video(par
, video
);
848 case PM2_TYPE_PERMEDIA2
:
849 pm2_RDAC_WR(par
, PM2I_RD_COLOR_MODE
, clrmode
);
851 case PM2_TYPE_PERMEDIA2V
:
852 pm2v_RDAC_WR(par
, PM2VI_RD_PIXEL_SIZE
, pixsize
);
853 pm2v_RDAC_WR(par
, PM2VI_RD_COLOR_FORMAT
, clrformat
);
856 set_pixclock(par
, pixclock
);
857 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
858 info
->var
.xres
, info
->var
.yres
, info
->var
.bits_per_pixel
);
863 * pm2fb_setcolreg - Sets a color register.
864 * @regno: boolean, 0 copy local, 1 get_user() function
865 * @red: frame buffer colormap structure
866 * @green: The green value which can be up to 16 bits wide
867 * @blue: The blue value which can be up to 16 bits wide.
868 * @transp: If supported the alpha value which can be up to 16 bits wide.
869 * @info: frame buffer info structure
871 * Set a single color register. The values supplied have a 16 bit
872 * magnitude which needs to be scaled in this function for the hardware.
873 * Pretty much a direct lift from tdfxfb.c.
875 * Returns negative errno on error, or zero on success.
877 static int pm2fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
,
878 unsigned blue
, unsigned transp
,
879 struct fb_info
*info
)
881 struct pm2fb_par
*par
= info
->par
;
883 if (regno
>= info
->cmap
.len
) /* no. of hw registers */
886 * Program hardware... do anything you want with transp
889 /* grayscale works only partially under directcolor */
890 if (info
->var
.grayscale
) {
891 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
892 red
= green
= blue
= (red
* 77 + green
* 151 + blue
* 28) >> 8;
896 * var->{color}.offset contains start of bitfield
897 * var->{color}.length contains length of bitfield
898 * {hardwarespecific} contains width of DAC
899 * cmap[X] is programmed to
900 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
901 * RAMDAC[X] is programmed to (red, green, blue)
904 * uses offset = 0 && length = DAC register width.
905 * var->{color}.offset is 0
906 * var->{color}.length contains widht of DAC
908 * DAC[X] is programmed to (red, green, blue)
910 * does not use RAMDAC (usually has 3 of them).
911 * var->{color}.offset contains start of bitfield
912 * var->{color}.length contains length of bitfield
913 * cmap is programmed to
914 * (red << red.offset) | (green << green.offset) |
915 * (blue << blue.offset) | (transp << transp.offset)
916 * RAMDAC does not exist
918 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
919 switch (info
->fix
.visual
) {
920 case FB_VISUAL_TRUECOLOR
:
921 case FB_VISUAL_PSEUDOCOLOR
:
922 red
= CNVT_TOHW(red
, info
->var
.red
.length
);
923 green
= CNVT_TOHW(green
, info
->var
.green
.length
);
924 blue
= CNVT_TOHW(blue
, info
->var
.blue
.length
);
925 transp
= CNVT_TOHW(transp
, info
->var
.transp
.length
);
927 case FB_VISUAL_DIRECTCOLOR
:
928 /* example here assumes 8 bit DAC. Might be different
929 * for your hardware */
930 red
= CNVT_TOHW(red
, 8);
931 green
= CNVT_TOHW(green
, 8);
932 blue
= CNVT_TOHW(blue
, 8);
933 /* hey, there is bug in transp handling... */
934 transp
= CNVT_TOHW(transp
, 8);
938 /* Truecolor has hardware independent palette */
939 if (info
->fix
.visual
== FB_VISUAL_TRUECOLOR
) {
945 v
= (red
<< info
->var
.red
.offset
) |
946 (green
<< info
->var
.green
.offset
) |
947 (blue
<< info
->var
.blue
.offset
) |
948 (transp
<< info
->var
.transp
.offset
);
950 switch (info
->var
.bits_per_pixel
) {
956 par
->palette
[regno
] = v
;
961 else if (info
->fix
.visual
== FB_VISUAL_PSEUDOCOLOR
)
962 set_color(par
, regno
, red
, green
, blue
);
968 * pm2fb_pan_display - Pans the display.
969 * @var: frame buffer variable screen structure
970 * @info: frame buffer structure that represents a single frame buffer
972 * Pan (or wrap, depending on the `vmode' field) the display using the
973 * `xoffset' and `yoffset' fields of the `var' structure.
974 * If the values don't fit, return -EINVAL.
976 * Returns negative errno on error, or zero on success.
979 static int pm2fb_pan_display(struct fb_var_screeninfo
*var
,
980 struct fb_info
*info
)
982 struct pm2fb_par
*p
= info
->par
;
987 xres
= (var
->xres
+ 31) & ~31;
988 depth
= (var
->bits_per_pixel
+ 7) & ~7;
989 depth
= (depth
> 32) ? 32 : depth
;
990 base
= to3264(var
->yoffset
* xres
+ var
->xoffset
, depth
, 1);
992 pm2_WR(p
, PM2R_SCREEN_BASE
, base
);
997 * pm2fb_blank - Blanks the display.
998 * @blank_mode: the blank mode we want.
999 * @info: frame buffer structure that represents a single frame buffer
1001 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
1002 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1003 * video mode which doesn't support it. Implements VESA suspend
1004 * and powerdown modes on hardware that supports disabling hsync/vsync:
1005 * blank_mode == 2: suspend vsync
1006 * blank_mode == 3: suspend hsync
1007 * blank_mode == 4: powerdown
1009 * Returns negative errno on error, or zero on success.
1012 static int pm2fb_blank(int blank_mode
, struct fb_info
*info
)
1014 struct pm2fb_par
*par
= info
->par
;
1015 u32 video
= par
->video
;
1017 DPRINTK("blank_mode %d\n", blank_mode
);
1019 switch (blank_mode
) {
1020 case FB_BLANK_UNBLANK
:
1022 video
|= PM2F_VIDEO_ENABLE
;
1024 case FB_BLANK_NORMAL
:
1026 video
&= ~PM2F_VIDEO_ENABLE
;
1028 case FB_BLANK_VSYNC_SUSPEND
:
1030 video
&= ~(PM2F_VSYNC_MASK
| PM2F_BLANK_LOW
);
1032 case FB_BLANK_HSYNC_SUSPEND
:
1034 video
&= ~(PM2F_HSYNC_MASK
| PM2F_BLANK_LOW
);
1036 case FB_BLANK_POWERDOWN
:
1037 /* HSync: Off, VSync: Off */
1038 video
&= ~(PM2F_VSYNC_MASK
| PM2F_HSYNC_MASK
| PM2F_BLANK_LOW
);
1041 set_video(par
, video
);
1045 static int pm2fb_sync(struct fb_info
*info
)
1047 struct pm2fb_par
*par
= info
->par
;
1050 pm2_WR(par
, PM2R_SYNC
, 0);
1053 while (pm2_RD(par
, PM2R_OUT_FIFO_WORDS
) == 0)
1056 } while (pm2_RD(par
, PM2R_OUT_FIFO
) != PM2TAG(PM2R_SYNC
));
1062 * block operation. copy=0: rectangle fill, copy=1: rectangle copy.
1064 static void pm2fb_block_op(struct fb_info
* info
, int copy
,
1066 s32 x
, s32 y
, s32 w
, s32 h
,
1068 struct pm2fb_par
*par
= info
->par
;
1073 pm2_WR(par
, PM2R_CONFIG
, PM2F_CONFIG_FB_WRITE_ENABLE
|
1074 PM2F_CONFIG_FB_READ_SOURCE_ENABLE
);
1076 pm2_WR(par
, PM2R_FB_SOURCE_DELTA
,
1077 ((ysrc
-y
) & 0xfff) << 16 | ((xsrc
-x
) & 0xfff));
1079 pm2_WR(par
, PM2R_FB_BLOCK_COLOR
, color
);
1080 pm2_WR(par
, PM2R_RECTANGLE_ORIGIN
, (y
<< 16) | x
);
1081 pm2_WR(par
, PM2R_RECTANGLE_SIZE
, (h
<< 16) | w
);
1083 pm2_WR(par
, PM2R_RENDER
, PM2F_RENDER_RECTANGLE
|
1084 (x
<xsrc
? PM2F_INCREASE_X
: 0) |
1085 (y
<ysrc
? PM2F_INCREASE_Y
: 0) |
1086 (copy
? 0 : PM2F_RENDER_FASTFILL
));
1089 static void pm2fb_fillrect (struct fb_info
*info
,
1090 const struct fb_fillrect
*region
)
1092 struct fb_fillrect modded
;
1094 u32 color
= (info
->fix
.visual
== FB_VISUAL_TRUECOLOR
) ?
1095 ((u32
*)info
->pseudo_palette
)[region
->color
] : region
->color
;
1097 if (info
->state
!= FBINFO_STATE_RUNNING
)
1099 if ((info
->flags
& FBINFO_HWACCEL_DISABLED
) ||
1100 region
->rop
!= ROP_COPY
) {
1101 cfb_fillrect(info
, region
);
1105 vxres
= info
->var
.xres_virtual
;
1106 vyres
= info
->var
.yres_virtual
;
1108 memcpy(&modded
, region
, sizeof(struct fb_fillrect
));
1110 if(!modded
.width
|| !modded
.height
||
1111 modded
.dx
>= vxres
|| modded
.dy
>= vyres
)
1114 if(modded
.dx
+ modded
.width
> vxres
)
1115 modded
.width
= vxres
- modded
.dx
;
1116 if(modded
.dy
+ modded
.height
> vyres
)
1117 modded
.height
= vyres
- modded
.dy
;
1119 if(info
->var
.bits_per_pixel
== 8)
1120 color
|= color
<< 8;
1121 if(info
->var
.bits_per_pixel
<= 16)
1122 color
|= color
<< 16;
1124 if(info
->var
.bits_per_pixel
!= 24)
1125 pm2fb_block_op(info
, 0, 0, 0,
1126 modded
.dx
, modded
.dy
,
1127 modded
.width
, modded
.height
, color
);
1129 cfb_fillrect(info
, region
);
1132 static void pm2fb_copyarea(struct fb_info
*info
,
1133 const struct fb_copyarea
*area
)
1135 struct fb_copyarea modded
;
1138 if (info
->state
!= FBINFO_STATE_RUNNING
)
1140 if (info
->flags
& FBINFO_HWACCEL_DISABLED
) {
1141 cfb_copyarea(info
, area
);
1145 memcpy(&modded
, area
, sizeof(struct fb_copyarea
));
1147 vxres
= info
->var
.xres_virtual
;
1148 vyres
= info
->var
.yres_virtual
;
1150 if(!modded
.width
|| !modded
.height
||
1151 modded
.sx
>= vxres
|| modded
.sy
>= vyres
||
1152 modded
.dx
>= vxres
|| modded
.dy
>= vyres
)
1155 if(modded
.sx
+ modded
.width
> vxres
)
1156 modded
.width
= vxres
- modded
.sx
;
1157 if(modded
.dx
+ modded
.width
> vxres
)
1158 modded
.width
= vxres
- modded
.dx
;
1159 if(modded
.sy
+ modded
.height
> vyres
)
1160 modded
.height
= vyres
- modded
.sy
;
1161 if(modded
.dy
+ modded
.height
> vyres
)
1162 modded
.height
= vyres
- modded
.dy
;
1164 pm2fb_block_op(info
, 1, modded
.sx
, modded
.sy
,
1165 modded
.dx
, modded
.dy
,
1166 modded
.width
, modded
.height
, 0);
1169 /* ------------ Hardware Independent Functions ------------ */
1172 * Frame buffer operations
1175 static struct fb_ops pm2fb_ops
= {
1176 .owner
= THIS_MODULE
,
1177 .fb_check_var
= pm2fb_check_var
,
1178 .fb_set_par
= pm2fb_set_par
,
1179 .fb_setcolreg
= pm2fb_setcolreg
,
1180 .fb_blank
= pm2fb_blank
,
1181 .fb_pan_display
= pm2fb_pan_display
,
1182 .fb_fillrect
= pm2fb_fillrect
,
1183 .fb_copyarea
= pm2fb_copyarea
,
1184 .fb_imageblit
= cfb_imageblit
,
1185 .fb_sync
= pm2fb_sync
,
1194 * Device initialisation
1196 * Initialise and allocate resource for PCI device.
1198 * @param pdev PCI device.
1199 * @param id PCI device ID.
1201 static int __devinit
pm2fb_probe(struct pci_dev
*pdev
,
1202 const struct pci_device_id
*id
)
1204 struct pm2fb_par
*default_par
;
1205 struct fb_info
*info
;
1206 int err
, err_retval
= -ENXIO
;
1208 err
= pci_enable_device(pdev
);
1210 printk(KERN_WARNING
"pm2fb: Can't enable pdev: %d\n", err
);
1214 info
= framebuffer_alloc(sizeof(struct pm2fb_par
), &pdev
->dev
);
1217 default_par
= info
->par
;
1219 switch (pdev
->device
) {
1220 case PCI_DEVICE_ID_TI_TVP4020
:
1221 strcpy(pm2fb_fix
.id
, "TVP4020");
1222 default_par
->type
= PM2_TYPE_PERMEDIA2
;
1224 case PCI_DEVICE_ID_3DLABS_PERMEDIA2
:
1225 strcpy(pm2fb_fix
.id
, "Permedia2");
1226 default_par
->type
= PM2_TYPE_PERMEDIA2
;
1228 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V
:
1229 strcpy(pm2fb_fix
.id
, "Permedia2v");
1230 default_par
->type
= PM2_TYPE_PERMEDIA2V
;
1234 pm2fb_fix
.mmio_start
= pci_resource_start(pdev
, 0);
1235 pm2fb_fix
.mmio_len
= PM2_REGS_SIZE
;
1237 #if defined(__BIG_ENDIAN)
1239 * PM2 has a 64k register file, mapped twice in 128k. Lower
1240 * map is little-endian, upper map is big-endian.
1242 pm2fb_fix
.mmio_start
+= PM2_REGS_SIZE
;
1243 DPRINTK("Adjusting register base for big-endian.\n");
1245 DPRINTK("Register base at 0x%lx\n", pm2fb_fix
.mmio_start
);
1247 /* Registers - request region and map it. */
1248 if ( !request_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
,
1249 "pm2fb regbase") ) {
1250 printk(KERN_WARNING
"pm2fb: Can't reserve regbase.\n");
1251 goto err_exit_neither
;
1253 default_par
->v_regs
=
1254 ioremap_nocache(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1255 if ( !default_par
->v_regs
) {
1256 printk(KERN_WARNING
"pm2fb: Can't remap %s register area.\n",
1258 release_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1259 goto err_exit_neither
;
1262 /* Stash away memory register info for use when we reset the board */
1263 default_par
->mem_control
= pm2_RD(default_par
, PM2R_MEM_CONTROL
);
1264 default_par
->boot_address
= pm2_RD(default_par
, PM2R_BOOT_ADDRESS
);
1265 default_par
->mem_config
= pm2_RD(default_par
, PM2R_MEM_CONFIG
);
1266 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1267 default_par
->mem_control
, default_par
->boot_address
,
1268 default_par
->mem_config
);
1270 if(default_par
->mem_control
== 0 &&
1271 default_par
->boot_address
== 0x31 &&
1272 default_par
->mem_config
== 0x259fffff) {
1273 default_par
->memclock
= CVPPC_MEMCLOCK
;
1274 default_par
->mem_control
=0;
1275 default_par
->boot_address
=0x20;
1276 default_par
->mem_config
=0xe6002021;
1277 if (pdev
->subsystem_vendor
== 0x1048 &&
1278 pdev
->subsystem_device
== 0x0a31) {
1279 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1280 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1281 DPRINTK("We have not been initialized by VGA BIOS "
1282 "and are running on an Elsa Winner 2000 Office\n");
1283 DPRINTK("Initializing card timings manually...\n");
1284 default_par
->memclock
=70000;
1286 if (pdev
->subsystem_vendor
== 0x3d3d &&
1287 pdev
->subsystem_device
== 0x0100) {
1288 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1289 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1290 DPRINTK("We have not been initialized by VGA BIOS "
1291 "and are running on an 3dlabs reference board\n");
1292 DPRINTK("Initializing card timings manually...\n");
1293 default_par
->memclock
=74894;
1297 /* Now work out how big lfb is going to be. */
1298 switch(default_par
->mem_config
& PM2F_MEM_CONFIG_RAM_MASK
) {
1299 case PM2F_MEM_BANKS_1
:
1300 pm2fb_fix
.smem_len
=0x200000;
1302 case PM2F_MEM_BANKS_2
:
1303 pm2fb_fix
.smem_len
=0x400000;
1305 case PM2F_MEM_BANKS_3
:
1306 pm2fb_fix
.smem_len
=0x600000;
1308 case PM2F_MEM_BANKS_4
:
1309 pm2fb_fix
.smem_len
=0x800000;
1312 pm2fb_fix
.smem_start
= pci_resource_start(pdev
, 1);
1314 /* Linear frame buffer - request region and map it. */
1315 if ( !request_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
,
1317 printk(KERN_WARNING
"pm2fb: Can't reserve smem.\n");
1321 ioremap_nocache(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1322 if ( !info
->screen_base
) {
1323 printk(KERN_WARNING
"pm2fb: Can't ioremap smem area.\n");
1324 release_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1329 default_par
->mtrr_handle
= -1;
1331 default_par
->mtrr_handle
=
1332 mtrr_add(pm2fb_fix
.smem_start
,
1334 MTRR_TYPE_WRCOMB
, 1);
1337 info
->fbops
= &pm2fb_ops
;
1338 info
->fix
= pm2fb_fix
;
1339 info
->pseudo_palette
= default_par
->palette
;
1340 info
->flags
= FBINFO_DEFAULT
|
1341 FBINFO_HWACCEL_YPAN
|
1342 FBINFO_HWACCEL_COPYAREA
|
1343 FBINFO_HWACCEL_FILLRECT
;
1346 printk(KERN_DEBUG
"disabling acceleration\n");
1347 info
->flags
|= FBINFO_HWACCEL_DISABLED
;
1351 mode
= "640x480@60";
1353 err
= fb_find_mode(&info
->var
, info
, mode
, NULL
, 0, NULL
, 8);
1354 if (!err
|| err
== 4)
1355 info
->var
= pm2fb_var
;
1357 if (fb_alloc_cmap(&info
->cmap
, 256, 0) < 0)
1360 if (register_framebuffer(info
) < 0)
1363 printk(KERN_INFO
"fb%d: %s frame buffer device, memory = %dK.\n",
1364 info
->node
, info
->fix
.id
, pm2fb_fix
.smem_len
/ 1024);
1369 pci_set_drvdata(pdev
, info
);
1374 fb_dealloc_cmap(&info
->cmap
);
1376 iounmap(info
->screen_base
);
1377 release_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1379 iounmap(default_par
->v_regs
);
1380 release_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1382 framebuffer_release(info
);
1389 * Release all device resources.
1391 * @param pdev PCI device to clean up.
1393 static void __devexit
pm2fb_remove(struct pci_dev
*pdev
)
1395 struct fb_info
* info
= pci_get_drvdata(pdev
);
1396 struct fb_fix_screeninfo
* fix
= &info
->fix
;
1397 struct pm2fb_par
*par
= info
->par
;
1399 unregister_framebuffer(info
);
1402 if (par
->mtrr_handle
>= 0)
1403 mtrr_del(par
->mtrr_handle
, info
->fix
.smem_start
,
1404 info
->fix
.smem_len
);
1405 #endif /* CONFIG_MTRR */
1406 iounmap(info
->screen_base
);
1407 release_mem_region(fix
->smem_start
, fix
->smem_len
);
1408 iounmap(par
->v_regs
);
1409 release_mem_region(fix
->mmio_start
, fix
->mmio_len
);
1411 pci_set_drvdata(pdev
, NULL
);
1415 static struct pci_device_id pm2fb_id_table
[] = {
1416 { PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_TVP4020
,
1417 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1419 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2
,
1420 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1422 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2V
,
1423 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1425 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2V
,
1426 PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_NOT_DEFINED_VGA
<< 8,
1431 static struct pci_driver pm2fb_driver
= {
1433 .id_table
= pm2fb_id_table
,
1434 .probe
= pm2fb_probe
,
1435 .remove
= __devexit_p(pm2fb_remove
),
1438 MODULE_DEVICE_TABLE(pci
, pm2fb_id_table
);
1443 * Parse user speficied options.
1445 * This is, comma-separated options following `video=pm2fb:'.
1447 static int __init
pm2fb_setup(char *options
)
1451 if (!options
|| !*options
)
1454 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1457 if(!strcmp(this_opt
, "lowhsync")) {
1459 } else if(!strcmp(this_opt
, "lowvsync")) {
1462 } else if (!strncmp(this_opt
, "nomtrr", 6)) {
1465 } else if (!strncmp(this_opt
, "noaccel", 7)) {
1476 static int __init
pm2fb_init(void)
1479 char *option
= NULL
;
1481 if (fb_get_options("pm2fb", &option
))
1483 pm2fb_setup(option
);
1486 return pci_register_driver(&pm2fb_driver
);
1489 module_init(pm2fb_init
);
1496 static void __exit
pm2fb_exit(void)
1498 pci_unregister_driver(&pm2fb_driver
);
1503 module_exit(pm2fb_exit
);
1505 module_param(mode
, charp
, 0);
1506 MODULE_PARM_DESC(mode
, "Preferred video mode e.g. '648x480-8@60'");
1507 module_param(lowhsync
, bool, 0);
1508 MODULE_PARM_DESC(lowhsync
, "Force horizontal sync low regardless of mode");
1509 module_param(lowvsync
, bool, 0);
1510 MODULE_PARM_DESC(lowvsync
, "Force vertical sync low regardless of mode");
1511 module_param(noaccel
, bool, 0);
1512 MODULE_PARM_DESC(noaccel
, "Disable acceleration");
1514 module_param(nomtrr
, bool, 0);
1515 MODULE_PARM_DESC(nomtrr
, "Disable MTRR support (0 or 1=disabled) (default=0)");
1518 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1519 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1520 MODULE_LICENSE("GPL");