2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
19 * - use readl/writel instead of __raw_writel/__raw_readl
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
24 * - Replaced 0 and 1 by on or off when reading the
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exist
35 * - Added LCD power sysfs interface
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
65 * - added a forgotten return in h1940fb_init
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/workqueue.h>
86 #include <linux/wait.h>
87 #include <linux/platform_device.h>
88 #include <linux/clk.h>
91 #include <asm/uaccess.h>
92 #include <asm/div64.h>
94 #include <asm/mach/map.h>
95 #include <asm/arch/regs-lcd.h>
96 #include <asm/arch/regs-gpio.h>
97 #include <asm/arch/fb.h>
100 #include <linux/pm.h>
103 #include "s3c2410fb.h"
105 static struct s3c2410fb_mach_info
*mach_info
;
107 /* Debugging stuff */
108 #ifdef CONFIG_FB_S3C2410_DEBUG
109 static int debug
= 1;
111 static int debug
= 0;
114 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
116 /* useful functions */
118 /* s3c2410fb_set_lcdaddr
120 * initialise lcd controller address pointers
122 static void s3c2410fb_set_lcdaddr(struct fb_info
*info
)
124 unsigned long saddr1
, saddr2
, saddr3
;
125 int line_length
= info
->var
.xres
* info
->var
.bits_per_pixel
;
127 saddr1
= info
->fix
.smem_start
>> 1;
128 saddr2
= info
->fix
.smem_start
;
129 saddr2
+= (line_length
* info
->var
.yres
) / 8;
132 saddr3
= S3C2410_OFFSIZE(0) |
133 S3C2410_PAGEWIDTH((line_length
/ 16) & 0x3ff);
135 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1
);
136 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2
);
137 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3
);
139 writel(saddr1
, S3C2410_LCDSADDR1
);
140 writel(saddr2
, S3C2410_LCDSADDR2
);
141 writel(saddr3
, S3C2410_LCDSADDR3
);
144 /* s3c2410fb_calc_pixclk()
146 * calculate divisor for clk->pixclk
148 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info
*fbi
,
149 unsigned long pixclk
)
151 unsigned long clk
= clk_get_rate(fbi
->clk
);
152 unsigned long long div
;
154 /* pixclk is in picoseoncds, our clock is in Hz
156 * Hz -> picoseconds is / 10^-12
159 div
= (unsigned long long)clk
* pixclk
;
160 do_div(div
, 1000000UL);
161 do_div(div
, 1000000UL);
163 dprintk("pixclk %ld, divisor is %ld\n", pixclk
, (long)div
);
168 * s3c2410fb_check_var():
169 * Get the video params out of 'var'. If a value doesn't fit, round it up,
170 * if it's too big, return -EINVAL.
173 static int s3c2410fb_check_var(struct fb_var_screeninfo
*var
,
174 struct fb_info
*info
)
176 struct s3c2410fb_info
*fbi
= info
->par
;
177 struct s3c2410fb_mach_info
*mach_info
= fbi
->mach_info
;
178 struct s3c2410fb_display
*display
= NULL
;
181 dprintk("check_var(var=%p, info=%p)\n", var
, info
);
183 /* validate x/y resolution */
185 for (i
= 0; i
< mach_info
->num_displays
; i
++)
186 if (var
->yres
== mach_info
->displays
[i
].yres
&&
187 var
->xres
== mach_info
->displays
[i
].xres
&&
188 var
->bits_per_pixel
== mach_info
->displays
[i
].bpp
) {
189 display
= mach_info
->displays
+ i
;
190 fbi
->current_display
= i
;
195 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
196 var
->xres
, var
->yres
, var
->bits_per_pixel
);
200 /* it is always the size as the display */
201 var
->xres_virtual
= display
->xres
;
202 var
->yres_virtual
= display
->yres
;
204 /* copy lcd settings */
205 var
->left_margin
= display
->left_margin
;
206 var
->right_margin
= display
->right_margin
;
208 var
->transp
.offset
= 0;
209 var
->transp
.length
= 0;
210 /* set r/g/b positions */
211 switch (var
->bits_per_pixel
) {
216 var
->red
.length
= var
->bits_per_pixel
;
217 var
->green
= var
->red
;
218 var
->blue
= var
->red
;
221 if (display
->type
!= S3C2410_LCDCON1_TFT
) {
225 var
->green
.length
= 3;
226 var
->green
.offset
= 2;
227 var
->blue
.length
= 2;
228 var
->blue
.offset
= 0;
232 var
->green
= var
->red
;
233 var
->blue
= var
->red
;
240 var
->green
.length
= 4;
241 var
->green
.offset
= 4;
242 var
->blue
.length
= 4;
243 var
->blue
.offset
= 0;
248 if (display
->lcdcon5
& S3C2410_LCDCON5_FRM565
) {
249 /* 16 bpp, 565 format */
250 var
->red
.offset
= 11;
251 var
->green
.offset
= 5;
252 var
->blue
.offset
= 0;
254 var
->green
.length
= 6;
255 var
->blue
.length
= 5;
257 /* 16 bpp, 5551 format */
258 var
->red
.offset
= 11;
259 var
->green
.offset
= 6;
260 var
->blue
.offset
= 1;
262 var
->green
.length
= 5;
263 var
->blue
.length
= 5;
269 var
->red
.offset
= 16;
270 var
->green
.length
= 8;
271 var
->green
.offset
= 8;
272 var
->blue
.length
= 8;
273 var
->blue
.offset
= 0;
281 /* s3c2410fb_calculate_stn_lcd_regs
283 * calculate register values from var settings
285 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info
*info
,
286 struct s3c2410fb_hw
*regs
)
288 const struct s3c2410fb_info
*fbi
= info
->par
;
289 const struct fb_var_screeninfo
*var
= &info
->var
;
290 int type
= regs
->lcdcon1
& ~S3C2410_LCDCON1_TFT
;
291 int hs
= var
->xres
>> 2;
292 unsigned wdly
= (var
->left_margin
>> 4) - 1;
293 unsigned wlh
= (var
->hsync_len
>> 4) - 1;
295 dprintk("%s: var->xres = %d\n", __FUNCTION__
, var
->xres
);
296 dprintk("%s: var->yres = %d\n", __FUNCTION__
, var
->yres
);
297 dprintk("%s: var->bpp = %d\n", __FUNCTION__
, var
->bits_per_pixel
);
299 if (type
!= S3C2410_LCDCON1_STN4
)
302 regs
->lcdcon1
&= ~S3C2410_LCDCON1_MODEMASK
;
304 switch (var
->bits_per_pixel
) {
306 regs
->lcdcon1
|= S3C2410_LCDCON1_STN1BPP
;
309 regs
->lcdcon1
|= S3C2410_LCDCON1_STN2GREY
;
312 regs
->lcdcon1
|= S3C2410_LCDCON1_STN4GREY
;
315 regs
->lcdcon1
|= S3C2410_LCDCON1_STN8BPP
;
319 regs
->lcdcon1
|= S3C2410_LCDCON1_STN12BPP
;
324 /* invalid pixel depth */
325 dev_err(fbi
->dev
, "invalid bpp %d\n",
326 var
->bits_per_pixel
);
328 /* update X/Y info */
329 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
330 var
->left_margin
, var
->right_margin
, var
->hsync_len
);
332 regs
->lcdcon2
= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1);
340 regs
->lcdcon3
= S3C2410_LCDCON3_WDLY(wdly
) |
341 S3C2410_LCDCON3_LINEBLANK(var
->right_margin
/ 8) |
342 S3C2410_LCDCON3_HOZVAL(hs
- 1);
344 regs
->lcdcon4
= S3C2410_LCDCON4_WLH(wlh
);
347 /* s3c2410fb_calculate_tft_lcd_regs
349 * calculate register values from var settings
351 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info
*info
,
352 struct s3c2410fb_hw
*regs
)
354 const struct s3c2410fb_info
*fbi
= info
->par
;
355 const struct fb_var_screeninfo
*var
= &info
->var
;
357 dprintk("%s: var->xres = %d\n", __FUNCTION__
, var
->xres
);
358 dprintk("%s: var->yres = %d\n", __FUNCTION__
, var
->yres
);
359 dprintk("%s: var->bpp = %d\n", __FUNCTION__
, var
->bits_per_pixel
);
361 regs
->lcdcon1
&= ~S3C2410_LCDCON1_MODEMASK
;
363 switch (var
->bits_per_pixel
) {
365 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT1BPP
;
368 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT2BPP
;
371 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT4BPP
;
374 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT8BPP
;
377 regs
->lcdcon1
|= S3C2410_LCDCON1_TFT16BPP
;
381 /* invalid pixel depth */
382 dev_err(fbi
->dev
, "invalid bpp %d\n",
383 var
->bits_per_pixel
);
385 /* update X/Y info */
386 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
387 var
->upper_margin
, var
->lower_margin
, var
->vsync_len
);
389 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
390 var
->left_margin
, var
->right_margin
, var
->hsync_len
);
392 regs
->lcdcon2
= S3C2410_LCDCON2_LINEVAL(var
->yres
- 1) |
393 S3C2410_LCDCON2_VBPD(var
->upper_margin
- 1) |
394 S3C2410_LCDCON2_VFPD(var
->lower_margin
- 1) |
395 S3C2410_LCDCON2_VSPW(var
->vsync_len
- 1);
397 regs
->lcdcon3
= S3C2410_LCDCON3_HBPD(var
->right_margin
- 1) |
398 S3C2410_LCDCON3_HFPD(var
->left_margin
- 1) |
399 S3C2410_LCDCON3_HOZVAL(var
->xres
- 1);
401 regs
->lcdcon4
= S3C2410_LCDCON4_HSPW(var
->hsync_len
- 1);
404 /* s3c2410fb_activate_var
406 * activate (set) the controller from the given framebuffer
409 static void s3c2410fb_activate_var(struct fb_info
*info
)
411 struct s3c2410fb_info
*fbi
= info
->par
;
412 struct fb_var_screeninfo
*var
= &info
->var
;
413 struct s3c2410fb_mach_info
*mach_info
= fbi
->mach_info
;
414 struct s3c2410fb_display
*display
= mach_info
->displays
+
415 fbi
->current_display
;
417 /* set display type */
418 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_TFT
;
419 fbi
->regs
.lcdcon1
|= display
->type
;
421 if (var
->pixclock
> 0) {
422 int clkdiv
= s3c2410fb_calc_pixclk(fbi
, var
->pixclock
);
424 if (display
->type
== S3C2410_LCDCON1_TFT
) {
425 clkdiv
= (clkdiv
/ 2) - 1;
429 clkdiv
= (clkdiv
/ 2);
434 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
435 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_CLKVAL(clkdiv
);
438 if (display
->type
== S3C2410_LCDCON1_TFT
)
439 s3c2410fb_calculate_tft_lcd_regs(info
, &fbi
->regs
);
441 s3c2410fb_calculate_stn_lcd_regs(info
, &fbi
->regs
);
443 /* write new registers */
445 dprintk("new register set:\n");
446 dprintk("lcdcon[1] = 0x%08lx\n", fbi
->regs
.lcdcon1
);
447 dprintk("lcdcon[2] = 0x%08lx\n", fbi
->regs
.lcdcon2
);
448 dprintk("lcdcon[3] = 0x%08lx\n", fbi
->regs
.lcdcon3
);
449 dprintk("lcdcon[4] = 0x%08lx\n", fbi
->regs
.lcdcon4
);
450 dprintk("lcdcon[5] = 0x%08lx\n", fbi
->regs
.lcdcon5
);
452 writel(fbi
->regs
.lcdcon1
& ~S3C2410_LCDCON1_ENVID
, S3C2410_LCDCON1
);
453 writel(fbi
->regs
.lcdcon2
, S3C2410_LCDCON2
);
454 writel(fbi
->regs
.lcdcon3
, S3C2410_LCDCON3
);
455 writel(fbi
->regs
.lcdcon4
, S3C2410_LCDCON4
);
456 writel(fbi
->regs
.lcdcon5
, S3C2410_LCDCON5
);
458 /* set lcd address pointers */
459 s3c2410fb_set_lcdaddr(info
);
461 writel(fbi
->regs
.lcdcon1
, S3C2410_LCDCON1
);
465 * s3c2410fb_set_par - Alters the hardware state.
466 * @info: frame buffer structure that represents a single frame buffer
469 static int s3c2410fb_set_par(struct fb_info
*info
)
471 struct fb_var_screeninfo
*var
= &info
->var
;
473 switch (var
->bits_per_pixel
) {
475 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
478 info
->fix
.visual
= FB_VISUAL_MONO01
;
481 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
485 info
->fix
.line_length
= (var
->width
* var
->bits_per_pixel
) / 8;
487 /* activate this new configuration */
489 s3c2410fb_activate_var(info
);
493 static void schedule_palette_update(struct s3c2410fb_info
*fbi
,
494 unsigned int regno
, unsigned int val
)
498 void __iomem
*regs
= fbi
->io
;
500 local_irq_save(flags
);
502 fbi
->palette_buffer
[regno
] = val
;
504 if (!fbi
->palette_ready
) {
505 fbi
->palette_ready
= 1;
508 irqen
= readl(regs
+ S3C2410_LCDINTMSK
);
509 irqen
&= ~S3C2410_LCDINT_FRSYNC
;
510 writel(irqen
, regs
+ S3C2410_LCDINTMSK
);
513 local_irq_restore(flags
);
517 static inline unsigned int chan_to_field(unsigned int chan
,
518 struct fb_bitfield
*bf
)
521 chan
>>= 16 - bf
->length
;
522 return chan
<< bf
->offset
;
525 static int s3c2410fb_setcolreg(unsigned regno
,
526 unsigned red
, unsigned green
, unsigned blue
,
527 unsigned transp
, struct fb_info
*info
)
529 struct s3c2410fb_info
*fbi
= info
->par
;
532 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
533 regno, red, green, blue); */
535 switch (info
->fix
.visual
) {
536 case FB_VISUAL_TRUECOLOR
:
537 /* true-colour, use pseudo-palette */
540 u32
*pal
= info
->pseudo_palette
;
542 val
= chan_to_field(red
, &info
->var
.red
);
543 val
|= chan_to_field(green
, &info
->var
.green
);
544 val
|= chan_to_field(blue
, &info
->var
.blue
);
550 case FB_VISUAL_PSEUDOCOLOR
:
552 /* currently assume RGB 5-6-5 mode */
554 val
= ((red
>> 0) & 0xf800);
555 val
|= ((green
>> 5) & 0x07e0);
556 val
|= ((blue
>> 11) & 0x001f);
558 writel(val
, S3C2410_TFTPAL(regno
));
559 schedule_palette_update(fbi
, regno
, val
);
565 return 1; /* unknown type */
573 * @blank_mode: the blank mode we want.
574 * @info: frame buffer structure that represents a single frame buffer
576 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
577 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
578 * video mode which doesn't support it. Implements VESA suspend
579 * and powerdown modes on hardware that supports disabling hsync/vsync:
580 * blank_mode == 2: suspend vsync
581 * blank_mode == 3: suspend hsync
582 * blank_mode == 4: powerdown
584 * Returns negative errno on error, or zero on success.
587 static int s3c2410fb_blank(int blank_mode
, struct fb_info
*info
)
589 dprintk("blank(mode=%d, info=%p)\n", blank_mode
, info
);
591 if (mach_info
== NULL
)
594 if (blank_mode
== FB_BLANK_UNBLANK
)
595 writel(0x0, S3C2410_TPAL
);
597 dprintk("setting TPAL to output 0x000000\n");
598 writel(S3C2410_TPAL_EN
, S3C2410_TPAL
);
604 static int s3c2410fb_debug_show(struct device
*dev
,
605 struct device_attribute
*attr
, char *buf
)
607 return snprintf(buf
, PAGE_SIZE
, "%s\n", debug
? "on" : "off");
609 static int s3c2410fb_debug_store(struct device
*dev
,
610 struct device_attribute
*attr
,
611 const char *buf
, size_t len
)
613 if (mach_info
== NULL
)
619 if (strnicmp(buf
, "on", 2) == 0 ||
620 strnicmp(buf
, "1", 1) == 0) {
622 printk(KERN_DEBUG
"s3c2410fb: Debug On");
623 } else if (strnicmp(buf
, "off", 3) == 0 ||
624 strnicmp(buf
, "0", 1) == 0) {
626 printk(KERN_DEBUG
"s3c2410fb: Debug Off");
634 static DEVICE_ATTR(debug
, 0666, s3c2410fb_debug_show
, s3c2410fb_debug_store
);
636 static struct fb_ops s3c2410fb_ops
= {
637 .owner
= THIS_MODULE
,
638 .fb_check_var
= s3c2410fb_check_var
,
639 .fb_set_par
= s3c2410fb_set_par
,
640 .fb_blank
= s3c2410fb_blank
,
641 .fb_setcolreg
= s3c2410fb_setcolreg
,
642 .fb_fillrect
= cfb_fillrect
,
643 .fb_copyarea
= cfb_copyarea
,
644 .fb_imageblit
= cfb_imageblit
,
648 * s3c2410fb_map_video_memory():
649 * Allocates the DRAM memory for the frame buffer. This buffer is
650 * remapped into a non-cached, non-buffered, memory region to
651 * allow palette and pixel writes to occur without flushing the
652 * cache. Once this area is remapped, all virtual memory
653 * access to the video memory should occur at the new region.
655 static int __init
s3c2410fb_map_video_memory(struct fb_info
*info
)
657 struct s3c2410fb_info
*fbi
= info
->par
;
659 dprintk("map_video_memory(fbi=%p)\n", fbi
);
661 fbi
->map_size
= PAGE_ALIGN(info
->fix
.smem_len
+ PAGE_SIZE
);
662 fbi
->map_cpu
= dma_alloc_writecombine(fbi
->dev
, fbi
->map_size
,
663 &fbi
->map_dma
, GFP_KERNEL
);
665 fbi
->map_size
= info
->fix
.smem_len
;
668 /* prevent initial garbage on screen */
669 dprintk("map_video_memory: clear %p:%08x\n",
670 fbi
->map_cpu
, fbi
->map_size
);
671 memset(fbi
->map_cpu
, 0xf0, fbi
->map_size
);
673 fbi
->screen_dma
= fbi
->map_dma
;
674 info
->screen_base
= fbi
->map_cpu
;
675 info
->fix
.smem_start
= fbi
->screen_dma
;
677 dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
678 fbi
->map_dma
, fbi
->map_cpu
, info
->fix
.smem_len
);
681 return fbi
->map_cpu
? 0 : -ENOMEM
;
684 static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info
*fbi
)
686 dma_free_writecombine(fbi
->dev
, fbi
->map_size
, fbi
->map_cpu
,
690 static inline void modify_gpio(void __iomem
*reg
,
691 unsigned long set
, unsigned long mask
)
695 tmp
= readl(reg
) & ~mask
;
696 writel(tmp
| set
, reg
);
700 * s3c2410fb_init_registers - Initialise all LCD-related registers
702 static int s3c2410fb_init_registers(struct fb_info
*info
)
704 struct s3c2410fb_info
*fbi
= info
->par
;
706 void __iomem
*regs
= fbi
->io
;
708 /* Initialise LCD with values from haret */
710 local_irq_save(flags
);
712 /* modify the gpio(s) with interrupts set (bjd) */
714 modify_gpio(S3C2410_GPCUP
, mach_info
->gpcup
, mach_info
->gpcup_mask
);
715 modify_gpio(S3C2410_GPCCON
, mach_info
->gpccon
, mach_info
->gpccon_mask
);
716 modify_gpio(S3C2410_GPDUP
, mach_info
->gpdup
, mach_info
->gpdup_mask
);
717 modify_gpio(S3C2410_GPDCON
, mach_info
->gpdcon
, mach_info
->gpdcon_mask
);
719 local_irq_restore(flags
);
721 writel(fbi
->regs
.lcdcon1
, regs
+ S3C2410_LCDCON1
);
722 writel(fbi
->regs
.lcdcon2
, regs
+ S3C2410_LCDCON2
);
723 writel(fbi
->regs
.lcdcon3
, regs
+ S3C2410_LCDCON3
);
724 writel(fbi
->regs
.lcdcon4
, regs
+ S3C2410_LCDCON4
);
725 writel(fbi
->regs
.lcdcon5
, regs
+ S3C2410_LCDCON5
);
727 s3c2410fb_set_lcdaddr(info
);
729 dprintk("LPCSEL = 0x%08lx\n", mach_info
->lpcsel
);
730 writel(mach_info
->lpcsel
, regs
+ S3C2410_LPCSEL
);
732 dprintk("replacing TPAL %08x\n", readl(regs
+ S3C2410_TPAL
));
734 /* ensure temporary palette disabled */
735 writel(0x00, regs
+ S3C2410_TPAL
);
737 /* Enable video by setting the ENVID bit to 1 */
738 fbi
->regs
.lcdcon1
|= S3C2410_LCDCON1_ENVID
;
739 writel(fbi
->regs
.lcdcon1
, regs
+ S3C2410_LCDCON1
);
743 static void s3c2410fb_write_palette(struct s3c2410fb_info
*fbi
)
746 void __iomem
*regs
= fbi
->io
;
748 fbi
->palette_ready
= 0;
750 for (i
= 0; i
< 256; i
++) {
751 unsigned long ent
= fbi
->palette_buffer
[i
];
752 if (ent
== PALETTE_BUFF_CLEAR
)
755 writel(ent
, regs
+ S3C2410_TFTPAL(i
));
757 /* it seems the only way to know exactly
758 * if the palette wrote ok, is to check
759 * to see if the value verifies ok
762 if (readw(regs
+ S3C2410_TFTPAL(i
)) == ent
)
763 fbi
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
765 fbi
->palette_ready
= 1; /* retry */
769 static irqreturn_t
s3c2410fb_irq(int irq
, void *dev_id
)
771 struct s3c2410fb_info
*fbi
= dev_id
;
772 void __iomem
*regs
= fbi
->io
;
773 unsigned long lcdirq
= readl(regs
+ S3C2410_LCDINTPND
);
775 if (lcdirq
& S3C2410_LCDINT_FRSYNC
) {
776 if (fbi
->palette_ready
)
777 s3c2410fb_write_palette(fbi
);
779 writel(S3C2410_LCDINT_FRSYNC
, regs
+ S3C2410_LCDINTPND
);
780 writel(S3C2410_LCDINT_FRSYNC
, regs
+ S3C2410_LCDSRCPND
);
786 static char driver_name
[] = "s3c2410fb";
788 static int __init
s3c2410fb_probe(struct platform_device
*pdev
)
790 struct s3c2410fb_info
*info
;
791 struct s3c2410fb_display
*display
;
792 struct fb_info
*fbinfo
;
793 struct resource
*res
;
800 mach_info
= pdev
->dev
.platform_data
;
801 if (mach_info
== NULL
) {
803 "no platform data for lcd, cannot attach\n");
807 display
= mach_info
->displays
+ mach_info
->default_display
;
809 irq
= platform_get_irq(pdev
, 0);
811 dev_err(&pdev
->dev
, "no irq for device\n");
815 fbinfo
= framebuffer_alloc(sizeof(struct s3c2410fb_info
), &pdev
->dev
);
820 info
->dev
= &pdev
->dev
;
822 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
824 dev_err(&pdev
->dev
, "failed to get memory registers\n");
829 size
= (res
->end
- res
->start
) + 1;
830 info
->mem
= request_mem_region(res
->start
, size
, pdev
->name
);
831 if (info
->mem
== NULL
) {
832 dev_err(&pdev
->dev
, "failed to get memory region\n");
837 info
->io
= ioremap(res
->start
, size
);
838 if (info
->io
== NULL
) {
839 dev_err(&pdev
->dev
, "ioremap() of registers failed\n");
844 platform_set_drvdata(pdev
, fbinfo
);
846 dprintk("devinit\n");
848 strcpy(fbinfo
->fix
.id
, driver_name
);
850 info
->regs
.lcdcon1
= display
->lcdcon1
;
851 info
->regs
.lcdcon5
= display
->lcdcon5
;
853 /* Stop the video and unset ENVID if set */
854 info
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
855 lcdcon1
= readl(info
->io
+ S3C2410_LCDCON1
);
856 writel(lcdcon1
& ~S3C2410_LCDCON1_ENVID
, info
->io
+ S3C2410_LCDCON1
);
858 info
->mach_info
= pdev
->dev
.platform_data
;
859 info
->current_display
= mach_info
->default_display
;
861 fbinfo
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
862 fbinfo
->fix
.type_aux
= 0;
863 fbinfo
->fix
.xpanstep
= 0;
864 fbinfo
->fix
.ypanstep
= 0;
865 fbinfo
->fix
.ywrapstep
= 0;
866 fbinfo
->fix
.accel
= FB_ACCEL_NONE
;
868 fbinfo
->var
.nonstd
= 0;
869 fbinfo
->var
.activate
= FB_ACTIVATE_NOW
;
870 fbinfo
->var
.height
= display
->height
;
871 fbinfo
->var
.width
= display
->width
;
872 fbinfo
->var
.accel_flags
= 0;
873 fbinfo
->var
.vmode
= FB_VMODE_NONINTERLACED
;
875 fbinfo
->fbops
= &s3c2410fb_ops
;
876 fbinfo
->flags
= FBINFO_FLAG_DEFAULT
;
877 fbinfo
->pseudo_palette
= &info
->pseudo_pal
;
879 fbinfo
->var
.xres
= display
->xres
;
880 fbinfo
->var
.xres_virtual
= display
->xres
;
881 fbinfo
->var
.yres
= display
->yres
;
882 fbinfo
->var
.yres_virtual
= display
->yres
;
883 fbinfo
->var
.bits_per_pixel
= display
->bpp
;
884 fbinfo
->var
.left_margin
= display
->left_margin
;
885 fbinfo
->var
.right_margin
= display
->right_margin
;
887 fbinfo
->var
.upper_margin
= display
->upper_margin
;
888 fbinfo
->var
.lower_margin
= display
->lower_margin
;
889 fbinfo
->var
.vsync_len
= display
->vsync_len
;
890 fbinfo
->var
.hsync_len
= display
->hsync_len
;
892 fbinfo
->var
.red
.offset
= 11;
893 fbinfo
->var
.green
.offset
= 5;
894 fbinfo
->var
.blue
.offset
= 0;
895 fbinfo
->var
.transp
.offset
= 0;
896 fbinfo
->var
.red
.length
= 5;
897 fbinfo
->var
.green
.length
= 6;
898 fbinfo
->var
.blue
.length
= 5;
899 fbinfo
->var
.transp
.length
= 0;
901 /* find maximum required memory size for display */
902 for (i
= 0; i
< mach_info
->num_displays
; i
++) {
903 unsigned long smem_len
= mach_info
->displays
[i
].xres
;
905 smem_len
*= mach_info
->displays
[i
].yres
;
906 smem_len
*= mach_info
->displays
[i
].bpp
;
908 if (fbinfo
->fix
.smem_len
< smem_len
)
909 fbinfo
->fix
.smem_len
= smem_len
;
912 for (i
= 0; i
< 256; i
++)
913 info
->palette_buffer
[i
] = PALETTE_BUFF_CLEAR
;
915 ret
= request_irq(irq
, s3c2410fb_irq
, IRQF_DISABLED
, pdev
->name
, info
);
917 dev_err(&pdev
->dev
, "cannot get irq %d - err %d\n", irq
, ret
);
922 info
->clk
= clk_get(NULL
, "lcd");
923 if (!info
->clk
|| IS_ERR(info
->clk
)) {
924 printk(KERN_ERR
"failed to get lcd clock source\n");
929 clk_enable(info
->clk
);
930 dprintk("got and enabled clock\n");
934 /* Initialize video memory */
935 ret
= s3c2410fb_map_video_memory(fbinfo
);
937 printk(KERN_ERR
"Failed to allocate video RAM: %d\n", ret
);
942 dprintk("got video memory\n");
944 s3c2410fb_init_registers(fbinfo
);
946 s3c2410fb_check_var(&fbinfo
->var
, fbinfo
);
948 ret
= register_framebuffer(fbinfo
);
950 printk(KERN_ERR
"Failed to register framebuffer device: %d\n",
952 goto free_video_memory
;
955 /* create device files */
956 device_create_file(&pdev
->dev
, &dev_attr_debug
);
958 printk(KERN_INFO
"fb%d: %s frame buffer device\n",
959 fbinfo
->node
, fbinfo
->fix
.id
);
964 s3c2410fb_unmap_video_memory(info
);
966 clk_disable(info
->clk
);
973 release_resource(info
->mem
);
976 framebuffer_release(fbinfo
);
980 /* s3c2410fb_stop_lcd
982 * shutdown the lcd controller
984 static void s3c2410fb_stop_lcd(struct s3c2410fb_info
*fbi
)
988 local_irq_save(flags
);
990 fbi
->regs
.lcdcon1
&= ~S3C2410_LCDCON1_ENVID
;
991 writel(fbi
->regs
.lcdcon1
, fbi
->io
+ S3C2410_LCDCON1
);
993 local_irq_restore(flags
);
999 static int s3c2410fb_remove(struct platform_device
*pdev
)
1001 struct fb_info
*fbinfo
= platform_get_drvdata(pdev
);
1002 struct s3c2410fb_info
*info
= fbinfo
->par
;
1005 s3c2410fb_stop_lcd(info
);
1008 s3c2410fb_unmap_video_memory(info
);
1011 clk_disable(info
->clk
);
1016 irq
= platform_get_irq(pdev
, 0);
1017 free_irq(irq
, info
);
1019 release_resource(info
->mem
);
1022 unregister_framebuffer(fbinfo
);
1029 /* suspend and resume support for the lcd controller */
1030 static int s3c2410fb_suspend(struct platform_device
*dev
, pm_message_t state
)
1032 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1033 struct s3c2410fb_info
*info
= fbinfo
->par
;
1035 s3c2410fb_stop_lcd(info
);
1037 /* sleep before disabling the clock, we need to ensure
1038 * the LCD DMA engine is not going to get back on the bus
1039 * before the clock goes off again (bjd) */
1042 clk_disable(info
->clk
);
1047 static int s3c2410fb_resume(struct platform_device
*dev
)
1049 struct fb_info
*fbinfo
= platform_get_drvdata(dev
);
1050 struct s3c2410fb_info
*info
= fbinfo
->par
;
1052 clk_enable(info
->clk
);
1055 s3c2410fb_init_registers(info
);
1061 #define s3c2410fb_suspend NULL
1062 #define s3c2410fb_resume NULL
1065 static struct platform_driver s3c2410fb_driver
= {
1066 .probe
= s3c2410fb_probe
,
1067 .remove
= s3c2410fb_remove
,
1068 .suspend
= s3c2410fb_suspend
,
1069 .resume
= s3c2410fb_resume
,
1071 .name
= "s3c2410-lcd",
1072 .owner
= THIS_MODULE
,
1076 int __devinit
s3c2410fb_init(void)
1078 return platform_driver_register(&s3c2410fb_driver
);
1081 static void __exit
s3c2410fb_cleanup(void)
1083 platform_driver_unregister(&s3c2410fb_driver
);
1086 module_init(s3c2410fb_init
);
1087 module_exit(s3c2410fb_cleanup
);
1089 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1090 "Ben Dooks <ben-linux@fluff.org>");
1091 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1092 MODULE_LICENSE("GPL");