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[mirror_ubuntu-artful-kernel.git] / drivers / video / s3fb.c
1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/version.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
28 #include <video/vga.h>
29
30 #ifdef CONFIG_MTRR
31 #include <asm/mtrr.h>
32 #endif
33
34 struct s3fb_info {
35 int chip, rev, mclk_freq;
36 int mtrr_reg;
37 struct vgastate state;
38 struct mutex open_lock;
39 unsigned int ref_count;
40 u32 pseudo_palette[16];
41 };
42
43
44 /* ------------------------------------------------------------------------- */
45
46 static const struct svga_fb_format s3fb_formats[] = {
47 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
48 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
49 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
50 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
52 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
55 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
59 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
63 SVGA_FORMAT_END
64 };
65
66
67 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
68 60000, 240000, 14318};
69
70 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
71
72 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
73 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
74 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
75 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
76 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};
77
78 #define CHIP_UNKNOWN 0x00
79 #define CHIP_732_TRIO32 0x01
80 #define CHIP_764_TRIO64 0x02
81 #define CHIP_765_TRIO64VP 0x03
82 #define CHIP_767_TRIO64UVP 0x04
83 #define CHIP_775_TRIO64V2_DX 0x05
84 #define CHIP_785_TRIO64V2_GX 0x06
85 #define CHIP_551_PLATO_PX 0x07
86 #define CHIP_M65_AURORA64VP 0x08
87 #define CHIP_325_VIRGE 0x09
88 #define CHIP_988_VIRGE_VX 0x0A
89 #define CHIP_375_VIRGE_DX 0x0B
90 #define CHIP_385_VIRGE_GX 0x0C
91 #define CHIP_356_VIRGE_GX2 0x0D
92 #define CHIP_357_VIRGE_GX2P 0x0E
93 #define CHIP_359_VIRGE_GX2P 0x0F
94
95 #define CHIP_XXX_TRIO 0x80
96 #define CHIP_XXX_TRIO64V2_DXGX 0x81
97 #define CHIP_XXX_VIRGE_DXGX 0x82
98
99 #define CHIP_UNDECIDED_FLAG 0x80
100 #define CHIP_MASK 0xFF
101
102 /* CRT timing register sets */
103
104 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
105 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
106 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
107 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
108 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
109 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
110
111 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
112 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
113 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
114 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
115 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
116 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
117
118 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
119 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
120 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
121
122 static const struct svga_timing_regs s3_timing_regs = {
123 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
124 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
125 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
126 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
127 };
128
129
130 /* ------------------------------------------------------------------------- */
131
132 /* Module parameters */
133
134
135 static char *mode = "640x480-8@60";
136
137 #ifdef CONFIG_MTRR
138 static int mtrr = 1;
139 #endif
140
141 static int fasttext = 1;
142
143
144 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
145 MODULE_LICENSE("GPL");
146 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
147
148 module_param(mode, charp, 0444);
149 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");
150
151 #ifdef CONFIG_MTRR
152 module_param(mtrr, int, 0444);
153 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
154 #endif
155
156 module_param(fasttext, int, 0644);
157 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
158
159
160 /* ------------------------------------------------------------------------- */
161
162 /* Set font in S3 fast text mode */
163
164 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
165 {
166 const u8 *font = map->data;
167 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
168 int i, c;
169
170 if ((map->width != 8) || (map->height != 16) ||
171 (map->depth != 1) || (map->length != 256)) {
172 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
173 info->node, map->width, map->height, map->depth, map->length);
174 return;
175 }
176
177 fb += 2;
178 for (i = 0; i < map->height; i++) {
179 for (c = 0; c < map->length; c++) {
180 fb_writeb(font[c * map->height + i], fb + c * 4);
181 }
182 fb += 1024;
183 }
184 }
185
186 static int s3fb_get_tilemax(struct fb_info *info)
187 {
188 return 256;
189 }
190
191 static struct fb_tile_ops s3fb_tile_ops = {
192 .fb_settile = svga_settile,
193 .fb_tilecopy = svga_tilecopy,
194 .fb_tilefill = svga_tilefill,
195 .fb_tileblit = svga_tileblit,
196 .fb_tilecursor = svga_tilecursor,
197 .fb_get_tilemax = s3fb_get_tilemax,
198 };
199
200 static struct fb_tile_ops s3fb_fast_tile_ops = {
201 .fb_settile = s3fb_settile_fast,
202 .fb_tilecopy = svga_tilecopy,
203 .fb_tilefill = svga_tilefill,
204 .fb_tileblit = svga_tileblit,
205 .fb_tilecursor = svga_tilecursor,
206 .fb_get_tilemax = s3fb_get_tilemax,
207 };
208
209
210 /* ------------------------------------------------------------------------- */
211
212 /* image data is MSB-first, fb structure is MSB-first too */
213 static inline u32 expand_color(u32 c)
214 {
215 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
216 }
217
218 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
219 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
220 {
221 u32 fg = expand_color(image->fg_color);
222 u32 bg = expand_color(image->bg_color);
223 const u8 *src1, *src;
224 u8 __iomem *dst1;
225 u32 __iomem *dst;
226 u32 val;
227 int x, y;
228
229 src1 = image->data;
230 dst1 = info->screen_base + (image->dy * info->fix.line_length)
231 + ((image->dx / 8) * 4);
232
233 for (y = 0; y < image->height; y++) {
234 src = src1;
235 dst = (u32 __iomem *) dst1;
236 for (x = 0; x < image->width; x += 8) {
237 val = *(src++) * 0x01010101;
238 val = (val & fg) | (~val & bg);
239 fb_writel(val, dst++);
240 }
241 src1 += image->width / 8;
242 dst1 += info->fix.line_length;
243 }
244
245 }
246
247 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
248 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
249 {
250 u32 fg = expand_color(rect->color);
251 u8 __iomem *dst1;
252 u32 __iomem *dst;
253 int x, y;
254
255 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
256 + ((rect->dx / 8) * 4);
257
258 for (y = 0; y < rect->height; y++) {
259 dst = (u32 __iomem *) dst1;
260 for (x = 0; x < rect->width; x += 8) {
261 fb_writel(fg, dst++);
262 }
263 dst1 += info->fix.line_length;
264 }
265 }
266
267
268 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
269 static inline u32 expand_pixel(u32 c)
270 {
271 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
272 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
273 }
274
275 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
276 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
277 {
278 u32 fg = image->fg_color * 0x11111111;
279 u32 bg = image->bg_color * 0x11111111;
280 const u8 *src1, *src;
281 u8 __iomem *dst1;
282 u32 __iomem *dst;
283 u32 val;
284 int x, y;
285
286 src1 = image->data;
287 dst1 = info->screen_base + (image->dy * info->fix.line_length)
288 + ((image->dx / 8) * 4);
289
290 for (y = 0; y < image->height; y++) {
291 src = src1;
292 dst = (u32 __iomem *) dst1;
293 for (x = 0; x < image->width; x += 8) {
294 val = expand_pixel(*(src++));
295 val = (val & fg) | (~val & bg);
296 fb_writel(val, dst++);
297 }
298 src1 += image->width / 8;
299 dst1 += info->fix.line_length;
300 }
301 }
302
303 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
304 {
305 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
306 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
307 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
308 s3fb_iplan_imageblit(info, image);
309 else
310 s3fb_cfb4_imageblit(info, image);
311 } else
312 cfb_imageblit(info, image);
313 }
314
315 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
316 {
317 if ((info->var.bits_per_pixel == 4)
318 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
319 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
320 s3fb_iplan_fillrect(info, rect);
321 else
322 cfb_fillrect(info, rect);
323 }
324
325
326
327 /* ------------------------------------------------------------------------- */
328
329
330 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
331 {
332 u16 m, n, r;
333 u8 regval;
334
335 svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
336
337 /* Set VGA misc register */
338 regval = vga_r(NULL, VGA_MIS_R);
339 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
340
341 /* Set S3 clock registers */
342 vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));
343 vga_wseq(NULL, 0x13, m - 2);
344
345 udelay(1000);
346
347 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
348 regval = vga_rseq (NULL, 0x15); /* | 0x80; */
349 vga_wseq(NULL, 0x15, regval & ~(1<<5));
350 vga_wseq(NULL, 0x15, regval | (1<<5));
351 vga_wseq(NULL, 0x15, regval & ~(1<<5));
352 }
353
354
355 /* Open framebuffer */
356
357 static int s3fb_open(struct fb_info *info, int user)
358 {
359 struct s3fb_info *par = info->par;
360
361 mutex_lock(&(par->open_lock));
362 if (par->ref_count == 0) {
363 memset(&(par->state), 0, sizeof(struct vgastate));
364 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
365 par->state.num_crtc = 0x70;
366 par->state.num_seq = 0x20;
367 save_vga(&(par->state));
368 }
369
370 par->ref_count++;
371 mutex_unlock(&(par->open_lock));
372
373 return 0;
374 }
375
376 /* Close framebuffer */
377
378 static int s3fb_release(struct fb_info *info, int user)
379 {
380 struct s3fb_info *par = info->par;
381
382 mutex_lock(&(par->open_lock));
383 if (par->ref_count == 0) {
384 mutex_unlock(&(par->open_lock));
385 return -EINVAL;
386 }
387
388 if (par->ref_count == 1)
389 restore_vga(&(par->state));
390
391 par->ref_count--;
392 mutex_unlock(&(par->open_lock));
393
394 return 0;
395 }
396
397 /* Validate passed in var */
398
399 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
400 {
401 struct s3fb_info *par = info->par;
402 int rv, mem, step;
403
404 /* Find appropriate format */
405 rv = svga_match_format (s3fb_formats, var, NULL);
406 if ((rv < 0) || ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)))
407 { /* 24bpp on VIRGE VX, 32bpp on others */
408 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
409 return rv;
410 }
411
412 /* Do not allow to have real resoulution larger than virtual */
413 if (var->xres > var->xres_virtual)
414 var->xres_virtual = var->xres;
415
416 if (var->yres > var->yres_virtual)
417 var->yres_virtual = var->yres;
418
419 /* Round up xres_virtual to have proper alignment of lines */
420 step = s3fb_formats[rv].xresstep - 1;
421 var->xres_virtual = (var->xres_virtual+step) & ~step;
422
423 /* Check whether have enough memory */
424 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
425 if (mem > info->screen_size)
426 {
427 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
428 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
429 return -EINVAL;
430 }
431
432 rv = svga_check_timings (&s3_timing_regs, var, info->node);
433 if (rv < 0)
434 {
435 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
436 return rv;
437 }
438
439 return 0;
440 }
441
442 /* Set video mode from par */
443
444 static int s3fb_set_par(struct fb_info *info)
445 {
446 struct s3fb_info *par = info->par;
447 u32 value, mode, hmul, offset_value, screen_size, multiplex;
448 u32 bpp = info->var.bits_per_pixel;
449
450 if (bpp != 0) {
451 info->fix.ypanstep = 1;
452 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
453
454 info->flags &= ~FBINFO_MISC_TILEBLITTING;
455 info->tileops = NULL;
456
457 /* supports blit rectangles of any dimension */
458 info->pixmap.blit_x = ~(u32)0;
459 info->pixmap.blit_y = ~(u32)0;
460 offset_value = (info->var.xres_virtual * bpp) / 64;
461 screen_size = info->var.yres_virtual * info->fix.line_length;
462 } else {
463 info->fix.ypanstep = 16;
464 info->fix.line_length = 0;
465
466 info->flags |= FBINFO_MISC_TILEBLITTING;
467 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
468 /* supports 8x16 tiles only */
469 info->pixmap.blit_x = 1 << (8 - 1);
470 info->pixmap.blit_y = 1 << (16 - 1);
471
472 offset_value = info->var.xres_virtual / 16;
473 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
474 }
475
476 info->var.xoffset = 0;
477 info->var.yoffset = 0;
478 info->var.activate = FB_ACTIVATE_NOW;
479
480 /* Unlock registers */
481 vga_wcrt(NULL, 0x38, 0x48);
482 vga_wcrt(NULL, 0x39, 0xA5);
483 vga_wseq(NULL, 0x08, 0x06);
484 svga_wcrt_mask(0x11, 0x00, 0x80);
485
486 /* Blank screen and turn off sync */
487 svga_wseq_mask(0x01, 0x20, 0x20);
488 svga_wcrt_mask(0x17, 0x00, 0x80);
489
490 /* Set default values */
491 svga_set_default_gfx_regs();
492 svga_set_default_atc_regs();
493 svga_set_default_seq_regs();
494 svga_set_default_crt_regs();
495 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
496 svga_wcrt_multi(s3_start_address_regs, 0);
497
498 /* S3 specific initialization */
499 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
500 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
501
502 /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */
503 /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */
504 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */
505 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */
506
507 svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits
508
509 /* svga_wcrt_mask(0x58, 0x03, 0x03); */
510
511 /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
512 /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
513
514
515 /* Set the offset register */
516 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
517 svga_wcrt_multi(s3_offset_regs, offset_value);
518
519 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
520 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
521 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
522 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
523
524 vga_wcrt(NULL, 0x3A, 0x35);
525 svga_wattr(0x33, 0x00);
526
527 if (info->var.vmode & FB_VMODE_DOUBLE)
528 svga_wcrt_mask(0x09, 0x80, 0x80);
529 else
530 svga_wcrt_mask(0x09, 0x00, 0x80);
531
532 if (info->var.vmode & FB_VMODE_INTERLACED)
533 svga_wcrt_mask(0x42, 0x20, 0x20);
534 else
535 svga_wcrt_mask(0x42, 0x00, 0x20);
536
537 /* Disable hardware graphics cursor */
538 svga_wcrt_mask(0x45, 0x00, 0x01);
539 /* Disable Streams engine */
540 svga_wcrt_mask(0x67, 0x00, 0x0C);
541
542 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
543
544 /* S3 virge DX hack */
545 if (par->chip == CHIP_375_VIRGE_DX) {
546 vga_wcrt(NULL, 0x86, 0x80);
547 vga_wcrt(NULL, 0x90, 0x00);
548 }
549
550 /* S3 virge VX hack */
551 if (par->chip == CHIP_988_VIRGE_VX) {
552 vga_wcrt(NULL, 0x50, 0x00);
553 vga_wcrt(NULL, 0x67, 0x50);
554
555 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
556 vga_wcrt(NULL, 0x66, 0x90);
557 }
558
559 svga_wcrt_mask(0x31, 0x00, 0x40);
560 multiplex = 0;
561 hmul = 1;
562
563 /* Set mode-specific register values */
564 switch (mode) {
565 case 0:
566 pr_debug("fb%d: text mode\n", info->node);
567 svga_set_textmode_vga_regs();
568
569 /* Set additional registers like in 8-bit mode */
570 svga_wcrt_mask(0x50, 0x00, 0x30);
571 svga_wcrt_mask(0x67, 0x00, 0xF0);
572
573 /* Disable enhanced mode */
574 svga_wcrt_mask(0x3A, 0x00, 0x30);
575
576 if (fasttext) {
577 pr_debug("fb%d: high speed text mode set\n", info->node);
578 svga_wcrt_mask(0x31, 0x40, 0x40);
579 }
580 break;
581 case 1:
582 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
583 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
584
585 /* Set additional registers like in 8-bit mode */
586 svga_wcrt_mask(0x50, 0x00, 0x30);
587 svga_wcrt_mask(0x67, 0x00, 0xF0);
588
589 /* disable enhanced mode */
590 svga_wcrt_mask(0x3A, 0x00, 0x30);
591 break;
592 case 2:
593 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
594
595 /* Set additional registers like in 8-bit mode */
596 svga_wcrt_mask(0x50, 0x00, 0x30);
597 svga_wcrt_mask(0x67, 0x00, 0xF0);
598
599 /* disable enhanced mode */
600 svga_wcrt_mask(0x3A, 0x00, 0x30);
601 break;
602 case 3:
603 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
604 if (info->var.pixclock > 20000) {
605 svga_wcrt_mask(0x50, 0x00, 0x30);
606 svga_wcrt_mask(0x67, 0x00, 0xF0);
607 } else {
608 svga_wcrt_mask(0x50, 0x00, 0x30);
609 svga_wcrt_mask(0x67, 0x10, 0xF0);
610 multiplex = 1;
611 }
612 break;
613 case 4:
614 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
615 if (par->chip == CHIP_988_VIRGE_VX) {
616 if (info->var.pixclock > 20000)
617 svga_wcrt_mask(0x67, 0x20, 0xF0);
618 else
619 svga_wcrt_mask(0x67, 0x30, 0xF0);
620 } else {
621 svga_wcrt_mask(0x50, 0x10, 0x30);
622 svga_wcrt_mask(0x67, 0x30, 0xF0);
623 hmul = 2;
624 }
625 break;
626 case 5:
627 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
628 if (par->chip == CHIP_988_VIRGE_VX) {
629 if (info->var.pixclock > 20000)
630 svga_wcrt_mask(0x67, 0x40, 0xF0);
631 else
632 svga_wcrt_mask(0x67, 0x50, 0xF0);
633 } else {
634 svga_wcrt_mask(0x50, 0x10, 0x30);
635 svga_wcrt_mask(0x67, 0x50, 0xF0);
636 hmul = 2;
637 }
638 break;
639 case 6:
640 /* VIRGE VX case */
641 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
642 svga_wcrt_mask(0x67, 0xD0, 0xF0);
643 break;
644 case 7:
645 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
646 svga_wcrt_mask(0x50, 0x30, 0x30);
647 svga_wcrt_mask(0x67, 0xD0, 0xF0);
648 break;
649 default:
650 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
651 return -EINVAL;
652 }
653
654 if (par->chip != CHIP_988_VIRGE_VX) {
655 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
656 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
657 }
658
659 s3_set_pixclock(info, info->var.pixclock);
660 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
661 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
662 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
663 hmul, info->node);
664
665 /* Set interlaced mode start/end register */
666 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
667 value = ((value * hmul) / 8) - 5;
668 vga_wcrt(NULL, 0x3C, (value + 1) / 2);
669
670 memset_io(info->screen_base, 0x00, screen_size);
671 /* Device and screen back on */
672 svga_wcrt_mask(0x17, 0x80, 0x80);
673 svga_wseq_mask(0x01, 0x00, 0x20);
674
675 return 0;
676 }
677
678 /* Set a colour register */
679
680 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
681 u_int transp, struct fb_info *fb)
682 {
683 switch (fb->var.bits_per_pixel) {
684 case 0:
685 case 4:
686 if (regno >= 16)
687 return -EINVAL;
688
689 if ((fb->var.bits_per_pixel == 4) &&
690 (fb->var.nonstd == 0)) {
691 outb(0xF0, VGA_PEL_MSK);
692 outb(regno*16, VGA_PEL_IW);
693 } else {
694 outb(0x0F, VGA_PEL_MSK);
695 outb(regno, VGA_PEL_IW);
696 }
697 outb(red >> 10, VGA_PEL_D);
698 outb(green >> 10, VGA_PEL_D);
699 outb(blue >> 10, VGA_PEL_D);
700 break;
701 case 8:
702 if (regno >= 256)
703 return -EINVAL;
704
705 outb(0xFF, VGA_PEL_MSK);
706 outb(regno, VGA_PEL_IW);
707 outb(red >> 10, VGA_PEL_D);
708 outb(green >> 10, VGA_PEL_D);
709 outb(blue >> 10, VGA_PEL_D);
710 break;
711 case 16:
712 if (regno >= 16)
713 return -EINVAL;
714
715 if (fb->var.green.length == 5)
716 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
717 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
718 else if (fb->var.green.length == 6)
719 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
720 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
721 else return -EINVAL;
722 break;
723 case 24:
724 case 32:
725 if (regno >= 16)
726 return -EINVAL;
727
728 ((u32*)fb->pseudo_palette)[regno] = ((transp & 0xFF00) << 16) | ((red & 0xFF00) << 8) |
729 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
730 break;
731 default:
732 return -EINVAL;
733 }
734
735 return 0;
736 }
737
738
739 /* Set the display blanking state */
740
741 static int s3fb_blank(int blank_mode, struct fb_info *info)
742 {
743 switch (blank_mode) {
744 case FB_BLANK_UNBLANK:
745 pr_debug("fb%d: unblank\n", info->node);
746 svga_wcrt_mask(0x56, 0x00, 0x06);
747 svga_wseq_mask(0x01, 0x00, 0x20);
748 break;
749 case FB_BLANK_NORMAL:
750 pr_debug("fb%d: blank\n", info->node);
751 svga_wcrt_mask(0x56, 0x00, 0x06);
752 svga_wseq_mask(0x01, 0x20, 0x20);
753 break;
754 case FB_BLANK_HSYNC_SUSPEND:
755 pr_debug("fb%d: hsync\n", info->node);
756 svga_wcrt_mask(0x56, 0x02, 0x06);
757 svga_wseq_mask(0x01, 0x20, 0x20);
758 break;
759 case FB_BLANK_VSYNC_SUSPEND:
760 pr_debug("fb%d: vsync\n", info->node);
761 svga_wcrt_mask(0x56, 0x04, 0x06);
762 svga_wseq_mask(0x01, 0x20, 0x20);
763 break;
764 case FB_BLANK_POWERDOWN:
765 pr_debug("fb%d: sync down\n", info->node);
766 svga_wcrt_mask(0x56, 0x06, 0x06);
767 svga_wseq_mask(0x01, 0x20, 0x20);
768 break;
769 }
770
771 return 0;
772 }
773
774
775 /* Pan the display */
776
777 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
778
779 unsigned int offset;
780
781 /* Validate the offsets */
782 if ((var->xoffset + var->xres) > var->xres_virtual)
783 return -EINVAL;
784 if ((var->yoffset + var->yres) > var->yres_virtual)
785 return -EINVAL;
786
787 /* Calculate the offset */
788 if (var->bits_per_pixel == 0) {
789 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
790 offset = offset >> 2;
791 } else {
792 offset = (var->yoffset * info->fix.line_length) +
793 (var->xoffset * var->bits_per_pixel / 8);
794 offset = offset >> 2;
795 }
796
797 /* Set the offset */
798 svga_wcrt_multi(s3_start_address_regs, offset);
799
800 return 0;
801 }
802
803 /* ------------------------------------------------------------------------- */
804
805 /* Frame buffer operations */
806
807 static struct fb_ops s3fb_ops = {
808 .owner = THIS_MODULE,
809 .fb_open = s3fb_open,
810 .fb_release = s3fb_release,
811 .fb_check_var = s3fb_check_var,
812 .fb_set_par = s3fb_set_par,
813 .fb_setcolreg = s3fb_setcolreg,
814 .fb_blank = s3fb_blank,
815 .fb_pan_display = s3fb_pan_display,
816 .fb_fillrect = s3fb_fillrect,
817 .fb_copyarea = cfb_copyarea,
818 .fb_imageblit = s3fb_imageblit,
819 };
820
821 /* ------------------------------------------------------------------------- */
822
823 static int __devinit s3_identification(int chip)
824 {
825 if (chip == CHIP_XXX_TRIO) {
826 u8 cr30 = vga_rcrt(NULL, 0x30);
827 u8 cr2e = vga_rcrt(NULL, 0x2e);
828 u8 cr2f = vga_rcrt(NULL, 0x2f);
829
830 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
831 if (cr2e == 0x10)
832 return CHIP_732_TRIO32;
833 if (cr2e == 0x11) {
834 if (! (cr2f & 0x40))
835 return CHIP_764_TRIO64;
836 else
837 return CHIP_765_TRIO64VP;
838 }
839 }
840 }
841
842 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
843 u8 cr6f = vga_rcrt(NULL, 0x6f);
844
845 if (! (cr6f & 0x01))
846 return CHIP_775_TRIO64V2_DX;
847 else
848 return CHIP_785_TRIO64V2_GX;
849 }
850
851 if (chip == CHIP_XXX_VIRGE_DXGX) {
852 u8 cr6f = vga_rcrt(NULL, 0x6f);
853
854 if (! (cr6f & 0x01))
855 return CHIP_375_VIRGE_DX;
856 else
857 return CHIP_385_VIRGE_GX;
858 }
859
860 return CHIP_UNKNOWN;
861 }
862
863
864 /* PCI probe */
865
866 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
867 {
868 struct fb_info *info;
869 struct s3fb_info *par;
870 int rc;
871 u8 regval, cr38, cr39;
872
873 /* Ignore secondary VGA device because there is no VGA arbitration */
874 if (! svga_primary_device(dev)) {
875 dev_info(&(dev->dev), "ignoring secondary device\n");
876 return -ENODEV;
877 }
878
879 /* Allocate and fill driver data structure */
880 info = framebuffer_alloc(sizeof(struct s3fb_info), NULL);
881 if (!info) {
882 dev_err(&(dev->dev), "cannot allocate memory\n");
883 return -ENOMEM;
884 }
885
886 par = info->par;
887 mutex_init(&par->open_lock);
888
889 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
890 info->fbops = &s3fb_ops;
891
892 /* Prepare PCI device */
893 rc = pci_enable_device(dev);
894 if (rc < 0) {
895 dev_err(&(dev->dev), "cannot enable PCI device\n");
896 goto err_enable_device;
897 }
898
899 rc = pci_request_regions(dev, "s3fb");
900 if (rc < 0) {
901 dev_err(&(dev->dev), "cannot reserve framebuffer region\n");
902 goto err_request_regions;
903 }
904
905
906 info->fix.smem_start = pci_resource_start(dev, 0);
907 info->fix.smem_len = pci_resource_len(dev, 0);
908
909 /* Map physical IO memory address into kernel space */
910 info->screen_base = pci_iomap(dev, 0, 0);
911 if (! info->screen_base) {
912 rc = -ENOMEM;
913 dev_err(&(dev->dev), "iomap for framebuffer failed\n");
914 goto err_iomap;
915 }
916
917 /* Unlock regs */
918 cr38 = vga_rcrt(NULL, 0x38);
919 cr39 = vga_rcrt(NULL, 0x39);
920 vga_wseq(NULL, 0x08, 0x06);
921 vga_wcrt(NULL, 0x38, 0x48);
922 vga_wcrt(NULL, 0x39, 0xA5);
923
924 /* Find how many physical memory there is on card */
925 /* 0x36 register is accessible even if other registers are locked */
926 regval = vga_rcrt(NULL, 0x36);
927 info->screen_size = s3_memsizes[regval >> 5] << 10;
928 info->fix.smem_len = info->screen_size;
929
930 par->chip = id->driver_data & CHIP_MASK;
931 par->rev = vga_rcrt(NULL, 0x2f);
932 if (par->chip & CHIP_UNDECIDED_FLAG)
933 par->chip = s3_identification(par->chip);
934
935 /* Find MCLK frequency */
936 regval = vga_rseq(NULL, 0x10);
937 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
938 par->mclk_freq = par->mclk_freq >> (regval >> 5);
939
940 /* Restore locks */
941 vga_wcrt(NULL, 0x38, cr38);
942 vga_wcrt(NULL, 0x39, cr39);
943
944 strcpy(info->fix.id, s3_names [par->chip]);
945 info->fix.mmio_start = 0;
946 info->fix.mmio_len = 0;
947 info->fix.type = FB_TYPE_PACKED_PIXELS;
948 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
949 info->fix.ypanstep = 0;
950 info->fix.accel = FB_ACCEL_NONE;
951 info->pseudo_palette = (void*) (par->pseudo_palette);
952
953 /* Prepare startup mode */
954 rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8);
955 if (! ((rc == 1) || (rc == 2))) {
956 rc = -EINVAL;
957 dev_err(&(dev->dev), "mode %s not found\n", mode);
958 goto err_find_mode;
959 }
960
961 rc = fb_alloc_cmap(&info->cmap, 256, 0);
962 if (rc < 0) {
963 dev_err(&(dev->dev), "cannot allocate colormap\n");
964 goto err_alloc_cmap;
965 }
966
967 rc = register_framebuffer(info);
968 if (rc < 0) {
969 dev_err(&(dev->dev), "cannot register framebuffer\n");
970 goto err_reg_fb;
971 }
972
973 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
974 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
975
976 if (par->chip == CHIP_UNKNOWN)
977 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
978 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
979 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
980
981 /* Record a reference to the driver data */
982 pci_set_drvdata(dev, info);
983
984 #ifdef CONFIG_MTRR
985 if (mtrr) {
986 par->mtrr_reg = -1;
987 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
988 }
989 #endif
990
991 return 0;
992
993 /* Error handling */
994 err_reg_fb:
995 fb_dealloc_cmap(&info->cmap);
996 err_alloc_cmap:
997 err_find_mode:
998 pci_iounmap(dev, info->screen_base);
999 err_iomap:
1000 pci_release_regions(dev);
1001 err_request_regions:
1002 /* pci_disable_device(dev); */
1003 err_enable_device:
1004 framebuffer_release(info);
1005 return rc;
1006 }
1007
1008
1009 /* PCI remove */
1010
1011 static void __devexit s3_pci_remove(struct pci_dev *dev)
1012 {
1013 struct fb_info *info = pci_get_drvdata(dev);
1014
1015 if (info) {
1016
1017 #ifdef CONFIG_MTRR
1018 struct s3fb_info *par = info->par;
1019
1020 if (par->mtrr_reg >= 0) {
1021 mtrr_del(par->mtrr_reg, 0, 0);
1022 par->mtrr_reg = -1;
1023 }
1024 #endif
1025
1026 unregister_framebuffer(info);
1027 fb_dealloc_cmap(&info->cmap);
1028
1029 pci_iounmap(dev, info->screen_base);
1030 pci_release_regions(dev);
1031 /* pci_disable_device(dev); */
1032
1033 pci_set_drvdata(dev, NULL);
1034 framebuffer_release(info);
1035 }
1036 }
1037
1038 /* PCI suspend */
1039
1040 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1041 {
1042 struct fb_info *info = pci_get_drvdata(dev);
1043 struct s3fb_info *par = info->par;
1044
1045 dev_info(&(dev->dev), "suspend\n");
1046
1047 acquire_console_sem();
1048 mutex_lock(&(par->open_lock));
1049
1050 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1051 mutex_unlock(&(par->open_lock));
1052 release_console_sem();
1053 return 0;
1054 }
1055
1056 fb_set_suspend(info, 1);
1057
1058 pci_save_state(dev);
1059 pci_disable_device(dev);
1060 pci_set_power_state(dev, pci_choose_state(dev, state));
1061
1062 mutex_unlock(&(par->open_lock));
1063 release_console_sem();
1064
1065 return 0;
1066 }
1067
1068
1069 /* PCI resume */
1070
1071 static int s3_pci_resume(struct pci_dev* dev)
1072 {
1073 struct fb_info *info = pci_get_drvdata(dev);
1074 struct s3fb_info *par = info->par;
1075 int err;
1076
1077 dev_info(&(dev->dev), "resume\n");
1078
1079 acquire_console_sem();
1080 mutex_lock(&(par->open_lock));
1081
1082 if (par->ref_count == 0) {
1083 mutex_unlock(&(par->open_lock));
1084 release_console_sem();
1085 return 0;
1086 }
1087
1088 pci_set_power_state(dev, PCI_D0);
1089 pci_restore_state(dev);
1090 err = pci_enable_device(dev);
1091 if (err) {
1092 mutex_unlock(&(par->open_lock));
1093 release_console_sem();
1094 dev_err(&(dev->dev), "error %d enabling device for resume\n", err);
1095 return err;
1096 }
1097 pci_set_master(dev);
1098
1099 s3fb_set_par(info);
1100 fb_set_suspend(info, 0);
1101
1102 mutex_unlock(&(par->open_lock));
1103 release_console_sem();
1104
1105 return 0;
1106 }
1107
1108
1109 /* List of boards that we are trying to support */
1110
1111 static struct pci_device_id s3_devices[] __devinitdata = {
1112 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1113 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1114 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1115 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1116 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1117 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1118
1119 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1120 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1121 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1122 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1123 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1124 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1125
1126 {0, 0, 0, 0, 0, 0, 0}
1127 };
1128
1129
1130 MODULE_DEVICE_TABLE(pci, s3_devices);
1131
1132 static struct pci_driver s3fb_pci_driver = {
1133 .name = "s3fb",
1134 .id_table = s3_devices,
1135 .probe = s3_pci_probe,
1136 .remove = __devexit_p(s3_pci_remove),
1137 .suspend = s3_pci_suspend,
1138 .resume = s3_pci_resume,
1139 };
1140
1141 /* Parse user speficied options */
1142
1143 #ifndef MODULE
1144 static int __init s3fb_setup(char *options)
1145 {
1146 char *opt;
1147
1148 if (!options || !*options)
1149 return 0;
1150
1151 while ((opt = strsep(&options, ",")) != NULL) {
1152
1153 if (!*opt)
1154 continue;
1155 #ifdef CONFIG_MTRR
1156 else if (!strncmp(opt, "mtrr:", 5))
1157 mtrr = simple_strtoul(opt + 5, NULL, 0);
1158 #endif
1159 else if (!strncmp(opt, "fasttext:", 9))
1160 fasttext = simple_strtoul(opt + 9, NULL, 0);
1161 else
1162 mode = opt;
1163 }
1164
1165 return 0;
1166 }
1167 #endif
1168
1169 /* Cleanup */
1170
1171 static void __exit s3fb_cleanup(void)
1172 {
1173 pr_debug("s3fb: cleaning up\n");
1174 pci_unregister_driver(&s3fb_pci_driver);
1175 }
1176
1177 /* Driver Initialisation */
1178
1179 static int __init s3fb_init(void)
1180 {
1181
1182 #ifndef MODULE
1183 char *option = NULL;
1184
1185 if (fb_get_options("s3fb", &option))
1186 return -ENODEV;
1187 s3fb_setup(option);
1188 #endif
1189
1190 pr_debug("s3fb: initializing\n");
1191 return pci_register_driver(&s3fb_pci_driver);
1192 }
1193
1194 /* ------------------------------------------------------------------------- */
1195
1196 /* Modularization */
1197
1198 module_init(s3fb_init);
1199 module_exit(s3fb_cleanup);
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