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[mirror_ubuntu-zesty-kernel.git] / drivers / video / tdfxfb.c
1 /*
2 *
3 * tdfxfb.c
4 *
5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
6 *
7 * Copyright © 1999 Hannu Mallat
8 * All rights reserved
9 *
10 * Created : Thu Sep 23 18:17:43 1999, hmallat
11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
12 *
13 * Lots of the information here comes from the Daryll Strauss' Banshee
14 * patches to the XF86 server, and the rest comes from the 3dfx
15 * Banshee specification. I'm very much indebted to Daryll for his
16 * work on the X server.
17 *
18 * Voodoo3 support was contributed Harold Oga. Lots of additions
19 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
20 * Kesmarki. Thanks guys!
21 *
22 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
23 * behave very differently from the Voodoo3/4/5. For anyone wanting to
24 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
25 * located at http://www.sourceforge.net/projects/sstfb).
26 *
27 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
28 * I do wish the next version is a bit more complete. Without the XF86
29 * patches I couldn't have gotten even this far... for instance, the
30 * extensions to the VGA register set go completely unmentioned in the
31 * spec! Also, lots of references are made to the 'SST core', but no
32 * spec is publicly available, AFAIK.
33 *
34 * The structure of this driver comes pretty much from the Permedia
35 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
36 *
37 * TODO:
38 * - support for 16/32 bpp needs fixing (funky bootup penguin)
39 * - multihead support (basically need to support an array of fb_infos)
40 * - support other architectures (PPC, Alpha); does the fact that the VGA
41 * core can be accessed only thru I/O (not memory mapped) complicate
42 * things?
43 *
44 * Version history:
45 *
46 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
47 *
48 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
49 * reorg, hwcursor address page size alignment
50 * (for mmaping both frame buffer and regs),
51 * and my changes to get rid of hardcoded
52 * VGA i/o register locations (uses PCI
53 * configuration info now)
54 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
55 * improvements
56 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
57 * 0.1.0 (released 1999-10-06) initial version
58 *
59 */
60
61 #include <linux/config.h>
62 #include <linux/module.h>
63 #include <linux/kernel.h>
64 #include <linux/errno.h>
65 #include <linux/string.h>
66 #include <linux/mm.h>
67 #include <linux/tty.h>
68 #include <linux/slab.h>
69 #include <linux/delay.h>
70 #include <linux/interrupt.h>
71 #include <linux/fb.h>
72 #include <linux/init.h>
73 #include <linux/pci.h>
74 #include <linux/nvram.h>
75 #include <asm/io.h>
76 #include <linux/timer.h>
77 #include <linux/spinlock.h>
78
79 #include <video/tdfx.h>
80
81 #undef TDFXFB_DEBUG
82 #ifdef TDFXFB_DEBUG
83 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
84 #else
85 #define DPRINTK(a,b...)
86 #endif
87
88 #define BANSHEE_MAX_PIXCLOCK 270000
89 #define VOODOO3_MAX_PIXCLOCK 300000
90 #define VOODOO5_MAX_PIXCLOCK 350000
91
92 static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
93 .id = "3Dfx",
94 .type = FB_TYPE_PACKED_PIXELS,
95 .visual = FB_VISUAL_PSEUDOCOLOR,
96 .ypanstep = 1,
97 .ywrapstep = 1,
98 .accel = FB_ACCEL_3DFX_BANSHEE
99 };
100
101 static struct fb_var_screeninfo tdfx_var __devinitdata = {
102 /* "640x480, 8 bpp @ 60 Hz */
103 .xres = 640,
104 .yres = 480,
105 .xres_virtual = 640,
106 .yres_virtual = 1024,
107 .bits_per_pixel =8,
108 .red = {0, 8, 0},
109 .blue = {0, 8, 0},
110 .green = {0, 8, 0},
111 .activate = FB_ACTIVATE_NOW,
112 .height = -1,
113 .width = -1,
114 .accel_flags = FB_ACCELF_TEXT,
115 .pixclock = 39722,
116 .left_margin = 40,
117 .right_margin = 24,
118 .upper_margin = 32,
119 .lower_margin = 11,
120 .hsync_len = 96,
121 .vsync_len = 2,
122 .vmode = FB_VMODE_NONINTERLACED
123 };
124
125 /*
126 * PCI driver prototypes
127 */
128 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
129 const struct pci_device_id *id);
130 static void __devexit tdfxfb_remove(struct pci_dev *pdev);
131
132 static struct pci_device_id tdfxfb_id_table[] = {
133 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
134 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
135 0xff0000, 0 },
136 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
138 0xff0000, 0 },
139 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
141 0xff0000, 0 },
142 { 0, }
143 };
144
145 static struct pci_driver tdfxfb_driver = {
146 .name = "tdfxfb",
147 .id_table = tdfxfb_id_table,
148 .probe = tdfxfb_probe,
149 .remove = __devexit_p(tdfxfb_remove),
150 };
151
152 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
153
154 /*
155 * Frame buffer device API
156 */
157 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
158 static int tdfxfb_set_par(struct fb_info *info);
159 static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
160 u_int transp, struct fb_info *info);
161 static int tdfxfb_blank(int blank, struct fb_info *info);
162 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
163 static int banshee_wait_idle(struct fb_info *info);
164 #ifdef CONFIG_FB_3DFX_ACCEL
165 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
166 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
167 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
168 #endif /* CONFIG_FB_3DFX_ACCEL */
169
170 static struct fb_ops tdfxfb_ops = {
171 .owner = THIS_MODULE,
172 .fb_check_var = tdfxfb_check_var,
173 .fb_set_par = tdfxfb_set_par,
174 .fb_setcolreg = tdfxfb_setcolreg,
175 .fb_blank = tdfxfb_blank,
176 .fb_pan_display = tdfxfb_pan_display,
177 .fb_sync = banshee_wait_idle,
178 #ifdef CONFIG_FB_3DFX_ACCEL
179 .fb_fillrect = tdfxfb_fillrect,
180 .fb_copyarea = tdfxfb_copyarea,
181 .fb_imageblit = tdfxfb_imageblit,
182 #else
183 .fb_fillrect = cfb_fillrect,
184 .fb_copyarea = cfb_copyarea,
185 .fb_imageblit = cfb_imageblit,
186 #endif
187 .fb_cursor = soft_cursor,
188 };
189
190 /*
191 * do_xxx: Hardware-specific functions
192 */
193 static u32 do_calc_pll(int freq, int *freq_out);
194 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
195 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
196
197 /*
198 * Driver data
199 */
200 static int nopan = 0;
201 static int nowrap = 1; // not implemented (yet)
202 static char *mode_option __devinitdata = NULL;
203
204 /* -------------------------------------------------------------------------
205 * Hardware-specific funcions
206 * ------------------------------------------------------------------------- */
207
208 #ifdef VGA_REG_IO
209 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
210
211 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
212 #else
213 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
214 return inb(par->iobase + reg - 0x300);
215 }
216 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
217 outb(val, par->iobase + reg - 0x300);
218 }
219 #endif
220
221 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
222 vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
223 }
224
225 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
226 vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
227 }
228
229 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
230 vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
231 }
232
233 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
234 vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
235 }
236
237 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
238 vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
239 }
240
241 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
242 {
243 unsigned char tmp;
244
245 tmp = vga_inb(par, IS1_R);
246 vga_outb(par, ATT_IW, idx);
247 vga_outb(par, ATT_IW, val);
248 }
249
250 static inline void vga_disable_video(struct tdfx_par *par)
251 {
252 unsigned char s;
253
254 s = seq_inb(par, 0x01) | 0x20;
255 seq_outb(par, 0x00, 0x01);
256 seq_outb(par, 0x01, s);
257 seq_outb(par, 0x00, 0x03);
258 }
259
260 static inline void vga_enable_video(struct tdfx_par *par)
261 {
262 unsigned char s;
263
264 s = seq_inb(par, 0x01) & 0xdf;
265 seq_outb(par, 0x00, 0x01);
266 seq_outb(par, 0x01, s);
267 seq_outb(par, 0x00, 0x03);
268 }
269
270 static inline void vga_enable_palette(struct tdfx_par *par)
271 {
272 vga_inb(par, IS1_R);
273 vga_outb(par, ATT_IW, 0x20);
274 }
275
276 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
277 {
278 return readl(par->regbase_virt + reg);
279 }
280
281 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
282 {
283 writel(val, par->regbase_virt + reg);
284 }
285
286 static inline void banshee_make_room(struct tdfx_par *par, int size)
287 {
288 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
289 * won't quit if you ask for more. */
290 while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
291 }
292
293 static int banshee_wait_idle(struct fb_info *info)
294 {
295 struct tdfx_par *par = (struct tdfx_par *) info->par;
296 int i = 0;
297
298 banshee_make_room(par, 1);
299 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
300
301 while(1) {
302 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
303 if(i == 3) break;
304 }
305 return 0;
306 }
307
308 /*
309 * Set the color of a palette entry in 8bpp mode
310 */
311 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
312 {
313 banshee_make_room(par, 2);
314 tdfx_outl(par, DACADDR, regno);
315 tdfx_outl(par, DACDATA, c);
316 }
317
318 static u32 do_calc_pll(int freq, int* freq_out)
319 {
320 int m, n, k, best_m, best_n, best_k, best_error;
321 int fref = 14318;
322
323 best_error = freq;
324 best_n = best_m = best_k = 0;
325
326 for (k = 3; k >= 0; k--) {
327 for (m = 63; m >= 0; m--) {
328 /*
329 * Estimate value of n that produces target frequency
330 * with current m and k
331 */
332 int n_estimated = (freq * (m + 2) * (1 << k) / fref) - 2;
333
334 /* Search neighborhood of estimated n */
335 for (n = max(0, n_estimated - 1);
336 n <= min(255, n_estimated + 1); n++) {
337 /*
338 * Calculate PLL freqency with current m, k and
339 * estimated n
340 */
341 int f = fref * (n + 2) / (m + 2) / (1 << k);
342 int error = abs (f - freq);
343
344 /*
345 * If this is the closest we've come to the
346 * target frequency then remember n, m and k
347 */
348 if (error < best_error) {
349 best_error = error;
350 best_n = n;
351 best_m = m;
352 best_k = k;
353 }
354 }
355 }
356 }
357
358 n = best_n;
359 m = best_m;
360 k = best_k;
361 *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
362
363 return (n << 8) | (m << 2) | k;
364 }
365
366 static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
367 {
368 struct tdfx_par *par = (struct tdfx_par *) info->par;
369 int i;
370
371 banshee_wait_idle(info);
372
373 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
374
375 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
376
377 banshee_make_room(par, 3);
378 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
379 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
380 #if 0
381 tdfx_outl(par, PLLCTRL1, reg->mempll);
382 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
383 #endif
384 tdfx_outl(par, PLLCTRL0, reg->vidpll);
385
386 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
387
388 for (i = 0; i < 5; i++)
389 seq_outb(par, i, reg->seq[i]);
390
391 for (i = 0; i < 25; i++)
392 crt_outb(par, i, reg->crt[i]);
393
394 for (i = 0; i < 9; i++)
395 gra_outb(par, i, reg->gra[i]);
396
397 for (i = 0; i < 21; i++)
398 att_outb(par, i, reg->att[i]);
399
400 crt_outb(par, 0x1a, reg->ext[0]);
401 crt_outb(par, 0x1b, reg->ext[1]);
402
403 vga_enable_palette(par);
404 vga_enable_video(par);
405
406 banshee_make_room(par, 11);
407 tdfx_outl(par, VGAINIT0, reg->vgainit0);
408 tdfx_outl(par, DACMODE, reg->dacmode);
409 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
410 tdfx_outl(par, HWCURPATADDR, 0);
411
412 tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
413 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
414 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
415 tdfx_outl(par, VGAINIT1, reg->vgainit1);
416 tdfx_outl(par, MISCINIT0, reg->miscinit0);
417
418 banshee_make_room(par, 8);
419 tdfx_outl(par, SRCBASE, reg->srcbase);
420 tdfx_outl(par, DSTBASE, reg->dstbase);
421 tdfx_outl(par, COMMANDEXTRA_2D, 0);
422 tdfx_outl(par, CLIP0MIN, 0);
423 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
424 tdfx_outl(par, CLIP1MIN, 0);
425 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
426 tdfx_outl(par, SRCXY, 0);
427
428 banshee_wait_idle(info);
429 }
430
431 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
432 {
433 u32 draminit0;
434 u32 draminit1;
435 u32 miscinit1;
436
437 int num_chips;
438 int chip_size; /* in MB */
439 u32 lfbsize;
440 int has_sgram;
441
442 draminit0 = tdfx_inl(par, DRAMINIT0);
443 draminit1 = tdfx_inl(par, DRAMINIT1);
444
445 num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
446
447 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
448 /* Banshee/Voodoo3 */
449 has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
450 chip_size = has_sgram ? ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 2 : 1)
451 : 2;
452 } else {
453 /* Voodoo4/5 */
454 has_sgram = 0;
455 chip_size = 1 << ((draminit0 & DRAMINIT0_SGRAM_TYPE_MASK) >> DRAMINIT0_SGRAM_TYPE_SHIFT);
456 }
457 lfbsize = num_chips * chip_size * 1024 * 1024;
458
459 /* disable block writes for SDRAM */
460 miscinit1 = tdfx_inl(par, MISCINIT1);
461 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
462 miscinit1 |= MISCINIT1_CLUT_INV;
463
464 banshee_make_room(par, 1);
465 tdfx_outl(par, MISCINIT1, miscinit1);
466 return lfbsize;
467 }
468
469 /* ------------------------------------------------------------------------- */
470
471 static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
472 {
473 struct tdfx_par *par = (struct tdfx_par *) info->par;
474 u32 lpitch;
475
476 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
477 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
478 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
479 return -EINVAL;
480 }
481
482 if (var->xres != var->xres_virtual)
483 var->xres_virtual = var->xres;
484
485 if (var->yres > var->yres_virtual)
486 var->yres_virtual = var->yres;
487
488 if (var->xoffset) {
489 DPRINTK("xoffset not supported\n");
490 return -EINVAL;
491 }
492
493 /* Banshee doesn't support interlace, but Voodoo4/5 and probably Voodoo3 do. */
494 /* no direct information about device id now? use max_pixclock for this... */
495 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
496 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
497 DPRINTK("interlace not supported\n");
498 return -EINVAL;
499 }
500
501 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
502 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
503
504 if (var->xres < 320 || var->xres > 2048) {
505 DPRINTK("width not supported: %u\n", var->xres);
506 return -EINVAL;
507 }
508
509 if (var->yres < 200 || var->yres > 2048) {
510 DPRINTK("height not supported: %u\n", var->yres);
511 return -EINVAL;
512 }
513
514 if (lpitch * var->yres_virtual > info->fix.smem_len) {
515 var->yres_virtual = info->fix.smem_len/lpitch;
516 if (var->yres_virtual < var->yres) {
517 DPRINTK("no memory for screen (%ux%ux%u)\n",
518 var->xres, var->yres_virtual, var->bits_per_pixel);
519 return -EINVAL;
520 }
521 }
522
523 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
524 DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
525 return -EINVAL;
526 }
527
528 switch(var->bits_per_pixel) {
529 case 8:
530 var->red.length = var->green.length = var->blue.length = 8;
531 break;
532 case 16:
533 var->red.offset = 11;
534 var->red.length = 5;
535 var->green.offset = 5;
536 var->green.length = 6;
537 var->blue.offset = 0;
538 var->blue.length = 5;
539 break;
540 case 24:
541 var->red.offset=16;
542 var->green.offset=8;
543 var->blue.offset=0;
544 var->red.length = var->green.length = var->blue.length = 8;
545 case 32:
546 var->red.offset = 16;
547 var->green.offset = 8;
548 var->blue.offset = 0;
549 var->red.length = var->green.length = var->blue.length = 8;
550 break;
551 }
552 var->height = var->width = -1;
553
554 var->accel_flags = FB_ACCELF_TEXT;
555
556 DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
557 return 0;
558 }
559
560 static int tdfxfb_set_par(struct fb_info *info)
561 {
562 struct tdfx_par *par = (struct tdfx_par *) info->par;
563 u32 hdispend, hsyncsta, hsyncend, htotal;
564 u32 hd, hs, he, ht, hbs, hbe;
565 u32 vd, vs, ve, vt, vbs, vbe;
566 struct banshee_reg reg;
567 int fout, freq;
568 u32 wd, cpp;
569
570 par->baseline = 0;
571
572 memset(&reg, 0, sizeof(reg));
573 cpp = (info->var.bits_per_pixel + 7)/8;
574
575 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
576
577 /* PLL settings */
578 freq = PICOS2KHZ(info->var.pixclock);
579
580 reg.dacmode = 0;
581 reg.vidcfg &= ~VIDCFG_2X;
582
583 hdispend = info->var.xres;
584 hsyncsta = hdispend + info->var.right_margin;
585 hsyncend = hsyncsta + info->var.hsync_len;
586 htotal = hsyncend + info->var.left_margin;
587
588 if (freq > par->max_pixclock/2) {
589 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
590 reg.dacmode |= DACMODE_2X;
591 reg.vidcfg |= VIDCFG_2X;
592 hdispend >>= 1;
593 hsyncsta >>= 1;
594 hsyncend >>= 1;
595 htotal >>= 1;
596 }
597
598 hd = wd = (hdispend >> 3) - 1;
599 hs = (hsyncsta >> 3) - 1;
600 he = (hsyncend >> 3) - 1;
601 ht = (htotal >> 3) - 1;
602 hbs = hd;
603 hbe = ht;
604
605 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
606 vbs = vd = (info->var.yres << 1) - 1;
607 vs = vd + (info->var.lower_margin << 1);
608 ve = vs + (info->var.vsync_len << 1);
609 vbe = vt = ve + (info->var.upper_margin << 1) - 1;
610 } else {
611 vbs = vd = info->var.yres - 1;
612 vs = vd + info->var.lower_margin;
613 ve = vs + info->var.vsync_len;
614 vbe = vt = ve + info->var.upper_margin - 1;
615 }
616
617 /* this is all pretty standard VGA register stuffing */
618 reg.misc[0x00] = 0x0f |
619 (info->var.xres < 400 ? 0xa0 :
620 info->var.xres < 480 ? 0x60 :
621 info->var.xres < 768 ? 0xe0 : 0x20);
622
623 reg.gra[0x00] = 0x00;
624 reg.gra[0x01] = 0x00;
625 reg.gra[0x02] = 0x00;
626 reg.gra[0x03] = 0x00;
627 reg.gra[0x04] = 0x00;
628 reg.gra[0x05] = 0x40;
629 reg.gra[0x06] = 0x05;
630 reg.gra[0x07] = 0x0f;
631 reg.gra[0x08] = 0xff;
632
633 reg.att[0x00] = 0x00;
634 reg.att[0x01] = 0x01;
635 reg.att[0x02] = 0x02;
636 reg.att[0x03] = 0x03;
637 reg.att[0x04] = 0x04;
638 reg.att[0x05] = 0x05;
639 reg.att[0x06] = 0x06;
640 reg.att[0x07] = 0x07;
641 reg.att[0x08] = 0x08;
642 reg.att[0x09] = 0x09;
643 reg.att[0x0a] = 0x0a;
644 reg.att[0x0b] = 0x0b;
645 reg.att[0x0c] = 0x0c;
646 reg.att[0x0d] = 0x0d;
647 reg.att[0x0e] = 0x0e;
648 reg.att[0x0f] = 0x0f;
649 reg.att[0x10] = 0x41;
650 reg.att[0x11] = 0x00;
651 reg.att[0x12] = 0x0f;
652 reg.att[0x13] = 0x00;
653 reg.att[0x14] = 0x00;
654
655 reg.seq[0x00] = 0x03;
656 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
657 reg.seq[0x02] = 0x0f;
658 reg.seq[0x03] = 0x00;
659 reg.seq[0x04] = 0x0e;
660
661 reg.crt[0x00] = ht - 4;
662 reg.crt[0x01] = hd;
663 reg.crt[0x02] = hbs;
664 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
665 reg.crt[0x04] = hs;
666 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
667 reg.crt[0x06] = vt;
668 reg.crt[0x07] = ((vs & 0x200) >> 2) |
669 ((vd & 0x200) >> 3) |
670 ((vt & 0x200) >> 4) | 0x10 |
671 ((vbs & 0x100) >> 5) |
672 ((vs & 0x100) >> 6) |
673 ((vd & 0x100) >> 7) |
674 ((vt & 0x100) >> 8);
675 reg.crt[0x08] = 0x00;
676 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
677 reg.crt[0x0a] = 0x00;
678 reg.crt[0x0b] = 0x00;
679 reg.crt[0x0c] = 0x00;
680 reg.crt[0x0d] = 0x00;
681 reg.crt[0x0e] = 0x00;
682 reg.crt[0x0f] = 0x00;
683 reg.crt[0x10] = vs;
684 reg.crt[0x11] = (ve & 0x0f) | 0x20;
685 reg.crt[0x12] = vd;
686 reg.crt[0x13] = wd;
687 reg.crt[0x14] = 0x00;
688 reg.crt[0x15] = vbs;
689 reg.crt[0x16] = vbe + 1;
690 reg.crt[0x17] = 0xc3;
691 reg.crt[0x18] = 0xff;
692
693 /* Banshee's nonvga stuff */
694 reg.ext[0x00] = (((ht & 0x100) >> 8) |
695 ((hd & 0x100) >> 6) |
696 ((hbs & 0x100) >> 4) |
697 ((hbe & 0x40) >> 1) |
698 ((hs & 0x100) >> 2) |
699 ((he & 0x20) << 2));
700 reg.ext[0x01] = (((vt & 0x400) >> 10) |
701 ((vd & 0x400) >> 8) |
702 ((vbs & 0x400) >> 6) |
703 ((vbe & 0x400) >> 4));
704
705 reg.vgainit0 = VGAINIT0_8BIT_DAC |
706 VGAINIT0_EXT_ENABLE |
707 VGAINIT0_WAKEUP_3C3 |
708 VGAINIT0_ALT_READBACK |
709 VGAINIT0_EXTSHIFTOUT;
710 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
711
712 reg.cursloc = 0;
713
714 reg.cursc0 = 0;
715 reg.cursc1 = 0xffffff;
716
717 reg.stride = info->var.xres * cpp;
718 reg.startaddr = par->baseline * reg.stride;
719 reg.srcbase = reg.startaddr;
720 reg.dstbase = reg.startaddr;
721
722 /* PLL settings */
723 freq = PICOS2KHZ(info->var.pixclock);
724
725 reg.dacmode &= ~DACMODE_2X;
726 reg.vidcfg &= ~VIDCFG_2X;
727 if (freq > par->max_pixclock/2) {
728 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
729 reg.dacmode |= DACMODE_2X;
730 reg.vidcfg |= VIDCFG_2X;
731 }
732 reg.vidpll = do_calc_pll(freq, &fout);
733 #if 0
734 reg.mempll = do_calc_pll(..., &fout);
735 reg.gfxpll = do_calc_pll(..., &fout);
736 #endif
737
738 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
739 reg.screensize = info->var.xres | (info->var.yres << 13);
740 reg.vidcfg |= VIDCFG_HALF_MODE;
741 reg.crt[0x09] |= 0x80;
742 } else {
743 reg.screensize = info->var.xres | (info->var.yres << 12);
744 reg.vidcfg &= ~VIDCFG_HALF_MODE;
745 }
746 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
747 reg.vidcfg |= VIDCFG_INTERLACE;
748 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
749
750 #if defined(__BIG_ENDIAN)
751 switch (info->var.bits_per_pixel) {
752 case 8:
753 case 24:
754 reg.miscinit0 &= ~(1 << 30);
755 reg.miscinit0 &= ~(1 << 31);
756 break;
757 case 16:
758 reg.miscinit0 |= (1 << 30);
759 reg.miscinit0 |= (1 << 31);
760 break;
761 case 32:
762 reg.miscinit0 |= (1 << 30);
763 reg.miscinit0 &= ~(1 << 31);
764 break;
765 }
766 #endif
767 do_write_regs(info, &reg);
768
769 /* Now change fb_fix_screeninfo according to changes in par */
770 info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
771 info->fix.visual = (info->var.bits_per_pixel == 8)
772 ? FB_VISUAL_PSEUDOCOLOR
773 : FB_VISUAL_TRUECOLOR;
774 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
775 return 0;
776 }
777
778 /* A handy macro shamelessly pinched from matroxfb */
779 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
780
781 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
782 unsigned blue,unsigned transp,struct fb_info *info)
783 {
784 struct tdfx_par *par = (struct tdfx_par *) info->par;
785 u32 rgbcol;
786
787 if (regno >= info->cmap.len || regno > 255) return 1;
788
789 switch (info->fix.visual) {
790 case FB_VISUAL_PSEUDOCOLOR:
791 rgbcol =(((u32)red & 0xff00) << 8) |
792 (((u32)green & 0xff00) << 0) |
793 (((u32)blue & 0xff00) >> 8);
794 do_setpalentry(par, regno, rgbcol);
795 break;
796 /* Truecolor has no hardware color palettes. */
797 case FB_VISUAL_TRUECOLOR:
798 rgbcol = (CNVT_TOHW( red, info->var.red.length) << info->var.red.offset) |
799 (CNVT_TOHW( green, info->var.green.length) << info->var.green.offset) |
800 (CNVT_TOHW( blue, info->var.blue.length) << info->var.blue.offset) |
801 (CNVT_TOHW( transp, info->var.transp.length) << info->var.transp.offset);
802 ((u32*)(info->pseudo_palette))[regno] = rgbcol;
803 break;
804 default:
805 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
806 break;
807 }
808 return 0;
809 }
810
811 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
812 static int tdfxfb_blank(int blank, struct fb_info *info)
813 {
814 struct tdfx_par *par = (struct tdfx_par *) info->par;
815 u32 dacmode, state = 0, vgablank = 0;
816
817 dacmode = tdfx_inl(par, DACMODE);
818
819 switch (blank) {
820 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
821 state = 0;
822 vgablank = 0;
823 break;
824 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
825 state = 0;
826 vgablank = 1;
827 break;
828 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
829 state = BIT(3);
830 vgablank = 1;
831 break;
832 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
833 state = BIT(1);
834 vgablank = 1;
835 break;
836 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
837 state = BIT(1) | BIT(3);
838 vgablank = 1;
839 break;
840 }
841
842 dacmode &= ~(BIT(1) | BIT(3));
843 dacmode |= state;
844 banshee_make_room(par, 1);
845 tdfx_outl(par, DACMODE, dacmode);
846 if (vgablank)
847 vga_disable_video(par);
848 else
849 vga_enable_video(par);
850 return 0;
851 }
852
853 /*
854 * Set the starting position of the visible screen to var->yoffset
855 */
856 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
857 struct fb_info *info)
858 {
859 struct tdfx_par *par = (struct tdfx_par *) info->par;
860 u32 addr;
861
862 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
863 return -EINVAL;
864 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
865 return -EINVAL;
866
867 addr = var->yoffset * info->fix.line_length;
868 banshee_make_room(par, 1);
869 tdfx_outl(par, VIDDESKSTART, addr);
870
871 info->var.xoffset = var->xoffset;
872 info->var.yoffset = var->yoffset;
873 return 0;
874 }
875
876 #ifdef CONFIG_FB_3DFX_ACCEL
877 /*
878 * FillRect 2D command (solidfill or invert (via ROP_XOR))
879 */
880 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
881 {
882 struct tdfx_par *par = (struct tdfx_par *) info->par;
883 u32 bpp = info->var.bits_per_pixel;
884 u32 stride = info->fix.line_length;
885 u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
886 int tdfx_rop;
887
888 if (rect->rop == ROP_COPY)
889 tdfx_rop = TDFX_ROP_COPY;
890 else
891 tdfx_rop = TDFX_ROP_XOR;
892
893 banshee_make_room(par, 5);
894 tdfx_outl(par, DSTFORMAT, fmt);
895 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
896 tdfx_outl(par, COLORFORE, rect->color);
897 } else { /* FB_VISUAL_TRUECOLOR */
898 tdfx_outl(par, COLORFORE, ((u32*)(info->pseudo_palette))[rect->color]);
899 }
900 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
901 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
902 tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
903 }
904
905 /*
906 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
907 */
908 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
909 {
910 struct tdfx_par *par = (struct tdfx_par *) info->par;
911 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
912 u32 bpp = info->var.bits_per_pixel;
913 u32 stride = info->fix.line_length;
914 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
915 u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
916
917 if (area->sx <= area->dx) {
918 //-X
919 blitcmd |= BIT(14);
920 sx += area->width - 1;
921 dx += area->width - 1;
922 }
923 if (area->sy <= area->dy) {
924 //-Y
925 blitcmd |= BIT(15);
926 sy += area->height - 1;
927 dy += area->height - 1;
928 }
929
930 banshee_make_room(par, 6);
931
932 tdfx_outl(par, SRCFORMAT, fmt);
933 tdfx_outl(par, DSTFORMAT, fmt);
934 tdfx_outl(par, COMMAND_2D, blitcmd);
935 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
936 tdfx_outl(par, DSTXY, dx | (dy << 16));
937 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
938 }
939
940 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
941 {
942 struct tdfx_par *par = (struct tdfx_par *) info->par;
943 int size = image->height * ((image->width * image->depth + 7)>>3);
944 int fifo_free;
945 int i, stride = info->fix.line_length;
946 u32 bpp = info->var.bits_per_pixel;
947 u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
948 u8 *chardata = (u8 *) image->data;
949 u32 srcfmt;
950
951 if (image->depth != 1) {
952 //banshee_make_room(par, 6 + ((size + 3) >> 2));
953 //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
954 cfb_imageblit(info, image);
955 return;
956 } else {
957 banshee_make_room(par, 8);
958 switch (info->fix.visual) {
959 case FB_VISUAL_PSEUDOCOLOR:
960 tdfx_outl(par, COLORFORE, image->fg_color);
961 tdfx_outl(par, COLORBACK, image->bg_color);
962 break;
963 case FB_VISUAL_TRUECOLOR:
964 default:
965 tdfx_outl(par, COLORFORE, ((u32*)(info->pseudo_palette))[image->fg_color]);
966 tdfx_outl(par, COLORBACK, ((u32*)(info->pseudo_palette))[image->bg_color]);
967 }
968 #ifdef __BIG_ENDIAN
969 srcfmt = 0x400000 | BIT(20);
970 #else
971 srcfmt = 0x400000;
972 #endif
973 }
974
975 tdfx_outl(par, SRCXY, 0);
976 tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
977 tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
978 tdfx_outl(par, SRCFORMAT, srcfmt);
979 tdfx_outl(par, DSTFORMAT, dstfmt);
980 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
981
982 /* A count of how many free FIFO entries we've requested.
983 * When this goes negative, we need to request more. */
984 fifo_free = 0;
985
986 /* Send four bytes at a time of data */
987 for (i = (size >> 2) ; i > 0; i--) {
988 if(--fifo_free < 0) {
989 fifo_free=31;
990 banshee_make_room(par,fifo_free);
991 }
992 tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
993 chardata += 4;
994 }
995
996 /* Send the leftovers now */
997 banshee_make_room(par,3);
998 i = size%4;
999 switch (i) {
1000 case 0: break;
1001 case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
1002 case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
1003 case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
1004 }
1005 }
1006 #endif /* CONFIG_FB_3DFX_ACCEL */
1007
1008 #ifdef TDFX_HARDWARE_CURSOR
1009 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1010 {
1011 struct tdfx_par *par = (struct tdfx_par *) info->par;
1012 unsigned long flags;
1013
1014 /*
1015 * If the cursor is not be changed this means either we want the
1016 * current cursor state (if enable is set) or we want to query what
1017 * we can do with the cursor (if enable is not set)
1018 */
1019 if (!cursor->set) return 0;
1020
1021 /* Too large of a cursor :-( */
1022 if (cursor->image.width > 64 || cursor->image.height > 64)
1023 return -ENXIO;
1024
1025 /*
1026 * If we are going to be changing things we should disable
1027 * the cursor first
1028 */
1029 if (info->cursor.enable) {
1030 spin_lock_irqsave(&par->DAClock, flags);
1031 info->cursor.enable = 0;
1032 del_timer(&(par->hwcursor.timer));
1033 tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
1034 spin_unlock_irqrestore(&par->DAClock, flags);
1035 }
1036
1037 /* Disable the Cursor */
1038 if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
1039 return 0;
1040
1041 /* fix cursor color - XFree86 forgets to restore it properly */
1042 if (cursor->set && FB_CUR_SETCMAP) {
1043 struct fb_cmap cmap = cursor->image.cmap;
1044 unsigned long bg_color, fg_color;
1045
1046 cmap.len = 2; /* Voodoo 3+ only support 2 color cursors */
1047 fg_color = ((cmap.red[cmap.start] << 16) |
1048 (cmap.green[cmap.start] << 8) |
1049 (cmap.blue[cmap.start]));
1050 bg_color = ((cmap.red[cmap.start+1] << 16) |
1051 (cmap.green[cmap.start+1] << 8) |
1052 (cmap.blue[cmap.start+1]));
1053 fb_copy_cmap(&cmap, &info->cursor.image.cmap);
1054 spin_lock_irqsave(&par->DAClock, flags);
1055 banshee_make_room(par, 2);
1056 tdfx_outl(par, HWCURC0, bg_color);
1057 tdfx_outl(par, HWCURC1, fg_color);
1058 spin_unlock_irqrestore(&par->DAClock, flags);
1059 }
1060
1061 if (cursor->set && FB_CUR_SETPOS) {
1062 int x, y;
1063
1064 x = cursor->image.dx;
1065 y = cursor->image.dy;
1066 y -= info->var.yoffset;
1067 info->cursor.image.dx = x;
1068 info->cursor.image.dy = y;
1069 x += 63;
1070 y += 63;
1071 spin_lock_irqsave(&par->DAClock, flags);
1072 banshee_make_room(par, 1);
1073 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1074 spin_unlock_irqrestore(&par->DAClock, flags);
1075 }
1076
1077 /* Not supported so we fake it */
1078 if (cursor->set && FB_CUR_SETHOT) {
1079 info->cursor.hot.x = cursor->hot.x;
1080 info->cursor.hot.y = cursor->hot.y;
1081 }
1082
1083 if (cursor->set && FB_CUR_SETSHAPE) {
1084 /*
1085 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1086 * The reason is so the card can fetch 8 words at a time
1087 * and are stored on chip for use for the next 8 scanlines.
1088 * This reduces the number of times for access to draw the
1089 * cursor for each screen refresh.
1090 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1091 * (total of 8192 bits or 1024 Kbytes). The two patterns are
1092 * stored in such a way that pattern 0 always resides in the
1093 * lower half (least significant 64 bits) of a 128 bit word
1094 * and pattern 1 the upper half. If you examine the data of
1095 * the cursor image the graphics card uses then from the
1096 * begining you see line one of pattern 0, line one of
1097 * pattern 1, line two of pattern 0, line two of pattern 1,
1098 * etc etc. The linear stride for the cursor is always 16 bytes
1099 * (128 bits) which is the maximum cursor width times two for
1100 * the two monochrome patterns.
1101 */
1102 u8 *cursorbase = (u8 *) info->cursor.image.data;
1103 char *bitmap = (char *)cursor->image.data;
1104 char *mask = (char *) cursor->mask;
1105 int i, j, k, h = 0;
1106
1107 for (i = 0; i < 64; i++) {
1108 if (i < cursor->image.height) {
1109 j = (cursor->image.width + 7) >> 3;
1110 k = 8 - j;
1111
1112 for (;j > 0; j--) {
1113 /* Pattern 0. Copy the cursor bitmap to it */
1114 fb_writeb(*bitmap, cursorbase + h);
1115 bitmap++;
1116 /* Pattern 1. Copy the cursor mask to it */
1117 fb_writeb(*mask, cursorbase + h + 8);
1118 mask++;
1119 h++;
1120 }
1121 for (;k > 0; k--) {
1122 fb_writeb(0, cursorbase + h);
1123 fb_writeb(~0, cursorbase + h + 8);
1124 h++;
1125 }
1126 } else {
1127 fb_writel(0, cursorbase + h);
1128 fb_writel(0, cursorbase + h + 4);
1129 fb_writel(~0, cursorbase + h + 8);
1130 fb_writel(~0, cursorbase + h + 12);
1131 h += 16;
1132 }
1133 }
1134 }
1135 /* Turn the cursor on */
1136 cursor->enable = 1;
1137 info->cursor = *cursor;
1138 mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
1139 spin_lock_irqsave(&par->DAClock, flags);
1140 banshee_make_room(par, 1);
1141 tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
1142 spin_unlock_irqrestore(&par->DAClock, flags);
1143 return 0;
1144 }
1145 #endif
1146
1147 /**
1148 * tdfxfb_probe - Device Initializiation
1149 *
1150 * @pdev: PCI Device to initialize
1151 * @id: PCI Device ID
1152 *
1153 * Initializes and allocates resources for PCI device @pdev.
1154 *
1155 */
1156 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1157 const struct pci_device_id *id)
1158 {
1159 struct tdfx_par *default_par;
1160 struct fb_info *info;
1161 int size, err, lpitch;
1162
1163 if ((err = pci_enable_device(pdev))) {
1164 printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
1165 return err;
1166 }
1167
1168 size = sizeof(struct tdfx_par)+256*sizeof(u32);
1169
1170 info = framebuffer_alloc(size, &pdev->dev);
1171
1172 if (!info) return -ENOMEM;
1173
1174 default_par = info->par;
1175
1176 /* Configure the default fb_fix_screeninfo first */
1177 switch (pdev->device) {
1178 case PCI_DEVICE_ID_3DFX_BANSHEE:
1179 strcat(tdfx_fix.id, " Banshee");
1180 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1181 break;
1182 case PCI_DEVICE_ID_3DFX_VOODOO3:
1183 strcat(tdfx_fix.id, " Voodoo3");
1184 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1185 break;
1186 case PCI_DEVICE_ID_3DFX_VOODOO5:
1187 strcat(tdfx_fix.id, " Voodoo5");
1188 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1189 break;
1190 }
1191
1192 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1193 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1194 default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1195 if (!default_par->regbase_virt) {
1196 printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
1197 goto out_err;
1198 }
1199
1200 if (!request_mem_region(pci_resource_start(pdev, 0),
1201 pci_resource_len(pdev, 0), "tdfx regbase")) {
1202 printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
1203 goto out_err;
1204 }
1205
1206 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1207 if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
1208 printk("fb: Can't count %s memory.\n", tdfx_fix.id);
1209 release_mem_region(pci_resource_start(pdev, 0),
1210 pci_resource_len(pdev, 0));
1211 goto out_err;
1212 }
1213
1214 if (!request_mem_region(pci_resource_start(pdev, 1),
1215 pci_resource_len(pdev, 1), "tdfx smem")) {
1216 printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
1217 release_mem_region(pci_resource_start(pdev, 0),
1218 pci_resource_len(pdev, 0));
1219 goto out_err;
1220 }
1221
1222 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1223 tdfx_fix.smem_len);
1224 if (!info->screen_base) {
1225 printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
1226 release_mem_region(pci_resource_start(pdev, 1),
1227 pci_resource_len(pdev, 1));
1228 release_mem_region(pci_resource_start(pdev, 0),
1229 pci_resource_len(pdev, 0));
1230 goto out_err;
1231 }
1232
1233 default_par->iobase = pci_resource_start(pdev, 2);
1234
1235 if (!request_region(pci_resource_start(pdev, 2),
1236 pci_resource_len(pdev, 2), "tdfx iobase")) {
1237 printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
1238 release_mem_region(pci_resource_start(pdev, 1),
1239 pci_resource_len(pdev, 1));
1240 release_mem_region(pci_resource_start(pdev, 0),
1241 pci_resource_len(pdev, 0));
1242 goto out_err;
1243 }
1244
1245 printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
1246
1247 tdfx_fix.ypanstep = nopan ? 0 : 1;
1248 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1249
1250 info->fbops = &tdfxfb_ops;
1251 info->fix = tdfx_fix;
1252 info->pseudo_palette = (void *)(default_par + 1);
1253 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1254 #ifdef CONFIG_FB_3DFX_ACCEL
1255 info->flags |= FBINFO_HWACCEL_FILLRECT |
1256 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_IMAGEBLIT;
1257 #endif
1258
1259 if (!mode_option)
1260 mode_option = "640x480@60";
1261
1262 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1263 if (!err || err == 4)
1264 info->var = tdfx_var;
1265
1266 /* maximize virtual vertical length */
1267 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1268 info->var.yres_virtual = info->fix.smem_len/lpitch;
1269 if (info->var.yres_virtual < info->var.yres)
1270 goto out_err;
1271
1272 #ifdef CONFIG_FB_3DFX_ACCEL
1273 /*
1274 * FIXME: Limit var->yres_virtual to 4096 because of screen artifacts
1275 * during scrolling. This is only present if 2D acceleration is
1276 * enabled.
1277 */
1278 if (info->var.yres_virtual > 4096)
1279 info->var.yres_virtual = 4096;
1280 #endif /* CONFIG_FB_3DFX_ACCEL */
1281
1282 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1283 printk(KERN_WARNING "tdfxfb: Can't allocate color map\n");
1284 goto out_err;
1285 }
1286
1287 if (register_framebuffer(info) < 0) {
1288 printk("tdfxfb: can't register framebuffer\n");
1289 fb_dealloc_cmap(&info->cmap);
1290 goto out_err;
1291 }
1292 /*
1293 * Our driver data
1294 */
1295 pci_set_drvdata(pdev, info);
1296 return 0;
1297
1298 out_err:
1299 /*
1300 * Cleanup after anything that was remapped/allocated.
1301 */
1302 if (default_par->regbase_virt)
1303 iounmap(default_par->regbase_virt);
1304 if (info->screen_base)
1305 iounmap(info->screen_base);
1306 framebuffer_release(info);
1307 return -ENXIO;
1308 }
1309
1310 #ifndef MODULE
1311 void tdfxfb_setup(char *options)
1312 {
1313 char* this_opt;
1314
1315 if (!options || !*options)
1316 return;
1317
1318 while ((this_opt = strsep(&options, ",")) != NULL) {
1319 if (!*this_opt)
1320 continue;
1321 if(!strcmp(this_opt, "nopan")) {
1322 nopan = 1;
1323 } else if(!strcmp(this_opt, "nowrap")) {
1324 nowrap = 1;
1325 } else {
1326 mode_option = this_opt;
1327 }
1328 }
1329 }
1330 #endif
1331
1332 /**
1333 * tdfxfb_remove - Device removal
1334 *
1335 * @pdev: PCI Device to cleanup
1336 *
1337 * Releases all resources allocated during the course of the driver's
1338 * lifetime for the PCI device @pdev.
1339 *
1340 */
1341 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1342 {
1343 struct fb_info *info = pci_get_drvdata(pdev);
1344 struct tdfx_par *par = (struct tdfx_par *) info->par;
1345
1346 unregister_framebuffer(info);
1347 iounmap(par->regbase_virt);
1348 iounmap(info->screen_base);
1349
1350 /* Clean up after reserved regions */
1351 release_region(pci_resource_start(pdev, 2),
1352 pci_resource_len(pdev, 2));
1353 release_mem_region(pci_resource_start(pdev, 1),
1354 pci_resource_len(pdev, 1));
1355 release_mem_region(pci_resource_start(pdev, 0),
1356 pci_resource_len(pdev, 0));
1357 pci_set_drvdata(pdev, NULL);
1358 framebuffer_release(info);
1359 }
1360
1361 static int __init tdfxfb_init(void)
1362 {
1363 #ifndef MODULE
1364 char *option = NULL;
1365
1366 if (fb_get_options("tdfxfb", &option))
1367 return -ENODEV;
1368
1369 tdfxfb_setup(option);
1370 #endif
1371 return pci_register_driver(&tdfxfb_driver);
1372 }
1373
1374 static void __exit tdfxfb_exit(void)
1375 {
1376 pci_unregister_driver(&tdfxfb_driver);
1377 }
1378
1379 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1380 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1381 MODULE_LICENSE("GPL");
1382
1383 module_init(tdfxfb_init);
1384 module_exit(tdfxfb_exit);
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