2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 static struct pll_map pll_value
[] = {
25 {CLK_25_175M
, CLE266_PLL_25_175M
, K800_PLL_25_175M
,
26 CX700_25_175M
, VX855_25_175M
},
27 {CLK_29_581M
, CLE266_PLL_29_581M
, K800_PLL_29_581M
,
28 CX700_29_581M
, VX855_29_581M
},
29 {CLK_26_880M
, CLE266_PLL_26_880M
, K800_PLL_26_880M
,
30 CX700_26_880M
, VX855_26_880M
},
31 {CLK_31_490M
, CLE266_PLL_31_490M
, K800_PLL_31_490M
,
32 CX700_31_490M
, VX855_31_490M
},
33 {CLK_31_500M
, CLE266_PLL_31_500M
, K800_PLL_31_500M
,
34 CX700_31_500M
, VX855_31_500M
},
35 {CLK_31_728M
, CLE266_PLL_31_728M
, K800_PLL_31_728M
,
36 CX700_31_728M
, VX855_31_728M
},
37 {CLK_32_668M
, CLE266_PLL_32_668M
, K800_PLL_32_668M
,
38 CX700_32_668M
, VX855_32_668M
},
39 {CLK_36_000M
, CLE266_PLL_36_000M
, K800_PLL_36_000M
,
40 CX700_36_000M
, VX855_36_000M
},
41 {CLK_40_000M
, CLE266_PLL_40_000M
, K800_PLL_40_000M
,
42 CX700_40_000M
, VX855_40_000M
},
43 {CLK_41_291M
, CLE266_PLL_41_291M
, K800_PLL_41_291M
,
44 CX700_41_291M
, VX855_41_291M
},
45 {CLK_43_163M
, CLE266_PLL_43_163M
, K800_PLL_43_163M
,
46 CX700_43_163M
, VX855_43_163M
},
47 {CLK_45_250M
, CLE266_PLL_45_250M
, K800_PLL_45_250M
,
48 CX700_45_250M
, VX855_45_250M
},
49 {CLK_46_000M
, CLE266_PLL_46_000M
, K800_PLL_46_000M
,
50 CX700_46_000M
, VX855_46_000M
},
51 {CLK_46_996M
, CLE266_PLL_46_996M
, K800_PLL_46_996M
,
52 CX700_46_996M
, VX855_46_996M
},
53 {CLK_48_000M
, CLE266_PLL_48_000M
, K800_PLL_48_000M
,
54 CX700_48_000M
, VX855_48_000M
},
55 {CLK_48_875M
, CLE266_PLL_48_875M
, K800_PLL_48_875M
,
56 CX700_48_875M
, VX855_48_875M
},
57 {CLK_49_500M
, CLE266_PLL_49_500M
, K800_PLL_49_500M
,
58 CX700_49_500M
, VX855_49_500M
},
59 {CLK_52_406M
, CLE266_PLL_52_406M
, K800_PLL_52_406M
,
60 CX700_52_406M
, VX855_52_406M
},
61 {CLK_52_977M
, CLE266_PLL_52_977M
, K800_PLL_52_977M
,
62 CX700_52_977M
, VX855_52_977M
},
63 {CLK_56_250M
, CLE266_PLL_56_250M
, K800_PLL_56_250M
,
64 CX700_56_250M
, VX855_56_250M
},
65 {CLK_57_275M
, 0, 0, 0, VX855_57_275M
},
66 {CLK_60_466M
, CLE266_PLL_60_466M
, K800_PLL_60_466M
,
67 CX700_60_466M
, VX855_60_466M
},
68 {CLK_61_500M
, CLE266_PLL_61_500M
, K800_PLL_61_500M
,
69 CX700_61_500M
, VX855_61_500M
},
70 {CLK_65_000M
, CLE266_PLL_65_000M
, K800_PLL_65_000M
,
71 CX700_65_000M
, VX855_65_000M
},
72 {CLK_65_178M
, CLE266_PLL_65_178M
, K800_PLL_65_178M
,
73 CX700_65_178M
, VX855_65_178M
},
74 {CLK_66_750M
, CLE266_PLL_66_750M
, K800_PLL_66_750M
,
75 CX700_66_750M
, VX855_66_750M
},
76 {CLK_68_179M
, CLE266_PLL_68_179M
, K800_PLL_68_179M
,
77 CX700_68_179M
, VX855_68_179M
},
78 {CLK_69_924M
, CLE266_PLL_69_924M
, K800_PLL_69_924M
,
79 CX700_69_924M
, VX855_69_924M
},
80 {CLK_70_159M
, CLE266_PLL_70_159M
, K800_PLL_70_159M
,
81 CX700_70_159M
, VX855_70_159M
},
82 {CLK_72_000M
, CLE266_PLL_72_000M
, K800_PLL_72_000M
,
83 CX700_72_000M
, VX855_72_000M
},
84 {CLK_78_750M
, CLE266_PLL_78_750M
, K800_PLL_78_750M
,
85 CX700_78_750M
, VX855_78_750M
},
86 {CLK_80_136M
, CLE266_PLL_80_136M
, K800_PLL_80_136M
,
87 CX700_80_136M
, VX855_80_136M
},
88 {CLK_83_375M
, CLE266_PLL_83_375M
, K800_PLL_83_375M
,
89 CX700_83_375M
, VX855_83_375M
},
90 {CLK_83_950M
, CLE266_PLL_83_950M
, K800_PLL_83_950M
,
91 CX700_83_950M
, VX855_83_950M
},
92 {CLK_84_750M
, CLE266_PLL_84_750M
, K800_PLL_84_750M
,
93 CX700_84_750M
, VX855_84_750M
},
94 {CLK_85_860M
, CLE266_PLL_85_860M
, K800_PLL_85_860M
,
95 CX700_85_860M
, VX855_85_860M
},
96 {CLK_88_750M
, CLE266_PLL_88_750M
, K800_PLL_88_750M
,
97 CX700_88_750M
, VX855_88_750M
},
98 {CLK_94_500M
, CLE266_PLL_94_500M
, K800_PLL_94_500M
,
99 CX700_94_500M
, VX855_94_500M
},
100 {CLK_97_750M
, CLE266_PLL_97_750M
, K800_PLL_97_750M
,
101 CX700_97_750M
, VX855_97_750M
},
102 {CLK_101_000M
, CLE266_PLL_101_000M
, K800_PLL_101_000M
,
103 CX700_101_000M
, VX855_101_000M
},
104 {CLK_106_500M
, CLE266_PLL_106_500M
, K800_PLL_106_500M
,
105 CX700_106_500M
, VX855_106_500M
},
106 {CLK_108_000M
, CLE266_PLL_108_000M
, K800_PLL_108_000M
,
107 CX700_108_000M
, VX855_108_000M
},
108 {CLK_113_309M
, CLE266_PLL_113_309M
, K800_PLL_113_309M
,
109 CX700_113_309M
, VX855_113_309M
},
110 {CLK_118_840M
, CLE266_PLL_118_840M
, K800_PLL_118_840M
,
111 CX700_118_840M
, VX855_118_840M
},
112 {CLK_119_000M
, CLE266_PLL_119_000M
, K800_PLL_119_000M
,
113 CX700_119_000M
, VX855_119_000M
},
114 {CLK_121_750M
, CLE266_PLL_121_750M
, K800_PLL_121_750M
,
116 {CLK_125_104M
, CLE266_PLL_125_104M
, K800_PLL_125_104M
,
118 {CLK_133_308M
, CLE266_PLL_133_308M
, K800_PLL_133_308M
,
120 {CLK_135_000M
, CLE266_PLL_135_000M
, K800_PLL_135_000M
,
121 CX700_135_000M
, VX855_135_000M
},
122 {CLK_136_700M
, CLE266_PLL_136_700M
, K800_PLL_136_700M
,
123 CX700_136_700M
, VX855_136_700M
},
124 {CLK_138_400M
, CLE266_PLL_138_400M
, K800_PLL_138_400M
,
125 CX700_138_400M
, VX855_138_400M
},
126 {CLK_146_760M
, CLE266_PLL_146_760M
, K800_PLL_146_760M
,
127 CX700_146_760M
, VX855_146_760M
},
128 {CLK_153_920M
, CLE266_PLL_153_920M
, K800_PLL_153_920M
,
129 CX700_153_920M
, VX855_153_920M
},
130 {CLK_156_000M
, CLE266_PLL_156_000M
, K800_PLL_156_000M
,
131 CX700_156_000M
, VX855_156_000M
},
132 {CLK_157_500M
, CLE266_PLL_157_500M
, K800_PLL_157_500M
,
133 CX700_157_500M
, VX855_157_500M
},
134 {CLK_162_000M
, CLE266_PLL_162_000M
, K800_PLL_162_000M
,
135 CX700_162_000M
, VX855_162_000M
},
136 {CLK_187_000M
, CLE266_PLL_187_000M
, K800_PLL_187_000M
,
137 CX700_187_000M
, VX855_187_000M
},
138 {CLK_193_295M
, CLE266_PLL_193_295M
, K800_PLL_193_295M
,
139 CX700_193_295M
, VX855_193_295M
},
140 {CLK_202_500M
, CLE266_PLL_202_500M
, K800_PLL_202_500M
,
141 CX700_202_500M
, VX855_202_500M
},
142 {CLK_204_000M
, CLE266_PLL_204_000M
, K800_PLL_204_000M
,
143 CX700_204_000M
, VX855_204_000M
},
144 {CLK_218_500M
, CLE266_PLL_218_500M
, K800_PLL_218_500M
,
145 CX700_218_500M
, VX855_218_500M
},
146 {CLK_234_000M
, CLE266_PLL_234_000M
, K800_PLL_234_000M
,
147 CX700_234_000M
, VX855_234_000M
},
148 {CLK_267_250M
, CLE266_PLL_267_250M
, K800_PLL_267_250M
,
149 CX700_267_250M
, VX855_267_250M
},
150 {CLK_297_500M
, CLE266_PLL_297_500M
, K800_PLL_297_500M
,
151 CX700_297_500M
, VX855_297_500M
},
152 {CLK_74_481M
, CLE266_PLL_74_481M
, K800_PLL_74_481M
,
153 CX700_74_481M
, VX855_74_481M
},
154 {CLK_172_798M
, CLE266_PLL_172_798M
, K800_PLL_172_798M
,
155 CX700_172_798M
, VX855_172_798M
},
156 {CLK_122_614M
, CLE266_PLL_122_614M
, K800_PLL_122_614M
,
157 CX700_122_614M
, VX855_122_614M
},
158 {CLK_74_270M
, CLE266_PLL_74_270M
, K800_PLL_74_270M
,
160 {CLK_148_500M
, CLE266_PLL_148_500M
, K800_PLL_148_500M
,
161 CX700_148_500M
, VX855_148_500M
}
164 static struct fifo_depth_select display_fifo_depth_reg
= {
165 /* IGA1 FIFO Depth_Select */
166 {IGA1_FIFO_DEPTH_SELECT_REG_NUM
, {{SR17
, 0, 7} } },
167 /* IGA2 FIFO Depth_Select */
168 {IGA2_FIFO_DEPTH_SELECT_REG_NUM
,
169 {{CR68
, 4, 7}, {CR94
, 7, 7}, {CR95
, 7, 7} } }
172 static struct fifo_threshold_select fifo_threshold_select_reg
= {
173 /* IGA1 FIFO Threshold Select */
174 {IGA1_FIFO_THRESHOLD_REG_NUM
, {{SR16
, 0, 5}, {SR16
, 7, 7} } },
175 /* IGA2 FIFO Threshold Select */
176 {IGA2_FIFO_THRESHOLD_REG_NUM
, {{CR68
, 0, 3}, {CR95
, 4, 6} } }
179 static struct fifo_high_threshold_select fifo_high_threshold_select_reg
= {
180 /* IGA1 FIFO High Threshold Select */
181 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM
, {{SR18
, 0, 5}, {SR18
, 7, 7} } },
182 /* IGA2 FIFO High Threshold Select */
183 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM
, {{CR92
, 0, 3}, {CR95
, 0, 2} } }
186 static struct display_queue_expire_num display_queue_expire_num_reg
= {
187 /* IGA1 Display Queue Expire Num */
188 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM
, {{SR22
, 0, 4} } },
189 /* IGA2 Display Queue Expire Num */
190 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM
, {{CR94
, 0, 6} } }
193 /* Definition Fetch Count Registers*/
194 static struct fetch_count fetch_count_reg
= {
195 /* IGA1 Fetch Count Register */
196 {IGA1_FETCH_COUNT_REG_NUM
, {{SR1C
, 0, 7}, {SR1D
, 0, 1} } },
197 /* IGA2 Fetch Count Register */
198 {IGA2_FETCH_COUNT_REG_NUM
, {{CR65
, 0, 7}, {CR67
, 2, 3} } }
201 static struct iga1_crtc_timing iga1_crtc_reg
= {
202 /* IGA1 Horizontal Total */
203 {IGA1_HOR_TOTAL_REG_NUM
, {{CR00
, 0, 7}, {CR36
, 3, 3} } },
204 /* IGA1 Horizontal Addressable Video */
205 {IGA1_HOR_ADDR_REG_NUM
, {{CR01
, 0, 7} } },
206 /* IGA1 Horizontal Blank Start */
207 {IGA1_HOR_BLANK_START_REG_NUM
, {{CR02
, 0, 7} } },
208 /* IGA1 Horizontal Blank End */
209 {IGA1_HOR_BLANK_END_REG_NUM
,
210 {{CR03
, 0, 4}, {CR05
, 7, 7}, {CR33
, 5, 5} } },
211 /* IGA1 Horizontal Sync Start */
212 {IGA1_HOR_SYNC_START_REG_NUM
, {{CR04
, 0, 7}, {CR33
, 4, 4} } },
213 /* IGA1 Horizontal Sync End */
214 {IGA1_HOR_SYNC_END_REG_NUM
, {{CR05
, 0, 4} } },
215 /* IGA1 Vertical Total */
216 {IGA1_VER_TOTAL_REG_NUM
,
217 {{CR06
, 0, 7}, {CR07
, 0, 0}, {CR07
, 5, 5}, {CR35
, 0, 0} } },
218 /* IGA1 Vertical Addressable Video */
219 {IGA1_VER_ADDR_REG_NUM
,
220 {{CR12
, 0, 7}, {CR07
, 1, 1}, {CR07
, 6, 6}, {CR35
, 2, 2} } },
221 /* IGA1 Vertical Blank Start */
222 {IGA1_VER_BLANK_START_REG_NUM
,
223 {{CR15
, 0, 7}, {CR07
, 3, 3}, {CR09
, 5, 5}, {CR35
, 3, 3} } },
224 /* IGA1 Vertical Blank End */
225 {IGA1_VER_BLANK_END_REG_NUM
, {{CR16
, 0, 7} } },
226 /* IGA1 Vertical Sync Start */
227 {IGA1_VER_SYNC_START_REG_NUM
,
228 {{CR10
, 0, 7}, {CR07
, 2, 2}, {CR07
, 7, 7}, {CR35
, 1, 1} } },
229 /* IGA1 Vertical Sync End */
230 {IGA1_VER_SYNC_END_REG_NUM
, {{CR11
, 0, 3} } }
233 static struct iga2_crtc_timing iga2_crtc_reg
= {
234 /* IGA2 Horizontal Total */
235 {IGA2_HOR_TOTAL_REG_NUM
, {{CR50
, 0, 7}, {CR55
, 0, 3} } },
236 /* IGA2 Horizontal Addressable Video */
237 {IGA2_HOR_ADDR_REG_NUM
, {{CR51
, 0, 7}, {CR55
, 4, 6} } },
238 /* IGA2 Horizontal Blank Start */
239 {IGA2_HOR_BLANK_START_REG_NUM
, {{CR52
, 0, 7}, {CR54
, 0, 2} } },
240 /* IGA2 Horizontal Blank End */
241 {IGA2_HOR_BLANK_END_REG_NUM
,
242 {{CR53
, 0, 7}, {CR54
, 3, 5}, {CR5D
, 6, 6} } },
243 /* IGA2 Horizontal Sync Start */
244 {IGA2_HOR_SYNC_START_REG_NUM
,
245 {{CR56
, 0, 7}, {CR54
, 6, 7}, {CR5C
, 7, 7}, {CR5D
, 7, 7} } },
246 /* IGA2 Horizontal Sync End */
247 {IGA2_HOR_SYNC_END_REG_NUM
, {{CR57
, 0, 7}, {CR5C
, 6, 6} } },
248 /* IGA2 Vertical Total */
249 {IGA2_VER_TOTAL_REG_NUM
, {{CR58
, 0, 7}, {CR5D
, 0, 2} } },
250 /* IGA2 Vertical Addressable Video */
251 {IGA2_VER_ADDR_REG_NUM
, {{CR59
, 0, 7}, {CR5D
, 3, 5} } },
252 /* IGA2 Vertical Blank Start */
253 {IGA2_VER_BLANK_START_REG_NUM
, {{CR5A
, 0, 7}, {CR5C
, 0, 2} } },
254 /* IGA2 Vertical Blank End */
255 {IGA2_VER_BLANK_END_REG_NUM
, {{CR5B
, 0, 7}, {CR5C
, 3, 5} } },
256 /* IGA2 Vertical Sync Start */
257 {IGA2_VER_SYNC_START_REG_NUM
, {{CR5E
, 0, 7}, {CR5F
, 5, 7} } },
258 /* IGA2 Vertical Sync End */
259 {IGA2_VER_SYNC_END_REG_NUM
, {{CR5F
, 0, 4} } }
262 static struct rgbLUT palLUT_table
[] = {
264 /* Index 0x00~0x03 */
265 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
268 /* Index 0x04~0x07 */
269 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
272 /* Index 0x08~0x0B */
273 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
276 /* Index 0x0C~0x0F */
277 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
280 /* Index 0x10~0x13 */
281 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
284 /* Index 0x14~0x17 */
285 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
288 /* Index 0x18~0x1B */
289 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
292 /* Index 0x1C~0x1F */
293 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
296 /* Index 0x20~0x23 */
297 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
300 /* Index 0x24~0x27 */
301 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
304 /* Index 0x28~0x2B */
305 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
308 /* Index 0x2C~0x2F */
309 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
312 /* Index 0x30~0x33 */
313 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
316 /* Index 0x34~0x37 */
317 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
320 /* Index 0x38~0x3B */
321 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
324 /* Index 0x3C~0x3F */
325 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
328 /* Index 0x40~0x43 */
329 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
332 /* Index 0x44~0x47 */
333 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
336 /* Index 0x48~0x4B */
337 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
340 /* Index 0x4C~0x4F */
341 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
344 /* Index 0x50~0x53 */
345 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
348 /* Index 0x54~0x57 */
349 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
352 /* Index 0x58~0x5B */
353 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
356 /* Index 0x5C~0x5F */
357 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
360 /* Index 0x60~0x63 */
361 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
364 /* Index 0x64~0x67 */
365 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
368 /* Index 0x68~0x6B */
369 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
372 /* Index 0x6C~0x6F */
373 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
376 /* Index 0x70~0x73 */
377 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
380 /* Index 0x74~0x77 */
381 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
384 /* Index 0x78~0x7B */
385 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
388 /* Index 0x7C~0x7F */
389 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
392 /* Index 0x80~0x83 */
393 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
396 /* Index 0x84~0x87 */
397 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
400 /* Index 0x88~0x8B */
401 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
404 /* Index 0x8C~0x8F */
405 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
408 /* Index 0x90~0x93 */
409 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
412 /* Index 0x94~0x97 */
413 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
416 /* Index 0x98~0x9B */
417 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
420 /* Index 0x9C~0x9F */
421 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
424 /* Index 0xA0~0xA3 */
425 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
428 /* Index 0xA4~0xA7 */
429 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
432 /* Index 0xA8~0xAB */
433 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
436 /* Index 0xAC~0xAF */
437 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
440 /* Index 0xB0~0xB3 */
441 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
444 /* Index 0xB4~0xB7 */
445 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
448 /* Index 0xB8~0xBB */
449 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
452 /* Index 0xBC~0xBF */
453 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
456 /* Index 0xC0~0xC3 */
457 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
460 /* Index 0xC4~0xC7 */
461 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
464 /* Index 0xC8~0xCB */
465 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
468 /* Index 0xCC~0xCF */
469 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
472 /* Index 0xD0~0xD3 */
473 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
476 /* Index 0xD4~0xD7 */
477 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
480 /* Index 0xD8~0xDB */
481 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
484 /* Index 0xDC~0xDF */
485 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
488 /* Index 0xE0~0xE3 */
489 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
492 /* Index 0xE4~0xE7 */
493 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
496 /* Index 0xE8~0xEB */
497 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
500 /* Index 0xEC~0xEF */
501 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
504 /* Index 0xF0~0xF3 */
505 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
508 /* Index 0xF4~0xF7 */
509 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
512 /* Index 0xF8~0xFB */
513 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
516 /* Index 0xFC~0xFF */
517 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
522 static void set_crt_output_path(int set_iga
);
523 static void dvi_patch_skew_dvp0(void);
524 static void dvi_patch_skew_dvp1(void);
525 static void dvi_patch_skew_dvp_low(void);
526 static void set_dvi_output_path(int set_iga
, int output_interface
);
527 static void set_lcd_output_path(int set_iga
, int output_interface
);
528 static void load_fix_bit_crtc_reg(void);
529 static void init_gfx_chip_info(struct pci_dev
*pdev
,
530 const struct pci_device_id
*pdi
);
531 static void init_tmds_chip_info(void);
532 static void init_lvds_chip_info(void);
533 static void device_screen_off(void);
534 static void device_screen_on(void);
535 static void set_display_channel(void);
536 static void device_off(void);
537 static void device_on(void);
538 static void enable_second_display_channel(void);
539 static void disable_second_display_channel(void);
541 void viafb_write_reg(u8 index
, u16 io_port
, u8 data
)
543 outb(index
, io_port
);
544 outb(data
, io_port
+ 1);
545 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
547 u8
viafb_read_reg(int io_port
, u8 index
)
549 outb(index
, io_port
);
550 return inb(io_port
+ 1);
553 void viafb_lock_crt(void)
555 viafb_write_reg_mask(CR11
, VIACR
, BIT7
, BIT7
);
558 void viafb_unlock_crt(void)
560 viafb_write_reg_mask(CR11
, VIACR
, 0, BIT7
);
561 viafb_write_reg_mask(CR47
, VIACR
, 0, BIT0
);
564 void viafb_write_reg_mask(u8 index
, int io_port
, u8 data
, u8 mask
)
568 outb(index
, io_port
);
569 tmp
= inb(io_port
+ 1);
570 outb((data
& mask
) | (tmp
& (~mask
)), io_port
+ 1);
571 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
574 void write_dac_reg(u8 index
, u8 r
, u8 g
, u8 b
)
576 outb(index
, LUT_INDEX_WRITE
);
582 /*Set IGA path for each device*/
583 void viafb_set_iga_path(void)
586 if (viafb_SAMM_ON
== 1) {
588 if (viafb_primary_dev
== CRT_Device
)
589 viaparinfo
->crt_setting_info
->iga_path
= IGA1
;
591 viaparinfo
->crt_setting_info
->iga_path
= IGA2
;
595 if (viafb_primary_dev
== DVI_Device
)
596 viaparinfo
->tmds_setting_info
->iga_path
= IGA1
;
598 viaparinfo
->tmds_setting_info
->iga_path
= IGA2
;
602 if (viafb_primary_dev
== LCD_Device
) {
604 (viaparinfo
->chip_info
->gfx_chip_name
==
607 lvds_setting_info
->iga_path
= IGA2
;
609 crt_setting_info
->iga_path
= IGA1
;
611 tmds_setting_info
->iga_path
= IGA1
;
614 lvds_setting_info
->iga_path
= IGA1
;
616 viaparinfo
->lvds_setting_info
->iga_path
= IGA2
;
620 if (LCD2_Device
== viafb_primary_dev
)
621 viaparinfo
->lvds_setting_info2
->iga_path
= IGA1
;
623 viaparinfo
->lvds_setting_info2
->iga_path
= IGA2
;
628 if (viafb_CRT_ON
&& viafb_LCD_ON
) {
629 viaparinfo
->crt_setting_info
->iga_path
= IGA1
;
630 viaparinfo
->lvds_setting_info
->iga_path
= IGA2
;
631 } else if (viafb_CRT_ON
&& viafb_DVI_ON
) {
632 viaparinfo
->crt_setting_info
->iga_path
= IGA1
;
633 viaparinfo
->tmds_setting_info
->iga_path
= IGA2
;
634 } else if (viafb_LCD_ON
&& viafb_DVI_ON
) {
635 viaparinfo
->tmds_setting_info
->iga_path
= IGA1
;
636 viaparinfo
->lvds_setting_info
->iga_path
= IGA2
;
637 } else if (viafb_LCD_ON
&& viafb_LCD2_ON
) {
638 viaparinfo
->lvds_setting_info
->iga_path
= IGA2
;
639 viaparinfo
->lvds_setting_info2
->iga_path
= IGA2
;
640 } else if (viafb_CRT_ON
) {
641 viaparinfo
->crt_setting_info
->iga_path
= IGA1
;
642 } else if (viafb_LCD_ON
) {
643 viaparinfo
->lvds_setting_info
->iga_path
= IGA2
;
644 } else if (viafb_DVI_ON
) {
645 viaparinfo
->tmds_setting_info
->iga_path
= IGA1
;
650 void viafb_set_primary_address(u32 addr
)
652 DEBUG_MSG(KERN_DEBUG
"viafb_set_primary_address(0x%08X)\n", addr
);
653 viafb_write_reg(CR0D
, VIACR
, addr
& 0xFF);
654 viafb_write_reg(CR0C
, VIACR
, (addr
>> 8) & 0xFF);
655 viafb_write_reg(CR34
, VIACR
, (addr
>> 16) & 0xFF);
656 viafb_write_reg_mask(CR48
, VIACR
, (addr
>> 24) & 0x1F, 0x1F);
659 void viafb_set_secondary_address(u32 addr
)
661 DEBUG_MSG(KERN_DEBUG
"viafb_set_secondary_address(0x%08X)\n", addr
);
662 /* secondary display supports only quadword aligned memory */
663 viafb_write_reg_mask(CR62
, VIACR
, (addr
>> 2) & 0xFE, 0xFE);
664 viafb_write_reg(CR63
, VIACR
, (addr
>> 10) & 0xFF);
665 viafb_write_reg(CR64
, VIACR
, (addr
>> 18) & 0xFF);
666 viafb_write_reg_mask(CRA3
, VIACR
, (addr
>> 26) & 0x07, 0x07);
669 void viafb_set_primary_pitch(u32 pitch
)
671 DEBUG_MSG(KERN_DEBUG
"viafb_set_primary_pitch(0x%08X)\n", pitch
);
672 /* spec does not say that first adapter skips 3 bits but old
673 * code did it and seems to be reasonable in analogy to 2nd adapter
676 viafb_write_reg(0x13, VIACR
, pitch
& 0xFF);
677 viafb_write_reg_mask(0x35, VIACR
, (pitch
>> (8 - 5)) & 0xE0, 0xE0);
680 void viafb_set_secondary_pitch(u32 pitch
)
682 DEBUG_MSG(KERN_DEBUG
"viafb_set_secondary_pitch(0x%08X)\n", pitch
);
684 viafb_write_reg(0x66, VIACR
, pitch
& 0xFF);
685 viafb_write_reg_mask(0x67, VIACR
, (pitch
>> 8) & 0x03, 0x03);
686 viafb_write_reg_mask(0x71, VIACR
, (pitch
>> (10 - 7)) & 0x80, 0x80);
689 void viafb_set_primary_color_depth(u8 depth
)
693 DEBUG_MSG(KERN_DEBUG
"viafb_set_primary_color_depth(%d)\n", depth
);
711 printk(KERN_WARNING
"viafb_set_primary_color_depth: "
712 "Unsupported depth: %d\n", depth
);
716 viafb_write_reg_mask(0x15, VIASR
, value
, 0x1C);
719 void viafb_set_secondary_color_depth(u8 depth
)
723 DEBUG_MSG(KERN_DEBUG
"viafb_set_secondary_color_depth(%d)\n", depth
);
738 printk(KERN_WARNING
"viafb_set_secondary_color_depth: "
739 "Unsupported depth: %d\n", depth
);
743 viafb_write_reg_mask(0x67, VIACR
, value
, 0xC0);
746 static void set_color_register(u8 index
, u8 red
, u8 green
, u8 blue
)
748 outb(0xFF, 0x3C6); /* bit mask of palette */
755 void viafb_set_primary_color_register(u8 index
, u8 red
, u8 green
, u8 blue
)
757 viafb_write_reg_mask(0x1A, VIASR
, 0x00, 0x01);
758 set_color_register(index
, red
, green
, blue
);
761 void viafb_set_secondary_color_register(u8 index
, u8 red
, u8 green
, u8 blue
)
763 viafb_write_reg_mask(0x1A, VIASR
, 0x01, 0x01);
764 set_color_register(index
, red
, green
, blue
);
767 void viafb_set_output_path(int device
, int set_iga
, int output_interface
)
771 set_crt_output_path(set_iga
);
774 set_dvi_output_path(set_iga
, output_interface
);
777 set_lcd_output_path(set_iga
, output_interface
);
782 static void set_crt_output_path(int set_iga
)
784 viafb_write_reg_mask(CR36
, VIACR
, 0x00, BIT4
+ BIT5
);
788 viafb_write_reg_mask(SR16
, VIASR
, 0x00, BIT6
);
791 viafb_write_reg_mask(CR6A
, VIACR
, 0xC0, BIT6
+ BIT7
);
792 viafb_write_reg_mask(SR16
, VIASR
, 0x40, BIT6
);
797 static void dvi_patch_skew_dvp0(void)
799 /* Reset data driving first: */
800 viafb_write_reg_mask(SR1B
, VIASR
, 0, BIT1
);
801 viafb_write_reg_mask(SR2A
, VIASR
, 0, BIT4
);
803 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
804 case UNICHROME_P4M890
:
806 if ((viaparinfo
->tmds_setting_info
->h_active
== 1600) &&
807 (viaparinfo
->tmds_setting_info
->v_active
==
809 viafb_write_reg_mask(CR96
, VIACR
, 0x03,
812 viafb_write_reg_mask(CR96
, VIACR
, 0x07,
817 case UNICHROME_P4M900
:
819 viafb_write_reg_mask(CR96
, VIACR
, 0x07,
820 BIT0
+ BIT1
+ BIT2
+ BIT3
);
821 viafb_write_reg_mask(SR1B
, VIASR
, 0x02, BIT1
);
822 viafb_write_reg_mask(SR2A
, VIASR
, 0x10, BIT4
);
833 static void dvi_patch_skew_dvp1(void)
835 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
836 case UNICHROME_CX700
:
848 static void dvi_patch_skew_dvp_low(void)
850 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
851 case UNICHROME_K8M890
:
853 viafb_write_reg_mask(CR99
, VIACR
, 0x03, BIT0
+ BIT1
);
857 case UNICHROME_P4M900
:
859 viafb_write_reg_mask(CR99
, VIACR
, 0x08,
860 BIT0
+ BIT1
+ BIT2
+ BIT3
);
864 case UNICHROME_P4M890
:
866 viafb_write_reg_mask(CR99
, VIACR
, 0x0F,
867 BIT0
+ BIT1
+ BIT2
+ BIT3
);
878 static void set_dvi_output_path(int set_iga
, int output_interface
)
880 switch (output_interface
) {
882 viafb_write_reg_mask(CR6B
, VIACR
, 0x01, BIT0
);
884 if (set_iga
== IGA1
) {
885 viafb_write_reg_mask(CR96
, VIACR
, 0x00, BIT4
);
886 viafb_write_reg_mask(CR6C
, VIACR
, 0x21, BIT0
+
889 viafb_write_reg_mask(CR96
, VIACR
, 0x10, BIT4
);
890 viafb_write_reg_mask(CR6C
, VIACR
, 0xA1, BIT0
+
894 viafb_write_reg_mask(SR1E
, VIASR
, 0xC0, BIT7
+ BIT6
);
896 dvi_patch_skew_dvp0();
900 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CLE266
) {
902 viafb_write_reg_mask(CR93
, VIACR
, 0x21,
905 viafb_write_reg_mask(CR93
, VIACR
, 0xA1,
909 viafb_write_reg_mask(CR9B
, VIACR
, 0x00, BIT4
);
911 viafb_write_reg_mask(CR9B
, VIACR
, 0x10, BIT4
);
914 viafb_write_reg_mask(SR1E
, VIASR
, 0x30, BIT4
+ BIT5
);
915 dvi_patch_skew_dvp1();
917 case INTERFACE_DFP_HIGH
:
918 if (viaparinfo
->chip_info
->gfx_chip_name
!= UNICHROME_CLE266
) {
919 if (set_iga
== IGA1
) {
920 viafb_write_reg_mask(CR96
, VIACR
, 0x00, BIT4
);
921 viafb_write_reg_mask(CR97
, VIACR
, 0x03,
924 viafb_write_reg_mask(CR96
, VIACR
, 0x10, BIT4
);
925 viafb_write_reg_mask(CR97
, VIACR
, 0x13,
929 viafb_write_reg_mask(SR2A
, VIASR
, 0x0C, BIT2
+ BIT3
);
932 case INTERFACE_DFP_LOW
:
933 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CLE266
)
936 if (set_iga
== IGA1
) {
937 viafb_write_reg_mask(CR99
, VIACR
, 0x00, BIT4
);
938 viafb_write_reg_mask(CR9B
, VIACR
, 0x00, BIT4
);
940 viafb_write_reg_mask(CR99
, VIACR
, 0x10, BIT4
);
941 viafb_write_reg_mask(CR9B
, VIACR
, 0x10, BIT4
);
944 viafb_write_reg_mask(SR2A
, VIASR
, 0x03, BIT0
+ BIT1
);
945 dvi_patch_skew_dvp_low();
950 viafb_write_reg_mask(CR99
, VIACR
, 0x00, BIT4
);
952 viafb_write_reg_mask(CR99
, VIACR
, 0x10, BIT4
);
956 if (set_iga
== IGA2
) {
957 enable_second_display_channel();
958 /* Disable LCD Scaling */
959 viafb_write_reg_mask(CR79
, VIACR
, 0x00, BIT0
);
963 static void set_lcd_output_path(int set_iga
, int output_interface
)
966 "set_lcd_output_path, iga:%d,out_interface:%d\n",
967 set_iga
, output_interface
);
970 viafb_write_reg_mask(CR6B
, VIACR
, 0x00, BIT3
);
971 viafb_write_reg_mask(CR6A
, VIACR
, 0x08, BIT3
);
973 disable_second_display_channel();
977 viafb_write_reg_mask(CR6B
, VIACR
, 0x00, BIT3
);
978 viafb_write_reg_mask(CR6A
, VIACR
, 0x08, BIT3
);
980 enable_second_display_channel();
984 switch (output_interface
) {
986 if (set_iga
== IGA1
) {
987 viafb_write_reg_mask(CR96
, VIACR
, 0x00, BIT4
);
989 viafb_write_reg(CR91
, VIACR
, 0x00);
990 viafb_write_reg_mask(CR96
, VIACR
, 0x10, BIT4
);
996 viafb_write_reg_mask(CR9B
, VIACR
, 0x00, BIT4
);
998 viafb_write_reg(CR91
, VIACR
, 0x00);
999 viafb_write_reg_mask(CR9B
, VIACR
, 0x10, BIT4
);
1003 case INTERFACE_DFP_HIGH
:
1004 if (set_iga
== IGA1
)
1005 viafb_write_reg_mask(CR97
, VIACR
, 0x00, BIT4
);
1007 viafb_write_reg(CR91
, VIACR
, 0x00);
1008 viafb_write_reg_mask(CR97
, VIACR
, 0x10, BIT4
);
1009 viafb_write_reg_mask(CR96
, VIACR
, 0x10, BIT4
);
1013 case INTERFACE_DFP_LOW
:
1014 if (set_iga
== IGA1
)
1015 viafb_write_reg_mask(CR99
, VIACR
, 0x00, BIT4
);
1017 viafb_write_reg(CR91
, VIACR
, 0x00);
1018 viafb_write_reg_mask(CR99
, VIACR
, 0x10, BIT4
);
1019 viafb_write_reg_mask(CR9B
, VIACR
, 0x10, BIT4
);
1025 if ((UNICHROME_K8M890
== viaparinfo
->chip_info
->gfx_chip_name
)
1026 || (UNICHROME_P4M890
==
1027 viaparinfo
->chip_info
->gfx_chip_name
))
1028 viafb_write_reg_mask(CR97
, VIACR
, 0x84,
1029 BIT7
+ BIT2
+ BIT1
+ BIT0
);
1030 if (set_iga
== IGA1
) {
1031 viafb_write_reg_mask(CR97
, VIACR
, 0x00, BIT4
);
1032 viafb_write_reg_mask(CR99
, VIACR
, 0x00, BIT4
);
1034 viafb_write_reg(CR91
, VIACR
, 0x00);
1035 viafb_write_reg_mask(CR97
, VIACR
, 0x10, BIT4
);
1036 viafb_write_reg_mask(CR99
, VIACR
, 0x10, BIT4
);
1040 case INTERFACE_LVDS0
:
1041 case INTERFACE_LVDS0LVDS1
:
1042 if (set_iga
== IGA1
)
1043 viafb_write_reg_mask(CR99
, VIACR
, 0x00, BIT4
);
1045 viafb_write_reg_mask(CR99
, VIACR
, 0x10, BIT4
);
1049 case INTERFACE_LVDS1
:
1050 if (set_iga
== IGA1
)
1051 viafb_write_reg_mask(CR97
, VIACR
, 0x00, BIT4
);
1053 viafb_write_reg_mask(CR97
, VIACR
, 0x10, BIT4
);
1058 static void load_fix_bit_crtc_reg(void)
1060 /* always set to 1 */
1061 viafb_write_reg_mask(CR03
, VIACR
, 0x80, BIT7
);
1062 /* line compare should set all bits = 1 (extend modes) */
1063 viafb_write_reg(CR18
, VIACR
, 0xff);
1064 /* line compare should set all bits = 1 (extend modes) */
1065 viafb_write_reg_mask(CR07
, VIACR
, 0x10, BIT4
);
1066 /* line compare should set all bits = 1 (extend modes) */
1067 viafb_write_reg_mask(CR09
, VIACR
, 0x40, BIT6
);
1068 /* line compare should set all bits = 1 (extend modes) */
1069 viafb_write_reg_mask(CR35
, VIACR
, 0x10, BIT4
);
1070 /* line compare should set all bits = 1 (extend modes) */
1071 viafb_write_reg_mask(CR33
, VIACR
, 0x06, BIT0
+ BIT1
+ BIT2
);
1072 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1073 /* extend mode always set to e3h */
1074 viafb_write_reg(CR17
, VIACR
, 0xe3);
1075 /* extend mode always set to 0h */
1076 viafb_write_reg(CR08
, VIACR
, 0x00);
1077 /* extend mode always set to 0h */
1078 viafb_write_reg(CR14
, VIACR
, 0x00);
1080 /* If K8M800, enable Prefetch Mode. */
1081 if ((viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K800
)
1082 || (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K8M890
))
1083 viafb_write_reg_mask(CR33
, VIACR
, 0x08, BIT3
);
1084 if ((viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CLE266
)
1085 && (viaparinfo
->chip_info
->gfx_chip_revision
== CLE266_REVISION_AX
))
1086 viafb_write_reg_mask(SR1A
, VIASR
, 0x02, BIT1
);
1090 void viafb_load_reg(int timing_value
, int viafb_load_reg_num
,
1091 struct io_register
*reg
,
1099 int start_index
, end_index
, cr_index
;
1102 for (i
= 0; i
< viafb_load_reg_num
; i
++) {
1105 start_index
= reg
[i
].start_bit
;
1106 end_index
= reg
[i
].end_bit
;
1107 cr_index
= reg
[i
].io_addr
;
1109 shift_next_reg
= bit_num
;
1110 for (j
= start_index
; j
<= end_index
; j
++) {
1111 /*if (bit_num==8) timing_value = timing_value >>8; */
1112 reg_mask
= reg_mask
| (BIT0
<< j
);
1113 get_bit
= (timing_value
& (BIT0
<< bit_num
));
1115 data
| ((get_bit
>> shift_next_reg
) << start_index
);
1118 if (io_type
== VIACR
)
1119 viafb_write_reg_mask(cr_index
, VIACR
, data
, reg_mask
);
1121 viafb_write_reg_mask(cr_index
, VIASR
, data
, reg_mask
);
1126 /* Write Registers */
1127 void viafb_write_regx(struct io_reg RegTable
[], int ItemNum
)
1130 unsigned char RegTemp
;
1132 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1134 for (i
= 0; i
< ItemNum
; i
++) {
1135 outb(RegTable
[i
].index
, RegTable
[i
].port
);
1136 RegTemp
= inb(RegTable
[i
].port
+ 1);
1137 RegTemp
= (RegTemp
& (~RegTable
[i
].mask
)) | RegTable
[i
].value
;
1138 outb(RegTemp
, RegTable
[i
].port
+ 1);
1142 void viafb_load_fetch_count_reg(int h_addr
, int bpp_byte
, int set_iga
)
1145 int viafb_load_reg_num
;
1146 struct io_register
*reg
= NULL
;
1150 reg_value
= IGA1_FETCH_COUNT_FORMULA(h_addr
, bpp_byte
);
1151 viafb_load_reg_num
= fetch_count_reg
.
1152 iga1_fetch_count_reg
.reg_num
;
1153 reg
= fetch_count_reg
.iga1_fetch_count_reg
.reg
;
1154 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIASR
);
1157 reg_value
= IGA2_FETCH_COUNT_FORMULA(h_addr
, bpp_byte
);
1158 viafb_load_reg_num
= fetch_count_reg
.
1159 iga2_fetch_count_reg
.reg_num
;
1160 reg
= fetch_count_reg
.iga2_fetch_count_reg
.reg
;
1161 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIACR
);
1167 void viafb_load_FIFO_reg(int set_iga
, int hor_active
, int ver_active
)
1170 int viafb_load_reg_num
;
1171 struct io_register
*reg
= NULL
;
1172 int iga1_fifo_max_depth
= 0, iga1_fifo_threshold
=
1173 0, iga1_fifo_high_threshold
= 0, iga1_display_queue_expire_num
= 0;
1174 int iga2_fifo_max_depth
= 0, iga2_fifo_threshold
=
1175 0, iga2_fifo_high_threshold
= 0, iga2_display_queue_expire_num
= 0;
1177 if (set_iga
== IGA1
) {
1178 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K800
) {
1179 iga1_fifo_max_depth
= K800_IGA1_FIFO_MAX_DEPTH
;
1180 iga1_fifo_threshold
= K800_IGA1_FIFO_THRESHOLD
;
1181 iga1_fifo_high_threshold
=
1182 K800_IGA1_FIFO_HIGH_THRESHOLD
;
1183 /* If resolution > 1280x1024, expire length = 64, else
1184 expire length = 128 */
1185 if ((hor_active
> 1280) && (ver_active
> 1024))
1186 iga1_display_queue_expire_num
= 16;
1188 iga1_display_queue_expire_num
=
1189 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1193 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_PM800
) {
1194 iga1_fifo_max_depth
= P880_IGA1_FIFO_MAX_DEPTH
;
1195 iga1_fifo_threshold
= P880_IGA1_FIFO_THRESHOLD
;
1196 iga1_fifo_high_threshold
=
1197 P880_IGA1_FIFO_HIGH_THRESHOLD
;
1198 iga1_display_queue_expire_num
=
1199 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1201 /* If resolution > 1280x1024, expire length = 64, else
1202 expire length = 128 */
1203 if ((hor_active
> 1280) && (ver_active
> 1024))
1204 iga1_display_queue_expire_num
= 16;
1206 iga1_display_queue_expire_num
=
1207 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1210 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CN700
) {
1211 iga1_fifo_max_depth
= CN700_IGA1_FIFO_MAX_DEPTH
;
1212 iga1_fifo_threshold
= CN700_IGA1_FIFO_THRESHOLD
;
1213 iga1_fifo_high_threshold
=
1214 CN700_IGA1_FIFO_HIGH_THRESHOLD
;
1216 /* If resolution > 1280x1024, expire length = 64,
1217 else expire length = 128 */
1218 if ((hor_active
> 1280) && (ver_active
> 1024))
1219 iga1_display_queue_expire_num
= 16;
1221 iga1_display_queue_expire_num
=
1222 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1225 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CX700
) {
1226 iga1_fifo_max_depth
= CX700_IGA1_FIFO_MAX_DEPTH
;
1227 iga1_fifo_threshold
= CX700_IGA1_FIFO_THRESHOLD
;
1228 iga1_fifo_high_threshold
=
1229 CX700_IGA1_FIFO_HIGH_THRESHOLD
;
1230 iga1_display_queue_expire_num
=
1231 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1234 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K8M890
) {
1235 iga1_fifo_max_depth
= K8M890_IGA1_FIFO_MAX_DEPTH
;
1236 iga1_fifo_threshold
= K8M890_IGA1_FIFO_THRESHOLD
;
1237 iga1_fifo_high_threshold
=
1238 K8M890_IGA1_FIFO_HIGH_THRESHOLD
;
1239 iga1_display_queue_expire_num
=
1240 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1243 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_P4M890
) {
1244 iga1_fifo_max_depth
= P4M890_IGA1_FIFO_MAX_DEPTH
;
1245 iga1_fifo_threshold
= P4M890_IGA1_FIFO_THRESHOLD
;
1246 iga1_fifo_high_threshold
=
1247 P4M890_IGA1_FIFO_HIGH_THRESHOLD
;
1248 iga1_display_queue_expire_num
=
1249 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1252 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_P4M900
) {
1253 iga1_fifo_max_depth
= P4M900_IGA1_FIFO_MAX_DEPTH
;
1254 iga1_fifo_threshold
= P4M900_IGA1_FIFO_THRESHOLD
;
1255 iga1_fifo_high_threshold
=
1256 P4M900_IGA1_FIFO_HIGH_THRESHOLD
;
1257 iga1_display_queue_expire_num
=
1258 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1261 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_VX800
) {
1262 iga1_fifo_max_depth
= VX800_IGA1_FIFO_MAX_DEPTH
;
1263 iga1_fifo_threshold
= VX800_IGA1_FIFO_THRESHOLD
;
1264 iga1_fifo_high_threshold
=
1265 VX800_IGA1_FIFO_HIGH_THRESHOLD
;
1266 iga1_display_queue_expire_num
=
1267 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1270 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_VX855
) {
1271 iga1_fifo_max_depth
= VX855_IGA1_FIFO_MAX_DEPTH
;
1272 iga1_fifo_threshold
= VX855_IGA1_FIFO_THRESHOLD
;
1273 iga1_fifo_high_threshold
=
1274 VX855_IGA1_FIFO_HIGH_THRESHOLD
;
1275 iga1_display_queue_expire_num
=
1276 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
;
1279 /* Set Display FIFO Depath Select */
1280 reg_value
= IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth
);
1281 viafb_load_reg_num
=
1282 display_fifo_depth_reg
.iga1_fifo_depth_select_reg
.reg_num
;
1283 reg
= display_fifo_depth_reg
.iga1_fifo_depth_select_reg
.reg
;
1284 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIASR
);
1286 /* Set Display FIFO Threshold Select */
1287 reg_value
= IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold
);
1288 viafb_load_reg_num
=
1289 fifo_threshold_select_reg
.
1290 iga1_fifo_threshold_select_reg
.reg_num
;
1292 fifo_threshold_select_reg
.
1293 iga1_fifo_threshold_select_reg
.reg
;
1294 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIASR
);
1296 /* Set FIFO High Threshold Select */
1298 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold
);
1299 viafb_load_reg_num
=
1300 fifo_high_threshold_select_reg
.
1301 iga1_fifo_high_threshold_select_reg
.reg_num
;
1303 fifo_high_threshold_select_reg
.
1304 iga1_fifo_high_threshold_select_reg
.reg
;
1305 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIASR
);
1307 /* Set Display Queue Expire Num */
1309 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1310 (iga1_display_queue_expire_num
);
1311 viafb_load_reg_num
=
1312 display_queue_expire_num_reg
.
1313 iga1_display_queue_expire_num_reg
.reg_num
;
1315 display_queue_expire_num_reg
.
1316 iga1_display_queue_expire_num_reg
.reg
;
1317 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIASR
);
1320 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K800
) {
1321 iga2_fifo_max_depth
= K800_IGA2_FIFO_MAX_DEPTH
;
1322 iga2_fifo_threshold
= K800_IGA2_FIFO_THRESHOLD
;
1323 iga2_fifo_high_threshold
=
1324 K800_IGA2_FIFO_HIGH_THRESHOLD
;
1326 /* If resolution > 1280x1024, expire length = 64,
1327 else expire length = 128 */
1328 if ((hor_active
> 1280) && (ver_active
> 1024))
1329 iga2_display_queue_expire_num
= 16;
1331 iga2_display_queue_expire_num
=
1332 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1335 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_PM800
) {
1336 iga2_fifo_max_depth
= P880_IGA2_FIFO_MAX_DEPTH
;
1337 iga2_fifo_threshold
= P880_IGA2_FIFO_THRESHOLD
;
1338 iga2_fifo_high_threshold
=
1339 P880_IGA2_FIFO_HIGH_THRESHOLD
;
1341 /* If resolution > 1280x1024, expire length = 64,
1342 else expire length = 128 */
1343 if ((hor_active
> 1280) && (ver_active
> 1024))
1344 iga2_display_queue_expire_num
= 16;
1346 iga2_display_queue_expire_num
=
1347 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1350 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CN700
) {
1351 iga2_fifo_max_depth
= CN700_IGA2_FIFO_MAX_DEPTH
;
1352 iga2_fifo_threshold
= CN700_IGA2_FIFO_THRESHOLD
;
1353 iga2_fifo_high_threshold
=
1354 CN700_IGA2_FIFO_HIGH_THRESHOLD
;
1356 /* If resolution > 1280x1024, expire length = 64,
1357 else expire length = 128 */
1358 if ((hor_active
> 1280) && (ver_active
> 1024))
1359 iga2_display_queue_expire_num
= 16;
1361 iga2_display_queue_expire_num
=
1362 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1365 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CX700
) {
1366 iga2_fifo_max_depth
= CX700_IGA2_FIFO_MAX_DEPTH
;
1367 iga2_fifo_threshold
= CX700_IGA2_FIFO_THRESHOLD
;
1368 iga2_fifo_high_threshold
=
1369 CX700_IGA2_FIFO_HIGH_THRESHOLD
;
1370 iga2_display_queue_expire_num
=
1371 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1374 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K8M890
) {
1375 iga2_fifo_max_depth
= K8M890_IGA2_FIFO_MAX_DEPTH
;
1376 iga2_fifo_threshold
= K8M890_IGA2_FIFO_THRESHOLD
;
1377 iga2_fifo_high_threshold
=
1378 K8M890_IGA2_FIFO_HIGH_THRESHOLD
;
1379 iga2_display_queue_expire_num
=
1380 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1383 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_P4M890
) {
1384 iga2_fifo_max_depth
= P4M890_IGA2_FIFO_MAX_DEPTH
;
1385 iga2_fifo_threshold
= P4M890_IGA2_FIFO_THRESHOLD
;
1386 iga2_fifo_high_threshold
=
1387 P4M890_IGA2_FIFO_HIGH_THRESHOLD
;
1388 iga2_display_queue_expire_num
=
1389 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1392 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_P4M900
) {
1393 iga2_fifo_max_depth
= P4M900_IGA2_FIFO_MAX_DEPTH
;
1394 iga2_fifo_threshold
= P4M900_IGA2_FIFO_THRESHOLD
;
1395 iga2_fifo_high_threshold
=
1396 P4M900_IGA2_FIFO_HIGH_THRESHOLD
;
1397 iga2_display_queue_expire_num
=
1398 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1401 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_VX800
) {
1402 iga2_fifo_max_depth
= VX800_IGA2_FIFO_MAX_DEPTH
;
1403 iga2_fifo_threshold
= VX800_IGA2_FIFO_THRESHOLD
;
1404 iga2_fifo_high_threshold
=
1405 VX800_IGA2_FIFO_HIGH_THRESHOLD
;
1406 iga2_display_queue_expire_num
=
1407 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1410 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_VX855
) {
1411 iga2_fifo_max_depth
= VX855_IGA2_FIFO_MAX_DEPTH
;
1412 iga2_fifo_threshold
= VX855_IGA2_FIFO_THRESHOLD
;
1413 iga2_fifo_high_threshold
=
1414 VX855_IGA2_FIFO_HIGH_THRESHOLD
;
1415 iga2_display_queue_expire_num
=
1416 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
;
1419 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K800
) {
1420 /* Set Display FIFO Depath Select */
1422 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth
)
1424 /* Patch LCD in IGA2 case */
1425 viafb_load_reg_num
=
1426 display_fifo_depth_reg
.
1427 iga2_fifo_depth_select_reg
.reg_num
;
1429 display_fifo_depth_reg
.
1430 iga2_fifo_depth_select_reg
.reg
;
1431 viafb_load_reg(reg_value
,
1432 viafb_load_reg_num
, reg
, VIACR
);
1435 /* Set Display FIFO Depath Select */
1437 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth
);
1438 viafb_load_reg_num
=
1439 display_fifo_depth_reg
.
1440 iga2_fifo_depth_select_reg
.reg_num
;
1442 display_fifo_depth_reg
.
1443 iga2_fifo_depth_select_reg
.reg
;
1444 viafb_load_reg(reg_value
,
1445 viafb_load_reg_num
, reg
, VIACR
);
1448 /* Set Display FIFO Threshold Select */
1449 reg_value
= IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold
);
1450 viafb_load_reg_num
=
1451 fifo_threshold_select_reg
.
1452 iga2_fifo_threshold_select_reg
.reg_num
;
1454 fifo_threshold_select_reg
.
1455 iga2_fifo_threshold_select_reg
.reg
;
1456 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIACR
);
1458 /* Set FIFO High Threshold Select */
1460 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold
);
1461 viafb_load_reg_num
=
1462 fifo_high_threshold_select_reg
.
1463 iga2_fifo_high_threshold_select_reg
.reg_num
;
1465 fifo_high_threshold_select_reg
.
1466 iga2_fifo_high_threshold_select_reg
.reg
;
1467 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIACR
);
1469 /* Set Display Queue Expire Num */
1471 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1472 (iga2_display_queue_expire_num
);
1473 viafb_load_reg_num
=
1474 display_queue_expire_num_reg
.
1475 iga2_display_queue_expire_num_reg
.reg_num
;
1477 display_queue_expire_num_reg
.
1478 iga2_display_queue_expire_num_reg
.reg
;
1479 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIACR
);
1485 u32
viafb_get_clk_value(int clk
)
1489 for (i
= 0; i
< NUM_TOTAL_PLL_TABLE
; i
++) {
1490 if (clk
== pll_value
[i
].clk
) {
1491 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
1492 case UNICHROME_CLE266
:
1493 case UNICHROME_K400
:
1494 return pll_value
[i
].cle266_pll
;
1496 case UNICHROME_K800
:
1497 case UNICHROME_PM800
:
1498 case UNICHROME_CN700
:
1499 return pll_value
[i
].k800_pll
;
1501 case UNICHROME_CX700
:
1502 case UNICHROME_K8M890
:
1503 case UNICHROME_P4M890
:
1504 case UNICHROME_P4M900
:
1505 case UNICHROME_VX800
:
1506 return pll_value
[i
].cx700_pll
;
1507 case UNICHROME_VX855
:
1508 return pll_value
[i
].vx855_pll
;
1513 DEBUG_MSG(KERN_INFO
"Can't find match PLL value\n\n");
1518 void viafb_set_vclock(u32 CLK
, int set_iga
)
1520 unsigned char RegTemp
;
1522 /* H.W. Reset : ON */
1523 viafb_write_reg_mask(CR17
, VIACR
, 0x00, BIT7
);
1525 if (set_iga
== IGA1
) {
1526 /* Change D,N FOR VCLK */
1527 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
1528 case UNICHROME_CLE266
:
1529 case UNICHROME_K400
:
1530 viafb_write_reg(SR46
, VIASR
, CLK
/ 0x100);
1531 viafb_write_reg(SR47
, VIASR
, CLK
% 0x100);
1534 case UNICHROME_K800
:
1535 case UNICHROME_PM800
:
1536 case UNICHROME_CN700
:
1537 case UNICHROME_CX700
:
1538 case UNICHROME_K8M890
:
1539 case UNICHROME_P4M890
:
1540 case UNICHROME_P4M900
:
1541 case UNICHROME_VX800
:
1542 case UNICHROME_VX855
:
1543 viafb_write_reg(SR44
, VIASR
, CLK
/ 0x10000);
1544 DEBUG_MSG(KERN_INFO
"\nSR44=%x", CLK
/ 0x10000);
1545 viafb_write_reg(SR45
, VIASR
, (CLK
& 0xFFFF) / 0x100);
1546 DEBUG_MSG(KERN_INFO
"\nSR45=%x",
1547 (CLK
& 0xFFFF) / 0x100);
1548 viafb_write_reg(SR46
, VIASR
, CLK
% 0x100);
1549 DEBUG_MSG(KERN_INFO
"\nSR46=%x", CLK
% 0x100);
1554 if (set_iga
== IGA2
) {
1555 /* Change D,N FOR LCK */
1556 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
1557 case UNICHROME_CLE266
:
1558 case UNICHROME_K400
:
1559 viafb_write_reg(SR44
, VIASR
, CLK
/ 0x100);
1560 viafb_write_reg(SR45
, VIASR
, CLK
% 0x100);
1563 case UNICHROME_K800
:
1564 case UNICHROME_PM800
:
1565 case UNICHROME_CN700
:
1566 case UNICHROME_CX700
:
1567 case UNICHROME_K8M890
:
1568 case UNICHROME_P4M890
:
1569 case UNICHROME_P4M900
:
1570 case UNICHROME_VX800
:
1571 case UNICHROME_VX855
:
1572 viafb_write_reg(SR4A
, VIASR
, CLK
/ 0x10000);
1573 viafb_write_reg(SR4B
, VIASR
, (CLK
& 0xFFFF) / 0x100);
1574 viafb_write_reg(SR4C
, VIASR
, CLK
% 0x100);
1579 /* H.W. Reset : OFF */
1580 viafb_write_reg_mask(CR17
, VIACR
, 0x80, BIT7
);
1583 if (set_iga
== IGA1
) {
1584 viafb_write_reg_mask(SR40
, VIASR
, 0x02, BIT1
);
1585 viafb_write_reg_mask(SR40
, VIASR
, 0x00, BIT1
);
1588 if (set_iga
== IGA2
) {
1589 viafb_write_reg_mask(SR40
, VIASR
, 0x01, BIT0
);
1590 viafb_write_reg_mask(SR40
, VIASR
, 0x00, BIT0
);
1594 RegTemp
= inb(VIARMisc
);
1595 outb(RegTemp
| (BIT2
+ BIT3
), VIAWMisc
);
1598 void viafb_load_crtc_timing(struct display_timing device_timing
,
1602 int viafb_load_reg_num
= 0;
1604 struct io_register
*reg
= NULL
;
1608 for (i
= 0; i
< 12; i
++) {
1609 if (set_iga
== IGA1
) {
1613 IGA1_HOR_TOTAL_FORMULA(device_timing
.
1615 viafb_load_reg_num
=
1616 iga1_crtc_reg
.hor_total
.reg_num
;
1617 reg
= iga1_crtc_reg
.hor_total
.reg
;
1621 IGA1_HOR_ADDR_FORMULA(device_timing
.
1623 viafb_load_reg_num
=
1624 iga1_crtc_reg
.hor_addr
.reg_num
;
1625 reg
= iga1_crtc_reg
.hor_addr
.reg
;
1627 case H_BLANK_START_INDEX
:
1629 IGA1_HOR_BLANK_START_FORMULA
1630 (device_timing
.hor_blank_start
);
1631 viafb_load_reg_num
=
1632 iga1_crtc_reg
.hor_blank_start
.reg_num
;
1633 reg
= iga1_crtc_reg
.hor_blank_start
.reg
;
1635 case H_BLANK_END_INDEX
:
1637 IGA1_HOR_BLANK_END_FORMULA
1638 (device_timing
.hor_blank_start
,
1639 device_timing
.hor_blank_end
);
1640 viafb_load_reg_num
=
1641 iga1_crtc_reg
.hor_blank_end
.reg_num
;
1642 reg
= iga1_crtc_reg
.hor_blank_end
.reg
;
1644 case H_SYNC_START_INDEX
:
1646 IGA1_HOR_SYNC_START_FORMULA
1647 (device_timing
.hor_sync_start
);
1648 viafb_load_reg_num
=
1649 iga1_crtc_reg
.hor_sync_start
.reg_num
;
1650 reg
= iga1_crtc_reg
.hor_sync_start
.reg
;
1652 case H_SYNC_END_INDEX
:
1654 IGA1_HOR_SYNC_END_FORMULA
1655 (device_timing
.hor_sync_start
,
1656 device_timing
.hor_sync_end
);
1657 viafb_load_reg_num
=
1658 iga1_crtc_reg
.hor_sync_end
.reg_num
;
1659 reg
= iga1_crtc_reg
.hor_sync_end
.reg
;
1663 IGA1_VER_TOTAL_FORMULA(device_timing
.
1665 viafb_load_reg_num
=
1666 iga1_crtc_reg
.ver_total
.reg_num
;
1667 reg
= iga1_crtc_reg
.ver_total
.reg
;
1671 IGA1_VER_ADDR_FORMULA(device_timing
.
1673 viafb_load_reg_num
=
1674 iga1_crtc_reg
.ver_addr
.reg_num
;
1675 reg
= iga1_crtc_reg
.ver_addr
.reg
;
1677 case V_BLANK_START_INDEX
:
1679 IGA1_VER_BLANK_START_FORMULA
1680 (device_timing
.ver_blank_start
);
1681 viafb_load_reg_num
=
1682 iga1_crtc_reg
.ver_blank_start
.reg_num
;
1683 reg
= iga1_crtc_reg
.ver_blank_start
.reg
;
1685 case V_BLANK_END_INDEX
:
1687 IGA1_VER_BLANK_END_FORMULA
1688 (device_timing
.ver_blank_start
,
1689 device_timing
.ver_blank_end
);
1690 viafb_load_reg_num
=
1691 iga1_crtc_reg
.ver_blank_end
.reg_num
;
1692 reg
= iga1_crtc_reg
.ver_blank_end
.reg
;
1694 case V_SYNC_START_INDEX
:
1696 IGA1_VER_SYNC_START_FORMULA
1697 (device_timing
.ver_sync_start
);
1698 viafb_load_reg_num
=
1699 iga1_crtc_reg
.ver_sync_start
.reg_num
;
1700 reg
= iga1_crtc_reg
.ver_sync_start
.reg
;
1702 case V_SYNC_END_INDEX
:
1704 IGA1_VER_SYNC_END_FORMULA
1705 (device_timing
.ver_sync_start
,
1706 device_timing
.ver_sync_end
);
1707 viafb_load_reg_num
=
1708 iga1_crtc_reg
.ver_sync_end
.reg_num
;
1709 reg
= iga1_crtc_reg
.ver_sync_end
.reg
;
1715 if (set_iga
== IGA2
) {
1719 IGA2_HOR_TOTAL_FORMULA(device_timing
.
1721 viafb_load_reg_num
=
1722 iga2_crtc_reg
.hor_total
.reg_num
;
1723 reg
= iga2_crtc_reg
.hor_total
.reg
;
1727 IGA2_HOR_ADDR_FORMULA(device_timing
.
1729 viafb_load_reg_num
=
1730 iga2_crtc_reg
.hor_addr
.reg_num
;
1731 reg
= iga2_crtc_reg
.hor_addr
.reg
;
1733 case H_BLANK_START_INDEX
:
1735 IGA2_HOR_BLANK_START_FORMULA
1736 (device_timing
.hor_blank_start
);
1737 viafb_load_reg_num
=
1738 iga2_crtc_reg
.hor_blank_start
.reg_num
;
1739 reg
= iga2_crtc_reg
.hor_blank_start
.reg
;
1741 case H_BLANK_END_INDEX
:
1743 IGA2_HOR_BLANK_END_FORMULA
1744 (device_timing
.hor_blank_start
,
1745 device_timing
.hor_blank_end
);
1746 viafb_load_reg_num
=
1747 iga2_crtc_reg
.hor_blank_end
.reg_num
;
1748 reg
= iga2_crtc_reg
.hor_blank_end
.reg
;
1750 case H_SYNC_START_INDEX
:
1752 IGA2_HOR_SYNC_START_FORMULA
1753 (device_timing
.hor_sync_start
);
1754 if (UNICHROME_CN700
<=
1755 viaparinfo
->chip_info
->gfx_chip_name
)
1756 viafb_load_reg_num
=
1757 iga2_crtc_reg
.hor_sync_start
.
1760 viafb_load_reg_num
= 3;
1761 reg
= iga2_crtc_reg
.hor_sync_start
.reg
;
1763 case H_SYNC_END_INDEX
:
1765 IGA2_HOR_SYNC_END_FORMULA
1766 (device_timing
.hor_sync_start
,
1767 device_timing
.hor_sync_end
);
1768 viafb_load_reg_num
=
1769 iga2_crtc_reg
.hor_sync_end
.reg_num
;
1770 reg
= iga2_crtc_reg
.hor_sync_end
.reg
;
1774 IGA2_VER_TOTAL_FORMULA(device_timing
.
1776 viafb_load_reg_num
=
1777 iga2_crtc_reg
.ver_total
.reg_num
;
1778 reg
= iga2_crtc_reg
.ver_total
.reg
;
1782 IGA2_VER_ADDR_FORMULA(device_timing
.
1784 viafb_load_reg_num
=
1785 iga2_crtc_reg
.ver_addr
.reg_num
;
1786 reg
= iga2_crtc_reg
.ver_addr
.reg
;
1788 case V_BLANK_START_INDEX
:
1790 IGA2_VER_BLANK_START_FORMULA
1791 (device_timing
.ver_blank_start
);
1792 viafb_load_reg_num
=
1793 iga2_crtc_reg
.ver_blank_start
.reg_num
;
1794 reg
= iga2_crtc_reg
.ver_blank_start
.reg
;
1796 case V_BLANK_END_INDEX
:
1798 IGA2_VER_BLANK_END_FORMULA
1799 (device_timing
.ver_blank_start
,
1800 device_timing
.ver_blank_end
);
1801 viafb_load_reg_num
=
1802 iga2_crtc_reg
.ver_blank_end
.reg_num
;
1803 reg
= iga2_crtc_reg
.ver_blank_end
.reg
;
1805 case V_SYNC_START_INDEX
:
1807 IGA2_VER_SYNC_START_FORMULA
1808 (device_timing
.ver_sync_start
);
1809 viafb_load_reg_num
=
1810 iga2_crtc_reg
.ver_sync_start
.reg_num
;
1811 reg
= iga2_crtc_reg
.ver_sync_start
.reg
;
1813 case V_SYNC_END_INDEX
:
1815 IGA2_VER_SYNC_END_FORMULA
1816 (device_timing
.ver_sync_start
,
1817 device_timing
.ver_sync_end
);
1818 viafb_load_reg_num
=
1819 iga2_crtc_reg
.ver_sync_end
.reg_num
;
1820 reg
= iga2_crtc_reg
.ver_sync_end
.reg
;
1825 viafb_load_reg(reg_value
, viafb_load_reg_num
, reg
, VIACR
);
1831 void viafb_fill_crtc_timing(struct crt_mode_table
*crt_table
,
1832 struct VideoModeTable
*video_mode
, int bpp_byte
, int set_iga
)
1834 struct display_timing crt_reg
;
1840 for (i
= 0; i
< video_mode
->mode_array
; i
++) {
1843 if (crt_table
[i
].refresh_rate
== viaparinfo
->
1844 crt_setting_info
->refresh_rate
)
1848 crt_reg
= crt_table
[index
].crtc
;
1850 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1851 /* So we would delete border. */
1852 if ((viafb_LCD_ON
| viafb_DVI_ON
)
1853 && video_mode
->crtc
[0].crtc
.hor_addr
== 640
1854 && video_mode
->crtc
[0].crtc
.ver_addr
== 480
1855 && viaparinfo
->crt_setting_info
->refresh_rate
== 60) {
1856 /* The border is 8 pixels. */
1857 crt_reg
.hor_blank_start
= crt_reg
.hor_blank_start
- 8;
1859 /* Blanking time should add left and right borders. */
1860 crt_reg
.hor_blank_end
= crt_reg
.hor_blank_end
+ 16;
1863 h_addr
= crt_reg
.hor_addr
;
1864 v_addr
= crt_reg
.ver_addr
;
1866 /* update polarity for CRT timing */
1867 if (crt_table
[index
].h_sync_polarity
== NEGATIVE
) {
1868 if (crt_table
[index
].v_sync_polarity
== NEGATIVE
)
1869 outb((inb(VIARMisc
) & (~(BIT6
+ BIT7
))) |
1870 (BIT6
+ BIT7
), VIAWMisc
);
1872 outb((inb(VIARMisc
) & (~(BIT6
+ BIT7
))) | (BIT6
),
1875 if (crt_table
[index
].v_sync_polarity
== NEGATIVE
)
1876 outb((inb(VIARMisc
) & (~(BIT6
+ BIT7
))) | (BIT7
),
1879 outb((inb(VIARMisc
) & (~(BIT6
+ BIT7
))), VIAWMisc
);
1882 if (set_iga
== IGA1
) {
1884 viafb_write_reg(CR09
, VIACR
, 0x00); /*initial CR09=0 */
1885 viafb_write_reg_mask(CR11
, VIACR
, 0x00, BIT4
+ BIT5
+ BIT6
);
1886 viafb_write_reg_mask(CR17
, VIACR
, 0x00, BIT7
);
1891 viafb_load_crtc_timing(crt_reg
, IGA1
);
1894 viafb_load_crtc_timing(crt_reg
, IGA2
);
1898 load_fix_bit_crtc_reg();
1900 viafb_write_reg_mask(CR17
, VIACR
, 0x80, BIT7
);
1901 viafb_load_fetch_count_reg(h_addr
, bpp_byte
, set_iga
);
1904 if ((viaparinfo
->chip_info
->gfx_chip_name
!= UNICHROME_CLE266
)
1905 && (viaparinfo
->chip_info
->gfx_chip_name
!= UNICHROME_K400
))
1906 viafb_load_FIFO_reg(set_iga
, h_addr
, v_addr
);
1908 pll_D_N
= viafb_get_clk_value(crt_table
[index
].clk
);
1909 DEBUG_MSG(KERN_INFO
"PLL=%x", pll_D_N
);
1910 viafb_set_vclock(pll_D_N
, set_iga
);
1914 void viafb_init_chip_info(struct pci_dev
*pdev
,
1915 const struct pci_device_id
*pdi
)
1917 init_gfx_chip_info(pdev
, pdi
);
1918 init_tmds_chip_info();
1919 init_lvds_chip_info();
1921 viaparinfo
->crt_setting_info
->iga_path
= IGA1
;
1922 viaparinfo
->crt_setting_info
->refresh_rate
= viafb_refresh
;
1924 /*Set IGA path for each device */
1925 viafb_set_iga_path();
1927 viaparinfo
->lvds_setting_info
->display_method
= viafb_lcd_dsp_method
;
1928 viaparinfo
->lvds_setting_info
->get_lcd_size_method
=
1929 GET_LCD_SIZE_BY_USER_SETTING
;
1930 viaparinfo
->lvds_setting_info
->lcd_mode
= viafb_lcd_mode
;
1931 viaparinfo
->lvds_setting_info2
->display_method
=
1932 viaparinfo
->lvds_setting_info
->display_method
;
1933 viaparinfo
->lvds_setting_info2
->lcd_mode
=
1934 viaparinfo
->lvds_setting_info
->lcd_mode
;
1937 void viafb_update_device_setting(int hres
, int vres
,
1938 int bpp
, int vmode_refresh
, int flag
)
1941 viaparinfo
->crt_setting_info
->h_active
= hres
;
1942 viaparinfo
->crt_setting_info
->v_active
= vres
;
1943 viaparinfo
->crt_setting_info
->bpp
= bpp
;
1944 viaparinfo
->crt_setting_info
->refresh_rate
=
1947 viaparinfo
->tmds_setting_info
->h_active
= hres
;
1948 viaparinfo
->tmds_setting_info
->v_active
= vres
;
1950 viaparinfo
->lvds_setting_info
->h_active
= hres
;
1951 viaparinfo
->lvds_setting_info
->v_active
= vres
;
1952 viaparinfo
->lvds_setting_info
->bpp
= bpp
;
1953 viaparinfo
->lvds_setting_info
->refresh_rate
=
1955 viaparinfo
->lvds_setting_info2
->h_active
= hres
;
1956 viaparinfo
->lvds_setting_info2
->v_active
= vres
;
1957 viaparinfo
->lvds_setting_info2
->bpp
= bpp
;
1958 viaparinfo
->lvds_setting_info2
->refresh_rate
=
1962 if (viaparinfo
->tmds_setting_info
->iga_path
== IGA2
) {
1963 viaparinfo
->tmds_setting_info
->h_active
= hres
;
1964 viaparinfo
->tmds_setting_info
->v_active
= vres
;
1967 if (viaparinfo
->lvds_setting_info
->iga_path
== IGA2
) {
1968 viaparinfo
->lvds_setting_info
->h_active
= hres
;
1969 viaparinfo
->lvds_setting_info
->v_active
= vres
;
1970 viaparinfo
->lvds_setting_info
->bpp
= bpp
;
1971 viaparinfo
->lvds_setting_info
->refresh_rate
=
1974 if (IGA2
== viaparinfo
->lvds_setting_info2
->iga_path
) {
1975 viaparinfo
->lvds_setting_info2
->h_active
= hres
;
1976 viaparinfo
->lvds_setting_info2
->v_active
= vres
;
1977 viaparinfo
->lvds_setting_info2
->bpp
= bpp
;
1978 viaparinfo
->lvds_setting_info2
->refresh_rate
=
1984 static void init_gfx_chip_info(struct pci_dev
*pdev
,
1985 const struct pci_device_id
*pdi
)
1989 viaparinfo
->chip_info
->gfx_chip_name
= pdi
->driver_data
;
1991 /* Check revision of CLE266 Chip */
1992 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CLE266
) {
1993 /* CR4F only define in CLE266.CX chip */
1994 tmp
= viafb_read_reg(VIACR
, CR4F
);
1995 viafb_write_reg(CR4F
, VIACR
, 0x55);
1996 if (viafb_read_reg(VIACR
, CR4F
) != 0x55)
1997 viaparinfo
->chip_info
->gfx_chip_revision
=
2000 viaparinfo
->chip_info
->gfx_chip_revision
=
2002 /* restore orignal CR4F value */
2003 viafb_write_reg(CR4F
, VIACR
, tmp
);
2006 if (viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CX700
) {
2007 tmp
= viafb_read_reg(VIASR
, SR43
);
2008 DEBUG_MSG(KERN_INFO
"SR43:%X\n", tmp
);
2010 viaparinfo
->chip_info
->gfx_chip_revision
=
2011 CX700_REVISION_700M2
;
2012 } else if (tmp
& 0x40) {
2013 viaparinfo
->chip_info
->gfx_chip_revision
=
2014 CX700_REVISION_700M
;
2016 viaparinfo
->chip_info
->gfx_chip_revision
=
2021 /* Determine which 2D engine we have */
2022 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
2023 case UNICHROME_VX800
:
2024 case UNICHROME_VX855
:
2025 viaparinfo
->chip_info
->twod_engine
= VIA_2D_ENG_M1
;
2027 case UNICHROME_K8M890
:
2028 case UNICHROME_P4M900
:
2029 viaparinfo
->chip_info
->twod_engine
= VIA_2D_ENG_H5
;
2032 viaparinfo
->chip_info
->twod_engine
= VIA_2D_ENG_H2
;
2037 static void init_tmds_chip_info(void)
2039 viafb_tmds_trasmitter_identify();
2041 if (INTERFACE_NONE
== viaparinfo
->chip_info
->tmds_chip_info
.
2043 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
2044 case UNICHROME_CX700
:
2046 /* we should check support by hardware layout.*/
2047 if ((viafb_display_hardware_layout
==
2049 || (viafb_display_hardware_layout
==
2050 HW_LAYOUT_LCD_DVI
)) {
2051 viaparinfo
->chip_info
->tmds_chip_info
.
2052 output_interface
= INTERFACE_TMDS
;
2054 viaparinfo
->chip_info
->tmds_chip_info
.
2060 case UNICHROME_K8M890
:
2061 case UNICHROME_P4M900
:
2062 case UNICHROME_P4M890
:
2063 /* TMDS on PCIE, we set DFPLOW as default. */
2064 viaparinfo
->chip_info
->tmds_chip_info
.output_interface
=
2069 /* set DVP1 default for DVI */
2070 viaparinfo
->chip_info
->tmds_chip_info
2071 .output_interface
= INTERFACE_DVP1
;
2076 DEBUG_MSG(KERN_INFO
"TMDS Chip = %d\n",
2077 viaparinfo
->chip_info
->tmds_chip_info
.tmds_chip_name
);
2078 viafb_init_dvi_size(&viaparinfo
->shared
->chip_info
.tmds_chip_info
,
2079 &viaparinfo
->shared
->tmds_setting_info
);
2082 static void init_lvds_chip_info(void)
2084 if (viafb_lcd_panel_id
> LCD_PANEL_ID_MAXIMUM
)
2085 viaparinfo
->lvds_setting_info
->get_lcd_size_method
=
2086 GET_LCD_SIZE_BY_VGA_BIOS
;
2088 viaparinfo
->lvds_setting_info
->get_lcd_size_method
=
2089 GET_LCD_SIZE_BY_USER_SETTING
;
2091 viafb_lvds_trasmitter_identify();
2092 viafb_init_lcd_size();
2093 viafb_init_lvds_output_interface(&viaparinfo
->chip_info
->lvds_chip_info
,
2094 viaparinfo
->lvds_setting_info
);
2095 if (viaparinfo
->chip_info
->lvds_chip_info2
.lvds_chip_name
) {
2096 viafb_init_lvds_output_interface(&viaparinfo
->chip_info
->
2097 lvds_chip_info2
, viaparinfo
->lvds_setting_info2
);
2099 /*If CX700,two singel LCD, we need to reassign
2100 LCD interface to different LVDS port */
2101 if ((UNICHROME_CX700
== viaparinfo
->chip_info
->gfx_chip_name
)
2102 && (HW_LAYOUT_LCD1_LCD2
== viafb_display_hardware_layout
)) {
2103 if ((INTEGRATED_LVDS
== viaparinfo
->chip_info
->lvds_chip_info
.
2104 lvds_chip_name
) && (INTEGRATED_LVDS
==
2105 viaparinfo
->chip_info
->
2106 lvds_chip_info2
.lvds_chip_name
)) {
2107 viaparinfo
->chip_info
->lvds_chip_info
.output_interface
=
2109 viaparinfo
->chip_info
->lvds_chip_info2
.
2115 DEBUG_MSG(KERN_INFO
"LVDS Chip = %d\n",
2116 viaparinfo
->chip_info
->lvds_chip_info
.lvds_chip_name
);
2117 DEBUG_MSG(KERN_INFO
"LVDS1 output_interface = %d\n",
2118 viaparinfo
->chip_info
->lvds_chip_info
.output_interface
);
2119 DEBUG_MSG(KERN_INFO
"LVDS2 output_interface = %d\n",
2120 viaparinfo
->chip_info
->lvds_chip_info
.output_interface
);
2123 void viafb_init_dac(int set_iga
)
2128 if (set_iga
== IGA1
) {
2129 /* access Primary Display's LUT */
2130 viafb_write_reg_mask(SR1A
, VIASR
, 0x00, BIT0
);
2132 viafb_write_reg_mask(SR1B
, VIASR
, 0x00, BIT7
+ BIT6
);
2133 for (i
= 0; i
< 256; i
++) {
2134 write_dac_reg(i
, palLUT_table
[i
].red
,
2135 palLUT_table
[i
].green
,
2136 palLUT_table
[i
].blue
);
2139 viafb_write_reg_mask(SR1B
, VIASR
, 0xC0, BIT7
+ BIT6
);
2141 tmp
= viafb_read_reg(VIACR
, CR6A
);
2142 /* access Secondary Display's LUT */
2143 viafb_write_reg_mask(CR6A
, VIACR
, 0x40, BIT6
);
2144 viafb_write_reg_mask(SR1A
, VIASR
, 0x01, BIT0
);
2145 for (i
= 0; i
< 256; i
++) {
2146 write_dac_reg(i
, palLUT_table
[i
].red
,
2147 palLUT_table
[i
].green
,
2148 palLUT_table
[i
].blue
);
2150 /* set IGA1 DAC for default */
2151 viafb_write_reg_mask(SR1A
, VIASR
, 0x00, BIT0
);
2152 viafb_write_reg(CR6A
, VIACR
, tmp
);
2156 static void device_screen_off(void)
2158 /* turn off CRT screen (IGA1) */
2159 viafb_write_reg_mask(SR01
, VIASR
, 0x20, BIT5
);
2162 static void device_screen_on(void)
2164 /* turn on CRT screen (IGA1) */
2165 viafb_write_reg_mask(SR01
, VIASR
, 0x00, BIT5
);
2168 static void set_display_channel(void)
2170 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2171 is keeped on lvds_setting_info2 */
2172 if (viafb_LCD2_ON
&&
2173 viaparinfo
->lvds_setting_info2
->device_lcd_dualedge
) {
2174 /* For dual channel LCD: */
2175 /* Set to Dual LVDS channel. */
2176 viafb_write_reg_mask(CRD2
, VIACR
, 0x20, BIT4
+ BIT5
);
2177 } else if (viafb_LCD_ON
&& viafb_DVI_ON
) {
2179 /* Set to LVDS1 + TMDS channel. */
2180 viafb_write_reg_mask(CRD2
, VIACR
, 0x10, BIT4
+ BIT5
);
2181 } else if (viafb_DVI_ON
) {
2182 /* Set to single TMDS channel. */
2183 viafb_write_reg_mask(CRD2
, VIACR
, 0x30, BIT4
+ BIT5
);
2184 } else if (viafb_LCD_ON
) {
2185 if (viaparinfo
->lvds_setting_info
->device_lcd_dualedge
) {
2186 /* For dual channel LCD: */
2187 /* Set to Dual LVDS channel. */
2188 viafb_write_reg_mask(CRD2
, VIACR
, 0x20, BIT4
+ BIT5
);
2190 /* Set to LVDS0 + LVDS1 channel. */
2191 viafb_write_reg_mask(CRD2
, VIACR
, 0x00, BIT4
+ BIT5
);
2196 int viafb_setmode(struct VideoModeTable
*vmode_tbl
, int video_bpp
,
2197 struct VideoModeTable
*vmode_tbl1
, int video_bpp1
)
2201 u8 value
, index
, mask
;
2202 struct crt_mode_table
*crt_timing
;
2203 struct crt_mode_table
*crt_timing1
= NULL
;
2205 device_screen_off();
2206 crt_timing
= vmode_tbl
->crtc
;
2208 if (viafb_SAMM_ON
== 1) {
2209 crt_timing1
= vmode_tbl1
->crtc
;
2215 /* Write Common Setting for Video Mode */
2216 switch (viaparinfo
->chip_info
->gfx_chip_name
) {
2217 case UNICHROME_CLE266
:
2218 viafb_write_regx(CLE266_ModeXregs
, NUM_TOTAL_CLE266_ModeXregs
);
2221 case UNICHROME_K400
:
2222 viafb_write_regx(KM400_ModeXregs
, NUM_TOTAL_KM400_ModeXregs
);
2225 case UNICHROME_K800
:
2226 case UNICHROME_PM800
:
2227 viafb_write_regx(CN400_ModeXregs
, NUM_TOTAL_CN400_ModeXregs
);
2230 case UNICHROME_CN700
:
2231 case UNICHROME_K8M890
:
2232 case UNICHROME_P4M890
:
2233 case UNICHROME_P4M900
:
2234 viafb_write_regx(CN700_ModeXregs
, NUM_TOTAL_CN700_ModeXregs
);
2237 case UNICHROME_CX700
:
2238 case UNICHROME_VX800
:
2239 viafb_write_regx(CX700_ModeXregs
, NUM_TOTAL_CX700_ModeXregs
);
2242 case UNICHROME_VX855
:
2243 viafb_write_regx(VX855_ModeXregs
, NUM_TOTAL_VX855_ModeXregs
);
2249 /* Fill VPIT Parameters */
2250 /* Write Misc Register */
2251 outb(VPIT
.Misc
, VIAWMisc
);
2253 /* Write Sequencer */
2254 for (i
= 1; i
<= StdSR
; i
++) {
2256 outb(VPIT
.SR
[i
- 1], VIASR
+ 1);
2259 viafb_write_reg_mask(0x15, VIASR
, 0xA2, 0xA2);
2260 viafb_set_iga_path();
2263 viafb_fill_crtc_timing(crt_timing
, vmode_tbl
, video_bpp
/ 8, IGA1
);
2265 /* Write Graphic Controller */
2266 for (i
= 0; i
< StdGR
; i
++) {
2268 outb(VPIT
.GR
[i
], VIAGR
+ 1);
2271 /* Write Attribute Controller */
2272 for (i
= 0; i
< StdAR
; i
++) {
2275 outb(VPIT
.AR
[i
], VIAAR
);
2281 /* Update Patch Register */
2283 if ((viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CLE266
2284 || viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_K400
)
2285 && vmode_tbl
->crtc
[0].crtc
.hor_addr
== 1024
2286 && vmode_tbl
->crtc
[0].crtc
.ver_addr
== 768) {
2287 for (j
= 0; j
< res_patch_table
[0].table_length
; j
++) {
2288 index
= res_patch_table
[0].io_reg_table
[j
].index
;
2289 port
= res_patch_table
[0].io_reg_table
[j
].port
;
2290 value
= res_patch_table
[0].io_reg_table
[j
].value
;
2291 mask
= res_patch_table
[0].io_reg_table
[j
].mask
;
2292 viafb_write_reg_mask(index
, port
, value
, mask
);
2296 viafb_set_primary_pitch(viafbinfo
->fix
.line_length
);
2297 viafb_set_secondary_pitch(viafb_dual_fb
? viafbinfo1
->fix
.line_length
2298 : viafbinfo
->fix
.line_length
);
2299 viafb_set_primary_color_depth(viaparinfo
->depth
);
2300 viafb_set_secondary_color_depth(viafb_dual_fb
? viaparinfo1
->depth
2301 : viaparinfo
->depth
);
2302 /* Update Refresh Rate Setting */
2304 /* Clear On Screen */
2308 if (viafb_SAMM_ON
&& (viaparinfo
->crt_setting_info
->iga_path
==
2310 viafb_fill_crtc_timing(crt_timing1
, vmode_tbl1
,
2312 viaparinfo
->crt_setting_info
->iga_path
);
2314 viafb_fill_crtc_timing(crt_timing
, vmode_tbl
,
2316 viaparinfo
->crt_setting_info
->iga_path
);
2319 set_crt_output_path(viaparinfo
->crt_setting_info
->iga_path
);
2321 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2322 to 8 alignment (1368),there is several pixels (2 pixels)
2323 on right side of screen. */
2324 if (vmode_tbl
->crtc
[0].crtc
.hor_addr
% 8) {
2326 viafb_write_reg(CR02
, VIACR
,
2327 viafb_read_reg(VIACR
, CR02
) - 1);
2333 if (viafb_SAMM_ON
&&
2334 (viaparinfo
->tmds_setting_info
->iga_path
== IGA2
)) {
2335 viafb_dvi_set_mode(viafb_get_mode
2336 (viaparinfo
->tmds_setting_info
->h_active
,
2337 viaparinfo
->tmds_setting_info
->
2339 video_bpp1
, viaparinfo
->
2340 tmds_setting_info
->iga_path
);
2342 viafb_dvi_set_mode(viafb_get_mode
2343 (viaparinfo
->tmds_setting_info
->h_active
,
2345 tmds_setting_info
->v_active
),
2346 video_bpp
, viaparinfo
->
2347 tmds_setting_info
->iga_path
);
2352 if (viafb_SAMM_ON
&&
2353 (viaparinfo
->lvds_setting_info
->iga_path
== IGA2
)) {
2354 viaparinfo
->lvds_setting_info
->bpp
= video_bpp1
;
2355 viafb_lcd_set_mode(crt_timing1
, viaparinfo
->
2357 &viaparinfo
->chip_info
->lvds_chip_info
);
2359 /* IGA1 doesn't have LCD scaling, so set it center. */
2360 if (viaparinfo
->lvds_setting_info
->iga_path
== IGA1
) {
2361 viaparinfo
->lvds_setting_info
->display_method
=
2364 viaparinfo
->lvds_setting_info
->bpp
= video_bpp
;
2365 viafb_lcd_set_mode(crt_timing
, viaparinfo
->
2367 &viaparinfo
->chip_info
->lvds_chip_info
);
2370 if (viafb_LCD2_ON
) {
2371 if (viafb_SAMM_ON
&&
2372 (viaparinfo
->lvds_setting_info2
->iga_path
== IGA2
)) {
2373 viaparinfo
->lvds_setting_info2
->bpp
= video_bpp1
;
2374 viafb_lcd_set_mode(crt_timing1
, viaparinfo
->
2376 &viaparinfo
->chip_info
->lvds_chip_info2
);
2378 /* IGA1 doesn't have LCD scaling, so set it center. */
2379 if (viaparinfo
->lvds_setting_info2
->iga_path
== IGA1
) {
2380 viaparinfo
->lvds_setting_info2
->display_method
=
2383 viaparinfo
->lvds_setting_info2
->bpp
= video_bpp
;
2384 viafb_lcd_set_mode(crt_timing
, viaparinfo
->
2386 &viaparinfo
->chip_info
->lvds_chip_info2
);
2390 if ((viaparinfo
->chip_info
->gfx_chip_name
== UNICHROME_CX700
)
2391 && (viafb_LCD_ON
|| viafb_DVI_ON
))
2392 set_display_channel();
2394 /* If set mode normally, save resolution information for hot-plug . */
2395 if (!viafb_hotplug
) {
2396 viafb_hotplug_Xres
= vmode_tbl
->crtc
[0].crtc
.hor_addr
;
2397 viafb_hotplug_Yres
= vmode_tbl
->crtc
[0].crtc
.ver_addr
;
2398 viafb_hotplug_bpp
= video_bpp
;
2399 viafb_hotplug_refresh
= viafb_refresh
;
2402 viafb_DeviceStatus
= DVI_Device
;
2404 viafb_DeviceStatus
= CRT_Device
;
2408 if (viafb_SAMM_ON
== 1)
2409 viafb_write_reg_mask(CR6A
, VIACR
, 0xC0, BIT6
+ BIT7
);
2415 int viafb_get_pixclock(int hres
, int vres
, int vmode_refresh
)
2419 for (i
= 0; i
< NUM_TOTAL_RES_MAP_REFRESH
; i
++) {
2420 if ((hres
== res_map_refresh_tbl
[i
].hres
)
2421 && (vres
== res_map_refresh_tbl
[i
].vres
)
2422 && (vmode_refresh
== res_map_refresh_tbl
[i
].vmode_refresh
))
2423 return res_map_refresh_tbl
[i
].pixclock
;
2425 return RES_640X480_60HZ_PIXCLOCK
;
2429 int viafb_get_refresh(int hres
, int vres
, u32 long_refresh
)
2431 #define REFRESH_TOLERANCE 3
2432 int i
, nearest
= -1, diff
= REFRESH_TOLERANCE
;
2433 for (i
= 0; i
< NUM_TOTAL_RES_MAP_REFRESH
; i
++) {
2434 if ((hres
== res_map_refresh_tbl
[i
].hres
)
2435 && (vres
== res_map_refresh_tbl
[i
].vres
)
2436 && (diff
> (abs(long_refresh
-
2437 res_map_refresh_tbl
[i
].vmode_refresh
)))) {
2438 diff
= abs(long_refresh
- res_map_refresh_tbl
[i
].
2443 #undef REFRESH_TOLERANCE
2445 return res_map_refresh_tbl
[nearest
].vmode_refresh
;
2449 static void device_off(void)
2451 viafb_crt_disable();
2452 viafb_dvi_disable();
2453 viafb_lcd_disable();
2456 static void device_on(void)
2458 if (viafb_CRT_ON
== 1)
2460 if (viafb_DVI_ON
== 1)
2462 if (viafb_LCD_ON
== 1)
2466 void viafb_crt_disable(void)
2468 viafb_write_reg_mask(CR36
, VIACR
, BIT5
+ BIT4
, BIT5
+ BIT4
);
2471 void viafb_crt_enable(void)
2473 viafb_write_reg_mask(CR36
, VIACR
, 0x0, BIT5
+ BIT4
);
2476 static void enable_second_display_channel(void)
2478 /* to enable second display channel. */
2479 viafb_write_reg_mask(CR6A
, VIACR
, 0x00, BIT6
);
2480 viafb_write_reg_mask(CR6A
, VIACR
, BIT7
, BIT7
);
2481 viafb_write_reg_mask(CR6A
, VIACR
, BIT6
, BIT6
);
2484 static void disable_second_display_channel(void)
2486 /* to disable second display channel. */
2487 viafb_write_reg_mask(CR6A
, VIACR
, 0x00, BIT6
);
2488 viafb_write_reg_mask(CR6A
, VIACR
, 0x00, BIT7
);
2489 viafb_write_reg_mask(CR6A
, VIACR
, BIT6
, BIT6
);
2492 static u_int16_t via_function3
[] = {
2493 CLE266_FUNCTION3
, KM400_FUNCTION3
, CN400_FUNCTION3
, CN700_FUNCTION3
,
2494 CX700_FUNCTION3
, KM800_FUNCTION3
, KM890_FUNCTION3
, P4M890_FUNCTION3
,
2495 P4M900_FUNCTION3
, VX800_FUNCTION3
, VX855_FUNCTION3
,
2498 /* Get the BIOS-configured framebuffer size from PCI configuration space
2499 * of function 3 in the respective chipset */
2500 int viafb_get_fb_size_from_pci(void)
2503 u_int8_t offset
= 0;
2505 u_int32_t VideoMemSize
;
2507 /* search for the "FUNCTION3" device in this chipset */
2508 for (i
= 0; i
< ARRAY_SIZE(via_function3
); i
++) {
2509 struct pci_dev
*pdev
;
2511 pdev
= pci_get_device(PCI_VENDOR_ID_VIA
, via_function3
[i
],
2516 DEBUG_MSG(KERN_INFO
"Device ID = %x\n", pdev
->device
);
2518 switch (pdev
->device
) {
2519 case CLE266_FUNCTION3
:
2520 case KM400_FUNCTION3
:
2523 case CN400_FUNCTION3
:
2524 case CN700_FUNCTION3
:
2525 case CX700_FUNCTION3
:
2526 case KM800_FUNCTION3
:
2527 case KM890_FUNCTION3
:
2528 case P4M890_FUNCTION3
:
2529 case P4M900_FUNCTION3
:
2530 case VX800_FUNCTION3
:
2531 case VX855_FUNCTION3
:
2532 /*case CN750_FUNCTION3: */
2540 pci_read_config_dword(pdev
, offset
, &FBSize
);
2545 printk(KERN_ERR
"cannot determine framebuffer size\n");
2549 FBSize
= FBSize
& 0x00007000;
2550 DEBUG_MSG(KERN_INFO
"FB Size = %x\n", FBSize
);
2552 if (viaparinfo
->chip_info
->gfx_chip_name
< UNICHROME_CX700
) {
2555 VideoMemSize
= (16 << 20); /*16M */
2559 VideoMemSize
= (32 << 20); /*32M */
2563 VideoMemSize
= (64 << 20); /*64M */
2567 VideoMemSize
= (32 << 20); /*32M */
2573 VideoMemSize
= (8 << 20); /*8M */
2577 VideoMemSize
= (16 << 20); /*16M */
2581 VideoMemSize
= (32 << 20); /*32M */
2585 VideoMemSize
= (64 << 20); /*64M */
2589 VideoMemSize
= (128 << 20); /*128M */
2593 VideoMemSize
= (256 << 20); /*256M */
2596 case 0x00007000: /* Only on VX855/875 */
2597 VideoMemSize
= (512 << 20); /*512M */
2601 VideoMemSize
= (32 << 20); /*32M */
2606 return VideoMemSize
;
2609 void viafb_set_dpa_gfx(int output_interface
, struct GFX_DPA_SETTING\
2612 switch (output_interface
) {
2613 case INTERFACE_DVP0
:
2615 /* DVP0 Clock Polarity and Adjust: */
2616 viafb_write_reg_mask(CR96
, VIACR
,
2617 p_gfx_dpa_setting
->DVP0
, 0x0F);
2619 /* DVP0 Clock and Data Pads Driving: */
2620 viafb_write_reg_mask(SR1E
, VIASR
,
2621 p_gfx_dpa_setting
->DVP0ClockDri_S
, BIT2
);
2622 viafb_write_reg_mask(SR2A
, VIASR
,
2623 p_gfx_dpa_setting
->DVP0ClockDri_S1
,
2625 viafb_write_reg_mask(SR1B
, VIASR
,
2626 p_gfx_dpa_setting
->DVP0DataDri_S
, BIT1
);
2627 viafb_write_reg_mask(SR2A
, VIASR
,
2628 p_gfx_dpa_setting
->DVP0DataDri_S1
, BIT5
);
2632 case INTERFACE_DVP1
:
2634 /* DVP1 Clock Polarity and Adjust: */
2635 viafb_write_reg_mask(CR9B
, VIACR
,
2636 p_gfx_dpa_setting
->DVP1
, 0x0F);
2638 /* DVP1 Clock and Data Pads Driving: */
2639 viafb_write_reg_mask(SR65
, VIASR
,
2640 p_gfx_dpa_setting
->DVP1Driving
, 0x0F);
2644 case INTERFACE_DFP_HIGH
:
2646 viafb_write_reg_mask(CR97
, VIACR
,
2647 p_gfx_dpa_setting
->DFPHigh
, 0x0F);
2651 case INTERFACE_DFP_LOW
:
2653 viafb_write_reg_mask(CR99
, VIACR
,
2654 p_gfx_dpa_setting
->DFPLow
, 0x0F);
2660 viafb_write_reg_mask(CR97
, VIACR
,
2661 p_gfx_dpa_setting
->DFPHigh
, 0x0F);
2662 viafb_write_reg_mask(CR99
, VIACR
,
2663 p_gfx_dpa_setting
->DFPLow
, 0x0F);
2669 /*According var's xres, yres fill var's other timing information*/
2670 void viafb_fill_var_timing_info(struct fb_var_screeninfo
*var
, int refresh
,
2671 struct VideoModeTable
*vmode_tbl
)
2673 struct crt_mode_table
*crt_timing
= NULL
;
2674 struct display_timing crt_reg
;
2675 int i
= 0, index
= 0;
2676 crt_timing
= vmode_tbl
->crtc
;
2677 for (i
= 0; i
< vmode_tbl
->mode_array
; i
++) {
2679 if (crt_timing
[i
].refresh_rate
== refresh
)
2683 crt_reg
= crt_timing
[index
].crtc
;
2684 var
->pixclock
= viafb_get_pixclock(var
->xres
, var
->yres
, refresh
);
2686 crt_reg
.hor_total
- (crt_reg
.hor_sync_start
+ crt_reg
.hor_sync_end
);
2687 var
->right_margin
= crt_reg
.hor_sync_start
- crt_reg
.hor_addr
;
2688 var
->hsync_len
= crt_reg
.hor_sync_end
;
2690 crt_reg
.ver_total
- (crt_reg
.ver_sync_start
+ crt_reg
.ver_sync_end
);
2691 var
->lower_margin
= crt_reg
.ver_sync_start
- crt_reg
.ver_addr
;
2692 var
->vsync_len
= crt_reg
.ver_sync_end
;