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viafb: rework color setting
[mirror_ubuntu-artful-kernel.git] / drivers / video / via / hw.c
1 /*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22 #include "global.h"
23
24 static struct pll_map pll_value[] = {
25 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
26 CX700_25_175M, VX855_25_175M},
27 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
28 CX700_29_581M, VX855_29_581M},
29 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
30 CX700_26_880M, VX855_26_880M},
31 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
32 CX700_31_490M, VX855_31_490M},
33 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
34 CX700_31_500M, VX855_31_500M},
35 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
36 CX700_31_728M, VX855_31_728M},
37 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
38 CX700_32_668M, VX855_32_668M},
39 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
40 CX700_36_000M, VX855_36_000M},
41 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
42 CX700_40_000M, VX855_40_000M},
43 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
44 CX700_41_291M, VX855_41_291M},
45 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
46 CX700_43_163M, VX855_43_163M},
47 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
48 CX700_45_250M, VX855_45_250M},
49 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
50 CX700_46_000M, VX855_46_000M},
51 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
52 CX700_46_996M, VX855_46_996M},
53 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
54 CX700_48_000M, VX855_48_000M},
55 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
56 CX700_48_875M, VX855_48_875M},
57 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
58 CX700_49_500M, VX855_49_500M},
59 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
60 CX700_52_406M, VX855_52_406M},
61 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
62 CX700_52_977M, VX855_52_977M},
63 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
64 CX700_56_250M, VX855_56_250M},
65 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
66 CX700_60_466M, VX855_60_466M},
67 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
68 CX700_61_500M, VX855_61_500M},
69 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
70 CX700_65_000M, VX855_65_000M},
71 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
72 CX700_65_178M, VX855_65_178M},
73 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
74 CX700_66_750M, VX855_66_750M},
75 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
76 CX700_68_179M, VX855_68_179M},
77 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
78 CX700_69_924M, VX855_69_924M},
79 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
80 CX700_70_159M, VX855_70_159M},
81 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
82 CX700_72_000M, VX855_72_000M},
83 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
84 CX700_78_750M, VX855_78_750M},
85 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
86 CX700_80_136M, VX855_80_136M},
87 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
88 CX700_83_375M, VX855_83_375M},
89 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
90 CX700_83_950M, VX855_83_950M},
91 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
92 CX700_84_750M, VX855_84_750M},
93 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
94 CX700_85_860M, VX855_85_860M},
95 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
96 CX700_88_750M, VX855_88_750M},
97 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
98 CX700_94_500M, VX855_94_500M},
99 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
100 CX700_97_750M, VX855_97_750M},
101 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
102 CX700_101_000M, VX855_101_000M},
103 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
104 CX700_106_500M, VX855_106_500M},
105 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
106 CX700_108_000M, VX855_108_000M},
107 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
108 CX700_113_309M, VX855_113_309M},
109 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
110 CX700_118_840M, VX855_118_840M},
111 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
112 CX700_119_000M, VX855_119_000M},
113 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
114 CX700_121_750M, 0},
115 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
116 CX700_125_104M, 0},
117 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
118 CX700_133_308M, 0},
119 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
120 CX700_135_000M, VX855_135_000M},
121 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
122 CX700_136_700M, VX855_136_700M},
123 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
124 CX700_138_400M, VX855_138_400M},
125 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
126 CX700_146_760M, VX855_146_760M},
127 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
128 CX700_153_920M, VX855_153_920M},
129 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
130 CX700_156_000M, VX855_156_000M},
131 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
132 CX700_157_500M, VX855_157_500M},
133 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
134 CX700_162_000M, VX855_162_000M},
135 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
136 CX700_187_000M, VX855_187_000M},
137 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
138 CX700_193_295M, VX855_193_295M},
139 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
140 CX700_202_500M, VX855_202_500M},
141 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
142 CX700_204_000M, VX855_204_000M},
143 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
144 CX700_218_500M, VX855_218_500M},
145 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
146 CX700_234_000M, VX855_234_000M},
147 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
148 CX700_267_250M, VX855_267_250M},
149 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
150 CX700_297_500M, VX855_297_500M},
151 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
152 CX700_74_481M, VX855_74_481M},
153 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
154 CX700_172_798M, VX855_172_798M},
155 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
156 CX700_122_614M, VX855_122_614M},
157 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
158 CX700_74_270M, 0},
159 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
160 CX700_148_500M, VX855_148_500M}
161 };
162
163 static struct fifo_depth_select display_fifo_depth_reg = {
164 /* IGA1 FIFO Depth_Select */
165 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
166 /* IGA2 FIFO Depth_Select */
167 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
168 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
169 };
170
171 static struct fifo_threshold_select fifo_threshold_select_reg = {
172 /* IGA1 FIFO Threshold Select */
173 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
174 /* IGA2 FIFO Threshold Select */
175 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
176 };
177
178 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
179 /* IGA1 FIFO High Threshold Select */
180 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
181 /* IGA2 FIFO High Threshold Select */
182 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
183 };
184
185 static struct display_queue_expire_num display_queue_expire_num_reg = {
186 /* IGA1 Display Queue Expire Num */
187 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
188 /* IGA2 Display Queue Expire Num */
189 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
190 };
191
192 /* Definition Fetch Count Registers*/
193 static struct fetch_count fetch_count_reg = {
194 /* IGA1 Fetch Count Register */
195 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
196 /* IGA2 Fetch Count Register */
197 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
198 };
199
200 static struct iga1_crtc_timing iga1_crtc_reg = {
201 /* IGA1 Horizontal Total */
202 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
203 /* IGA1 Horizontal Addressable Video */
204 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
205 /* IGA1 Horizontal Blank Start */
206 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
207 /* IGA1 Horizontal Blank End */
208 {IGA1_HOR_BLANK_END_REG_NUM,
209 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
210 /* IGA1 Horizontal Sync Start */
211 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
212 /* IGA1 Horizontal Sync End */
213 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
214 /* IGA1 Vertical Total */
215 {IGA1_VER_TOTAL_REG_NUM,
216 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
217 /* IGA1 Vertical Addressable Video */
218 {IGA1_VER_ADDR_REG_NUM,
219 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
220 /* IGA1 Vertical Blank Start */
221 {IGA1_VER_BLANK_START_REG_NUM,
222 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
223 /* IGA1 Vertical Blank End */
224 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
225 /* IGA1 Vertical Sync Start */
226 {IGA1_VER_SYNC_START_REG_NUM,
227 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
228 /* IGA1 Vertical Sync End */
229 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
230 };
231
232 static struct iga2_crtc_timing iga2_crtc_reg = {
233 /* IGA2 Horizontal Total */
234 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
235 /* IGA2 Horizontal Addressable Video */
236 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
237 /* IGA2 Horizontal Blank Start */
238 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
239 /* IGA2 Horizontal Blank End */
240 {IGA2_HOR_BLANK_END_REG_NUM,
241 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
242 /* IGA2 Horizontal Sync Start */
243 {IGA2_HOR_SYNC_START_REG_NUM,
244 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
245 /* IGA2 Horizontal Sync End */
246 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
247 /* IGA2 Vertical Total */
248 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
249 /* IGA2 Vertical Addressable Video */
250 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
251 /* IGA2 Vertical Blank Start */
252 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
253 /* IGA2 Vertical Blank End */
254 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
255 /* IGA2 Vertical Sync Start */
256 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
257 /* IGA2 Vertical Sync End */
258 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
259 };
260
261 static struct rgbLUT palLUT_table[] = {
262 /* {R,G,B} */
263 /* Index 0x00~0x03 */
264 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
265 0x2A,
266 0x2A},
267 /* Index 0x04~0x07 */
268 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
269 0x2A,
270 0x2A},
271 /* Index 0x08~0x0B */
272 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
273 0x3F,
274 0x3F},
275 /* Index 0x0C~0x0F */
276 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
277 0x3F,
278 0x3F},
279 /* Index 0x10~0x13 */
280 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
281 0x0B,
282 0x0B},
283 /* Index 0x14~0x17 */
284 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
285 0x18,
286 0x18},
287 /* Index 0x18~0x1B */
288 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
289 0x28,
290 0x28},
291 /* Index 0x1C~0x1F */
292 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
293 0x3F,
294 0x3F},
295 /* Index 0x20~0x23 */
296 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
297 0x00,
298 0x3F},
299 /* Index 0x24~0x27 */
300 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
301 0x00,
302 0x10},
303 /* Index 0x28~0x2B */
304 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
305 0x2F,
306 0x00},
307 /* Index 0x2C~0x2F */
308 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
309 0x3F,
310 0x00},
311 /* Index 0x30~0x33 */
312 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
313 0x3F,
314 0x2F},
315 /* Index 0x34~0x37 */
316 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
317 0x10,
318 0x3F},
319 /* Index 0x38~0x3B */
320 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
321 0x1F,
322 0x3F},
323 /* Index 0x3C~0x3F */
324 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
325 0x1F,
326 0x27},
327 /* Index 0x40~0x43 */
328 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
329 0x3F,
330 0x1F},
331 /* Index 0x44~0x47 */
332 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
333 0x3F,
334 0x1F},
335 /* Index 0x48~0x4B */
336 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
337 0x3F,
338 0x37},
339 /* Index 0x4C~0x4F */
340 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
341 0x27,
342 0x3F},
343 /* Index 0x50~0x53 */
344 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
345 0x2D,
346 0x3F},
347 /* Index 0x54~0x57 */
348 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
349 0x2D,
350 0x31},
351 /* Index 0x58~0x5B */
352 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
353 0x3A,
354 0x2D},
355 /* Index 0x5C~0x5F */
356 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
357 0x3F,
358 0x2D},
359 /* Index 0x60~0x63 */
360 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
361 0x3F,
362 0x3A},
363 /* Index 0x64~0x67 */
364 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
365 0x31,
366 0x3F},
367 /* Index 0x68~0x6B */
368 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
369 0x00,
370 0x1C},
371 /* Index 0x6C~0x6F */
372 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
373 0x00,
374 0x07},
375 /* Index 0x70~0x73 */
376 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
377 0x15,
378 0x00},
379 /* Index 0x74~0x77 */
380 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
381 0x1C,
382 0x00},
383 /* Index 0x78~0x7B */
384 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
385 0x1C,
386 0x15},
387 /* Index 0x7C~0x7F */
388 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
389 0x07,
390 0x1C},
391 /* Index 0x80~0x83 */
392 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
393 0x0E,
394 0x1C},
395 /* Index 0x84~0x87 */
396 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
397 0x0E,
398 0x11},
399 /* Index 0x88~0x8B */
400 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
401 0x18,
402 0x0E},
403 /* Index 0x8C~0x8F */
404 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
405 0x1C,
406 0x0E},
407 /* Index 0x90~0x93 */
408 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
409 0x1C,
410 0x18},
411 /* Index 0x94~0x97 */
412 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
413 0x11,
414 0x1C},
415 /* Index 0x98~0x9B */
416 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
417 0x14,
418 0x1C},
419 /* Index 0x9C~0x9F */
420 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
421 0x14,
422 0x16},
423 /* Index 0xA0~0xA3 */
424 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
425 0x1A,
426 0x14},
427 /* Index 0xA4~0xA7 */
428 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
429 0x1C,
430 0x14},
431 /* Index 0xA8~0xAB */
432 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
433 0x1C,
434 0x1A},
435 /* Index 0xAC~0xAF */
436 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
437 0x16,
438 0x1C},
439 /* Index 0xB0~0xB3 */
440 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
441 0x00,
442 0x10},
443 /* Index 0xB4~0xB7 */
444 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
445 0x00,
446 0x04},
447 /* Index 0xB8~0xBB */
448 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
449 0x0C,
450 0x00},
451 /* Index 0xBC~0xBF */
452 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
453 0x10,
454 0x00},
455 /* Index 0xC0~0xC3 */
456 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
457 0x10,
458 0x0C},
459 /* Index 0xC4~0xC7 */
460 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
461 0x04,
462 0x10},
463 /* Index 0xC8~0xCB */
464 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
465 0x08,
466 0x10},
467 /* Index 0xCC~0xCF */
468 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
469 0x08,
470 0x0A},
471 /* Index 0xD0~0xD3 */
472 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
473 0x0E,
474 0x08},
475 /* Index 0xD4~0xD7 */
476 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
477 0x10,
478 0x08},
479 /* Index 0xD8~0xDB */
480 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
481 0x10,
482 0x0E},
483 /* Index 0xDC~0xDF */
484 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
485 0x0A,
486 0x10},
487 /* Index 0xE0~0xE3 */
488 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
489 0x0B,
490 0x10},
491 /* Index 0xE4~0xE7 */
492 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
493 0x0B,
494 0x0C},
495 /* Index 0xE8~0xEB */
496 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
497 0x0F,
498 0x0B},
499 /* Index 0xEC~0xEF */
500 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
501 0x10,
502 0x0B},
503 /* Index 0xF0~0xF3 */
504 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
505 0x10,
506 0x0F},
507 /* Index 0xF4~0xF7 */
508 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
509 0x0C,
510 0x10},
511 /* Index 0xF8~0xFB */
512 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
513 0x00,
514 0x00},
515 /* Index 0xFC~0xFF */
516 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
517 0x00,
518 0x00}
519 };
520
521 static void set_crt_output_path(int set_iga);
522 static void dvi_patch_skew_dvp0(void);
523 static void dvi_patch_skew_dvp1(void);
524 static void dvi_patch_skew_dvp_low(void);
525 static void set_dvi_output_path(int set_iga, int output_interface);
526 static void set_lcd_output_path(int set_iga, int output_interface);
527 static void load_fix_bit_crtc_reg(void);
528 static void init_gfx_chip_info(struct pci_dev *pdev,
529 const struct pci_device_id *pdi);
530 static void init_tmds_chip_info(void);
531 static void init_lvds_chip_info(void);
532 static void device_screen_off(void);
533 static void device_screen_on(void);
534 static void set_display_channel(void);
535 static void device_off(void);
536 static void device_on(void);
537 static void enable_second_display_channel(void);
538 static void disable_second_display_channel(void);
539
540 void viafb_write_reg(u8 index, u16 io_port, u8 data)
541 {
542 outb(index, io_port);
543 outb(data, io_port + 1);
544 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
545 }
546 u8 viafb_read_reg(int io_port, u8 index)
547 {
548 outb(index, io_port);
549 return inb(io_port + 1);
550 }
551
552 void viafb_lock_crt(void)
553 {
554 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
555 }
556
557 void viafb_unlock_crt(void)
558 {
559 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
560 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
561 }
562
563 void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
564 {
565 u8 tmp;
566
567 outb(index, io_port);
568 tmp = inb(io_port + 1);
569 outb((data & mask) | (tmp & (~mask)), io_port + 1);
570 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
571 }
572
573 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
574 {
575 outb(index, LUT_INDEX_WRITE);
576 outb(r, LUT_DATA);
577 outb(g, LUT_DATA);
578 outb(b, LUT_DATA);
579 }
580
581 /*Set IGA path for each device*/
582 void viafb_set_iga_path(void)
583 {
584
585 if (viafb_SAMM_ON == 1) {
586 if (viafb_CRT_ON) {
587 if (viafb_primary_dev == CRT_Device)
588 viaparinfo->crt_setting_info->iga_path = IGA1;
589 else
590 viaparinfo->crt_setting_info->iga_path = IGA2;
591 }
592
593 if (viafb_DVI_ON) {
594 if (viafb_primary_dev == DVI_Device)
595 viaparinfo->tmds_setting_info->iga_path = IGA1;
596 else
597 viaparinfo->tmds_setting_info->iga_path = IGA2;
598 }
599
600 if (viafb_LCD_ON) {
601 if (viafb_primary_dev == LCD_Device) {
602 if (viafb_dual_fb &&
603 (viaparinfo->chip_info->gfx_chip_name ==
604 UNICHROME_CLE266)) {
605 viaparinfo->
606 lvds_setting_info->iga_path = IGA2;
607 viaparinfo->
608 crt_setting_info->iga_path = IGA1;
609 viaparinfo->
610 tmds_setting_info->iga_path = IGA1;
611 } else
612 viaparinfo->
613 lvds_setting_info->iga_path = IGA1;
614 } else {
615 viaparinfo->lvds_setting_info->iga_path = IGA2;
616 }
617 }
618 if (viafb_LCD2_ON) {
619 if (LCD2_Device == viafb_primary_dev)
620 viaparinfo->lvds_setting_info2->iga_path = IGA1;
621 else
622 viaparinfo->lvds_setting_info2->iga_path = IGA2;
623 }
624 } else {
625 viafb_SAMM_ON = 0;
626
627 if (viafb_CRT_ON && viafb_LCD_ON) {
628 viaparinfo->crt_setting_info->iga_path = IGA1;
629 viaparinfo->lvds_setting_info->iga_path = IGA2;
630 } else if (viafb_CRT_ON && viafb_DVI_ON) {
631 viaparinfo->crt_setting_info->iga_path = IGA1;
632 viaparinfo->tmds_setting_info->iga_path = IGA2;
633 } else if (viafb_LCD_ON && viafb_DVI_ON) {
634 viaparinfo->tmds_setting_info->iga_path = IGA1;
635 viaparinfo->lvds_setting_info->iga_path = IGA2;
636 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
637 viaparinfo->lvds_setting_info->iga_path = IGA2;
638 viaparinfo->lvds_setting_info2->iga_path = IGA2;
639 } else if (viafb_CRT_ON) {
640 viaparinfo->crt_setting_info->iga_path = IGA1;
641 } else if (viafb_LCD_ON) {
642 viaparinfo->lvds_setting_info->iga_path = IGA2;
643 } else if (viafb_DVI_ON) {
644 viaparinfo->tmds_setting_info->iga_path = IGA1;
645 }
646 }
647 }
648
649 void viafb_set_primary_address(u32 addr)
650 {
651 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
652 viafb_write_reg(CR0D, VIACR, addr & 0xFF);
653 viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
654 viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
655 viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
656 }
657
658 void viafb_set_secondary_address(u32 addr)
659 {
660 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
661 /* secondary display supports only quadword aligned memory */
662 viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
663 viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
664 viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
665 viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
666 }
667
668 void viafb_set_primary_pitch(u32 pitch)
669 {
670 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
671 /* spec does not say that first adapter skips 3 bits but old
672 * code did it and seems to be reasonable in analogy to 2nd adapter
673 */
674 pitch = pitch >> 3;
675 viafb_write_reg(0x13, VIACR, pitch & 0xFF);
676 viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
677 }
678
679 void viafb_set_secondary_pitch(u32 pitch)
680 {
681 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
682 pitch = pitch >> 3;
683 viafb_write_reg(0x66, VIACR, pitch & 0xFF);
684 viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
685 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
686 }
687
688 void viafb_set_primary_color_depth(u8 depth)
689 {
690 u8 value;
691
692 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
693 switch (depth) {
694 case 8:
695 value = 0x00;
696 break;
697 case 16:
698 value = 0x14;
699 break;
700 case 24:
701 value = 0x0C;
702 break;
703 default:
704 printk(KERN_WARNING "viafb_set_primary_color_depth: "
705 "Unsupported depth: %d\n", depth);
706 return;
707 }
708
709 viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
710 }
711
712 void viafb_set_secondary_color_depth(u8 depth)
713 {
714 u8 value;
715
716 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
717 switch (depth) {
718 case 8:
719 value = 0x00;
720 break;
721 case 16:
722 value = 0x40;
723 break;
724 case 24:
725 value = 0xC0;
726 break;
727 default:
728 printk(KERN_WARNING "viafb_set_secondary_color_depth: "
729 "Unsupported depth: %d\n", depth);
730 return;
731 }
732
733 viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
734 }
735
736 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
737 {
738 outb(0xFF, 0x3C6); /* bit mask of palette */
739 outb(index, 0x3C8);
740 outb(red, 0x3C9);
741 outb(green, 0x3C9);
742 outb(blue, 0x3C9);
743 }
744
745 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
746 {
747 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
748 set_color_register(index, red, green, blue);
749 }
750
751 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
752 {
753 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
754 set_color_register(index, red, green, blue);
755 }
756
757 void viafb_set_output_path(int device, int set_iga, int output_interface)
758 {
759 switch (device) {
760 case DEVICE_CRT:
761 set_crt_output_path(set_iga);
762 break;
763 case DEVICE_DVI:
764 set_dvi_output_path(set_iga, output_interface);
765 break;
766 case DEVICE_LCD:
767 set_lcd_output_path(set_iga, output_interface);
768 break;
769 }
770 }
771
772 static void set_crt_output_path(int set_iga)
773 {
774 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
775
776 switch (set_iga) {
777 case IGA1:
778 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
779 break;
780 case IGA2:
781 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
782 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
783 break;
784 }
785 }
786
787 static void dvi_patch_skew_dvp0(void)
788 {
789 /* Reset data driving first: */
790 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
791 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
792
793 switch (viaparinfo->chip_info->gfx_chip_name) {
794 case UNICHROME_P4M890:
795 {
796 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
797 (viaparinfo->tmds_setting_info->v_active ==
798 1200))
799 viafb_write_reg_mask(CR96, VIACR, 0x03,
800 BIT0 + BIT1 + BIT2);
801 else
802 viafb_write_reg_mask(CR96, VIACR, 0x07,
803 BIT0 + BIT1 + BIT2);
804 break;
805 }
806
807 case UNICHROME_P4M900:
808 {
809 viafb_write_reg_mask(CR96, VIACR, 0x07,
810 BIT0 + BIT1 + BIT2 + BIT3);
811 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
812 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
813 break;
814 }
815
816 default:
817 {
818 break;
819 }
820 }
821 }
822
823 static void dvi_patch_skew_dvp1(void)
824 {
825 switch (viaparinfo->chip_info->gfx_chip_name) {
826 case UNICHROME_CX700:
827 {
828 break;
829 }
830
831 default:
832 {
833 break;
834 }
835 }
836 }
837
838 static void dvi_patch_skew_dvp_low(void)
839 {
840 switch (viaparinfo->chip_info->gfx_chip_name) {
841 case UNICHROME_K8M890:
842 {
843 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
844 break;
845 }
846
847 case UNICHROME_P4M900:
848 {
849 viafb_write_reg_mask(CR99, VIACR, 0x08,
850 BIT0 + BIT1 + BIT2 + BIT3);
851 break;
852 }
853
854 case UNICHROME_P4M890:
855 {
856 viafb_write_reg_mask(CR99, VIACR, 0x0F,
857 BIT0 + BIT1 + BIT2 + BIT3);
858 break;
859 }
860
861 default:
862 {
863 break;
864 }
865 }
866 }
867
868 static void set_dvi_output_path(int set_iga, int output_interface)
869 {
870 switch (output_interface) {
871 case INTERFACE_DVP0:
872 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
873
874 if (set_iga == IGA1) {
875 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
876 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
877 BIT5 + BIT7);
878 } else {
879 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
880 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
881 BIT5 + BIT7);
882 }
883
884 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
885
886 dvi_patch_skew_dvp0();
887 break;
888
889 case INTERFACE_DVP1:
890 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
891 if (set_iga == IGA1)
892 viafb_write_reg_mask(CR93, VIACR, 0x21,
893 BIT0 + BIT5 + BIT7);
894 else
895 viafb_write_reg_mask(CR93, VIACR, 0xA1,
896 BIT0 + BIT5 + BIT7);
897 } else {
898 if (set_iga == IGA1)
899 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
900 else
901 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
902 }
903
904 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
905 dvi_patch_skew_dvp1();
906 break;
907 case INTERFACE_DFP_HIGH:
908 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
909 if (set_iga == IGA1) {
910 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
911 viafb_write_reg_mask(CR97, VIACR, 0x03,
912 BIT0 + BIT1 + BIT4);
913 } else {
914 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
915 viafb_write_reg_mask(CR97, VIACR, 0x13,
916 BIT0 + BIT1 + BIT4);
917 }
918 }
919 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
920 break;
921
922 case INTERFACE_DFP_LOW:
923 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
924 break;
925
926 if (set_iga == IGA1) {
927 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
928 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
929 } else {
930 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
931 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
932 }
933
934 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
935 dvi_patch_skew_dvp_low();
936 break;
937
938 case INTERFACE_TMDS:
939 if (set_iga == IGA1)
940 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
941 else
942 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
943 break;
944 }
945
946 if (set_iga == IGA2) {
947 enable_second_display_channel();
948 /* Disable LCD Scaling */
949 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
950 }
951 }
952
953 static void set_lcd_output_path(int set_iga, int output_interface)
954 {
955 DEBUG_MSG(KERN_INFO
956 "set_lcd_output_path, iga:%d,out_interface:%d\n",
957 set_iga, output_interface);
958 switch (set_iga) {
959 case IGA1:
960 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
961 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
962
963 disable_second_display_channel();
964 break;
965
966 case IGA2:
967 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
968 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
969
970 enable_second_display_channel();
971 break;
972 }
973
974 switch (output_interface) {
975 case INTERFACE_DVP0:
976 if (set_iga == IGA1) {
977 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
978 } else {
979 viafb_write_reg(CR91, VIACR, 0x00);
980 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
981 }
982 break;
983
984 case INTERFACE_DVP1:
985 if (set_iga == IGA1)
986 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
987 else {
988 viafb_write_reg(CR91, VIACR, 0x00);
989 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
990 }
991 break;
992
993 case INTERFACE_DFP_HIGH:
994 if (set_iga == IGA1)
995 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
996 else {
997 viafb_write_reg(CR91, VIACR, 0x00);
998 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
999 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
1000 }
1001 break;
1002
1003 case INTERFACE_DFP_LOW:
1004 if (set_iga == IGA1)
1005 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1006 else {
1007 viafb_write_reg(CR91, VIACR, 0x00);
1008 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1009 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
1010 }
1011
1012 break;
1013
1014 case INTERFACE_DFP:
1015 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
1016 || (UNICHROME_P4M890 ==
1017 viaparinfo->chip_info->gfx_chip_name))
1018 viafb_write_reg_mask(CR97, VIACR, 0x84,
1019 BIT7 + BIT2 + BIT1 + BIT0);
1020 if (set_iga == IGA1) {
1021 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1022 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1023 } else {
1024 viafb_write_reg(CR91, VIACR, 0x00);
1025 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1026 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1027 }
1028 break;
1029
1030 case INTERFACE_LVDS0:
1031 case INTERFACE_LVDS0LVDS1:
1032 if (set_iga == IGA1)
1033 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1034 else
1035 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1036
1037 break;
1038
1039 case INTERFACE_LVDS1:
1040 if (set_iga == IGA1)
1041 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1042 else
1043 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1044 break;
1045 }
1046 }
1047
1048 static void load_fix_bit_crtc_reg(void)
1049 {
1050 /* always set to 1 */
1051 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1052 /* line compare should set all bits = 1 (extend modes) */
1053 viafb_write_reg(CR18, VIACR, 0xff);
1054 /* line compare should set all bits = 1 (extend modes) */
1055 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1056 /* line compare should set all bits = 1 (extend modes) */
1057 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1058 /* line compare should set all bits = 1 (extend modes) */
1059 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1060 /* line compare should set all bits = 1 (extend modes) */
1061 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1062 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1063 /* extend mode always set to e3h */
1064 viafb_write_reg(CR17, VIACR, 0xe3);
1065 /* extend mode always set to 0h */
1066 viafb_write_reg(CR08, VIACR, 0x00);
1067 /* extend mode always set to 0h */
1068 viafb_write_reg(CR14, VIACR, 0x00);
1069
1070 /* If K8M800, enable Prefetch Mode. */
1071 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1072 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1073 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1074 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1075 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1076 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1077
1078 }
1079
1080 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1081 struct io_register *reg,
1082 int io_type)
1083 {
1084 int reg_mask;
1085 int bit_num = 0;
1086 int data;
1087 int i, j;
1088 int shift_next_reg;
1089 int start_index, end_index, cr_index;
1090 u16 get_bit;
1091
1092 for (i = 0; i < viafb_load_reg_num; i++) {
1093 reg_mask = 0;
1094 data = 0;
1095 start_index = reg[i].start_bit;
1096 end_index = reg[i].end_bit;
1097 cr_index = reg[i].io_addr;
1098
1099 shift_next_reg = bit_num;
1100 for (j = start_index; j <= end_index; j++) {
1101 /*if (bit_num==8) timing_value = timing_value >>8; */
1102 reg_mask = reg_mask | (BIT0 << j);
1103 get_bit = (timing_value & (BIT0 << bit_num));
1104 data =
1105 data | ((get_bit >> shift_next_reg) << start_index);
1106 bit_num++;
1107 }
1108 if (io_type == VIACR)
1109 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1110 else
1111 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1112 }
1113
1114 }
1115
1116 /* Write Registers */
1117 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1118 {
1119 int i;
1120 unsigned char RegTemp;
1121
1122 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1123
1124 for (i = 0; i < ItemNum; i++) {
1125 outb(RegTable[i].index, RegTable[i].port);
1126 RegTemp = inb(RegTable[i].port + 1);
1127 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1128 outb(RegTemp, RegTable[i].port + 1);
1129 }
1130 }
1131
1132 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1133 {
1134 int reg_value;
1135 int viafb_load_reg_num;
1136 struct io_register *reg = NULL;
1137
1138 switch (set_iga) {
1139 case IGA1:
1140 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1141 viafb_load_reg_num = fetch_count_reg.
1142 iga1_fetch_count_reg.reg_num;
1143 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1144 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1145 break;
1146 case IGA2:
1147 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1148 viafb_load_reg_num = fetch_count_reg.
1149 iga2_fetch_count_reg.reg_num;
1150 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1151 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1152 break;
1153 }
1154
1155 }
1156
1157 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1158 {
1159 int reg_value;
1160 int viafb_load_reg_num;
1161 struct io_register *reg = NULL;
1162 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1163 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1164 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1165 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1166
1167 if (set_iga == IGA1) {
1168 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1169 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1170 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1171 iga1_fifo_high_threshold =
1172 K800_IGA1_FIFO_HIGH_THRESHOLD;
1173 /* If resolution > 1280x1024, expire length = 64, else
1174 expire length = 128 */
1175 if ((hor_active > 1280) && (ver_active > 1024))
1176 iga1_display_queue_expire_num = 16;
1177 else
1178 iga1_display_queue_expire_num =
1179 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1180
1181 }
1182
1183 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1184 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1185 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1186 iga1_fifo_high_threshold =
1187 P880_IGA1_FIFO_HIGH_THRESHOLD;
1188 iga1_display_queue_expire_num =
1189 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1190
1191 /* If resolution > 1280x1024, expire length = 64, else
1192 expire length = 128 */
1193 if ((hor_active > 1280) && (ver_active > 1024))
1194 iga1_display_queue_expire_num = 16;
1195 else
1196 iga1_display_queue_expire_num =
1197 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1198 }
1199
1200 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1201 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1202 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1203 iga1_fifo_high_threshold =
1204 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1205
1206 /* If resolution > 1280x1024, expire length = 64,
1207 else expire length = 128 */
1208 if ((hor_active > 1280) && (ver_active > 1024))
1209 iga1_display_queue_expire_num = 16;
1210 else
1211 iga1_display_queue_expire_num =
1212 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1213 }
1214
1215 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1216 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1217 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1218 iga1_fifo_high_threshold =
1219 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1220 iga1_display_queue_expire_num =
1221 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1222 }
1223
1224 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1225 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1226 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1227 iga1_fifo_high_threshold =
1228 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1229 iga1_display_queue_expire_num =
1230 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1231 }
1232
1233 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1234 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1235 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1236 iga1_fifo_high_threshold =
1237 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1238 iga1_display_queue_expire_num =
1239 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1240 }
1241
1242 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1243 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1244 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1245 iga1_fifo_high_threshold =
1246 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1247 iga1_display_queue_expire_num =
1248 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1249 }
1250
1251 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1252 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1253 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1254 iga1_fifo_high_threshold =
1255 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1256 iga1_display_queue_expire_num =
1257 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1258 }
1259
1260 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1261 iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1262 iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1263 iga1_fifo_high_threshold =
1264 VX855_IGA1_FIFO_HIGH_THRESHOLD;
1265 iga1_display_queue_expire_num =
1266 VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1267 }
1268
1269 /* Set Display FIFO Depath Select */
1270 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1271 viafb_load_reg_num =
1272 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1273 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1274 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1275
1276 /* Set Display FIFO Threshold Select */
1277 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1278 viafb_load_reg_num =
1279 fifo_threshold_select_reg.
1280 iga1_fifo_threshold_select_reg.reg_num;
1281 reg =
1282 fifo_threshold_select_reg.
1283 iga1_fifo_threshold_select_reg.reg;
1284 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1285
1286 /* Set FIFO High Threshold Select */
1287 reg_value =
1288 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1289 viafb_load_reg_num =
1290 fifo_high_threshold_select_reg.
1291 iga1_fifo_high_threshold_select_reg.reg_num;
1292 reg =
1293 fifo_high_threshold_select_reg.
1294 iga1_fifo_high_threshold_select_reg.reg;
1295 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1296
1297 /* Set Display Queue Expire Num */
1298 reg_value =
1299 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1300 (iga1_display_queue_expire_num);
1301 viafb_load_reg_num =
1302 display_queue_expire_num_reg.
1303 iga1_display_queue_expire_num_reg.reg_num;
1304 reg =
1305 display_queue_expire_num_reg.
1306 iga1_display_queue_expire_num_reg.reg;
1307 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1308
1309 } else {
1310 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1311 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1312 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1313 iga2_fifo_high_threshold =
1314 K800_IGA2_FIFO_HIGH_THRESHOLD;
1315
1316 /* If resolution > 1280x1024, expire length = 64,
1317 else expire length = 128 */
1318 if ((hor_active > 1280) && (ver_active > 1024))
1319 iga2_display_queue_expire_num = 16;
1320 else
1321 iga2_display_queue_expire_num =
1322 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1323 }
1324
1325 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1326 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1327 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1328 iga2_fifo_high_threshold =
1329 P880_IGA2_FIFO_HIGH_THRESHOLD;
1330
1331 /* If resolution > 1280x1024, expire length = 64,
1332 else expire length = 128 */
1333 if ((hor_active > 1280) && (ver_active > 1024))
1334 iga2_display_queue_expire_num = 16;
1335 else
1336 iga2_display_queue_expire_num =
1337 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1338 }
1339
1340 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1341 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1342 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1343 iga2_fifo_high_threshold =
1344 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1345
1346 /* If resolution > 1280x1024, expire length = 64,
1347 else expire length = 128 */
1348 if ((hor_active > 1280) && (ver_active > 1024))
1349 iga2_display_queue_expire_num = 16;
1350 else
1351 iga2_display_queue_expire_num =
1352 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1353 }
1354
1355 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1356 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1357 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1358 iga2_fifo_high_threshold =
1359 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1360 iga2_display_queue_expire_num =
1361 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1362 }
1363
1364 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1365 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1366 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1367 iga2_fifo_high_threshold =
1368 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1369 iga2_display_queue_expire_num =
1370 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1371 }
1372
1373 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1374 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1375 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1376 iga2_fifo_high_threshold =
1377 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1378 iga2_display_queue_expire_num =
1379 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1380 }
1381
1382 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1383 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1384 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1385 iga2_fifo_high_threshold =
1386 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1387 iga2_display_queue_expire_num =
1388 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1389 }
1390
1391 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1392 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1393 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1394 iga2_fifo_high_threshold =
1395 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1396 iga2_display_queue_expire_num =
1397 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1398 }
1399
1400 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1401 iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1402 iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1403 iga2_fifo_high_threshold =
1404 VX855_IGA2_FIFO_HIGH_THRESHOLD;
1405 iga2_display_queue_expire_num =
1406 VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1407 }
1408
1409 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1410 /* Set Display FIFO Depath Select */
1411 reg_value =
1412 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1413 - 1;
1414 /* Patch LCD in IGA2 case */
1415 viafb_load_reg_num =
1416 display_fifo_depth_reg.
1417 iga2_fifo_depth_select_reg.reg_num;
1418 reg =
1419 display_fifo_depth_reg.
1420 iga2_fifo_depth_select_reg.reg;
1421 viafb_load_reg(reg_value,
1422 viafb_load_reg_num, reg, VIACR);
1423 } else {
1424
1425 /* Set Display FIFO Depath Select */
1426 reg_value =
1427 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1428 viafb_load_reg_num =
1429 display_fifo_depth_reg.
1430 iga2_fifo_depth_select_reg.reg_num;
1431 reg =
1432 display_fifo_depth_reg.
1433 iga2_fifo_depth_select_reg.reg;
1434 viafb_load_reg(reg_value,
1435 viafb_load_reg_num, reg, VIACR);
1436 }
1437
1438 /* Set Display FIFO Threshold Select */
1439 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1440 viafb_load_reg_num =
1441 fifo_threshold_select_reg.
1442 iga2_fifo_threshold_select_reg.reg_num;
1443 reg =
1444 fifo_threshold_select_reg.
1445 iga2_fifo_threshold_select_reg.reg;
1446 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1447
1448 /* Set FIFO High Threshold Select */
1449 reg_value =
1450 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1451 viafb_load_reg_num =
1452 fifo_high_threshold_select_reg.
1453 iga2_fifo_high_threshold_select_reg.reg_num;
1454 reg =
1455 fifo_high_threshold_select_reg.
1456 iga2_fifo_high_threshold_select_reg.reg;
1457 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1458
1459 /* Set Display Queue Expire Num */
1460 reg_value =
1461 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1462 (iga2_display_queue_expire_num);
1463 viafb_load_reg_num =
1464 display_queue_expire_num_reg.
1465 iga2_display_queue_expire_num_reg.reg_num;
1466 reg =
1467 display_queue_expire_num_reg.
1468 iga2_display_queue_expire_num_reg.reg;
1469 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1470
1471 }
1472
1473 }
1474
1475 u32 viafb_get_clk_value(int clk)
1476 {
1477 int i;
1478
1479 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1480 if (clk == pll_value[i].clk) {
1481 switch (viaparinfo->chip_info->gfx_chip_name) {
1482 case UNICHROME_CLE266:
1483 case UNICHROME_K400:
1484 return pll_value[i].cle266_pll;
1485
1486 case UNICHROME_K800:
1487 case UNICHROME_PM800:
1488 case UNICHROME_CN700:
1489 return pll_value[i].k800_pll;
1490
1491 case UNICHROME_CX700:
1492 case UNICHROME_K8M890:
1493 case UNICHROME_P4M890:
1494 case UNICHROME_P4M900:
1495 case UNICHROME_VX800:
1496 return pll_value[i].cx700_pll;
1497 case UNICHROME_VX855:
1498 return pll_value[i].vx855_pll;
1499 }
1500 }
1501 }
1502
1503 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1504 return 0;
1505 }
1506
1507 /* Set VCLK*/
1508 void viafb_set_vclock(u32 CLK, int set_iga)
1509 {
1510 unsigned char RegTemp;
1511
1512 /* H.W. Reset : ON */
1513 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1514
1515 if (set_iga == IGA1) {
1516 /* Change D,N FOR VCLK */
1517 switch (viaparinfo->chip_info->gfx_chip_name) {
1518 case UNICHROME_CLE266:
1519 case UNICHROME_K400:
1520 viafb_write_reg(SR46, VIASR, CLK / 0x100);
1521 viafb_write_reg(SR47, VIASR, CLK % 0x100);
1522 break;
1523
1524 case UNICHROME_K800:
1525 case UNICHROME_PM800:
1526 case UNICHROME_CN700:
1527 case UNICHROME_CX700:
1528 case UNICHROME_K8M890:
1529 case UNICHROME_P4M890:
1530 case UNICHROME_P4M900:
1531 case UNICHROME_VX800:
1532 case UNICHROME_VX855:
1533 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1534 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1535 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1536 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1537 (CLK & 0xFFFF) / 0x100);
1538 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1539 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1540 break;
1541 }
1542 }
1543
1544 if (set_iga == IGA2) {
1545 /* Change D,N FOR LCK */
1546 switch (viaparinfo->chip_info->gfx_chip_name) {
1547 case UNICHROME_CLE266:
1548 case UNICHROME_K400:
1549 viafb_write_reg(SR44, VIASR, CLK / 0x100);
1550 viafb_write_reg(SR45, VIASR, CLK % 0x100);
1551 break;
1552
1553 case UNICHROME_K800:
1554 case UNICHROME_PM800:
1555 case UNICHROME_CN700:
1556 case UNICHROME_CX700:
1557 case UNICHROME_K8M890:
1558 case UNICHROME_P4M890:
1559 case UNICHROME_P4M900:
1560 case UNICHROME_VX800:
1561 case UNICHROME_VX855:
1562 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1563 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1564 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1565 break;
1566 }
1567 }
1568
1569 /* H.W. Reset : OFF */
1570 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1571
1572 /* Reset PLL */
1573 if (set_iga == IGA1) {
1574 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1575 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1576 }
1577
1578 if (set_iga == IGA2) {
1579 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1580 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1581 }
1582
1583 /* Fire! */
1584 RegTemp = inb(VIARMisc);
1585 outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1586 }
1587
1588 void viafb_load_crtc_timing(struct display_timing device_timing,
1589 int set_iga)
1590 {
1591 int i;
1592 int viafb_load_reg_num = 0;
1593 int reg_value = 0;
1594 struct io_register *reg = NULL;
1595
1596 viafb_unlock_crt();
1597
1598 for (i = 0; i < 12; i++) {
1599 if (set_iga == IGA1) {
1600 switch (i) {
1601 case H_TOTAL_INDEX:
1602 reg_value =
1603 IGA1_HOR_TOTAL_FORMULA(device_timing.
1604 hor_total);
1605 viafb_load_reg_num =
1606 iga1_crtc_reg.hor_total.reg_num;
1607 reg = iga1_crtc_reg.hor_total.reg;
1608 break;
1609 case H_ADDR_INDEX:
1610 reg_value =
1611 IGA1_HOR_ADDR_FORMULA(device_timing.
1612 hor_addr);
1613 viafb_load_reg_num =
1614 iga1_crtc_reg.hor_addr.reg_num;
1615 reg = iga1_crtc_reg.hor_addr.reg;
1616 break;
1617 case H_BLANK_START_INDEX:
1618 reg_value =
1619 IGA1_HOR_BLANK_START_FORMULA
1620 (device_timing.hor_blank_start);
1621 viafb_load_reg_num =
1622 iga1_crtc_reg.hor_blank_start.reg_num;
1623 reg = iga1_crtc_reg.hor_blank_start.reg;
1624 break;
1625 case H_BLANK_END_INDEX:
1626 reg_value =
1627 IGA1_HOR_BLANK_END_FORMULA
1628 (device_timing.hor_blank_start,
1629 device_timing.hor_blank_end);
1630 viafb_load_reg_num =
1631 iga1_crtc_reg.hor_blank_end.reg_num;
1632 reg = iga1_crtc_reg.hor_blank_end.reg;
1633 break;
1634 case H_SYNC_START_INDEX:
1635 reg_value =
1636 IGA1_HOR_SYNC_START_FORMULA
1637 (device_timing.hor_sync_start);
1638 viafb_load_reg_num =
1639 iga1_crtc_reg.hor_sync_start.reg_num;
1640 reg = iga1_crtc_reg.hor_sync_start.reg;
1641 break;
1642 case H_SYNC_END_INDEX:
1643 reg_value =
1644 IGA1_HOR_SYNC_END_FORMULA
1645 (device_timing.hor_sync_start,
1646 device_timing.hor_sync_end);
1647 viafb_load_reg_num =
1648 iga1_crtc_reg.hor_sync_end.reg_num;
1649 reg = iga1_crtc_reg.hor_sync_end.reg;
1650 break;
1651 case V_TOTAL_INDEX:
1652 reg_value =
1653 IGA1_VER_TOTAL_FORMULA(device_timing.
1654 ver_total);
1655 viafb_load_reg_num =
1656 iga1_crtc_reg.ver_total.reg_num;
1657 reg = iga1_crtc_reg.ver_total.reg;
1658 break;
1659 case V_ADDR_INDEX:
1660 reg_value =
1661 IGA1_VER_ADDR_FORMULA(device_timing.
1662 ver_addr);
1663 viafb_load_reg_num =
1664 iga1_crtc_reg.ver_addr.reg_num;
1665 reg = iga1_crtc_reg.ver_addr.reg;
1666 break;
1667 case V_BLANK_START_INDEX:
1668 reg_value =
1669 IGA1_VER_BLANK_START_FORMULA
1670 (device_timing.ver_blank_start);
1671 viafb_load_reg_num =
1672 iga1_crtc_reg.ver_blank_start.reg_num;
1673 reg = iga1_crtc_reg.ver_blank_start.reg;
1674 break;
1675 case V_BLANK_END_INDEX:
1676 reg_value =
1677 IGA1_VER_BLANK_END_FORMULA
1678 (device_timing.ver_blank_start,
1679 device_timing.ver_blank_end);
1680 viafb_load_reg_num =
1681 iga1_crtc_reg.ver_blank_end.reg_num;
1682 reg = iga1_crtc_reg.ver_blank_end.reg;
1683 break;
1684 case V_SYNC_START_INDEX:
1685 reg_value =
1686 IGA1_VER_SYNC_START_FORMULA
1687 (device_timing.ver_sync_start);
1688 viafb_load_reg_num =
1689 iga1_crtc_reg.ver_sync_start.reg_num;
1690 reg = iga1_crtc_reg.ver_sync_start.reg;
1691 break;
1692 case V_SYNC_END_INDEX:
1693 reg_value =
1694 IGA1_VER_SYNC_END_FORMULA
1695 (device_timing.ver_sync_start,
1696 device_timing.ver_sync_end);
1697 viafb_load_reg_num =
1698 iga1_crtc_reg.ver_sync_end.reg_num;
1699 reg = iga1_crtc_reg.ver_sync_end.reg;
1700 break;
1701
1702 }
1703 }
1704
1705 if (set_iga == IGA2) {
1706 switch (i) {
1707 case H_TOTAL_INDEX:
1708 reg_value =
1709 IGA2_HOR_TOTAL_FORMULA(device_timing.
1710 hor_total);
1711 viafb_load_reg_num =
1712 iga2_crtc_reg.hor_total.reg_num;
1713 reg = iga2_crtc_reg.hor_total.reg;
1714 break;
1715 case H_ADDR_INDEX:
1716 reg_value =
1717 IGA2_HOR_ADDR_FORMULA(device_timing.
1718 hor_addr);
1719 viafb_load_reg_num =
1720 iga2_crtc_reg.hor_addr.reg_num;
1721 reg = iga2_crtc_reg.hor_addr.reg;
1722 break;
1723 case H_BLANK_START_INDEX:
1724 reg_value =
1725 IGA2_HOR_BLANK_START_FORMULA
1726 (device_timing.hor_blank_start);
1727 viafb_load_reg_num =
1728 iga2_crtc_reg.hor_blank_start.reg_num;
1729 reg = iga2_crtc_reg.hor_blank_start.reg;
1730 break;
1731 case H_BLANK_END_INDEX:
1732 reg_value =
1733 IGA2_HOR_BLANK_END_FORMULA
1734 (device_timing.hor_blank_start,
1735 device_timing.hor_blank_end);
1736 viafb_load_reg_num =
1737 iga2_crtc_reg.hor_blank_end.reg_num;
1738 reg = iga2_crtc_reg.hor_blank_end.reg;
1739 break;
1740 case H_SYNC_START_INDEX:
1741 reg_value =
1742 IGA2_HOR_SYNC_START_FORMULA
1743 (device_timing.hor_sync_start);
1744 if (UNICHROME_CN700 <=
1745 viaparinfo->chip_info->gfx_chip_name)
1746 viafb_load_reg_num =
1747 iga2_crtc_reg.hor_sync_start.
1748 reg_num;
1749 else
1750 viafb_load_reg_num = 3;
1751 reg = iga2_crtc_reg.hor_sync_start.reg;
1752 break;
1753 case H_SYNC_END_INDEX:
1754 reg_value =
1755 IGA2_HOR_SYNC_END_FORMULA
1756 (device_timing.hor_sync_start,
1757 device_timing.hor_sync_end);
1758 viafb_load_reg_num =
1759 iga2_crtc_reg.hor_sync_end.reg_num;
1760 reg = iga2_crtc_reg.hor_sync_end.reg;
1761 break;
1762 case V_TOTAL_INDEX:
1763 reg_value =
1764 IGA2_VER_TOTAL_FORMULA(device_timing.
1765 ver_total);
1766 viafb_load_reg_num =
1767 iga2_crtc_reg.ver_total.reg_num;
1768 reg = iga2_crtc_reg.ver_total.reg;
1769 break;
1770 case V_ADDR_INDEX:
1771 reg_value =
1772 IGA2_VER_ADDR_FORMULA(device_timing.
1773 ver_addr);
1774 viafb_load_reg_num =
1775 iga2_crtc_reg.ver_addr.reg_num;
1776 reg = iga2_crtc_reg.ver_addr.reg;
1777 break;
1778 case V_BLANK_START_INDEX:
1779 reg_value =
1780 IGA2_VER_BLANK_START_FORMULA
1781 (device_timing.ver_blank_start);
1782 viafb_load_reg_num =
1783 iga2_crtc_reg.ver_blank_start.reg_num;
1784 reg = iga2_crtc_reg.ver_blank_start.reg;
1785 break;
1786 case V_BLANK_END_INDEX:
1787 reg_value =
1788 IGA2_VER_BLANK_END_FORMULA
1789 (device_timing.ver_blank_start,
1790 device_timing.ver_blank_end);
1791 viafb_load_reg_num =
1792 iga2_crtc_reg.ver_blank_end.reg_num;
1793 reg = iga2_crtc_reg.ver_blank_end.reg;
1794 break;
1795 case V_SYNC_START_INDEX:
1796 reg_value =
1797 IGA2_VER_SYNC_START_FORMULA
1798 (device_timing.ver_sync_start);
1799 viafb_load_reg_num =
1800 iga2_crtc_reg.ver_sync_start.reg_num;
1801 reg = iga2_crtc_reg.ver_sync_start.reg;
1802 break;
1803 case V_SYNC_END_INDEX:
1804 reg_value =
1805 IGA2_VER_SYNC_END_FORMULA
1806 (device_timing.ver_sync_start,
1807 device_timing.ver_sync_end);
1808 viafb_load_reg_num =
1809 iga2_crtc_reg.ver_sync_end.reg_num;
1810 reg = iga2_crtc_reg.ver_sync_end.reg;
1811 break;
1812
1813 }
1814 }
1815 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1816 }
1817
1818 viafb_lock_crt();
1819 }
1820
1821 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1822 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1823 {
1824 struct display_timing crt_reg;
1825 int i;
1826 int index = 0;
1827 int h_addr, v_addr;
1828 u32 pll_D_N;
1829
1830 for (i = 0; i < video_mode->mode_array; i++) {
1831 index = i;
1832
1833 if (crt_table[i].refresh_rate == viaparinfo->
1834 crt_setting_info->refresh_rate)
1835 break;
1836 }
1837
1838 crt_reg = crt_table[index].crtc;
1839
1840 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1841 /* So we would delete border. */
1842 if ((viafb_LCD_ON | viafb_DVI_ON)
1843 && video_mode->crtc[0].crtc.hor_addr == 640
1844 && video_mode->crtc[0].crtc.ver_addr == 480
1845 && viaparinfo->crt_setting_info->refresh_rate == 60) {
1846 /* The border is 8 pixels. */
1847 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1848
1849 /* Blanking time should add left and right borders. */
1850 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1851 }
1852
1853 h_addr = crt_reg.hor_addr;
1854 v_addr = crt_reg.ver_addr;
1855
1856 /* update polarity for CRT timing */
1857 if (crt_table[index].h_sync_polarity == NEGATIVE) {
1858 if (crt_table[index].v_sync_polarity == NEGATIVE)
1859 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1860 (BIT6 + BIT7), VIAWMisc);
1861 else
1862 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1863 VIAWMisc);
1864 } else {
1865 if (crt_table[index].v_sync_polarity == NEGATIVE)
1866 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1867 VIAWMisc);
1868 else
1869 outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1870 }
1871
1872 if (set_iga == IGA1) {
1873 viafb_unlock_crt();
1874 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1875 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1876 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1877 }
1878
1879 switch (set_iga) {
1880 case IGA1:
1881 viafb_load_crtc_timing(crt_reg, IGA1);
1882 break;
1883 case IGA2:
1884 viafb_load_crtc_timing(crt_reg, IGA2);
1885 break;
1886 }
1887
1888 load_fix_bit_crtc_reg();
1889 viafb_lock_crt();
1890 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1891 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1892
1893 /* load FIFO */
1894 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1895 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1896 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1897
1898 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1899 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1900 viafb_set_vclock(pll_D_N, set_iga);
1901
1902 }
1903
1904 void viafb_init_chip_info(struct pci_dev *pdev,
1905 const struct pci_device_id *pdi)
1906 {
1907 init_gfx_chip_info(pdev, pdi);
1908 init_tmds_chip_info();
1909 init_lvds_chip_info();
1910
1911 viaparinfo->crt_setting_info->iga_path = IGA1;
1912 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1913
1914 /*Set IGA path for each device */
1915 viafb_set_iga_path();
1916
1917 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1918 viaparinfo->lvds_setting_info->get_lcd_size_method =
1919 GET_LCD_SIZE_BY_USER_SETTING;
1920 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1921 viaparinfo->lvds_setting_info2->display_method =
1922 viaparinfo->lvds_setting_info->display_method;
1923 viaparinfo->lvds_setting_info2->lcd_mode =
1924 viaparinfo->lvds_setting_info->lcd_mode;
1925 }
1926
1927 void viafb_update_device_setting(int hres, int vres,
1928 int bpp, int vmode_refresh, int flag)
1929 {
1930 if (flag == 0) {
1931 viaparinfo->crt_setting_info->h_active = hres;
1932 viaparinfo->crt_setting_info->v_active = vres;
1933 viaparinfo->crt_setting_info->bpp = bpp;
1934 viaparinfo->crt_setting_info->refresh_rate =
1935 vmode_refresh;
1936
1937 viaparinfo->tmds_setting_info->h_active = hres;
1938 viaparinfo->tmds_setting_info->v_active = vres;
1939
1940 viaparinfo->lvds_setting_info->h_active = hres;
1941 viaparinfo->lvds_setting_info->v_active = vres;
1942 viaparinfo->lvds_setting_info->bpp = bpp;
1943 viaparinfo->lvds_setting_info->refresh_rate =
1944 vmode_refresh;
1945 viaparinfo->lvds_setting_info2->h_active = hres;
1946 viaparinfo->lvds_setting_info2->v_active = vres;
1947 viaparinfo->lvds_setting_info2->bpp = bpp;
1948 viaparinfo->lvds_setting_info2->refresh_rate =
1949 vmode_refresh;
1950 } else {
1951
1952 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1953 viaparinfo->tmds_setting_info->h_active = hres;
1954 viaparinfo->tmds_setting_info->v_active = vres;
1955 }
1956
1957 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1958 viaparinfo->lvds_setting_info->h_active = hres;
1959 viaparinfo->lvds_setting_info->v_active = vres;
1960 viaparinfo->lvds_setting_info->bpp = bpp;
1961 viaparinfo->lvds_setting_info->refresh_rate =
1962 vmode_refresh;
1963 }
1964 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1965 viaparinfo->lvds_setting_info2->h_active = hres;
1966 viaparinfo->lvds_setting_info2->v_active = vres;
1967 viaparinfo->lvds_setting_info2->bpp = bpp;
1968 viaparinfo->lvds_setting_info2->refresh_rate =
1969 vmode_refresh;
1970 }
1971 }
1972 }
1973
1974 static void init_gfx_chip_info(struct pci_dev *pdev,
1975 const struct pci_device_id *pdi)
1976 {
1977 u8 tmp;
1978
1979 viaparinfo->chip_info->gfx_chip_name = pdi->driver_data;
1980
1981 /* Check revision of CLE266 Chip */
1982 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1983 /* CR4F only define in CLE266.CX chip */
1984 tmp = viafb_read_reg(VIACR, CR4F);
1985 viafb_write_reg(CR4F, VIACR, 0x55);
1986 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1987 viaparinfo->chip_info->gfx_chip_revision =
1988 CLE266_REVISION_AX;
1989 else
1990 viaparinfo->chip_info->gfx_chip_revision =
1991 CLE266_REVISION_CX;
1992 /* restore orignal CR4F value */
1993 viafb_write_reg(CR4F, VIACR, tmp);
1994 }
1995
1996 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1997 tmp = viafb_read_reg(VIASR, SR43);
1998 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1999 if (tmp & 0x02) {
2000 viaparinfo->chip_info->gfx_chip_revision =
2001 CX700_REVISION_700M2;
2002 } else if (tmp & 0x40) {
2003 viaparinfo->chip_info->gfx_chip_revision =
2004 CX700_REVISION_700M;
2005 } else {
2006 viaparinfo->chip_info->gfx_chip_revision =
2007 CX700_REVISION_700;
2008 }
2009 }
2010 }
2011
2012 static void init_tmds_chip_info(void)
2013 {
2014 viafb_tmds_trasmitter_identify();
2015
2016 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2017 output_interface) {
2018 switch (viaparinfo->chip_info->gfx_chip_name) {
2019 case UNICHROME_CX700:
2020 {
2021 /* we should check support by hardware layout.*/
2022 if ((viafb_display_hardware_layout ==
2023 HW_LAYOUT_DVI_ONLY)
2024 || (viafb_display_hardware_layout ==
2025 HW_LAYOUT_LCD_DVI)) {
2026 viaparinfo->chip_info->tmds_chip_info.
2027 output_interface = INTERFACE_TMDS;
2028 } else {
2029 viaparinfo->chip_info->tmds_chip_info.
2030 output_interface =
2031 INTERFACE_NONE;
2032 }
2033 break;
2034 }
2035 case UNICHROME_K8M890:
2036 case UNICHROME_P4M900:
2037 case UNICHROME_P4M890:
2038 /* TMDS on PCIE, we set DFPLOW as default. */
2039 viaparinfo->chip_info->tmds_chip_info.output_interface =
2040 INTERFACE_DFP_LOW;
2041 break;
2042 default:
2043 {
2044 /* set DVP1 default for DVI */
2045 viaparinfo->chip_info->tmds_chip_info
2046 .output_interface = INTERFACE_DVP1;
2047 }
2048 }
2049 }
2050
2051 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2052 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2053 viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2054 &viaparinfo->shared->tmds_setting_info);
2055 }
2056
2057 static void init_lvds_chip_info(void)
2058 {
2059 if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2060 viaparinfo->lvds_setting_info->get_lcd_size_method =
2061 GET_LCD_SIZE_BY_VGA_BIOS;
2062 else
2063 viaparinfo->lvds_setting_info->get_lcd_size_method =
2064 GET_LCD_SIZE_BY_USER_SETTING;
2065
2066 viafb_lvds_trasmitter_identify();
2067 viafb_init_lcd_size();
2068 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2069 viaparinfo->lvds_setting_info);
2070 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2071 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2072 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2073 }
2074 /*If CX700,two singel LCD, we need to reassign
2075 LCD interface to different LVDS port */
2076 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2077 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2078 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2079 lvds_chip_name) && (INTEGRATED_LVDS ==
2080 viaparinfo->chip_info->
2081 lvds_chip_info2.lvds_chip_name)) {
2082 viaparinfo->chip_info->lvds_chip_info.output_interface =
2083 INTERFACE_LVDS0;
2084 viaparinfo->chip_info->lvds_chip_info2.
2085 output_interface =
2086 INTERFACE_LVDS1;
2087 }
2088 }
2089
2090 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2091 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2092 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2093 viaparinfo->chip_info->lvds_chip_info.output_interface);
2094 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2095 viaparinfo->chip_info->lvds_chip_info.output_interface);
2096 }
2097
2098 void viafb_init_dac(int set_iga)
2099 {
2100 int i;
2101 u8 tmp;
2102
2103 if (set_iga == IGA1) {
2104 /* access Primary Display's LUT */
2105 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2106 /* turn off LCK */
2107 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2108 for (i = 0; i < 256; i++) {
2109 write_dac_reg(i, palLUT_table[i].red,
2110 palLUT_table[i].green,
2111 palLUT_table[i].blue);
2112 }
2113 /* turn on LCK */
2114 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2115 } else {
2116 tmp = viafb_read_reg(VIACR, CR6A);
2117 /* access Secondary Display's LUT */
2118 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2119 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2120 for (i = 0; i < 256; i++) {
2121 write_dac_reg(i, palLUT_table[i].red,
2122 palLUT_table[i].green,
2123 palLUT_table[i].blue);
2124 }
2125 /* set IGA1 DAC for default */
2126 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2127 viafb_write_reg(CR6A, VIACR, tmp);
2128 }
2129 }
2130
2131 static void device_screen_off(void)
2132 {
2133 /* turn off CRT screen (IGA1) */
2134 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2135 }
2136
2137 static void device_screen_on(void)
2138 {
2139 /* turn on CRT screen (IGA1) */
2140 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2141 }
2142
2143 static void set_display_channel(void)
2144 {
2145 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2146 is keeped on lvds_setting_info2 */
2147 if (viafb_LCD2_ON &&
2148 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2149 /* For dual channel LCD: */
2150 /* Set to Dual LVDS channel. */
2151 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2152 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2153 /* For LCD+DFP: */
2154 /* Set to LVDS1 + TMDS channel. */
2155 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2156 } else if (viafb_DVI_ON) {
2157 /* Set to single TMDS channel. */
2158 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2159 } else if (viafb_LCD_ON) {
2160 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2161 /* For dual channel LCD: */
2162 /* Set to Dual LVDS channel. */
2163 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2164 } else {
2165 /* Set to LVDS0 + LVDS1 channel. */
2166 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2167 }
2168 }
2169 }
2170
2171 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2172 struct VideoModeTable *vmode_tbl1, int video_bpp1)
2173 {
2174 int i, j;
2175 int port;
2176 u8 value, index, mask;
2177 struct crt_mode_table *crt_timing;
2178 struct crt_mode_table *crt_timing1 = NULL;
2179
2180 device_screen_off();
2181 crt_timing = vmode_tbl->crtc;
2182
2183 if (viafb_SAMM_ON == 1) {
2184 crt_timing1 = vmode_tbl1->crtc;
2185 }
2186
2187 inb(VIAStatus);
2188 outb(0x00, VIAAR);
2189
2190 /* Write Common Setting for Video Mode */
2191 switch (viaparinfo->chip_info->gfx_chip_name) {
2192 case UNICHROME_CLE266:
2193 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2194 break;
2195
2196 case UNICHROME_K400:
2197 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2198 break;
2199
2200 case UNICHROME_K800:
2201 case UNICHROME_PM800:
2202 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2203 break;
2204
2205 case UNICHROME_CN700:
2206 case UNICHROME_K8M890:
2207 case UNICHROME_P4M890:
2208 case UNICHROME_P4M900:
2209 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2210 break;
2211
2212 case UNICHROME_CX700:
2213 case UNICHROME_VX800:
2214 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2215 break;
2216
2217 case UNICHROME_VX855:
2218 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2219 break;
2220 }
2221
2222 device_off();
2223
2224 /* Fill VPIT Parameters */
2225 /* Write Misc Register */
2226 outb(VPIT.Misc, VIAWMisc);
2227
2228 /* Write Sequencer */
2229 for (i = 1; i <= StdSR; i++) {
2230 outb(i, VIASR);
2231 outb(VPIT.SR[i - 1], VIASR + 1);
2232 }
2233
2234 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2235 viafb_set_iga_path();
2236
2237 /* Write CRTC */
2238 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2239
2240 /* Write Graphic Controller */
2241 for (i = 0; i < StdGR; i++) {
2242 outb(i, VIAGR);
2243 outb(VPIT.GR[i], VIAGR + 1);
2244 }
2245
2246 /* Write Attribute Controller */
2247 for (i = 0; i < StdAR; i++) {
2248 inb(VIAStatus);
2249 outb(i, VIAAR);
2250 outb(VPIT.AR[i], VIAAR);
2251 }
2252
2253 inb(VIAStatus);
2254 outb(0x20, VIAAR);
2255
2256 /* Update Patch Register */
2257
2258 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2259 || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2260 && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2261 && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2262 for (j = 0; j < res_patch_table[0].table_length; j++) {
2263 index = res_patch_table[0].io_reg_table[j].index;
2264 port = res_patch_table[0].io_reg_table[j].port;
2265 value = res_patch_table[0].io_reg_table[j].value;
2266 mask = res_patch_table[0].io_reg_table[j].mask;
2267 viafb_write_reg_mask(index, port, value, mask);
2268 }
2269 }
2270
2271 viafb_set_primary_pitch(viafbinfo->fix.line_length);
2272 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2273 : viafbinfo->fix.line_length);
2274 viafb_set_primary_color_depth(viaparinfo->depth);
2275 viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2276 : viaparinfo->depth);
2277 /* Update Refresh Rate Setting */
2278
2279 /* Clear On Screen */
2280
2281 /* CRT set mode */
2282 if (viafb_CRT_ON) {
2283 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2284 IGA2)) {
2285 viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2286 video_bpp1 / 8,
2287 viaparinfo->crt_setting_info->iga_path);
2288 } else {
2289 viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2290 video_bpp / 8,
2291 viaparinfo->crt_setting_info->iga_path);
2292 }
2293
2294 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2295
2296 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2297 to 8 alignment (1368),there is several pixels (2 pixels)
2298 on right side of screen. */
2299 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2300 viafb_unlock_crt();
2301 viafb_write_reg(CR02, VIACR,
2302 viafb_read_reg(VIACR, CR02) - 1);
2303 viafb_lock_crt();
2304 }
2305 }
2306
2307 if (viafb_DVI_ON) {
2308 if (viafb_SAMM_ON &&
2309 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2310 viafb_dvi_set_mode(viafb_get_mode
2311 (viaparinfo->tmds_setting_info->h_active,
2312 viaparinfo->tmds_setting_info->
2313 v_active),
2314 video_bpp1, viaparinfo->
2315 tmds_setting_info->iga_path);
2316 } else {
2317 viafb_dvi_set_mode(viafb_get_mode
2318 (viaparinfo->tmds_setting_info->h_active,
2319 viaparinfo->
2320 tmds_setting_info->v_active),
2321 video_bpp, viaparinfo->
2322 tmds_setting_info->iga_path);
2323 }
2324 }
2325
2326 if (viafb_LCD_ON) {
2327 if (viafb_SAMM_ON &&
2328 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2329 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2330 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2331 lvds_setting_info,
2332 &viaparinfo->chip_info->lvds_chip_info);
2333 } else {
2334 /* IGA1 doesn't have LCD scaling, so set it center. */
2335 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2336 viaparinfo->lvds_setting_info->display_method =
2337 LCD_CENTERING;
2338 }
2339 viaparinfo->lvds_setting_info->bpp = video_bpp;
2340 viafb_lcd_set_mode(crt_timing, viaparinfo->
2341 lvds_setting_info,
2342 &viaparinfo->chip_info->lvds_chip_info);
2343 }
2344 }
2345 if (viafb_LCD2_ON) {
2346 if (viafb_SAMM_ON &&
2347 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2348 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2349 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2350 lvds_setting_info2,
2351 &viaparinfo->chip_info->lvds_chip_info2);
2352 } else {
2353 /* IGA1 doesn't have LCD scaling, so set it center. */
2354 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2355 viaparinfo->lvds_setting_info2->display_method =
2356 LCD_CENTERING;
2357 }
2358 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2359 viafb_lcd_set_mode(crt_timing, viaparinfo->
2360 lvds_setting_info2,
2361 &viaparinfo->chip_info->lvds_chip_info2);
2362 }
2363 }
2364
2365 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2366 && (viafb_LCD_ON || viafb_DVI_ON))
2367 set_display_channel();
2368
2369 /* If set mode normally, save resolution information for hot-plug . */
2370 if (!viafb_hotplug) {
2371 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2372 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2373 viafb_hotplug_bpp = video_bpp;
2374 viafb_hotplug_refresh = viafb_refresh;
2375
2376 if (viafb_DVI_ON)
2377 viafb_DeviceStatus = DVI_Device;
2378 else
2379 viafb_DeviceStatus = CRT_Device;
2380 }
2381 device_on();
2382
2383 if (viafb_SAMM_ON == 1)
2384 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2385
2386 device_screen_on();
2387 return 1;
2388 }
2389
2390 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2391 {
2392 int i;
2393
2394 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2395 if ((hres == res_map_refresh_tbl[i].hres)
2396 && (vres == res_map_refresh_tbl[i].vres)
2397 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2398 return res_map_refresh_tbl[i].pixclock;
2399 }
2400 return RES_640X480_60HZ_PIXCLOCK;
2401
2402 }
2403
2404 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2405 {
2406 #define REFRESH_TOLERANCE 3
2407 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2408 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2409 if ((hres == res_map_refresh_tbl[i].hres)
2410 && (vres == res_map_refresh_tbl[i].vres)
2411 && (diff > (abs(long_refresh -
2412 res_map_refresh_tbl[i].vmode_refresh)))) {
2413 diff = abs(long_refresh - res_map_refresh_tbl[i].
2414 vmode_refresh);
2415 nearest = i;
2416 }
2417 }
2418 #undef REFRESH_TOLERANCE
2419 if (nearest > 0)
2420 return res_map_refresh_tbl[nearest].vmode_refresh;
2421 return 60;
2422 }
2423
2424 static void device_off(void)
2425 {
2426 viafb_crt_disable();
2427 viafb_dvi_disable();
2428 viafb_lcd_disable();
2429 }
2430
2431 static void device_on(void)
2432 {
2433 if (viafb_CRT_ON == 1)
2434 viafb_crt_enable();
2435 if (viafb_DVI_ON == 1)
2436 viafb_dvi_enable();
2437 if (viafb_LCD_ON == 1)
2438 viafb_lcd_enable();
2439 }
2440
2441 void viafb_crt_disable(void)
2442 {
2443 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2444 }
2445
2446 void viafb_crt_enable(void)
2447 {
2448 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2449 }
2450
2451 static void enable_second_display_channel(void)
2452 {
2453 /* to enable second display channel. */
2454 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2455 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2456 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2457 }
2458
2459 static void disable_second_display_channel(void)
2460 {
2461 /* to disable second display channel. */
2462 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2463 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2464 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2465 }
2466
2467 int viafb_get_fb_size_from_pci(void)
2468 {
2469 unsigned long configid, deviceid, FBSize = 0;
2470 int VideoMemSize;
2471 int DeviceFound = false;
2472
2473 for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2474 outl(configid, (unsigned long)0xCF8);
2475 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2476
2477 switch (deviceid) {
2478 case CLE266:
2479 case KM400:
2480 outl(configid + 0xE0, (unsigned long)0xCF8);
2481 FBSize = inl((unsigned long)0xCFC);
2482 DeviceFound = true; /* Found device id */
2483 break;
2484
2485 case CN400_FUNCTION3:
2486 case CN700_FUNCTION3:
2487 case CX700_FUNCTION3:
2488 case KM800_FUNCTION3:
2489 case KM890_FUNCTION3:
2490 case P4M890_FUNCTION3:
2491 case P4M900_FUNCTION3:
2492 case VX800_FUNCTION3:
2493 case VX855_FUNCTION3:
2494 /*case CN750_FUNCTION3: */
2495 outl(configid + 0xA0, (unsigned long)0xCF8);
2496 FBSize = inl((unsigned long)0xCFC);
2497 DeviceFound = true; /* Found device id */
2498 break;
2499
2500 default:
2501 break;
2502 }
2503
2504 if (DeviceFound)
2505 break;
2506 }
2507
2508 DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2509
2510 FBSize = FBSize & 0x00007000;
2511 DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2512
2513 if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2514 switch (FBSize) {
2515 case 0x00004000:
2516 VideoMemSize = (16 << 20); /*16M */
2517 break;
2518
2519 case 0x00005000:
2520 VideoMemSize = (32 << 20); /*32M */
2521 break;
2522
2523 case 0x00006000:
2524 VideoMemSize = (64 << 20); /*64M */
2525 break;
2526
2527 default:
2528 VideoMemSize = (32 << 20); /*32M */
2529 break;
2530 }
2531 } else {
2532 switch (FBSize) {
2533 case 0x00001000:
2534 VideoMemSize = (8 << 20); /*8M */
2535 break;
2536
2537 case 0x00002000:
2538 VideoMemSize = (16 << 20); /*16M */
2539 break;
2540
2541 case 0x00003000:
2542 VideoMemSize = (32 << 20); /*32M */
2543 break;
2544
2545 case 0x00004000:
2546 VideoMemSize = (64 << 20); /*64M */
2547 break;
2548
2549 case 0x00005000:
2550 VideoMemSize = (128 << 20); /*128M */
2551 break;
2552
2553 case 0x00006000:
2554 VideoMemSize = (256 << 20); /*256M */
2555 break;
2556
2557 case 0x00007000: /* Only on VX855/875 */
2558 VideoMemSize = (512 << 20); /*512M */
2559 break;
2560
2561 default:
2562 VideoMemSize = (32 << 20); /*32M */
2563 break;
2564 }
2565 }
2566
2567 return VideoMemSize;
2568 }
2569
2570 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2571 *p_gfx_dpa_setting)
2572 {
2573 switch (output_interface) {
2574 case INTERFACE_DVP0:
2575 {
2576 /* DVP0 Clock Polarity and Adjust: */
2577 viafb_write_reg_mask(CR96, VIACR,
2578 p_gfx_dpa_setting->DVP0, 0x0F);
2579
2580 /* DVP0 Clock and Data Pads Driving: */
2581 viafb_write_reg_mask(SR1E, VIASR,
2582 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2583 viafb_write_reg_mask(SR2A, VIASR,
2584 p_gfx_dpa_setting->DVP0ClockDri_S1,
2585 BIT4);
2586 viafb_write_reg_mask(SR1B, VIASR,
2587 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2588 viafb_write_reg_mask(SR2A, VIASR,
2589 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2590 break;
2591 }
2592
2593 case INTERFACE_DVP1:
2594 {
2595 /* DVP1 Clock Polarity and Adjust: */
2596 viafb_write_reg_mask(CR9B, VIACR,
2597 p_gfx_dpa_setting->DVP1, 0x0F);
2598
2599 /* DVP1 Clock and Data Pads Driving: */
2600 viafb_write_reg_mask(SR65, VIASR,
2601 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2602 break;
2603 }
2604
2605 case INTERFACE_DFP_HIGH:
2606 {
2607 viafb_write_reg_mask(CR97, VIACR,
2608 p_gfx_dpa_setting->DFPHigh, 0x0F);
2609 break;
2610 }
2611
2612 case INTERFACE_DFP_LOW:
2613 {
2614 viafb_write_reg_mask(CR99, VIACR,
2615 p_gfx_dpa_setting->DFPLow, 0x0F);
2616 break;
2617 }
2618
2619 case INTERFACE_DFP:
2620 {
2621 viafb_write_reg_mask(CR97, VIACR,
2622 p_gfx_dpa_setting->DFPHigh, 0x0F);
2623 viafb_write_reg_mask(CR99, VIACR,
2624 p_gfx_dpa_setting->DFPLow, 0x0F);
2625 break;
2626 }
2627 }
2628 }
2629
2630 /*According var's xres, yres fill var's other timing information*/
2631 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2632 struct VideoModeTable *vmode_tbl)
2633 {
2634 struct crt_mode_table *crt_timing = NULL;
2635 struct display_timing crt_reg;
2636 int i = 0, index = 0;
2637 crt_timing = vmode_tbl->crtc;
2638 for (i = 0; i < vmode_tbl->mode_array; i++) {
2639 index = i;
2640 if (crt_timing[i].refresh_rate == refresh)
2641 break;
2642 }
2643
2644 crt_reg = crt_timing[index].crtc;
2645 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2646 var->left_margin =
2647 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2648 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2649 var->hsync_len = crt_reg.hor_sync_end;
2650 var->upper_margin =
2651 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2652 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2653 var->vsync_len = crt_reg.ver_sync_end;
2654 }
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