drivers/video/w100fb.h

   1 /*
   2  * linux/drivers/video/w100fb.h
   3  *
   4  * Frame Buffer Device for ATI w100 (Wallaby)
   5  *
   6  * Copyright (C) 2002, ATI Corp.
   7  * Copyright (C) 2004-2005 Richard Purdie
   8  * Copyright (c) 2005 Ian Molton <spyro@f2s.com>
   9  *
  10  * Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
  11  *
  12  * w32xx support by Ian Molton
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  *
  18  */
  19
  20 #if !defined (_W100FB_H)
  21 #define _W100FB_H
  22
  23 /* Block CIF Start: */
  24 #define mmCHIP_ID           0x0000
  25 #define mmREVISION_ID       0x0004
  26 #define mmWRAP_BUF_A        0x0008
  27 #define mmWRAP_BUF_B        0x000C
  28 #define mmWRAP_TOP_DIR      0x0010
  29 #define mmWRAP_START_DIR    0x0014
  30 #define mmCIF_CNTL          0x0018
  31 #define mmCFGREG_BASE       0x001C
  32 #define mmCIF_IO            0x0020
  33 #define mmCIF_READ_DBG      0x0024
  34 #define mmCIF_WRITE_DBG     0x0028
  35 #define cfgIND_ADDR_A_0     0x0000
  36 #define cfgIND_ADDR_A_1     0x0001
  37 #define cfgIND_ADDR_A_2     0x0002
  38 #define cfgIND_DATA_A       0x0003
  39 #define cfgREG_BASE         0x0004
  40 #define cfgINTF_CNTL        0x0005
  41 #define cfgSTATUS           0x0006
  42 #define cfgCPU_DEFAULTS     0x0007
  43 #define cfgIND_ADDR_B_0     0x0008
  44 #define cfgIND_ADDR_B_1     0x0009
  45 #define cfgIND_ADDR_B_2     0x000A
  46 #define cfgIND_DATA_B       0x000B
  47 #define cfgPM4_RPTR         0x000C
  48 #define cfgSCRATCH          0x000D
  49 #define cfgPM4_WRPTR_0      0x000E
  50 #define cfgPM4_WRPTR_1      0x000F
  51 /* Block CIF End: */
  52
  53 /* Block CP Start: */
  54 #define mmSCRATCH_UMSK      0x0280
  55 #define mmSCRATCH_ADDR      0x0284
  56 #define mmGEN_INT_CNTL      0x0200
  57 #define mmGEN_INT_STATUS    0x0204
  58 /* Block CP End: */
  59
  60 /* Block DISPLAY Start: */
  61 #define mmLCD_FORMAT        0x0410
  62 #define mmGRAPHIC_CTRL      0x0414
  63 #define mmGRAPHIC_OFFSET    0x0418
  64 #define mmGRAPHIC_PITCH     0x041C
  65 #define mmCRTC_TOTAL        0x0420
  66 #define mmACTIVE_H_DISP     0x0424
  67 #define mmACTIVE_V_DISP     0x0428
  68 #define mmGRAPHIC_H_DISP    0x042C
  69 #define mmGRAPHIC_V_DISP    0x0430
  70 #define mmVIDEO_CTRL        0x0434
  71 #define mmGRAPHIC_KEY       0x0438
  72 #define mmBRIGHTNESS_CNTL   0x045C
  73 #define mmDISP_INT_CNTL     0x0488
  74 #define mmCRTC_SS           0x048C
  75 #define mmCRTC_LS           0x0490
  76 #define mmCRTC_REV          0x0494
  77 #define mmCRTC_DCLK         0x049C
  78 #define mmCRTC_GS           0x04A0
  79 #define mmCRTC_VPOS_GS      0x04A4
  80 #define mmCRTC_GCLK         0x04A8
  81 #define mmCRTC_GOE          0x04AC
  82 #define mmCRTC_FRAME        0x04B0
  83 #define mmCRTC_FRAME_VPOS   0x04B4
  84 #define mmGPIO_DATA         0x04B8
  85 #define mmGPIO_CNTL1        0x04BC
  86 #define mmGPIO_CNTL2        0x04C0
  87 #define mmLCDD_CNTL1        0x04C4
  88 #define mmLCDD_CNTL2        0x04C8
  89 #define mmGENLCD_CNTL1      0x04CC
  90 #define mmGENLCD_CNTL2      0x04D0
  91 #define mmDISP_DEBUG        0x04D4
  92 #define mmDISP_DB_BUF_CNTL  0x04D8
  93 #define mmDISP_CRC_SIG      0x04DC
  94 #define mmCRTC_DEFAULT_COUNT    0x04E0
  95 #define mmLCD_BACKGROUND_COLOR  0x04E4
  96 #define mmCRTC_PS2          0x04E8
  97 #define mmCRTC_PS2_VPOS     0x04EC
  98 #define mmCRTC_PS1_ACTIVE   0x04F0
  99 #define mmCRTC_PS1_NACTIVE  0x04F4
 100 #define mmCRTC_GCLK_EXT     0x04F8
 101 #define mmCRTC_ALW          0x04FC
 102 #define mmCRTC_ALW_VPOS     0x0500
 103 #define mmCRTC_PSK          0x0504
 104 #define mmCRTC_PSK_HPOS     0x0508
 105 #define mmCRTC_CV4_START    0x050C
 106 #define mmCRTC_CV4_END      0x0510
 107 #define mmCRTC_CV4_HPOS     0x0514
 108 #define mmCRTC_ECK          0x051C
 109 #define mmREFRESH_CNTL      0x0520
 110 #define mmGENLCD_CNTL3      0x0524
 111 #define mmGPIO_DATA2        0x0528
 112 #define mmGPIO_CNTL3        0x052C
 113 #define mmGPIO_CNTL4        0x0530
 114 #define mmCHIP_STRAP        0x0534
 115 #define mmDISP_DEBUG2       0x0538
 116 #define mmDEBUG_BUS_CNTL    0x053C
 117 #define mmGAMMA_VALUE1      0x0540
 118 #define mmGAMMA_VALUE2      0x0544
 119 #define mmGAMMA_SLOPE       0x0548
 120 #define mmGEN_STATUS        0x054C
 121 #define mmHW_INT            0x0550
 122 /* Block DISPLAY End: */
 123
 124 /* Block GFX Start: */
 125 #define mmBRUSH_OFFSET        0x108C
 126 #define mmBRUSH_Y_X           0x1074
 127 #define mmDEFAULT_PITCH_OFFSET      0x10A0
 128 #define mmDEFAULT_SC_BOTTOM_RIGHT   0x10A8
 129 #define mmDEFAULT2_SC_BOTTOM_RIGHT  0x10AC
 130 #define mmGLOBAL_ALPHA        0x1210
 131 #define mmFILTER_COEF         0x1214
 132 #define mmMVC_CNTL_START      0x11E0
 133 #define mmE2_ARITHMETIC_CNTL  0x1220
 134 #define mmENG_CNTL            0x13E8
 135 #define mmENG_PERF_CNT        0x13F0
 136 /* Block GFX End: */
 137
 138 /* Block IDCT Start: */
 139 #define mmIDCT_RUNS         0x0C00
 140 #define mmIDCT_LEVELS       0x0C04
 141 #define mmIDCT_CONTROL      0x0C3C
 142 #define mmIDCT_AUTH_CONTROL 0x0C08
 143 #define mmIDCT_AUTH         0x0C0C
 144 /* Block IDCT End: */
 145
 146 /* Block MC Start: */
 147 #define mmMEM_CNTL             0x0180
 148 #define mmMEM_ARB              0x0184
 149 #define mmMC_FB_LOCATION       0x0188
 150 #define mmMEM_EXT_CNTL         0x018C
 151 #define mmMC_EXT_MEM_LOCATION  0x0190
 152 #define mmMEM_EXT_TIMING_CNTL  0x0194
 153 #define mmMEM_SDRAM_MODE_REG   0x0198
 154 #define mmMEM_IO_CNTL          0x019C
 155 #define mmMC_DEBUG             0x01A0
 156 #define mmMC_BIST_CTRL         0x01A4
 157 #define mmMC_BIST_COLLAR_READ  0x01A8
 158 #define mmTC_MISMATCH          0x01AC
 159 #define mmMC_PERF_MON_CNTL     0x01B0
 160 #define mmMC_PERF_COUNTERS     0x01B4
 161 /* Block MC End: */
 162
 163 /* Block BM Start: */
 164 #define mmBM_EXT_MEM_BANDWIDTH    0x0A00
 165 #define mmBM_OFFSET               0x0A04
 166 #define mmBM_MEM_EXT_TIMING_CNTL  0x0A08
 167 #define mmBM_MEM_EXT_CNTL         0x0A0C
 168 #define mmBM_MEM_MODE_REG         0x0A10
 169 #define mmBM_MEM_IO_CNTL          0x0A18
 170 #define mmBM_CONFIG               0x0A1C
 171 #define mmBM_STATUS               0x0A20
 172 #define mmBM_DEBUG                0x0A24
 173 #define mmBM_PERF_MON_CNTL        0x0A28
 174 #define mmBM_PERF_COUNTERS        0x0A2C
 175 #define mmBM_PERF2_MON_CNTL       0x0A30
 176 #define mmBM_PERF2_COUNTERS       0x0A34
 177 /* Block BM End: */
 178
 179 /* Block RBBM Start: */
 180 #define mmWAIT_UNTIL        0x1400
 181 #define mmISYNC_CNTL        0x1404
 182 #define mmRBBM_CNTL         0x0144
 183 #define mmNQWAIT_UNTIL      0x0150
 184 /* Block RBBM End: */
 185
 186 /* Block CG Start: */
 187 #define mmCLK_PIN_CNTL      0x0080
 188 #define mmPLL_REF_FB_DIV    0x0084
 189 #define mmPLL_CNTL          0x0088
 190 #define mmSCLK_CNTL         0x008C
 191 #define mmPCLK_CNTL         0x0090
 192 #define mmCLK_TEST_CNTL     0x0094
 193 #define mmPWRMGT_CNTL       0x0098
 194 #define mmPWRMGT_STATUS     0x009C
 195 /* Block CG End: */
 196
 197 /* default value definitions */
 198 #define defWRAP_TOP_DIR        0x00000000
 199 #define defWRAP_START_DIR      0x00000000
 200 #define defCFGREG_BASE         0x00000000
 201 #define defCIF_IO              0x000C0902
 202 #define defINTF_CNTL           0x00000011
 203 #define defCPU_DEFAULTS        0x00000006
 204 #define defHW_INT              0x00000000
 205 #define defMC_EXT_MEM_LOCATION 0x07ff0000
 206 #define defTC_MISMATCH         0x00000000
 207
 208 #define W100_CFG_BASE          0x0
 209 #define W100_CFG_LEN           0x10
 210 #define W100_REG_BASE          0x10000
 211 #define W100_REG_LEN           0x2000
 212 #define MEM_INT_BASE_VALUE     0x100000
 213 #define MEM_EXT_BASE_VALUE     0x800000
 214 #define MEM_INT_SIZE           0x05ffff
 215 #define MEM_WINDOW_BASE        0x100000
 216 #define MEM_WINDOW_SIZE        0xf00000
 217
 218 #define WRAP_BUF_BASE_VALUE    0x80000
 219 #define WRAP_BUF_TOP_VALUE     0xbffff
 220
 221 #define CHIP_ID_W100           0x57411002
 222 #define CHIP_ID_W3200          0x56441002
 223 #define CHIP_ID_W3220          0x57441002
 224
 225 /* Register structure definitions */
 226
 227 struct wrap_top_dir_t {
 228         unsigned long top_addr  : 23;
 229         unsigned long           : 9;
 230 } __attribute__((packed));
 231
 232 union wrap_top_dir_u {
 233         unsigned long val : 32;
 234         struct wrap_top_dir_t f;
 235 } __attribute__((packed));
 236
 237 struct wrap_start_dir_t {
 238         unsigned long start_addr : 23;
 239         unsigned long            : 9;
 240 } __attribute__((packed));
 241
 242 union wrap_start_dir_u {
 243         unsigned long val : 32;
 244         struct wrap_start_dir_t f;
 245 } __attribute__((packed));
 246
 247 struct cif_cntl_t {
 248         unsigned long swap_reg                 : 2;
 249         unsigned long swap_fbuf_1              : 2;
 250         unsigned long swap_fbuf_2              : 2;
 251         unsigned long swap_fbuf_3              : 2;
 252         unsigned long pmi_int_disable          : 1;
 253         unsigned long pmi_schmen_disable       : 1;
 254         unsigned long intb_oe                  : 1;
 255         unsigned long en_wait_to_compensate_dq_prop_dly  : 1;
 256         unsigned long compensate_wait_rd_size  : 2;
 257         unsigned long wait_asserted_timeout_val  : 2;
 258         unsigned long wait_masked_val          : 2;
 259         unsigned long en_wait_timeout          : 1;
 260         unsigned long en_one_clk_setup_before_wait  : 1;
 261         unsigned long interrupt_active_high    : 1;
 262         unsigned long en_overwrite_straps      : 1;
 263         unsigned long strap_wait_active_hi     : 1;
 264         unsigned long lat_busy_count           : 2;
 265         unsigned long lat_rd_pm4_sclk_busy     : 1;
 266         unsigned long dis_system_bits          : 1;
 267         unsigned long dis_mr                   : 1;
 268         unsigned long cif_spare_1              : 4;
 269 } __attribute__((packed));
 270
 271 union cif_cntl_u {
 272         unsigned long val : 32;
 273         struct cif_cntl_t f;
 274 } __attribute__((packed));
 275
 276 struct cfgreg_base_t {
 277         unsigned long cfgreg_base  : 24;
 278         unsigned long              : 8;
 279 } __attribute__((packed));
 280
 281 union cfgreg_base_u {
 282         unsigned long val : 32;
 283         struct cfgreg_base_t f;
 284 } __attribute__((packed));
 285
 286 struct cif_io_t {
 287         unsigned long dq_srp     : 1;
 288         unsigned long dq_srn     : 1;
 289         unsigned long dq_sp      : 4;
 290         unsigned long dq_sn      : 4;
 291         unsigned long waitb_srp  : 1;
 292         unsigned long waitb_srn  : 1;
 293         unsigned long waitb_sp   : 4;
 294         unsigned long waitb_sn   : 4;
 295         unsigned long intb_srp   : 1;
 296         unsigned long intb_srn   : 1;
 297         unsigned long intb_sp    : 4;
 298         unsigned long intb_sn    : 4;
 299         unsigned long            : 2;
 300 } __attribute__((packed));
 301
 302 union cif_io_u {
 303         unsigned long val : 32;
 304         struct cif_io_t f;
 305 } __attribute__((packed));
 306
 307 struct cif_read_dbg_t {
 308         unsigned long unpacker_pre_fetch_trig_gen  : 2;
 309         unsigned long dly_second_rd_fetch_trig     : 1;
 310         unsigned long rst_rd_burst_id              : 1;
 311         unsigned long dis_rd_burst_id              : 1;
 312         unsigned long en_block_rd_when_packer_is_not_emp : 1;
 313         unsigned long dis_pre_fetch_cntl_sm        : 1;
 314         unsigned long rbbm_chrncy_dis              : 1;
 315         unsigned long rbbm_rd_after_wr_lat         : 2;
 316         unsigned long dis_be_during_rd             : 1;
 317         unsigned long one_clk_invalidate_pulse     : 1;
 318         unsigned long dis_chnl_priority            : 1;
 319         unsigned long rst_read_path_a_pls          : 1;
 320         unsigned long rst_read_path_b_pls          : 1;
 321         unsigned long dis_reg_rd_fetch_trig        : 1;
 322         unsigned long dis_rd_fetch_trig_from_ind_addr : 1;
 323         unsigned long dis_rd_same_byte_to_trig_fetch : 1;
 324         unsigned long dis_dir_wrap                 : 1;
 325         unsigned long dis_ring_buf_to_force_dec    : 1;
 326         unsigned long dis_addr_comp_in_16bit       : 1;
 327         unsigned long clr_w                        : 1;
 328         unsigned long err_rd_tag_is_3              : 1;
 329         unsigned long err_load_when_ful_a          : 1;
 330         unsigned long err_load_when_ful_b          : 1;
 331         unsigned long                              : 7;
 332 } __attribute__((packed));
 333
 334 union cif_read_dbg_u {
 335         unsigned long val : 32;
 336         struct cif_read_dbg_t f;
 337 } __attribute__((packed));
 338
 339 struct cif_write_dbg_t {
 340         unsigned long packer_timeout_count          : 2;
 341         unsigned long en_upper_load_cond            : 1;
 342         unsigned long en_chnl_change_cond           : 1;
 343         unsigned long dis_addr_comp_cond            : 1;
 344         unsigned long dis_load_same_byte_addr_cond  : 1;
 345         unsigned long dis_timeout_cond              : 1;
 346         unsigned long dis_timeout_during_rbbm       : 1;
 347         unsigned long dis_packer_ful_during_rbbm_timeout : 1;
 348         unsigned long en_dword_split_to_rbbm        : 1;
 349         unsigned long en_dummy_val                  : 1;
 350         unsigned long dummy_val_sel                 : 1;
 351         unsigned long mask_pm4_wrptr_dec            : 1;
 352         unsigned long dis_mc_clean_cond             : 1;
 353         unsigned long err_two_reqi_during_ful       : 1;
 354         unsigned long err_reqi_during_idle_clk      : 1;
 355         unsigned long err_global                    : 1;
 356         unsigned long en_wr_buf_dbg_load            : 1;
 357         unsigned long en_wr_buf_dbg_path            : 1;
 358         unsigned long sel_wr_buf_byte               : 3;
 359         unsigned long dis_rd_flush_wr               : 1;
 360         unsigned long dis_packer_ful_cond           : 1;
 361         unsigned long dis_invalidate_by_ops_chnl    : 1;
 362         unsigned long en_halt_when_reqi_err         : 1;
 363         unsigned long cif_spare_2                   : 5;
 364         unsigned long                               : 1;
 365 } __attribute__((packed));
 366
 367 union cif_write_dbg_u {
 368         unsigned long val : 32;
 369         struct cif_write_dbg_t f;
 370 } __attribute__((packed));
 371
 372
 373 struct intf_cntl_t {
 374         unsigned char ad_inc_a            : 1;
 375         unsigned char ring_buf_a          : 1;
 376         unsigned char rd_fetch_trigger_a  : 1;
 377         unsigned char rd_data_rdy_a       : 1;
 378         unsigned char ad_inc_b            : 1;
 379         unsigned char ring_buf_b          : 1;
 380         unsigned char rd_fetch_trigger_b  : 1;
 381         unsigned char rd_data_rdy_b       : 1;
 382 } __attribute__((packed));
 383
 384 union intf_cntl_u {
 385         unsigned char val : 8;
 386         struct intf_cntl_t f;
 387 } __attribute__((packed));
 388
 389 struct cpu_defaults_t {
 390         unsigned char unpack_rd_data     : 1;
 391         unsigned char access_ind_addr_a  : 1;
 392         unsigned char access_ind_addr_b  : 1;
 393         unsigned char access_scratch_reg : 1;
 394         unsigned char pack_wr_data       : 1;
 395         unsigned char transition_size    : 1;
 396         unsigned char en_read_buf_mode   : 1;
 397         unsigned char rd_fetch_scratch   : 1;
 398 } __attribute__((packed));
 399
 400 union cpu_defaults_u {
 401         unsigned char val : 8;
 402         struct cpu_defaults_t f;
 403 } __attribute__((packed));
 404
 405 struct crtc_total_t {
 406         unsigned long crtc_h_total : 10;
 407         unsigned long              : 6;
 408         unsigned long crtc_v_total : 10;
 409         unsigned long              : 6;
 410 } __attribute__((packed));
 411
 412 union crtc_total_u {
 413         unsigned long val : 32;
 414         struct crtc_total_t f;
 415 } __attribute__((packed));
 416
 417 struct crtc_ss_t {
 418         unsigned long ss_start    : 10;
 419         unsigned long             : 6;
 420         unsigned long ss_end      : 10;
 421         unsigned long             : 2;
 422         unsigned long ss_align    : 1;
 423         unsigned long ss_pol      : 1;
 424         unsigned long ss_run_mode : 1;
 425         unsigned long ss_en       : 1;
 426 } __attribute__((packed));
 427
 428 union crtc_ss_u {
 429         unsigned long val : 32;
 430         struct crtc_ss_t f;
 431 } __attribute__((packed));
 432
 433 struct active_h_disp_t {
 434         unsigned long active_h_start  : 10;
 435         unsigned long                 : 6;
 436         unsigned long active_h_end    : 10;
 437         unsigned long                 : 6;
 438 } __attribute__((packed));
 439
 440 union active_h_disp_u {
 441         unsigned long val : 32;
 442         struct active_h_disp_t f;
 443 } __attribute__((packed));
 444
 445 struct active_v_disp_t {
 446         unsigned long active_v_start  : 10;
 447         unsigned long                 : 6;
 448         unsigned long active_v_end    : 10;
 449         unsigned long                 : 6;
 450 } __attribute__((packed));
 451
 452 union active_v_disp_u {
 453         unsigned long val : 32;
 454         struct active_v_disp_t f;
 455 } __attribute__((packed));
 456
 457 struct graphic_h_disp_t {
 458         unsigned long graphic_h_start : 10;
 459         unsigned long                 : 6;
 460         unsigned long graphic_h_end   : 10;
 461         unsigned long                 : 6;
 462 } __attribute__((packed));
 463
 464 union graphic_h_disp_u {
 465         unsigned long val : 32;
 466         struct graphic_h_disp_t f;
 467 } __attribute__((packed));
 468
 469 struct graphic_v_disp_t {
 470         unsigned long graphic_v_start : 10;
 471         unsigned long                 : 6;
 472         unsigned long graphic_v_end   : 10;
 473         unsigned long                 : 6;
 474 } __attribute__((packed));
 475
 476 union graphic_v_disp_u{
 477         unsigned long val : 32;
 478         struct graphic_v_disp_t f;
 479 } __attribute__((packed));
 480
 481 struct graphic_ctrl_t_w100 {
 482         unsigned long color_depth       : 3;
 483         unsigned long portrait_mode     : 2;
 484         unsigned long low_power_on      : 1;
 485         unsigned long req_freq          : 4;
 486         unsigned long en_crtc           : 1;
 487         unsigned long en_graphic_req    : 1;
 488         unsigned long en_graphic_crtc   : 1;
 489         unsigned long total_req_graphic : 9;
 490         unsigned long lcd_pclk_on       : 1;
 491         unsigned long lcd_sclk_on       : 1;
 492         unsigned long pclk_running      : 1;
 493         unsigned long sclk_running      : 1;
 494         unsigned long                   : 6;
 495 } __attribute__((packed));
 496
 497 struct graphic_ctrl_t_w32xx {
 498         unsigned long color_depth       : 3;
 499         unsigned long portrait_mode     : 2;
 500         unsigned long low_power_on      : 1;
 501         unsigned long req_freq          : 4;
 502         unsigned long en_crtc           : 1;
 503         unsigned long en_graphic_req    : 1;
 504         unsigned long en_graphic_crtc   : 1;
 505         unsigned long total_req_graphic : 10;
 506         unsigned long lcd_pclk_on       : 1;
 507         unsigned long lcd_sclk_on       : 1;
 508         unsigned long pclk_running      : 1;
 509         unsigned long sclk_running      : 1;
 510         unsigned long                   : 5;
 511 } __attribute__((packed));
 512
 513 union graphic_ctrl_u {
 514         unsigned long val : 32;
 515         struct graphic_ctrl_t_w100 f_w100;
 516         struct graphic_ctrl_t_w32xx f_w32xx;
 517 } __attribute__((packed));
 518
 519 struct video_ctrl_t {
 520         unsigned long video_mode       : 1;
 521         unsigned long keyer_en         : 1;
 522         unsigned long en_video_req     : 1;
 523         unsigned long en_graphic_req_video  : 1;
 524         unsigned long en_video_crtc    : 1;
 525         unsigned long video_hor_exp    : 2;
 526         unsigned long video_ver_exp    : 2;
 527         unsigned long uv_combine       : 1;
 528         unsigned long total_req_video  : 9;
 529         unsigned long video_ch_sel     : 1;
 530         unsigned long video_portrait   : 2;
 531         unsigned long yuv2rgb_en       : 1;
 532         unsigned long yuv2rgb_option   : 1;
 533         unsigned long video_inv_hor    : 1;
 534         unsigned long video_inv_ver    : 1;
 535         unsigned long gamma_sel        : 2;
 536         unsigned long dis_limit        : 1;
 537         unsigned long en_uv_hblend     : 1;
 538         unsigned long rgb_gamma_sel    : 2;
 539 } __attribute__((packed));
 540
 541 union video_ctrl_u {
 542         unsigned long val : 32;
 543         struct video_ctrl_t f;
 544 } __attribute__((packed));
 545
 546 struct disp_db_buf_cntl_rd_t {
 547         unsigned long en_db_buf           : 1;
 548         unsigned long update_db_buf_done  : 1;
 549         unsigned long db_buf_cntl         : 6;
 550         unsigned long                     : 24;
 551 } __attribute__((packed));
 552
 553 union disp_db_buf_cntl_rd_u {
 554         unsigned long val : 32;
 555         struct disp_db_buf_cntl_rd_t f;
 556 } __attribute__((packed));
 557
 558 struct disp_db_buf_cntl_wr_t {
 559         unsigned long en_db_buf      : 1;
 560         unsigned long update_db_buf  : 1;
 561         unsigned long db_buf_cntl    : 6;
 562         unsigned long                : 24;
 563 } __attribute__((packed));
 564
 565 union disp_db_buf_cntl_wr_u {
 566         unsigned long val : 32;
 567         struct disp_db_buf_cntl_wr_t f;
 568 } __attribute__((packed));
 569
 570 struct gamma_value1_t {
 571         unsigned long gamma1   : 8;
 572         unsigned long gamma2   : 8;
 573         unsigned long gamma3   : 8;
 574         unsigned long gamma4   : 8;
 575 } __attribute__((packed));
 576
 577 union gamma_value1_u {
 578         unsigned long val : 32;
 579         struct gamma_value1_t f;
 580 } __attribute__((packed));
 581
 582 struct gamma_value2_t {
 583         unsigned long gamma5   : 8;
 584         unsigned long gamma6   : 8;
 585         unsigned long gamma7   : 8;
 586         unsigned long gamma8   : 8;
 587 } __attribute__((packed));
 588
 589 union gamma_value2_u {
 590         unsigned long val : 32;
 591         struct gamma_value2_t f;
 592 } __attribute__((packed));
 593
 594 struct gamma_slope_t {
 595         unsigned long slope1   : 3;
 596         unsigned long slope2   : 3;
 597         unsigned long slope3   : 3;
 598         unsigned long slope4   : 3;
 599         unsigned long slope5   : 3;
 600         unsigned long slope6   : 3;
 601         unsigned long slope7   : 3;
 602         unsigned long slope8   : 3;
 603         unsigned long          : 8;
 604 } __attribute__((packed));
 605
 606 union gamma_slope_u {
 607         unsigned long val : 32;
 608         struct gamma_slope_t f;
 609 } __attribute__((packed));
 610
 611 struct mc_ext_mem_location_t {
 612         unsigned long mc_ext_mem_start : 16;
 613         unsigned long mc_ext_mem_top   : 16;
 614 } __attribute__((packed));
 615
 616 union mc_ext_mem_location_u {
 617         unsigned long val : 32;
 618         struct mc_ext_mem_location_t f;
 619 } __attribute__((packed));
 620
 621 struct mc_fb_location_t {
 622         unsigned long mc_fb_start      : 16;
 623         unsigned long mc_fb_top        : 16;
 624 } __attribute__((packed));
 625
 626 union mc_fb_location_u {
 627         unsigned long val : 32;
 628         struct mc_fb_location_t f;
 629 } __attribute__((packed));
 630
 631 struct clk_pin_cntl_t {
 632         unsigned long osc_en           : 1;
 633         unsigned long osc_gain         : 5;
 634         unsigned long dont_use_xtalin  : 1;
 635         unsigned long xtalin_pm_en     : 1;
 636         unsigned long xtalin_dbl_en    : 1;
 637         unsigned long                  : 7;
 638         unsigned long cg_debug         : 16;
 639 } __attribute__((packed));
 640
 641 union clk_pin_cntl_u {
 642         unsigned long val : 32;
 643         struct clk_pin_cntl_t f;
 644 } __attribute__((packed));
 645
 646 struct pll_ref_fb_div_t {
 647         unsigned long pll_ref_div      : 4;
 648         unsigned long                  : 4;
 649         unsigned long pll_fb_div_int   : 6;
 650         unsigned long                  : 2;
 651         unsigned long pll_fb_div_frac  : 3;
 652         unsigned long                  : 1;
 653         unsigned long pll_reset_time   : 4;
 654         unsigned long pll_lock_time    : 8;
 655 } __attribute__((packed));
 656
 657 union pll_ref_fb_div_u {
 658         unsigned long val : 32;
 659         struct pll_ref_fb_div_t f;
 660 } __attribute__((packed));
 661
 662 struct pll_cntl_t {
 663         unsigned long pll_pwdn        : 1;
 664         unsigned long pll_reset       : 1;
 665         unsigned long pll_pm_en       : 1;
 666         unsigned long pll_mode        : 1;
 667         unsigned long pll_refclk_sel  : 1;
 668         unsigned long pll_fbclk_sel   : 1;
 669         unsigned long pll_tcpoff      : 1;
 670         unsigned long pll_pcp         : 3;
 671         unsigned long pll_pvg         : 3;
 672         unsigned long pll_vcofr       : 1;
 673         unsigned long pll_ioffset     : 2;
 674         unsigned long pll_pecc_mode   : 2;
 675         unsigned long pll_pecc_scon   : 2;
 676         unsigned long pll_dactal      : 4;
 677         unsigned long pll_cp_clip     : 2;
 678         unsigned long pll_conf        : 3;
 679         unsigned long pll_mbctrl      : 2;
 680         unsigned long pll_ring_off    : 1;
 681 } __attribute__((packed));
 682
 683 union pll_cntl_u {
 684         unsigned long val : 32;
 685         struct pll_cntl_t f;
 686 } __attribute__((packed));
 687
 688 struct sclk_cntl_t {
 689         unsigned long sclk_src_sel         : 2;
 690         unsigned long                      : 2;
 691         unsigned long sclk_post_div_fast   : 4;
 692         unsigned long sclk_clkon_hys       : 3;
 693         unsigned long sclk_post_div_slow   : 4;
 694         unsigned long disp_cg_ok2switch_en : 1;
 695         unsigned long sclk_force_reg       : 1;
 696         unsigned long sclk_force_disp      : 1;
 697         unsigned long sclk_force_mc        : 1;
 698         unsigned long sclk_force_extmc     : 1;
 699         unsigned long sclk_force_cp        : 1;
 700         unsigned long sclk_force_e2        : 1;
 701         unsigned long sclk_force_e3        : 1;
 702         unsigned long sclk_force_idct      : 1;
 703         unsigned long sclk_force_bist      : 1;
 704         unsigned long busy_extend_cp       : 1;
 705         unsigned long busy_extend_e2       : 1;
 706         unsigned long busy_extend_e3       : 1;
 707         unsigned long busy_extend_idct     : 1;
 708         unsigned long                      : 3;
 709 } __attribute__((packed));
 710
 711 union sclk_cntl_u {
 712         unsigned long val : 32;
 713         struct sclk_cntl_t f;
 714 } __attribute__((packed));
 715
 716 struct pclk_cntl_t {
 717         unsigned long pclk_src_sel     : 2;
 718         unsigned long                  : 2;
 719         unsigned long pclk_post_div    : 4;
 720         unsigned long                  : 8;
 721         unsigned long pclk_force_disp  : 1;
 722         unsigned long                  : 15;
 723 } __attribute__((packed));
 724
 725 union pclk_cntl_u {
 726         unsigned long val : 32;
 727         struct pclk_cntl_t f;
 728 } __attribute__((packed));
 729
 730
 731 #define TESTCLK_SRC_PLL   0x01
 732 #define TESTCLK_SRC_SCLK  0x02
 733 #define TESTCLK_SRC_PCLK  0x03
 734 /* 4 and 5 seem to by XTAL/M */
 735 #define TESTCLK_SRC_XTAL  0x06
 736
 737 struct clk_test_cntl_t {
 738         unsigned long testclk_sel      : 4;
 739         unsigned long                  : 3;
 740         unsigned long start_check_freq : 1;
 741         unsigned long tstcount_rst     : 1;
 742         unsigned long                  : 15;
 743         unsigned long test_count       : 8;
 744 } __attribute__((packed));
 745
 746 union clk_test_cntl_u {
 747         unsigned long val : 32;
 748         struct clk_test_cntl_t f;
 749 } __attribute__((packed));
 750
 751 struct pwrmgt_cntl_t {
 752         unsigned long pwm_enable           : 1;
 753         unsigned long                      : 1;
 754         unsigned long pwm_mode_req         : 2;
 755         unsigned long pwm_wakeup_cond      : 2;
 756         unsigned long pwm_fast_noml_hw_en  : 1;
 757         unsigned long pwm_noml_fast_hw_en  : 1;
 758         unsigned long pwm_fast_noml_cond   : 4;
 759         unsigned long pwm_noml_fast_cond   : 4;
 760         unsigned long pwm_idle_timer       : 8;
 761         unsigned long pwm_busy_timer       : 8;
 762 } __attribute__((packed));
 763
 764 union pwrmgt_cntl_u {
 765         unsigned long val : 32;
 766         struct pwrmgt_cntl_t f;
 767 } __attribute__((packed));
 768
 769 #endif
 770