drivers/video/xilinxfb.c

   1 /*
   2  * Xilinx TFT frame buffer driver
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * 2002-2007 (c) MontaVista Software, Inc.
   8  * 2007 (c) Secret Lab Technologies, Ltd.
   9  * 2009 (c) Xilinx Inc.
  10  *
  11  * This file is licensed under the terms of the GNU General Public License
  12  * version 2.  This program is licensed "as is" without any warranty of any
  13  * kind, whether express or implied.
  14  */
  15
  16 /*
  17  * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
  18  * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
  19  * was based on skeletonfb.c, Skeleton for a frame buffer device by
  20  * Geert Uytterhoeven.
  21  */
  22
  23 #include <linux/device.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/errno.h>
  27 #include <linux/string.h>
  28 #include <linux/mm.h>
  29 #include <linux/fb.h>
  30 #include <linux/init.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_address.h>
  35 #include <linux/io.h>
  36 #include <linux/xilinxfb.h>
  37 #include <linux/slab.h>
  38
  39 #ifdef CONFIG_PPC_DCR
  40 #include <asm/dcr.h>
  41 #endif
  42
  43 #define DRIVER_NAME             "xilinxfb"
  44
  45
  46 /*
  47  * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
  48  * the VGA port on the Xilinx ML40x board. This is a hardware display
  49  * controller for a 640x480 resolution TFT or VGA screen.
  50  *
  51  * The interface to the framebuffer is nice and simple.  There are two
  52  * control registers.  The first tells the LCD interface where in memory
  53  * the frame buffer is (only the 11 most significant bits are used, so
  54  * don't start thinking about scrolling).  The second allows the LCD to
  55  * be turned on or off as well as rotated 180 degrees.
  56  *
  57  * In case of direct PLB access the second control register will be at
  58  * an offset of 4 as compared to the DCR access where the offset is 1
  59  * i.e. REG_CTRL. So this is taken care in the function
  60  * xilinx_fb_out_be32 where it left shifts the offset 2 times in case of
  61  * direct PLB access.
  62  */
  63 #define NUM_REGS        2
  64 #define REG_FB_ADDR     0
  65 #define REG_CTRL        1
  66 #define REG_CTRL_ENABLE  0x0001
  67 #define REG_CTRL_ROTATE  0x0002
  68
  69 /*
  70  * The hardware only handles a single mode: 640x480 24 bit true
  71  * color. Each pixel gets a word (32 bits) of memory.  Within each word,
  72  * the 8 most significant bits are ignored, the next 8 bits are the red
  73  * level, the next 8 bits are the green level and the 8 least
  74  * significant bits are the blue level.  Each row of the LCD uses 1024
  75  * words, but only the first 640 pixels are displayed with the other 384
  76  * words being ignored.  There are 480 rows.
  77  */
  78 #define BYTES_PER_PIXEL 4
  79 #define BITS_PER_PIXEL  (BYTES_PER_PIXEL * 8)
  80
  81 #define RED_SHIFT       16
  82 #define GREEN_SHIFT     8
  83 #define BLUE_SHIFT      0
  84
  85 #define PALETTE_ENTRIES_NO      16      /* passed to fb_alloc_cmap() */
  86
  87 /*
  88  * Default xilinxfb configuration
  89  */
  90 static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
  91         .xres = 640,
  92         .yres = 480,
  93         .xvirt = 1024,
  94         .yvirt = 480,
  95 };
  96
  97 /*
  98  * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
  99  */
 100 static struct fb_fix_screeninfo xilinx_fb_fix = {
 101         .id =           "Xilinx",
 102         .type =         FB_TYPE_PACKED_PIXELS,
 103         .visual =       FB_VISUAL_TRUECOLOR,
 104         .accel =        FB_ACCEL_NONE
 105 };
 106
 107 static struct fb_var_screeninfo xilinx_fb_var = {
 108         .bits_per_pixel =       BITS_PER_PIXEL,
 109
 110         .red =          { RED_SHIFT, 8, 0 },
 111         .green =        { GREEN_SHIFT, 8, 0 },
 112         .blue =         { BLUE_SHIFT, 8, 0 },
 113         .transp =       { 0, 0, 0 },
 114
 115         .activate =     FB_ACTIVATE_NOW
 116 };
 117
 118
 119 #define PLB_ACCESS_FLAG 0x1             /* 1 = PLB, 0 = DCR */
 120
 121 struct xilinxfb_drvdata {
 122
 123         struct fb_info  info;           /* FB driver info record */
 124
 125         phys_addr_t     regs_phys;      /* phys. address of the control
 126                                                 registers */
 127         void __iomem    *regs;          /* virt. address of the control
 128                                                 registers */
 129 #ifdef CONFIG_PPC_DCR
 130         dcr_host_t      dcr_host;
 131         unsigned int    dcr_len;
 132 #endif
 133         void            *fb_virt;       /* virt. address of the frame buffer */
 134         dma_addr_t      fb_phys;        /* phys. address of the frame buffer */
 135         int             fb_alloced;     /* Flag, was the fb memory alloced? */
 136
 137         u8              flags;          /* features of the driver */
 138
 139         u32             reg_ctrl_default;
 140
 141         u32             pseudo_palette[PALETTE_ENTRIES_NO];
 142                                         /* Fake palette of 16 colors */
 143 };
 144
 145 #define to_xilinxfb_drvdata(_info) \
 146         container_of(_info, struct xilinxfb_drvdata, info)
 147
 148 /*
 149  * The XPS TFT Controller can be accessed through PLB or DCR interface.
 150  * To perform the read/write on the registers we need to check on
 151  * which bus its connected and call the appropriate write API.
 152  */
 153 static void xilinx_fb_out_be32(struct xilinxfb_drvdata *drvdata, u32 offset,
 154                                 u32 val)
 155 {
 156         if (drvdata->flags & PLB_ACCESS_FLAG)
 157                 out_be32(drvdata->regs + (offset << 2), val);
 158 #ifdef CONFIG_PPC_DCR
 159         else
 160                 dcr_write(drvdata->dcr_host, offset, val);
 161 #endif
 162 }
 163
 164 static int
 165 xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
 166         unsigned transp, struct fb_info *fbi)
 167 {
 168         u32 *palette = fbi->pseudo_palette;
 169
 170         if (regno >= PALETTE_ENTRIES_NO)
 171                 return -EINVAL;
 172
 173         if (fbi->var.grayscale) {
 174                 /* Convert color to grayscale.
 175                  * grayscale = 0.30*R + 0.59*G + 0.11*B */
 176                 red = green = blue =
 177                         (red * 77 + green * 151 + blue * 28 + 127) >> 8;
 178         }
 179
 180         /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
 181
 182         /* We only handle 8 bits of each color. */
 183         red >>= 8;
 184         green >>= 8;
 185         blue >>= 8;
 186         palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
 187                          (blue << BLUE_SHIFT);
 188
 189         return 0;
 190 }
 191
 192 static int
 193 xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
 194 {
 195         struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
 196
 197         switch (blank_mode) {
 198         case FB_BLANK_UNBLANK:
 199                 /* turn on panel */
 200                 xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
 201                 break;
 202
 203         case FB_BLANK_NORMAL:
 204         case FB_BLANK_VSYNC_SUSPEND:
 205         case FB_BLANK_HSYNC_SUSPEND:
 206         case FB_BLANK_POWERDOWN:
 207                 /* turn off panel */
 208                 xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
 209         default:
 210                 break;
 211
 212         }
 213         return 0; /* success */
 214 }
 215
 216 static struct fb_ops xilinxfb_ops =
 217 {
 218         .owner                  = THIS_MODULE,
 219         .fb_setcolreg           = xilinx_fb_setcolreg,
 220         .fb_blank               = xilinx_fb_blank,
 221         .fb_fillrect            = cfb_fillrect,
 222         .fb_copyarea            = cfb_copyarea,
 223         .fb_imageblit           = cfb_imageblit,
 224 };
 225
 226 /* ---------------------------------------------------------------------
 227  * Bus independent setup/teardown
 228  */
 229
 230 static int xilinxfb_assign(struct device *dev,
 231                            struct xilinxfb_drvdata *drvdata,
 232                            unsigned long physaddr,
 233                            struct xilinxfb_platform_data *pdata)
 234 {
 235         int rc;
 236         int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
 237
 238         if (drvdata->flags & PLB_ACCESS_FLAG) {
 239                 /*
 240                  * Map the control registers in if the controller
 241                  * is on direct PLB interface.
 242                  */
 243                 if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
 244                         dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
 245                                 physaddr);
 246                         rc = -ENODEV;
 247                         goto err_region;
 248                 }
 249
 250                 drvdata->regs_phys = physaddr;
 251                 drvdata->regs = ioremap(physaddr, 8);
 252                 if (!drvdata->regs) {
 253                         dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
 254                                 physaddr);
 255                         rc = -ENODEV;
 256                         goto err_map;
 257                 }
 258         }
 259
 260         /* Allocate the framebuffer memory */
 261         if (pdata->fb_phys) {
 262                 drvdata->fb_phys = pdata->fb_phys;
 263                 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
 264         } else {
 265                 drvdata->fb_alloced = 1;
 266                 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
 267                                         &drvdata->fb_phys, GFP_KERNEL);
 268         }
 269
 270         if (!drvdata->fb_virt) {
 271                 dev_err(dev, "Could not allocate frame buffer memory\n");
 272                 rc = -ENOMEM;
 273                 if (drvdata->flags & PLB_ACCESS_FLAG)
 274                         goto err_fbmem;
 275                 else
 276                         goto err_region;
 277         }
 278
 279         /* Clear (turn to black) the framebuffer */
 280         memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
 281
 282         /* Tell the hardware where the frame buffer is */
 283         xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
 284
 285         /* Turn on the display */
 286         drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
 287         if (pdata->rotate_screen)
 288                 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
 289         xilinx_fb_out_be32(drvdata, REG_CTRL,
 290                                         drvdata->reg_ctrl_default);
 291
 292         /* Fill struct fb_info */
 293         drvdata->info.device = dev;
 294         drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
 295         drvdata->info.fbops = &xilinxfb_ops;
 296         drvdata->info.fix = xilinx_fb_fix;
 297         drvdata->info.fix.smem_start = drvdata->fb_phys;
 298         drvdata->info.fix.smem_len = fbsize;
 299         drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
 300
 301         drvdata->info.pseudo_palette = drvdata->pseudo_palette;
 302         drvdata->info.flags = FBINFO_DEFAULT;
 303         drvdata->info.var = xilinx_fb_var;
 304         drvdata->info.var.height = pdata->screen_height_mm;
 305         drvdata->info.var.width = pdata->screen_width_mm;
 306         drvdata->info.var.xres = pdata->xres;
 307         drvdata->info.var.yres = pdata->yres;
 308         drvdata->info.var.xres_virtual = pdata->xvirt;
 309         drvdata->info.var.yres_virtual = pdata->yvirt;
 310
 311         /* Allocate a colour map */
 312         rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
 313         if (rc) {
 314                 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
 315                         PALETTE_ENTRIES_NO);
 316                 goto err_cmap;
 317         }
 318
 319         /* Register new frame buffer */
 320         rc = register_framebuffer(&drvdata->info);
 321         if (rc) {
 322                 dev_err(dev, "Could not register frame buffer\n");
 323                 goto err_regfb;
 324         }
 325
 326         if (drvdata->flags & PLB_ACCESS_FLAG) {
 327                 /* Put a banner in the log (for DEBUG) */
 328                 dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr,
 329                                         drvdata->regs);
 330         }
 331         /* Put a banner in the log (for DEBUG) */
 332         dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
 333                 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
 334
 335         return 0;       /* success */
 336
 337 err_regfb:
 338         fb_dealloc_cmap(&drvdata->info.cmap);
 339
 340 err_cmap:
 341         if (drvdata->fb_alloced)
 342                 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
 343                         drvdata->fb_phys);
 344         else
 345                 iounmap(drvdata->fb_virt);
 346
 347         /* Turn off the display */
 348         xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
 349
 350 err_fbmem:
 351         if (drvdata->flags & PLB_ACCESS_FLAG)
 352                 iounmap(drvdata->regs);
 353
 354 err_map:
 355         if (drvdata->flags & PLB_ACCESS_FLAG)
 356                 release_mem_region(physaddr, 8);
 357
 358 err_region:
 359         kfree(drvdata);
 360         dev_set_drvdata(dev, NULL);
 361
 362         return rc;
 363 }
 364
 365 static int xilinxfb_release(struct device *dev)
 366 {
 367         struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
 368
 369 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
 370         xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
 371 #endif
 372
 373         unregister_framebuffer(&drvdata->info);
 374
 375         fb_dealloc_cmap(&drvdata->info.cmap);
 376
 377         if (drvdata->fb_alloced)
 378                 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
 379                                   drvdata->fb_virt, drvdata->fb_phys);
 380         else
 381                 iounmap(drvdata->fb_virt);
 382
 383         /* Turn off the display */
 384         xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
 385
 386         /* Release the resources, as allocated based on interface */
 387         if (drvdata->flags & PLB_ACCESS_FLAG) {
 388                 iounmap(drvdata->regs);
 389                 release_mem_region(drvdata->regs_phys, 8);
 390         }
 391 #ifdef CONFIG_PPC_DCR
 392         else
 393                 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
 394 #endif
 395
 396         kfree(drvdata);
 397         dev_set_drvdata(dev, NULL);
 398
 399         return 0;
 400 }
 401
 402 /* ---------------------------------------------------------------------
 403  * OF bus binding
 404  */
 405
 406 static int xilinxfb_of_probe(struct platform_device *op)
 407 {
 408         const u32 *prop;
 409         u32 *p;
 410         u32 tft_access;
 411         struct xilinxfb_platform_data pdata;
 412         struct resource res;
 413         int size, rc;
 414         struct xilinxfb_drvdata *drvdata;
 415
 416         /* Copy with the default pdata (not a ptr reference!) */
 417         pdata = xilinx_fb_default_pdata;
 418
 419         /* Allocate the driver data region */
 420         drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
 421         if (!drvdata) {
 422                 dev_err(&op->dev, "Couldn't allocate device private record\n");
 423                 return -ENOMEM;
 424         }
 425
 426         /*
 427          * To check whether the core is connected directly to DCR or PLB
 428          * interface and initialize the tft_access accordingly.
 429          */
 430         p = (u32 *)of_get_property(op->dev.of_node, "xlnx,dcr-splb-slave-if", NULL);
 431         tft_access = p ? *p : 0;
 432
 433         /*
 434          * Fill the resource structure if its direct PLB interface
 435          * otherwise fill the dcr_host structure.
 436          */
 437         if (tft_access) {
 438                 drvdata->flags |= PLB_ACCESS_FLAG;
 439                 rc = of_address_to_resource(op->dev.of_node, 0, &res);
 440                 if (rc) {
 441                         dev_err(&op->dev, "invalid address\n");
 442                         goto err;
 443                 }
 444         }
 445 #ifdef CONFIG_PPC_DCR
 446         else {
 447                 int start;
 448                 res.start = 0;
 449                 start = dcr_resource_start(op->dev.of_node, 0);
 450                 drvdata->dcr_len = dcr_resource_len(op->dev.of_node, 0);
 451                 drvdata->dcr_host = dcr_map(op->dev.of_node, start, drvdata->dcr_len);
 452                 if (!DCR_MAP_OK(drvdata->dcr_host)) {
 453                         dev_err(&op->dev, "invalid DCR address\n");
 454                         goto err;
 455                 }
 456         }
 457 #endif
 458
 459         prop = of_get_property(op->dev.of_node, "phys-size", &size);
 460         if ((prop) && (size >= sizeof(u32)*2)) {
 461                 pdata.screen_width_mm = prop[0];
 462                 pdata.screen_height_mm = prop[1];
 463         }
 464
 465         prop = of_get_property(op->dev.of_node, "resolution", &size);
 466         if ((prop) && (size >= sizeof(u32)*2)) {
 467                 pdata.xres = prop[0];
 468                 pdata.yres = prop[1];
 469         }
 470
 471         prop = of_get_property(op->dev.of_node, "virtual-resolution", &size);
 472         if ((prop) && (size >= sizeof(u32)*2)) {
 473                 pdata.xvirt = prop[0];
 474                 pdata.yvirt = prop[1];
 475         }
 476
 477         if (of_find_property(op->dev.of_node, "rotate-display", NULL))
 478                 pdata.rotate_screen = 1;
 479
 480         dev_set_drvdata(&op->dev, drvdata);
 481         return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
 482
 483  err:
 484         kfree(drvdata);
 485         return -ENODEV;
 486 }
 487
 488 static int xilinxfb_of_remove(struct platform_device *op)
 489 {
 490         return xilinxfb_release(&op->dev);
 491 }
 492
 493 /* Match table for of_platform binding */
 494 static struct of_device_id xilinxfb_of_match[] = {
 495         { .compatible = "xlnx,xps-tft-1.00.a", },
 496         { .compatible = "xlnx,xps-tft-2.00.a", },
 497         { .compatible = "xlnx,xps-tft-2.01.a", },
 498         { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
 499         { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
 500         {},
 501 };
 502 MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
 503
 504 static struct platform_driver xilinxfb_of_driver = {
 505         .probe = xilinxfb_of_probe,
 506         .remove = xilinxfb_of_remove,
 507         .driver = {
 508                 .name = DRIVER_NAME,
 509                 .owner = THIS_MODULE,
 510                 .of_match_table = xilinxfb_of_match,
 511         },
 512 };
 513
 514 module_platform_driver(xilinxfb_of_driver);
 515
 516 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 517 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
 518 MODULE_LICENSE("GPL");