drivers/video/xilinxfb.c

   1 /*
   2  * Xilinx TFT frame buffer driver
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * 2002-2007 (c) MontaVista Software, Inc.
   8  * 2007 (c) Secret Lab Technologies, Ltd.
   9  * 2009 (c) Xilinx Inc.
  10  *
  11  * This file is licensed under the terms of the GNU General Public License
  12  * version 2.  This program is licensed "as is" without any warranty of any
  13  * kind, whether express or implied.
  14  */
  15
  16 /*
  17  * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
  18  * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
  19  * was based on skeletonfb.c, Skeleton for a frame buffer device by
  20  * Geert Uytterhoeven.
  21  */
  22
  23 #include <linux/device.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/errno.h>
  27 #include <linux/string.h>
  28 #include <linux/mm.h>
  29 #include <linux/fb.h>
  30 #include <linux/init.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_address.h>
  35 #include <linux/io.h>
  36 #include <linux/xilinxfb.h>
  37 #include <linux/slab.h>
  38
  39 #ifdef CONFIG_PPC_DCR
  40 #include <asm/dcr.h>
  41 #endif
  42
  43 #define DRIVER_NAME             "xilinxfb"
  44
  45
  46 /*
  47  * Xilinx calls it "TFT LCD Controller" though it can also be used for
  48  * the VGA port on the Xilinx ML40x board. This is a hardware display
  49  * controller for a 640x480 resolution TFT or VGA screen.
  50  *
  51  * The interface to the framebuffer is nice and simple.  There are two
  52  * control registers.  The first tells the LCD interface where in memory
  53  * the frame buffer is (only the 11 most significant bits are used, so
  54  * don't start thinking about scrolling).  The second allows the LCD to
  55  * be turned on or off as well as rotated 180 degrees.
  56  *
  57  * In case of direct BUS access the second control register will be at
  58  * an offset of 4 as compared to the DCR access where the offset is 1
  59  * i.e. REG_CTRL. So this is taken care in the function
  60  * xilinx_fb_out32 where it left shifts the offset 2 times in case of
  61  * direct BUS access.
  62  */
  63 #define NUM_REGS        2
  64 #define REG_FB_ADDR     0
  65 #define REG_CTRL        1
  66 #define REG_CTRL_ENABLE  0x0001
  67 #define REG_CTRL_ROTATE  0x0002
  68
  69 /*
  70  * The hardware only handles a single mode: 640x480 24 bit true
  71  * color. Each pixel gets a word (32 bits) of memory.  Within each word,
  72  * the 8 most significant bits are ignored, the next 8 bits are the red
  73  * level, the next 8 bits are the green level and the 8 least
  74  * significant bits are the blue level.  Each row of the LCD uses 1024
  75  * words, but only the first 640 pixels are displayed with the other 384
  76  * words being ignored.  There are 480 rows.
  77  */
  78 #define BYTES_PER_PIXEL 4
  79 #define BITS_PER_PIXEL  (BYTES_PER_PIXEL * 8)
  80
  81 #define RED_SHIFT       16
  82 #define GREEN_SHIFT     8
  83 #define BLUE_SHIFT      0
  84
  85 #define PALETTE_ENTRIES_NO      16      /* passed to fb_alloc_cmap() */
  86
  87 /*
  88  * Default xilinxfb configuration
  89  */
  90 static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
  91         .xres = 640,
  92         .yres = 480,
  93         .xvirt = 1024,
  94         .yvirt = 480,
  95 };
  96
  97 /*
  98  * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
  99  */
 100 static struct fb_fix_screeninfo xilinx_fb_fix = {
 101         .id =           "Xilinx",
 102         .type =         FB_TYPE_PACKED_PIXELS,
 103         .visual =       FB_VISUAL_TRUECOLOR,
 104         .accel =        FB_ACCEL_NONE
 105 };
 106
 107 static struct fb_var_screeninfo xilinx_fb_var = {
 108         .bits_per_pixel =       BITS_PER_PIXEL,
 109
 110         .red =          { RED_SHIFT, 8, 0 },
 111         .green =        { GREEN_SHIFT, 8, 0 },
 112         .blue =         { BLUE_SHIFT, 8, 0 },
 113         .transp =       { 0, 0, 0 },
 114
 115         .activate =     FB_ACTIVATE_NOW
 116 };
 117
 118
 119 #define BUS_ACCESS_FLAG         0x1 /* 1 = BUS, 0 = DCR */
 120 #define LITTLE_ENDIAN_ACCESS    0x2 /* LITTLE ENDIAN IO functions */
 121
 122 struct xilinxfb_drvdata {
 123
 124         struct fb_info  info;           /* FB driver info record */
 125
 126         phys_addr_t     regs_phys;      /* phys. address of the control
 127                                                 registers */
 128         void __iomem    *regs;          /* virt. address of the control
 129                                                 registers */
 130 #ifdef CONFIG_PPC_DCR
 131         dcr_host_t      dcr_host;
 132         unsigned int    dcr_len;
 133 #endif
 134         void            *fb_virt;       /* virt. address of the frame buffer */
 135         dma_addr_t      fb_phys;        /* phys. address of the frame buffer */
 136         int             fb_alloced;     /* Flag, was the fb memory alloced? */
 137
 138         u8              flags;          /* features of the driver */
 139
 140         u32             reg_ctrl_default;
 141
 142         u32             pseudo_palette[PALETTE_ENTRIES_NO];
 143                                         /* Fake palette of 16 colors */
 144 };
 145
 146 #define to_xilinxfb_drvdata(_info) \
 147         container_of(_info, struct xilinxfb_drvdata, info)
 148
 149 /*
 150  * The XPS TFT Controller can be accessed through BUS or DCR interface.
 151  * To perform the read/write on the registers we need to check on
 152  * which bus its connected and call the appropriate write API.
 153  */
 154 static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
 155                                 u32 val)
 156 {
 157         if (drvdata->flags & BUS_ACCESS_FLAG) {
 158                 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
 159                         iowrite32(val, drvdata->regs + (offset << 2));
 160                 else
 161                         iowrite32be(val, drvdata->regs + (offset << 2));
 162         }
 163 #ifdef CONFIG_PPC_DCR
 164         else
 165                 dcr_write(drvdata->dcr_host, offset, val);
 166 #endif
 167 }
 168
 169 static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
 170 {
 171         if (drvdata->flags & BUS_ACCESS_FLAG) {
 172                 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
 173                         return ioread32(drvdata->regs + (offset << 2));
 174                 else
 175                         return ioread32be(drvdata->regs + (offset << 2));
 176         }
 177 #ifdef CONFIG_PPC_DCR
 178         else
 179                 return dcr_read(drvdata->dcr_host, offset);
 180 #endif
 181         return 0;
 182 }
 183
 184 static int
 185 xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
 186         unsigned transp, struct fb_info *fbi)
 187 {
 188         u32 *palette = fbi->pseudo_palette;
 189
 190         if (regno >= PALETTE_ENTRIES_NO)
 191                 return -EINVAL;
 192
 193         if (fbi->var.grayscale) {
 194                 /* Convert color to grayscale.
 195                  * grayscale = 0.30*R + 0.59*G + 0.11*B */
 196                 red = green = blue =
 197                         (red * 77 + green * 151 + blue * 28 + 127) >> 8;
 198         }
 199
 200         /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
 201
 202         /* We only handle 8 bits of each color. */
 203         red >>= 8;
 204         green >>= 8;
 205         blue >>= 8;
 206         palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
 207                          (blue << BLUE_SHIFT);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
 214 {
 215         struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
 216
 217         switch (blank_mode) {
 218         case FB_BLANK_UNBLANK:
 219                 /* turn on panel */
 220                 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
 221                 break;
 222
 223         case FB_BLANK_NORMAL:
 224         case FB_BLANK_VSYNC_SUSPEND:
 225         case FB_BLANK_HSYNC_SUSPEND:
 226         case FB_BLANK_POWERDOWN:
 227                 /* turn off panel */
 228                 xilinx_fb_out32(drvdata, REG_CTRL, 0);
 229         default:
 230                 break;
 231
 232         }
 233         return 0; /* success */
 234 }
 235
 236 static struct fb_ops xilinxfb_ops =
 237 {
 238         .owner                  = THIS_MODULE,
 239         .fb_setcolreg           = xilinx_fb_setcolreg,
 240         .fb_blank               = xilinx_fb_blank,
 241         .fb_fillrect            = cfb_fillrect,
 242         .fb_copyarea            = cfb_copyarea,
 243         .fb_imageblit           = cfb_imageblit,
 244 };
 245
 246 /* ---------------------------------------------------------------------
 247  * Bus independent setup/teardown
 248  */
 249
 250 static int xilinxfb_assign(struct platform_device *pdev,
 251                            struct xilinxfb_drvdata *drvdata,
 252                            struct xilinxfb_platform_data *pdata)
 253 {
 254         int rc;
 255         struct device *dev = &pdev->dev;
 256         int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
 257
 258         if (drvdata->flags & BUS_ACCESS_FLAG) {
 259                 struct resource *res;
 260
 261                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 262                 drvdata->regs = devm_ioremap_resource(&pdev->dev, res);
 263                 if (IS_ERR(drvdata->regs))
 264                         return PTR_ERR(drvdata->regs);
 265
 266                 drvdata->regs_phys = res->start;
 267         }
 268
 269         /* Allocate the framebuffer memory */
 270         if (pdata->fb_phys) {
 271                 drvdata->fb_phys = pdata->fb_phys;
 272                 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
 273         } else {
 274                 drvdata->fb_alloced = 1;
 275                 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
 276                                         &drvdata->fb_phys, GFP_KERNEL);
 277         }
 278
 279         if (!drvdata->fb_virt) {
 280                 dev_err(dev, "Could not allocate frame buffer memory\n");
 281                 return -ENOMEM;
 282         }
 283
 284         /* Clear (turn to black) the framebuffer */
 285         memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
 286
 287         /* Tell the hardware where the frame buffer is */
 288         xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
 289         rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
 290         /* Endianess detection */
 291         if (rc != drvdata->fb_phys) {
 292                 drvdata->flags |= LITTLE_ENDIAN_ACCESS;
 293                 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
 294         }
 295
 296         /* Turn on the display */
 297         drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
 298         if (pdata->rotate_screen)
 299                 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
 300         xilinx_fb_out32(drvdata, REG_CTRL,
 301                                         drvdata->reg_ctrl_default);
 302
 303         /* Fill struct fb_info */
 304         drvdata->info.device = dev;
 305         drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
 306         drvdata->info.fbops = &xilinxfb_ops;
 307         drvdata->info.fix = xilinx_fb_fix;
 308         drvdata->info.fix.smem_start = drvdata->fb_phys;
 309         drvdata->info.fix.smem_len = fbsize;
 310         drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
 311
 312         drvdata->info.pseudo_palette = drvdata->pseudo_palette;
 313         drvdata->info.flags = FBINFO_DEFAULT;
 314         drvdata->info.var = xilinx_fb_var;
 315         drvdata->info.var.height = pdata->screen_height_mm;
 316         drvdata->info.var.width = pdata->screen_width_mm;
 317         drvdata->info.var.xres = pdata->xres;
 318         drvdata->info.var.yres = pdata->yres;
 319         drvdata->info.var.xres_virtual = pdata->xvirt;
 320         drvdata->info.var.yres_virtual = pdata->yvirt;
 321
 322         /* Allocate a colour map */
 323         rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
 324         if (rc) {
 325                 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
 326                         PALETTE_ENTRIES_NO);
 327                 goto err_cmap;
 328         }
 329
 330         /* Register new frame buffer */
 331         rc = register_framebuffer(&drvdata->info);
 332         if (rc) {
 333                 dev_err(dev, "Could not register frame buffer\n");
 334                 goto err_regfb;
 335         }
 336
 337         if (drvdata->flags & BUS_ACCESS_FLAG) {
 338                 /* Put a banner in the log (for DEBUG) */
 339                 dev_dbg(dev, "regs: phys=%pa, virt=%p\n",
 340                         &drvdata->regs_phys, drvdata->regs);
 341         }
 342         /* Put a banner in the log (for DEBUG) */
 343         dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
 344                 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
 345
 346         return 0;       /* success */
 347
 348 err_regfb:
 349         fb_dealloc_cmap(&drvdata->info.cmap);
 350
 351 err_cmap:
 352         if (drvdata->fb_alloced)
 353                 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
 354                         drvdata->fb_phys);
 355         else
 356                 iounmap(drvdata->fb_virt);
 357
 358         /* Turn off the display */
 359         xilinx_fb_out32(drvdata, REG_CTRL, 0);
 360
 361         return rc;
 362 }
 363
 364 static int xilinxfb_release(struct device *dev)
 365 {
 366         struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
 367
 368 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
 369         xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
 370 #endif
 371
 372         unregister_framebuffer(&drvdata->info);
 373
 374         fb_dealloc_cmap(&drvdata->info.cmap);
 375
 376         if (drvdata->fb_alloced)
 377                 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
 378                                   drvdata->fb_virt, drvdata->fb_phys);
 379         else
 380                 iounmap(drvdata->fb_virt);
 381
 382         /* Turn off the display */
 383         xilinx_fb_out32(drvdata, REG_CTRL, 0);
 384
 385 #ifdef CONFIG_PPC_DCR
 386         /* Release the resources, as allocated based on interface */
 387         if (!(drvdata->flags & BUS_ACCESS_FLAG))
 388                 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
 389 #endif
 390
 391         return 0;
 392 }
 393
 394 /* ---------------------------------------------------------------------
 395  * OF bus binding
 396  */
 397
 398 static int xilinxfb_of_probe(struct platform_device *pdev)
 399 {
 400         const u32 *prop;
 401         u32 tft_access = 0;
 402         struct xilinxfb_platform_data pdata;
 403         int size;
 404         struct xilinxfb_drvdata *drvdata;
 405
 406         /* Copy with the default pdata (not a ptr reference!) */
 407         pdata = xilinx_fb_default_pdata;
 408
 409         /* Allocate the driver data region */
 410         drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
 411         if (!drvdata)
 412                 return -ENOMEM;
 413
 414         /*
 415          * To check whether the core is connected directly to DCR or BUS
 416          * interface and initialize the tft_access accordingly.
 417          */
 418         of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if",
 419                              &tft_access);
 420
 421         /*
 422          * Fill the resource structure if its direct BUS interface
 423          * otherwise fill the dcr_host structure.
 424          */
 425         if (tft_access) {
 426                 drvdata->flags |= BUS_ACCESS_FLAG;
 427         }
 428 #ifdef CONFIG_PPC_DCR
 429         else {
 430                 int start;
 431                 start = dcr_resource_start(pdev->dev.of_node, 0);
 432                 drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0);
 433                 drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len);
 434                 if (!DCR_MAP_OK(drvdata->dcr_host)) {
 435                         dev_err(&pdev->dev, "invalid DCR address\n");
 436                         return -ENODEV;
 437                 }
 438         }
 439 #endif
 440
 441         prop = of_get_property(pdev->dev.of_node, "phys-size", &size);
 442         if ((prop) && (size >= sizeof(u32)*2)) {
 443                 pdata.screen_width_mm = prop[0];
 444                 pdata.screen_height_mm = prop[1];
 445         }
 446
 447         prop = of_get_property(pdev->dev.of_node, "resolution", &size);
 448         if ((prop) && (size >= sizeof(u32)*2)) {
 449                 pdata.xres = prop[0];
 450                 pdata.yres = prop[1];
 451         }
 452
 453         prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size);
 454         if ((prop) && (size >= sizeof(u32)*2)) {
 455                 pdata.xvirt = prop[0];
 456                 pdata.yvirt = prop[1];
 457         }
 458
 459         if (of_find_property(pdev->dev.of_node, "rotate-display", NULL))
 460                 pdata.rotate_screen = 1;
 461
 462         dev_set_drvdata(&pdev->dev, drvdata);
 463         return xilinxfb_assign(pdev, drvdata, &pdata);
 464 }
 465
 466 static int xilinxfb_of_remove(struct platform_device *op)
 467 {
 468         return xilinxfb_release(&op->dev);
 469 }
 470
 471 /* Match table for of_platform binding */
 472 static struct of_device_id xilinxfb_of_match[] = {
 473         { .compatible = "xlnx,xps-tft-1.00.a", },
 474         { .compatible = "xlnx,xps-tft-2.00.a", },
 475         { .compatible = "xlnx,xps-tft-2.01.a", },
 476         { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
 477         { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
 478         {},
 479 };
 480 MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
 481
 482 static struct platform_driver xilinxfb_of_driver = {
 483         .probe = xilinxfb_of_probe,
 484         .remove = xilinxfb_of_remove,
 485         .driver = {
 486                 .name = DRIVER_NAME,
 487                 .owner = THIS_MODULE,
 488                 .of_match_table = xilinxfb_of_match,
 489         },
 490 };
 491
 492 module_platform_driver(xilinxfb_of_driver);
 493
 494 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 495 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
 496 MODULE_LICENSE("GPL");