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w1: mxc_w1: Enable clock before calling clk_get_rate() on it
[mirror_ubuntu-bionic-kernel.git] / drivers / w1 / masters / mxc_w1.c
1 /*
2 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Luotao Fu, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/jiffies.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21
22 #include <linux/w1.h>
23
24 /*
25 * MXC W1 Register offsets
26 */
27 #define MXC_W1_CONTROL 0x00
28 # define MXC_W1_CONTROL_RDST BIT(3)
29 # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
30 # define MXC_W1_CONTROL_PST BIT(6)
31 # define MXC_W1_CONTROL_RPP BIT(7)
32 #define MXC_W1_TIME_DIVIDER 0x02
33 #define MXC_W1_RESET 0x04
34 # define MXC_W1_RESET_RST BIT(0)
35
36 struct mxc_w1_device {
37 void __iomem *regs;
38 struct clk *clk;
39 struct w1_bus_master bus_master;
40 };
41
42 /*
43 * this is the low level routine to
44 * reset the device on the One Wire interface
45 * on the hardware
46 */
47 static u8 mxc_w1_ds2_reset_bus(void *data)
48 {
49 struct mxc_w1_device *dev = data;
50 unsigned long timeout;
51
52 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
53
54 /* Wait for reset sequence 511+512us, use 1500us for sure */
55 timeout = jiffies + usecs_to_jiffies(1500);
56
57 udelay(511 + 512);
58
59 do {
60 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
61
62 /* PST bit is valid after the RPP bit is self-cleared */
63 if (!(ctrl & MXC_W1_CONTROL_RPP))
64 return !(ctrl & MXC_W1_CONTROL_PST);
65 } while (time_is_after_jiffies(timeout));
66
67 return 1;
68 }
69
70 /*
71 * this is the low level routine to read/write a bit on the One Wire
72 * interface on the hardware. It does write 0 if parameter bit is set
73 * to 0, otherwise a write 1/read.
74 */
75 static u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
76 {
77 struct mxc_w1_device *dev = data;
78 unsigned long timeout;
79
80 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
81
82 /* Wait for read/write bit (60us, Max 120us), use 200us for sure */
83 timeout = jiffies + usecs_to_jiffies(200);
84
85 udelay(60);
86
87 do {
88 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
89
90 /* RDST bit is valid after the WR1/RD bit is self-cleared */
91 if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
92 return !!(ctrl & MXC_W1_CONTROL_RDST);
93 } while (time_is_after_jiffies(timeout));
94
95 return 0;
96 }
97
98 static int mxc_w1_probe(struct platform_device *pdev)
99 {
100 struct mxc_w1_device *mdev;
101 unsigned long clkrate;
102 struct resource *res;
103 unsigned int clkdiv;
104 int err;
105
106 mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
107 GFP_KERNEL);
108 if (!mdev)
109 return -ENOMEM;
110
111 mdev->clk = devm_clk_get(&pdev->dev, NULL);
112 if (IS_ERR(mdev->clk))
113 return PTR_ERR(mdev->clk);
114
115 err = clk_prepare_enable(mdev->clk);
116 if (err)
117 return err;
118
119 clkrate = clk_get_rate(mdev->clk);
120 if (clkrate < 10000000)
121 dev_warn(&pdev->dev,
122 "Low clock frequency causes improper function\n");
123
124 clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
125 clkrate /= clkdiv;
126 if ((clkrate < 980000) || (clkrate > 1020000))
127 dev_warn(&pdev->dev,
128 "Incorrect time base frequency %lu Hz\n", clkrate);
129
130 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
131 mdev->regs = devm_ioremap_resource(&pdev->dev, res);
132 if (IS_ERR(mdev->regs)) {
133 err = PTR_ERR(mdev->regs);
134 goto out_disable_clk;
135 }
136
137 /* Software reset 1-Wire module */
138 writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
139 writeb(0, mdev->regs + MXC_W1_RESET);
140
141 writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
142
143 mdev->bus_master.data = mdev;
144 mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
145 mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
146
147 platform_set_drvdata(pdev, mdev);
148
149 err = w1_add_master_device(&mdev->bus_master);
150 if (err)
151 goto out_disable_clk;
152
153 return 0;
154
155 out_disable_clk:
156 clk_disable_unprepare(mdev->clk);
157 return err;
158 }
159
160 /*
161 * disassociate the w1 device from the driver
162 */
163 static int mxc_w1_remove(struct platform_device *pdev)
164 {
165 struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
166
167 w1_remove_master_device(&mdev->bus_master);
168
169 clk_disable_unprepare(mdev->clk);
170
171 return 0;
172 }
173
174 static const struct of_device_id mxc_w1_dt_ids[] = {
175 { .compatible = "fsl,imx21-owire" },
176 { /* sentinel */ }
177 };
178 MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
179
180 static struct platform_driver mxc_w1_driver = {
181 .driver = {
182 .name = "mxc_w1",
183 .of_match_table = mxc_w1_dt_ids,
184 },
185 .probe = mxc_w1_probe,
186 .remove = mxc_w1_remove,
187 };
188 module_platform_driver(mxc_w1_driver);
189
190 MODULE_LICENSE("GPL");
191 MODULE_AUTHOR("Freescale Semiconductors Inc");
192 MODULE_DESCRIPTION("Driver for One-Wire on MXC");