drivers/w1/w1_io.c

   1 /*
   2  *      w1_io.c
   3  *
   4  * Copyright (c) 2004 Evgeniy Polyakov <zbr@ioremap.net>
   5  *
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21
  22 #include <asm/io.h>
  23
  24 #include <linux/delay.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/module.h>
  27
  28 #include "w1.h"
  29 #include "w1_log.h"
  30
  31 static int w1_delay_parm = 1;
  32 module_param_named(delay_coef, w1_delay_parm, int, 0);
  33
  34 static u8 w1_crc8_table[] = {
  35         0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
  36         157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
  37         35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
  38         190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
  39         70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
  40         219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
  41         101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
  42         248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
  43         140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
  44         17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
  45         175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
  46         50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
  47         202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
  48         87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
  49         233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
  50         116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
  51 };
  52
  53 static void w1_delay(unsigned long tm)
  54 {
  55         udelay(tm * w1_delay_parm);
  56 }
  57
  58 static void w1_write_bit(struct w1_master *dev, int bit);
  59 static u8 w1_read_bit(struct w1_master *dev);
  60
  61 /**
  62  * Generates a write-0 or write-1 cycle and samples the level.
  63  */
  64 static u8 w1_touch_bit(struct w1_master *dev, int bit)
  65 {
  66         if (dev->bus_master->touch_bit)
  67                 return dev->bus_master->touch_bit(dev->bus_master->data, bit);
  68         else if (bit)
  69                 return w1_read_bit(dev);
  70         else {
  71                 w1_write_bit(dev, 0);
  72                 return 0;
  73         }
  74 }
  75
  76 /**
  77  * Generates a write-0 or write-1 cycle.
  78  * Only call if dev->bus_master->touch_bit is NULL
  79  */
  80 static void w1_write_bit(struct w1_master *dev, int bit)
  81 {
  82         if (bit) {
  83                 dev->bus_master->write_bit(dev->bus_master->data, 0);
  84                 w1_delay(6);
  85                 dev->bus_master->write_bit(dev->bus_master->data, 1);
  86                 w1_delay(64);
  87         } else {
  88                 dev->bus_master->write_bit(dev->bus_master->data, 0);
  89                 w1_delay(60);
  90                 dev->bus_master->write_bit(dev->bus_master->data, 1);
  91                 w1_delay(10);
  92         }
  93 }
  94
  95 /**
  96  * Pre-write operation, currently only supporting strong pullups.
  97  * Program the hardware for a strong pullup, if one has been requested and
  98  * the hardware supports it.
  99  *
 100  * @param dev     the master device
 101  */
 102 static void w1_pre_write(struct w1_master *dev)
 103 {
 104         if (dev->pullup_duration &&
 105                 dev->enable_pullup && dev->bus_master->set_pullup) {
 106                 dev->bus_master->set_pullup(dev->bus_master->data,
 107                         dev->pullup_duration);
 108         }
 109 }
 110
 111 /**
 112  * Post-write operation, currently only supporting strong pullups.
 113  * If a strong pullup was requested, clear it if the hardware supports
 114  * them, or execute the delay otherwise, in either case clear the request.
 115  *
 116  * @param dev     the master device
 117  */
 118 static void w1_post_write(struct w1_master *dev)
 119 {
 120         if (dev->pullup_duration) {
 121                 if (dev->enable_pullup && dev->bus_master->set_pullup)
 122                         dev->bus_master->set_pullup(dev->bus_master->data, 0);
 123                 else
 124                         msleep(dev->pullup_duration);
 125                 dev->pullup_duration = 0;
 126         }
 127 }
 128
 129 /**
 130  * Writes 8 bits.
 131  *
 132  * @param dev     the master device
 133  * @param byte    the byte to write
 134  */
 135 void w1_write_8(struct w1_master *dev, u8 byte)
 136 {
 137         int i;
 138
 139         if (dev->bus_master->write_byte) {
 140                 w1_pre_write(dev);
 141                 dev->bus_master->write_byte(dev->bus_master->data, byte);
 142         }
 143         else
 144                 for (i = 0; i < 8; ++i) {
 145                         if (i == 7)
 146                                 w1_pre_write(dev);
 147                         w1_touch_bit(dev, (byte >> i) & 0x1);
 148                 }
 149         w1_post_write(dev);
 150 }
 151 EXPORT_SYMBOL_GPL(w1_write_8);
 152
 153
 154 /**
 155  * Generates a write-1 cycle and samples the level.
 156  * Only call if dev->bus_master->touch_bit is NULL
 157  */
 158 static u8 w1_read_bit(struct w1_master *dev)
 159 {
 160         int result;
 161         unsigned long flags;
 162
 163         /* sample timing is critical here */
 164         local_irq_save(flags);
 165         dev->bus_master->write_bit(dev->bus_master->data, 0);
 166         w1_delay(6);
 167         dev->bus_master->write_bit(dev->bus_master->data, 1);
 168         w1_delay(9);
 169
 170         result = dev->bus_master->read_bit(dev->bus_master->data);
 171         local_irq_restore(flags);
 172
 173         w1_delay(55);
 174
 175         return result & 0x1;
 176 }
 177
 178 /**
 179  * Does a triplet - used for searching ROM addresses.
 180  * Return bits:
 181  *  bit 0 = id_bit
 182  *  bit 1 = comp_bit
 183  *  bit 2 = dir_taken
 184  * If both bits 0 & 1 are set, the search should be restarted.
 185  *
 186  * @param dev     the master device
 187  * @param bdir    the bit to write if both id_bit and comp_bit are 0
 188  * @return        bit fields - see above
 189  */
 190 u8 w1_triplet(struct w1_master *dev, int bdir)
 191 {
 192         if (dev->bus_master->triplet)
 193                 return dev->bus_master->triplet(dev->bus_master->data, bdir);
 194         else {
 195                 u8 id_bit   = w1_touch_bit(dev, 1);
 196                 u8 comp_bit = w1_touch_bit(dev, 1);
 197                 u8 retval;
 198
 199                 if (id_bit && comp_bit)
 200                         return 0x03;  /* error */
 201
 202                 if (!id_bit && !comp_bit) {
 203                         /* Both bits are valid, take the direction given */
 204                         retval = bdir ? 0x04 : 0;
 205                 } else {
 206                         /* Only one bit is valid, take that direction */
 207                         bdir = id_bit;
 208                         retval = id_bit ? 0x05 : 0x02;
 209                 }
 210
 211                 if (dev->bus_master->touch_bit)
 212                         w1_touch_bit(dev, bdir);
 213                 else
 214                         w1_write_bit(dev, bdir);
 215                 return retval;
 216         }
 217 }
 218
 219 /**
 220  * Reads 8 bits.
 221  *
 222  * @param dev     the master device
 223  * @return        the byte read
 224  */
 225 u8 w1_read_8(struct w1_master *dev)
 226 {
 227         int i;
 228         u8 res = 0;
 229
 230         if (dev->bus_master->read_byte)
 231                 res = dev->bus_master->read_byte(dev->bus_master->data);
 232         else
 233                 for (i = 0; i < 8; ++i)
 234                         res |= (w1_touch_bit(dev,1) << i);
 235
 236         return res;
 237 }
 238 EXPORT_SYMBOL_GPL(w1_read_8);
 239
 240 /**
 241  * Writes a series of bytes.
 242  *
 243  * @param dev     the master device
 244  * @param buf     pointer to the data to write
 245  * @param len     the number of bytes to write
 246  */
 247 void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
 248 {
 249         int i;
 250
 251         if (dev->bus_master->write_block) {
 252                 w1_pre_write(dev);
 253                 dev->bus_master->write_block(dev->bus_master->data, buf, len);
 254         }
 255         else
 256                 for (i = 0; i < len; ++i)
 257                         w1_write_8(dev, buf[i]); /* calls w1_pre_write */
 258         w1_post_write(dev);
 259 }
 260 EXPORT_SYMBOL_GPL(w1_write_block);
 261
 262 /**
 263  * Touches a series of bytes.
 264  *
 265  * @param dev     the master device
 266  * @param buf     pointer to the data to write
 267  * @param len     the number of bytes to write
 268  */
 269 void w1_touch_block(struct w1_master *dev, u8 *buf, int len)
 270 {
 271         int i, j;
 272         u8 tmp;
 273
 274         for (i = 0; i < len; ++i) {
 275                 tmp = 0;
 276                 for (j = 0; j < 8; ++j) {
 277                         if (j == 7)
 278                                 w1_pre_write(dev);
 279                         tmp |= w1_touch_bit(dev, (buf[i] >> j) & 0x1) << j;
 280                 }
 281
 282                 buf[i] = tmp;
 283         }
 284 }
 285 EXPORT_SYMBOL_GPL(w1_touch_block);
 286
 287 /**
 288  * Reads a series of bytes.
 289  *
 290  * @param dev     the master device
 291  * @param buf     pointer to the buffer to fill
 292  * @param len     the number of bytes to read
 293  * @return        the number of bytes read
 294  */
 295 u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
 296 {
 297         int i;
 298         u8 ret;
 299
 300         if (dev->bus_master->read_block)
 301                 ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
 302         else {
 303                 for (i = 0; i < len; ++i)
 304                         buf[i] = w1_read_8(dev);
 305                 ret = len;
 306         }
 307
 308         return ret;
 309 }
 310 EXPORT_SYMBOL_GPL(w1_read_block);
 311
 312 /**
 313  * Issues a reset bus sequence.
 314  *
 315  * @param  dev The bus master pointer
 316  * @return     0=Device present, 1=No device present or error
 317  */
 318 int w1_reset_bus(struct w1_master *dev)
 319 {
 320         int result;
 321
 322         if (dev->bus_master->reset_bus)
 323                 result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
 324         else {
 325                 dev->bus_master->write_bit(dev->bus_master->data, 0);
 326                 /* minimum 480, max ? us
 327                  * be nice and sleep, except 18b20 spec lists 960us maximum,
 328                  * so until we can sleep with microsecond accuracy, spin.
 329                  * Feel free to come up with some other way to give up the
 330                  * cpu for such a short amount of time AND get it back in
 331                  * the maximum amount of time.
 332                  */
 333                 w1_delay(480);
 334                 dev->bus_master->write_bit(dev->bus_master->data, 1);
 335                 w1_delay(70);
 336
 337                 result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
 338                 /* minmum 70 (above) + 410 = 480 us
 339                  * There aren't any timing requirements between a reset and
 340                  * the following transactions.  Sleeping is safe here.
 341                  */
 342                 /* w1_delay(410); min required time */
 343                 msleep(1);
 344         }
 345
 346         return result;
 347 }
 348 EXPORT_SYMBOL_GPL(w1_reset_bus);
 349
 350 u8 w1_calc_crc8(u8 * data, int len)
 351 {
 352         u8 crc = 0;
 353
 354         while (len--)
 355                 crc = w1_crc8_table[crc ^ *data++];
 356
 357         return crc;
 358 }
 359 EXPORT_SYMBOL_GPL(w1_calc_crc8);
 360
 361 void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
 362 {
 363         dev->attempts++;
 364         if (dev->bus_master->search)
 365                 dev->bus_master->search(dev->bus_master->data, dev,
 366                         search_type, cb);
 367         else
 368                 w1_search(dev, search_type, cb);
 369 }
 370
 371 /**
 372  * Resets the bus and then selects the slave by sending either a skip rom
 373  * or a rom match.
 374  * The w1 master lock must be held.
 375  *
 376  * @param sl    the slave to select
 377  * @return      0=success, anything else=error
 378  */
 379 int w1_reset_select_slave(struct w1_slave *sl)
 380 {
 381         if (w1_reset_bus(sl->master))
 382                 return -1;
 383
 384         if (sl->master->slave_count == 1)
 385                 w1_write_8(sl->master, W1_SKIP_ROM);
 386         else {
 387                 u8 match[9] = {W1_MATCH_ROM, };
 388                 u64 rn = le64_to_cpu(*((u64*)&sl->reg_num));
 389
 390                 memcpy(&match[1], &rn, 8);
 391                 w1_write_block(sl->master, match, 9);
 392         }
 393         return 0;
 394 }
 395 EXPORT_SYMBOL_GPL(w1_reset_select_slave);
 396
 397 /**
 398  * When the workflow with a slave amongst many requires several
 399  * successive commands a reset between each, this function is similar
 400  * to doing a reset then a match ROM for the last matched ROM. The
 401  * advantage being that the matched ROM step is skipped in favor of the
 402  * resume command. The slave must support the command of course.
 403  *
 404  * If the bus has only one slave, traditionnaly the match ROM is skipped
 405  * and a "SKIP ROM" is done for efficiency. On multi-slave busses, this
 406  * doesn't work of course, but the resume command is the next best thing.
 407  *
 408  * The w1 master lock must be held.
 409  *
 410  * @param dev     the master device
 411  */
 412 int w1_reset_resume_command(struct w1_master *dev)
 413 {
 414         if (w1_reset_bus(dev))
 415                 return -1;
 416
 417         /* This will make only the last matched slave perform a skip ROM. */
 418         w1_write_8(dev, W1_RESUME_CMD);
 419         return 0;
 420 }
 421 EXPORT_SYMBOL_GPL(w1_reset_resume_command);
 422
 423 /**
 424  * Put out a strong pull-up of the specified duration after the next write
 425  * operation.  Not all hardware supports strong pullups.  Hardware that
 426  * doesn't support strong pullups will sleep for the given time after the
 427  * write operation without a strong pullup.  This is a one shot request for
 428  * the next write, specifying zero will clear a previous request.
 429  * The w1 master lock must be held.
 430  *
 431  * @param delay time in milliseconds
 432  * @return      0=success, anything else=error
 433  */
 434 void w1_next_pullup(struct w1_master *dev, int delay)
 435 {
 436         dev->pullup_duration = delay;
 437 }
 438 EXPORT_SYMBOL_GPL(w1_next_pullup);