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1 /*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 * document number TBD : Patsburg (PBG)
37 * document number TBD : DH89xxCC
38 * document number TBD : Panther Point
39 * document number TBD : Lynx Point
40 * document number TBD : Lynx Point-LP
41 */
42
43 /*
44 * Includes, defines, variables, module parameters, ...
45 */
46
47 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
48
49 /* Module and version information */
50 #define DRV_NAME "iTCO_wdt"
51 #define DRV_VERSION "1.11"
52
53 /* Includes */
54 #include <linux/acpi.h> /* For ACPI support */
55 #include <linux/module.h> /* For module specific items */
56 #include <linux/moduleparam.h> /* For new moduleparam's */
57 #include <linux/types.h> /* For standard types (like size_t) */
58 #include <linux/errno.h> /* For the -ENODEV/... values */
59 #include <linux/kernel.h> /* For printk/panic/... */
60 #include <linux/watchdog.h> /* For the watchdog specific items */
61 #include <linux/init.h> /* For __init/__exit/... */
62 #include <linux/fs.h> /* For file operations */
63 #include <linux/platform_device.h> /* For platform_driver framework */
64 #include <linux/pci.h> /* For pci functions */
65 #include <linux/ioport.h> /* For io-port access */
66 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
67 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
68 #include <linux/io.h> /* For inb/outb/... */
69 #include <linux/platform_data/itco_wdt.h>
70
71 #include "iTCO_vendor.h"
72
73 /* Address definitions for the TCO */
74 /* TCO base address */
75 #define TCOBASE(p) ((p)->tco_res->start)
76 /* SMI Control and Enable Register */
77 #define SMI_EN(p) ((p)->smi_res->start)
78
79 #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
80 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
81 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
82 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
83 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
84 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
85 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
86 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
87 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
88
89 /* internal variables */
90 struct iTCO_wdt_private {
91 struct watchdog_device wddev;
92
93 /* TCO version/generation */
94 unsigned int iTCO_version;
95 struct resource *tco_res;
96 struct resource *smi_res;
97 /*
98 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
99 * or memory-mapped PMC register bit 4 (TCO version 3).
100 */
101 struct resource *gcs_pmc_res;
102 unsigned long __iomem *gcs_pmc;
103 /* the lock for io operations */
104 spinlock_t io_lock;
105 struct platform_device *dev;
106 /* the PCI-device */
107 struct pci_dev *pdev;
108 /* whether or not the watchdog has been suspended */
109 bool suspended;
110 };
111
112 /* module parameters */
113 #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
114 static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
115 module_param(heartbeat, int, 0);
116 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
117 "5..76 (TCO v1) or 3..614 (TCO v2), default="
118 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
119
120 static bool nowayout = WATCHDOG_NOWAYOUT;
121 module_param(nowayout, bool, 0);
122 MODULE_PARM_DESC(nowayout,
123 "Watchdog cannot be stopped once started (default="
124 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
125
126 static int turn_SMI_watchdog_clear_off = 1;
127 module_param(turn_SMI_watchdog_clear_off, int, 0);
128 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
129 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
130
131 /*
132 * Some TCO specific functions
133 */
134
135 /*
136 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
137 * every 0.6 seconds. v3's internal timer is stored as seconds (some
138 * datasheets incorrectly state 0.6 seconds).
139 */
140 static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
141 int secs)
142 {
143 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
144 }
145
146 static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
147 int ticks)
148 {
149 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
150 }
151
152 static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
153 {
154 u32 enable_bit;
155
156 switch (p->iTCO_version) {
157 case 5:
158 case 3:
159 enable_bit = 0x00000010;
160 break;
161 case 2:
162 enable_bit = 0x00000020;
163 break;
164 case 4:
165 case 1:
166 default:
167 enable_bit = 0x00000002;
168 break;
169 }
170
171 return enable_bit;
172 }
173
174 static void iTCO_wdt_set_NO_REBOOT_bit(struct iTCO_wdt_private *p)
175 {
176 u32 val32;
177
178 /* Set the NO_REBOOT bit: this disables reboots */
179 if (p->iTCO_version >= 2) {
180 val32 = readl(p->gcs_pmc);
181 val32 |= no_reboot_bit(p);
182 writel(val32, p->gcs_pmc);
183 } else if (p->iTCO_version == 1) {
184 pci_read_config_dword(p->pdev, 0xd4, &val32);
185 val32 |= no_reboot_bit(p);
186 pci_write_config_dword(p->pdev, 0xd4, val32);
187 }
188 }
189
190 static int iTCO_wdt_unset_NO_REBOOT_bit(struct iTCO_wdt_private *p)
191 {
192 u32 enable_bit = no_reboot_bit(p);
193 u32 val32 = 0;
194
195 /* Unset the NO_REBOOT bit: this enables reboots */
196 if (p->iTCO_version >= 2) {
197 val32 = readl(p->gcs_pmc);
198 val32 &= ~enable_bit;
199 writel(val32, p->gcs_pmc);
200
201 val32 = readl(p->gcs_pmc);
202 } else if (p->iTCO_version == 1) {
203 pci_read_config_dword(p->pdev, 0xd4, &val32);
204 val32 &= ~enable_bit;
205 pci_write_config_dword(p->pdev, 0xd4, val32);
206
207 pci_read_config_dword(p->pdev, 0xd4, &val32);
208 }
209
210 if (val32 & enable_bit)
211 return -EIO;
212
213 return 0;
214 }
215
216 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
217 {
218 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
219 unsigned int val;
220
221 spin_lock(&p->io_lock);
222
223 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
224
225 /* disable chipset's NO_REBOOT bit */
226 if (iTCO_wdt_unset_NO_REBOOT_bit(p)) {
227 spin_unlock(&p->io_lock);
228 pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
229 return -EIO;
230 }
231
232 /* Force the timer to its reload value by writing to the TCO_RLD
233 register */
234 if (p->iTCO_version >= 2)
235 outw(0x01, TCO_RLD(p));
236 else if (p->iTCO_version == 1)
237 outb(0x01, TCO_RLD(p));
238
239 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
240 val = inw(TCO1_CNT(p));
241 val &= 0xf7ff;
242 outw(val, TCO1_CNT(p));
243 val = inw(TCO1_CNT(p));
244 spin_unlock(&p->io_lock);
245
246 if (val & 0x0800)
247 return -1;
248 return 0;
249 }
250
251 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
252 {
253 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
254 unsigned int val;
255
256 spin_lock(&p->io_lock);
257
258 iTCO_vendor_pre_stop(p->smi_res);
259
260 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
261 val = inw(TCO1_CNT(p));
262 val |= 0x0800;
263 outw(val, TCO1_CNT(p));
264 val = inw(TCO1_CNT(p));
265
266 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
267 iTCO_wdt_set_NO_REBOOT_bit(p);
268
269 spin_unlock(&p->io_lock);
270
271 if ((val & 0x0800) == 0)
272 return -1;
273 return 0;
274 }
275
276 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
277 {
278 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
279
280 spin_lock(&p->io_lock);
281
282 iTCO_vendor_pre_keepalive(p->smi_res, wd_dev->timeout);
283
284 /* Reload the timer by writing to the TCO Timer Counter register */
285 if (p->iTCO_version >= 2) {
286 outw(0x01, TCO_RLD(p));
287 } else if (p->iTCO_version == 1) {
288 /* Reset the timeout status bit so that the timer
289 * needs to count down twice again before rebooting */
290 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
291
292 outb(0x01, TCO_RLD(p));
293 }
294
295 spin_unlock(&p->io_lock);
296 return 0;
297 }
298
299 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
300 {
301 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
302 unsigned int val16;
303 unsigned char val8;
304 unsigned int tmrval;
305
306 tmrval = seconds_to_ticks(p, t);
307
308 /* For TCO v1 the timer counts down twice before rebooting */
309 if (p->iTCO_version == 1)
310 tmrval /= 2;
311
312 /* from the specs: */
313 /* "Values of 0h-3h are ignored and should not be attempted" */
314 if (tmrval < 0x04)
315 return -EINVAL;
316 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
317 (p->iTCO_version == 1 && tmrval > 0x03f))
318 return -EINVAL;
319
320 iTCO_vendor_pre_set_heartbeat(tmrval);
321
322 /* Write new heartbeat to watchdog */
323 if (p->iTCO_version >= 2) {
324 spin_lock(&p->io_lock);
325 val16 = inw(TCOv2_TMR(p));
326 val16 &= 0xfc00;
327 val16 |= tmrval;
328 outw(val16, TCOv2_TMR(p));
329 val16 = inw(TCOv2_TMR(p));
330 spin_unlock(&p->io_lock);
331
332 if ((val16 & 0x3ff) != tmrval)
333 return -EINVAL;
334 } else if (p->iTCO_version == 1) {
335 spin_lock(&p->io_lock);
336 val8 = inb(TCOv1_TMR(p));
337 val8 &= 0xc0;
338 val8 |= (tmrval & 0xff);
339 outb(val8, TCOv1_TMR(p));
340 val8 = inb(TCOv1_TMR(p));
341 spin_unlock(&p->io_lock);
342
343 if ((val8 & 0x3f) != tmrval)
344 return -EINVAL;
345 }
346
347 wd_dev->timeout = t;
348 return 0;
349 }
350
351 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
352 {
353 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
354 unsigned int val16;
355 unsigned char val8;
356 unsigned int time_left = 0;
357
358 /* read the TCO Timer */
359 if (p->iTCO_version >= 2) {
360 spin_lock(&p->io_lock);
361 val16 = inw(TCO_RLD(p));
362 val16 &= 0x3ff;
363 spin_unlock(&p->io_lock);
364
365 time_left = ticks_to_seconds(p, val16);
366 } else if (p->iTCO_version == 1) {
367 spin_lock(&p->io_lock);
368 val8 = inb(TCO_RLD(p));
369 val8 &= 0x3f;
370 if (!(inw(TCO1_STS(p)) & 0x0008))
371 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
372 spin_unlock(&p->io_lock);
373
374 time_left = ticks_to_seconds(p, val8);
375 }
376 return time_left;
377 }
378
379 /*
380 * Kernel Interfaces
381 */
382
383 static const struct watchdog_info ident = {
384 .options = WDIOF_SETTIMEOUT |
385 WDIOF_KEEPALIVEPING |
386 WDIOF_MAGICCLOSE,
387 .firmware_version = 0,
388 .identity = DRV_NAME,
389 };
390
391 static const struct watchdog_ops iTCO_wdt_ops = {
392 .owner = THIS_MODULE,
393 .start = iTCO_wdt_start,
394 .stop = iTCO_wdt_stop,
395 .ping = iTCO_wdt_ping,
396 .set_timeout = iTCO_wdt_set_timeout,
397 .get_timeleft = iTCO_wdt_get_timeleft,
398 };
399
400 /*
401 * Init & exit routines
402 */
403
404 static void iTCO_wdt_cleanup(struct iTCO_wdt_private *p)
405 {
406 /* Stop the timer before we leave */
407 if (!nowayout)
408 iTCO_wdt_stop(&p->wddev);
409
410 /* Deregister */
411 watchdog_unregister_device(&p->wddev);
412
413 /* release resources */
414 release_region(p->tco_res->start,
415 resource_size(p->tco_res));
416 release_region(p->smi_res->start,
417 resource_size(p->smi_res));
418 if (p->iTCO_version >= 2) {
419 iounmap(p->gcs_pmc);
420 release_mem_region(p->gcs_pmc_res->start,
421 resource_size(p->gcs_pmc_res));
422 }
423 }
424
425 static int iTCO_wdt_probe(struct platform_device *dev)
426 {
427 struct itco_wdt_platform_data *pdata = dev_get_platdata(&dev->dev);
428 struct iTCO_wdt_private *p;
429 unsigned long val32;
430 int ret;
431
432 if (!pdata)
433 return -ENODEV;
434
435 p = devm_kzalloc(&dev->dev, sizeof(*p), GFP_KERNEL);
436 if (!p)
437 return -ENOMEM;
438
439 spin_lock_init(&p->io_lock);
440
441 p->tco_res = platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
442 if (!p->tco_res)
443 return -ENODEV;
444
445 p->smi_res = platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
446 if (!p->smi_res)
447 return -ENODEV;
448
449 p->iTCO_version = pdata->version;
450 p->dev = dev;
451 p->pdev = to_pci_dev(dev->dev.parent);
452
453 /*
454 * Get the Memory-Mapped GCS or PMC register, we need it for the
455 * NO_REBOOT flag (TCO v2 and v3).
456 */
457 if (p->iTCO_version >= 2) {
458 p->gcs_pmc_res = platform_get_resource(dev,
459 IORESOURCE_MEM,
460 ICH_RES_MEM_GCS_PMC);
461
462 if (!p->gcs_pmc_res)
463 return -ENODEV;
464
465 if (!request_mem_region(p->gcs_pmc_res->start,
466 resource_size(p->gcs_pmc_res),
467 dev->name))
468 return -EBUSY;
469
470 p->gcs_pmc = ioremap(p->gcs_pmc_res->start,
471 resource_size(p->gcs_pmc_res));
472 if (!p->gcs_pmc) {
473 ret = -EIO;
474 goto unreg_gcs_pmc;
475 }
476 }
477
478 /* Check chipset's NO_REBOOT bit */
479 if (iTCO_wdt_unset_NO_REBOOT_bit(p) &&
480 iTCO_vendor_check_noreboot_on()) {
481 pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
482 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
483 goto unmap_gcs_pmc;
484 }
485
486 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
487 iTCO_wdt_set_NO_REBOOT_bit(p);
488
489 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
490 if (!request_region(p->smi_res->start,
491 resource_size(p->smi_res), dev->name)) {
492 pr_err("I/O address 0x%04llx already in use, device disabled\n",
493 (u64)SMI_EN(p));
494 ret = -EBUSY;
495 goto unmap_gcs_pmc;
496 }
497 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
498 /*
499 * Bit 13: TCO_EN -> 0
500 * Disables TCO logic generating an SMI#
501 */
502 val32 = inl(SMI_EN(p));
503 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
504 outl(val32, SMI_EN(p));
505 }
506
507 if (!request_region(p->tco_res->start,
508 resource_size(p->tco_res), dev->name)) {
509 pr_err("I/O address 0x%04llx already in use, device disabled\n",
510 (u64)TCOBASE(p));
511 ret = -EBUSY;
512 goto unreg_smi;
513 }
514
515 pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
516 pdata->name, pdata->version, (u64)TCOBASE(p));
517
518 /* Clear out the (probably old) status */
519 switch (p->iTCO_version) {
520 case 5:
521 case 4:
522 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
523 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
524 break;
525 case 3:
526 outl(0x20008, TCO1_STS(p));
527 break;
528 case 2:
529 case 1:
530 default:
531 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
532 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
533 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
534 break;
535 }
536
537 p->wddev.info = &ident,
538 p->wddev.ops = &iTCO_wdt_ops,
539 p->wddev.bootstatus = 0;
540 p->wddev.timeout = WATCHDOG_TIMEOUT;
541 watchdog_set_nowayout(&p->wddev, nowayout);
542 p->wddev.parent = &dev->dev;
543
544 watchdog_set_drvdata(&p->wddev, p);
545 platform_set_drvdata(dev, p);
546
547 /* Make sure the watchdog is not running */
548 iTCO_wdt_stop(&p->wddev);
549
550 /* Check that the heartbeat value is within it's range;
551 if not reset to the default */
552 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
553 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
554 pr_info("timeout value out of range, using %d\n",
555 WATCHDOG_TIMEOUT);
556 }
557
558 ret = watchdog_register_device(&p->wddev);
559 if (ret != 0) {
560 pr_err("cannot register watchdog device (err=%d)\n", ret);
561 goto unreg_tco;
562 }
563
564 pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
565 heartbeat, nowayout);
566
567 return 0;
568
569 unreg_tco:
570 release_region(p->tco_res->start, resource_size(p->tco_res));
571 unreg_smi:
572 release_region(p->smi_res->start, resource_size(p->smi_res));
573 unmap_gcs_pmc:
574 if (p->iTCO_version >= 2)
575 iounmap(p->gcs_pmc);
576 unreg_gcs_pmc:
577 if (p->iTCO_version >= 2)
578 release_mem_region(p->gcs_pmc_res->start,
579 resource_size(p->gcs_pmc_res));
580 return ret;
581 }
582
583 static int iTCO_wdt_remove(struct platform_device *dev)
584 {
585 struct iTCO_wdt_private *p = platform_get_drvdata(dev);
586
587 if (p->tco_res || p->smi_res)
588 iTCO_wdt_cleanup(p);
589
590 return 0;
591 }
592
593 static void iTCO_wdt_shutdown(struct platform_device *dev)
594 {
595 struct iTCO_wdt_private *p = platform_get_drvdata(dev);
596
597 iTCO_wdt_stop(&p->wddev);
598 }
599
600 #ifdef CONFIG_PM_SLEEP
601 /*
602 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
603 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
604 * watchdog is stopped by the platform firmware.
605 */
606
607 #ifdef CONFIG_ACPI
608 static inline bool need_suspend(void)
609 {
610 return acpi_target_system_state() == ACPI_STATE_S0;
611 }
612 #else
613 static inline bool need_suspend(void) { return true; }
614 #endif
615
616 static int iTCO_wdt_suspend_noirq(struct device *dev)
617 {
618 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
619 int ret = 0;
620
621 p->suspended = false;
622 if (watchdog_active(&p->wddev) && need_suspend()) {
623 ret = iTCO_wdt_stop(&p->wddev);
624 if (!ret)
625 p->suspended = true;
626 }
627 return ret;
628 }
629
630 static int iTCO_wdt_resume_noirq(struct device *dev)
631 {
632 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
633
634 if (p->suspended)
635 iTCO_wdt_start(&p->wddev);
636
637 return 0;
638 }
639
640 static const struct dev_pm_ops iTCO_wdt_pm = {
641 .suspend_noirq = iTCO_wdt_suspend_noirq,
642 .resume_noirq = iTCO_wdt_resume_noirq,
643 };
644
645 #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
646 #else
647 #define ITCO_WDT_PM_OPS NULL
648 #endif /* CONFIG_PM_SLEEP */
649
650 static struct platform_driver iTCO_wdt_driver = {
651 .probe = iTCO_wdt_probe,
652 .remove = iTCO_wdt_remove,
653 .shutdown = iTCO_wdt_shutdown,
654 .driver = {
655 .name = DRV_NAME,
656 .pm = ITCO_WDT_PM_OPS,
657 },
658 };
659
660 static int __init iTCO_wdt_init_module(void)
661 {
662 int err;
663
664 pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
665
666 err = platform_driver_register(&iTCO_wdt_driver);
667 if (err)
668 return err;
669
670 return 0;
671 }
672
673 static void __exit iTCO_wdt_cleanup_module(void)
674 {
675 platform_driver_unregister(&iTCO_wdt_driver);
676 pr_info("Watchdog Module Unloaded\n");
677 }
678
679 module_init(iTCO_wdt_init_module);
680 module_exit(iTCO_wdt_cleanup_module);
681
682 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
683 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
684 MODULE_VERSION(DRV_VERSION);
685 MODULE_LICENSE("GPL");
686 MODULE_ALIAS("platform:" DRV_NAME);