2 * IBM Automatic Server Restart driver.
4 * Copyright (c) 2005 Andrey Panin <pazke@donpac.ru>
6 * Based on driver written by Pete Reynolds.
7 * Copyright (c) IBM Corporation, 1998-2004.
9 * This software may be used and distributed according to the terms
10 * of the GNU Public License, incorporated herein by reference.
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/timer.h>
19 #include <linux/miscdevice.h>
20 #include <linux/watchdog.h>
21 #include <linux/dmi.h>
23 #include <linux/uaccess.h>
35 #define PFX "ibmasr: "
37 #define TOPAZ_ASR_REG_OFFSET 4
38 #define TOPAZ_ASR_TOGGLE 0x40
39 #define TOPAZ_ASR_DISABLE 0x80
41 /* PEARL ASR S/W REGISTER SUPERIO PORT ADDRESSES */
42 #define PEARL_BASE 0xe04
43 #define PEARL_WRITE 0xe06
44 #define PEARL_READ 0xe07
46 #define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
47 #define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
49 /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
50 #define JASPER_ASR_REG_OFFSET 0x38
52 #define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
53 #define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
55 #define JUNIPER_BASE_ADDRESS 0x54b /* Base address of Juniper ASR */
56 #define JUNIPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1 enable = 0 */
57 #define JUNIPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
59 #define SPRUCE_BASE_ADDRESS 0x118e /* Base address of Spruce ASR */
60 #define SPRUCE_ASR_DISABLE_MASK 0x01 /* bit 1: disable = 1 enable = 0 */
61 #define SPRUCE_ASR_TOGGLE_MASK 0x02 /* bit 0: 0, then 1, then 0 */
64 static int nowayout
= WATCHDOG_NOWAYOUT
;
66 static unsigned long asr_is_open
;
67 static char asr_expect_close
;
69 static unsigned int asr_type
, asr_base
, asr_length
;
70 static unsigned int asr_read_addr
, asr_write_addr
;
71 static unsigned char asr_toggle_mask
, asr_disable_mask
;
72 static spinlock_t asr_lock
;
74 static void __asr_toggle(void)
78 reg
= inb(asr_read_addr
);
80 outb(reg
& ~asr_toggle_mask
, asr_write_addr
);
81 reg
= inb(asr_read_addr
);
83 outb(reg
| asr_toggle_mask
, asr_write_addr
);
84 reg
= inb(asr_read_addr
);
86 outb(reg
& ~asr_toggle_mask
, asr_write_addr
);
87 reg
= inb(asr_read_addr
);
88 spin_unlock(&asr_lock
);
91 static void asr_toggle(void)
95 spin_unlock(&asr_lock
);
98 static void asr_enable(void)
102 spin_lock(&asr_lock
);
103 if (asr_type
== ASMTYPE_TOPAZ
) {
104 /* asr_write_addr == asr_read_addr */
105 reg
= inb(asr_read_addr
);
106 outb(reg
& ~(TOPAZ_ASR_TOGGLE
| TOPAZ_ASR_DISABLE
),
110 * First make sure the hardware timer is reset by toggling
111 * ASR hardware timer line.
115 reg
= inb(asr_read_addr
);
116 outb(reg
& ~asr_disable_mask
, asr_write_addr
);
118 reg
= inb(asr_read_addr
);
119 spin_unlock(&asr_lock
);
122 static void asr_disable(void)
126 spin_lock(&asr_lock
);
127 reg
= inb(asr_read_addr
);
129 if (asr_type
== ASMTYPE_TOPAZ
)
130 /* asr_write_addr == asr_read_addr */
131 outb(reg
| TOPAZ_ASR_TOGGLE
| TOPAZ_ASR_DISABLE
,
134 outb(reg
| asr_toggle_mask
, asr_write_addr
);
135 reg
= inb(asr_read_addr
);
137 outb(reg
| asr_disable_mask
, asr_write_addr
);
139 reg
= inb(asr_read_addr
);
140 spin_unlock(&asr_lock
);
143 static int __init
asr_get_base_address(void)
145 unsigned char low
, high
;
146 const char *type
= "";
152 /* SELECT SuperIO CHIP FOR QUERYING
153 (WRITE 0x07 TO BOTH 0x2E and 0x2F) */
157 /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */
161 /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */
165 asr_base
= (high
<< 16) | low
;
166 asr_read_addr
= asr_write_addr
=
167 asr_base
+ TOPAZ_ASR_REG_OFFSET
;
177 pdev
= pci_get_bus_and_slot(0, DEVFN(0x1f, 0));
180 pci_read_config_dword(pdev
, 0x58, &r
);
181 asr_base
= r
& 0xFFFE;
184 /* FIXME: need to use pci_config_lock here,
185 but it's not exported */
187 /* spin_lock_irqsave(&pci_config_lock, flags);*/
189 /* Select the SuperIO chip in the PCI I/O port register */
190 outl(0x8000f858, 0xcf8);
192 /* BUS 0, Slot 1F, fnc 0, offset 58 */
195 * Read the base address for the SuperIO chip.
196 * Only the lower 16 bits are valid, but the address is word
197 * aligned so the last bit must be masked off.
199 asr_base
= inl(0xcfc) & 0xfffe;
201 /* spin_unlock_irqrestore(&pci_config_lock, flags);*/
203 asr_read_addr
= asr_write_addr
=
204 asr_base
+ JASPER_ASR_REG_OFFSET
;
205 asr_toggle_mask
= JASPER_ASR_TOGGLE_MASK
;
206 asr_disable_mask
= JASPER_ASR_DISABLE_MASK
;
207 asr_length
= JASPER_ASR_REG_OFFSET
+ 1;
213 asr_base
= PEARL_BASE
;
214 asr_read_addr
= PEARL_READ
;
215 asr_write_addr
= PEARL_WRITE
;
216 asr_toggle_mask
= PEARL_ASR_TOGGLE_MASK
;
217 asr_disable_mask
= PEARL_ASR_DISABLE_MASK
;
221 case ASMTYPE_JUNIPER
:
223 asr_base
= JUNIPER_BASE_ADDRESS
;
224 asr_read_addr
= asr_write_addr
= asr_base
;
225 asr_toggle_mask
= JUNIPER_ASR_TOGGLE_MASK
;
226 asr_disable_mask
= JUNIPER_ASR_DISABLE_MASK
;
231 asr_base
= SPRUCE_BASE_ADDRESS
;
232 asr_read_addr
= asr_write_addr
= asr_base
;
233 asr_toggle_mask
= SPRUCE_ASR_TOGGLE_MASK
;
234 asr_disable_mask
= SPRUCE_ASR_DISABLE_MASK
;
238 if (!request_region(asr_base
, asr_length
, "ibmasr")) {
239 printk(KERN_ERR PFX
"address %#x already in use\n",
244 printk(KERN_INFO PFX
"found %sASR @ addr %#x\n", type
, asr_base
);
250 static ssize_t
asr_write(struct file
*file
, const char __user
*buf
,
251 size_t count
, loff_t
*ppos
)
257 /* In case it was set long ago */
258 asr_expect_close
= 0;
260 for (i
= 0; i
!= count
; i
++) {
262 if (get_user(c
, buf
+ i
))
265 asr_expect_close
= 42;
273 static long asr_ioctl(struct file
*file
, unsigned int cmd
, unsigned long arg
)
275 static const struct watchdog_info ident
= {
276 .options
= WDIOF_KEEPALIVEPING
|
278 .identity
= "IBM ASR",
280 void __user
*argp
= (void __user
*)arg
;
281 int __user
*p
= argp
;
285 case WDIOC_GETSUPPORT
:
286 return copy_to_user(argp
, &ident
, sizeof(ident
)) ? -EFAULT
: 0;
287 case WDIOC_GETSTATUS
:
288 case WDIOC_GETBOOTSTATUS
:
289 return put_user(0, p
);
290 case WDIOC_SETOPTIONS
:
292 int new_options
, retval
= -EINVAL
;
293 if (get_user(new_options
, p
))
295 if (new_options
& WDIOS_DISABLECARD
) {
299 if (new_options
& WDIOS_ENABLECARD
) {
306 case WDIOC_KEEPALIVE
:
310 * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT
311 * and WDIOC_GETTIMEOUT always returns 256.
313 case WDIOC_GETTIMEOUT
:
315 return put_user(heartbeat
, p
);
321 static int asr_open(struct inode
*inode
, struct file
*file
)
323 if (test_and_set_bit(0, &asr_is_open
))
329 return nonseekable_open(inode
, file
);
332 static int asr_release(struct inode
*inode
, struct file
*file
)
334 if (asr_expect_close
== 42)
338 "unexpected close, not stopping watchdog!\n");
341 clear_bit(0, &asr_is_open
);
342 asr_expect_close
= 0;
346 static const struct file_operations asr_fops
= {
347 .owner
= THIS_MODULE
,
350 .unlocked_ioctl
= asr_ioctl
,
352 .release
= asr_release
,
355 static struct miscdevice asr_miscdev
= {
356 .minor
= WATCHDOG_MINOR
,
367 static struct ibmasr_id __initdata ibmasr_id_table
[] = {
368 { "IBM Automatic Server Restart - eserver xSeries 220", ASMTYPE_TOPAZ
},
369 { "IBM Automatic Server Restart - Machine Type 8673", ASMTYPE_PEARL
},
370 { "IBM Automatic Server Restart - Machine Type 8480", ASMTYPE_JASPER
},
371 { "IBM Automatic Server Restart - Machine Type 8482", ASMTYPE_JUNIPER
},
372 { "IBM Automatic Server Restart - Machine Type 8648", ASMTYPE_SPRUCE
},
376 static int __init
ibmasr_init(void)
378 struct ibmasr_id
*id
;
381 for (id
= ibmasr_id_table
; id
->desc
; id
++) {
382 if (dmi_find_device(DMI_DEV_TYPE_OTHER
, id
->desc
, NULL
)) {
391 spin_lock_init(&asr_lock
);
393 rc
= asr_get_base_address();
397 rc
= misc_register(&asr_miscdev
);
399 release_region(asr_base
, asr_length
);
400 printk(KERN_ERR PFX
"failed to register misc device\n");
407 static void __exit
ibmasr_exit(void)
412 misc_deregister(&asr_miscdev
);
414 release_region(asr_base
, asr_length
);
417 module_init(ibmasr_init
);
418 module_exit(ibmasr_exit
);
420 module_param(nowayout
, int, 0);
421 MODULE_PARM_DESC(nowayout
,
422 "Watchdog cannot be stopped once started (default="
423 __MODULE_STRING(WATCHDOG_NOWAYOUT
) ")");
425 MODULE_DESCRIPTION("IBM Automatic Server Restart driver");
426 MODULE_AUTHOR("Andrey Panin");
427 MODULE_LICENSE("GPL");
428 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR
);