drivers/watchdog/intel_scu_watchdog.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *      Intel_SCU 0.2:  An Intel SCU IOH Based Watchdog Device
   4  *                      for Intel part #(s):
   5  *                              - AF82MP20 PCH
   6  *
   7  *      Copyright (C) 2009-2010 Intel Corporation. All rights reserved.
   8  */
   9
  10 #ifndef __INTEL_SCU_WATCHDOG_H
  11 #define __INTEL_SCU_WATCHDOG_H
  12
  13 #define WDT_VER "0.3"
  14
  15 /* minimum time between interrupts */
  16 #define MIN_TIME_CYCLE 1
  17
  18 /* Time from warning to reboot is 2 seconds */
  19 #define DEFAULT_SOFT_TO_HARD_MARGIN 2
  20
  21 #define MAX_TIME 170
  22
  23 #define DEFAULT_TIME 5
  24
  25 #define MAX_SOFT_TO_HARD_MARGIN (MAX_TIME-MIN_TIME_CYCLE)
  26
  27 /* Ajustment to clock tick frequency to make timing come out right */
  28 #define FREQ_ADJUSTMENT 8
  29
  30 struct intel_scu_watchdog_dev {
  31         ulong driver_open;
  32         ulong driver_closed;
  33         u32 timer_started;
  34         u32 timer_set;
  35         u32 threshold;
  36         u32 soft_threshold;
  37         u32 __iomem *timer_load_count_addr;
  38         u32 __iomem *timer_current_value_addr;
  39         u32 __iomem *timer_control_addr;
  40         u32 __iomem *timer_clear_interrupt_addr;
  41         u32 __iomem *timer_interrupt_status_addr;
  42         struct sfi_timer_table_entry *timer_tbl_ptr;
  43         struct notifier_block intel_scu_notifier;
  44         struct miscdevice miscdev;
  45 };
  46
  47 extern int sfi_mtimer_num;
  48
  49 /* extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint); */
  50 #endif /* __INTEL_SCU_WATCHDOG_H */