drivers/watchdog/lantiq_wdt.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
   7  *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
   8  *  Based on EP93xx wdt driver
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/bitops.h>
  13 #include <linux/watchdog.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/uaccess.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/regmap.h>
  19 #include <linux/mfd/syscon.h>
  20
  21 #include <lantiq_soc.h>
  22
  23 #define LTQ_XRX_RCU_RST_STAT            0x0014
  24 #define LTQ_XRX_RCU_RST_STAT_WDT        BIT(31)
  25
  26 /* CPU0 Reset Source Register */
  27 #define LTQ_FALCON_SYS1_CPU0RS          0x0060
  28 /* reset cause mask */
  29 #define LTQ_FALCON_SYS1_CPU0RS_MASK     0x0007
  30 #define LTQ_FALCON_SYS1_CPU0RS_WDT      0x02
  31
  32 /*
  33  * Section 3.4 of the datasheet
  34  * The password sequence protects the WDT control register from unintended
  35  * write actions, which might cause malfunction of the WDT.
  36  *
  37  * essentially the following two magic passwords need to be written to allow
  38  * IO access to the WDT core
  39  */
  40 #define LTQ_WDT_CR_PW1          0x00BE0000
  41 #define LTQ_WDT_CR_PW2          0x00DC0000
  42
  43 #define LTQ_WDT_CR              0x0             /* watchdog control register */
  44 #define  LTQ_WDT_CR_GEN         BIT(31)         /* enable bit */
  45 /* Pre-warning limit set to 1/16 of max WDT period */
  46 #define  LTQ_WDT_CR_PWL         (0x3 << 26)
  47 /* set clock divider to 0x40000 */
  48 #define  LTQ_WDT_CR_CLKDIV      (0x3 << 24)
  49 #define  LTQ_WDT_CR_PW_MASK     GENMASK(23, 16) /* Password field */
  50 #define  LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
  51 #define LTQ_WDT_SR              0x8             /* watchdog status register */
  52 #define  LTQ_WDT_SR_EN          BIT(31)         /* Enable */
  53 #define  LTQ_WDT_SR_VALUE_MASK  GENMASK(15, 0)  /* Timer value */
  54
  55 #define LTQ_WDT_DIVIDER         0x40000
  56
  57 static bool nowayout = WATCHDOG_NOWAYOUT;
  58
  59 struct ltq_wdt_hw {
  60         int (*bootstatus_get)(struct device *dev);
  61 };
  62
  63 struct ltq_wdt_priv {
  64         struct watchdog_device wdt;
  65         void __iomem *membase;
  66         unsigned long clk_rate;
  67 };
  68
  69 static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
  70 {
  71         return __raw_readl(priv->membase + offset);
  72 }
  73
  74 static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
  75 {
  76         __raw_writel(val, priv->membase + offset);
  77 }
  78
  79 static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
  80                          u32 offset)
  81 {
  82         u32 val = ltq_wdt_r32(priv, offset);
  83
  84         val &= ~(clear);
  85         val |= set;
  86         ltq_wdt_w32(priv, val, offset);
  87 }
  88
  89 static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
  90 {
  91         return container_of(wdt, struct ltq_wdt_priv, wdt);
  92 }
  93
  94 static struct watchdog_info ltq_wdt_info = {
  95         .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  96                    WDIOF_CARDRESET,
  97         .identity = "ltq_wdt",
  98 };
  99
 100 static int ltq_wdt_start(struct watchdog_device *wdt)
 101 {
 102         struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 103         u32 timeout;
 104
 105         timeout = wdt->timeout * priv->clk_rate;
 106
 107         ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
 108         /* write the second magic plus the configuration and new timeout */
 109         ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
 110                      LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
 111                      LTQ_WDT_CR_PW2 | timeout,
 112                      LTQ_WDT_CR);
 113
 114         return 0;
 115 }
 116
 117 static int ltq_wdt_stop(struct watchdog_device *wdt)
 118 {
 119         struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 120
 121         ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
 122         ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
 123                      LTQ_WDT_CR_PW2, LTQ_WDT_CR);
 124
 125         return 0;
 126 }
 127
 128 static int ltq_wdt_ping(struct watchdog_device *wdt)
 129 {
 130         struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 131         u32 timeout;
 132
 133         timeout = wdt->timeout * priv->clk_rate;
 134
 135         ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
 136         /* write the second magic plus the configuration and new timeout */
 137         ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
 138                      LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
 139
 140         return 0;
 141 }
 142
 143 static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
 144 {
 145         struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 146         u64 timeout;
 147
 148         timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
 149         return do_div(timeout, priv->clk_rate);
 150 }
 151
 152 static const struct watchdog_ops ltq_wdt_ops = {
 153         .owner          = THIS_MODULE,
 154         .start          = ltq_wdt_start,
 155         .stop           = ltq_wdt_stop,
 156         .ping           = ltq_wdt_ping,
 157         .get_timeleft   = ltq_wdt_get_timeleft,
 158 };
 159
 160 static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
 161 {
 162         struct regmap *rcu_regmap;
 163         u32 val;
 164         int err;
 165
 166         rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
 167         if (IS_ERR(rcu_regmap))
 168                 return PTR_ERR(rcu_regmap);
 169
 170         err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
 171         if (err)
 172                 return err;
 173
 174         if (val & LTQ_XRX_RCU_RST_STAT_WDT)
 175                 return WDIOF_CARDRESET;
 176
 177         return 0;
 178 }
 179
 180 static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
 181 {
 182         struct regmap *rcu_regmap;
 183         u32 val;
 184         int err;
 185
 186         rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
 187                                                      "lantiq,rcu");
 188         if (IS_ERR(rcu_regmap))
 189                 return PTR_ERR(rcu_regmap);
 190
 191         err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
 192         if (err)
 193                 return err;
 194
 195         if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
 196                 return WDIOF_CARDRESET;
 197
 198         return 0;
 199 }
 200
 201 static int ltq_wdt_probe(struct platform_device *pdev)
 202 {
 203         struct device *dev = &pdev->dev;
 204         struct ltq_wdt_priv *priv;
 205         struct watchdog_device *wdt;
 206         struct clk *clk;
 207         const struct ltq_wdt_hw *ltq_wdt_hw;
 208         int ret;
 209         u32 status;
 210
 211         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 212         if (!priv)
 213                 return -ENOMEM;
 214
 215         priv->membase = devm_platform_ioremap_resource(pdev, 0);
 216         if (IS_ERR(priv->membase))
 217                 return PTR_ERR(priv->membase);
 218
 219         /* we do not need to enable the clock as it is always running */
 220         clk = clk_get_io();
 221         priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
 222         if (!priv->clk_rate) {
 223                 dev_err(dev, "clock rate less than divider %i\n",
 224                         LTQ_WDT_DIVIDER);
 225                 return -EINVAL;
 226         }
 227
 228         wdt = &priv->wdt;
 229         wdt->info               = &ltq_wdt_info;
 230         wdt->ops                = &ltq_wdt_ops;
 231         wdt->min_timeout        = 1;
 232         wdt->max_timeout        = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
 233         wdt->timeout            = wdt->max_timeout;
 234         wdt->parent             = dev;
 235
 236         ltq_wdt_hw = of_device_get_match_data(dev);
 237         if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
 238                 ret = ltq_wdt_hw->bootstatus_get(dev);
 239                 if (ret >= 0)
 240                         wdt->bootstatus = ret;
 241         }
 242
 243         watchdog_set_nowayout(wdt, nowayout);
 244         watchdog_init_timeout(wdt, 0, dev);
 245
 246         status = ltq_wdt_r32(priv, LTQ_WDT_SR);
 247         if (status & LTQ_WDT_SR_EN) {
 248                 /*
 249                  * If the watchdog is already running overwrite it with our
 250                  * new settings. Stop is not needed as the start call will
 251                  * replace all settings anyway.
 252                  */
 253                 ltq_wdt_start(wdt);
 254                 set_bit(WDOG_HW_RUNNING, &wdt->status);
 255         }
 256
 257         return devm_watchdog_register_device(dev, wdt);
 258 }
 259
 260 static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
 261         .bootstatus_get = ltq_wdt_xrx_bootstatus_get,
 262 };
 263
 264 static const struct ltq_wdt_hw ltq_wdt_falcon = {
 265         .bootstatus_get = ltq_wdt_falcon_bootstatus_get,
 266 };
 267
 268 static const struct of_device_id ltq_wdt_match[] = {
 269         { .compatible = "lantiq,wdt", .data = NULL },
 270         { .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
 271         { .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
 272         {},
 273 };
 274 MODULE_DEVICE_TABLE(of, ltq_wdt_match);
 275
 276 static struct platform_driver ltq_wdt_driver = {
 277         .probe = ltq_wdt_probe,
 278         .driver = {
 279                 .name = "wdt",
 280                 .of_match_table = ltq_wdt_match,
 281         },
 282 };
 283
 284 module_platform_driver(ltq_wdt_driver);
 285
 286 module_param(nowayout, bool, 0);
 287 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
 288 MODULE_AUTHOR("John Crispin <john@phrozen.org>");
 289 MODULE_DESCRIPTION("Lantiq SoC Watchdog");
 290 MODULE_LICENSE("GPL");