1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek Watchdog Driver
5 * Copyright (C) 2014 Matthias Brugger
7 * Matthias Brugger <matthias.bgg@gmail.com>
12 #include <dt-bindings/reset-controller/mt2712-resets.h>
13 #include <dt-bindings/reset-controller/mt8183-resets.h>
14 #include <dt-bindings/reset-controller/mt8192-resets.h>
15 #include <dt-bindings/reset/mt8195-resets.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset-controller.h>
27 #include <linux/types.h>
28 #include <linux/watchdog.h>
29 #include <linux/interrupt.h>
31 #define WDT_MAX_TIMEOUT 31
32 #define WDT_MIN_TIMEOUT 2
33 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
35 #define WDT_LENGTH 0x04
36 #define WDT_LENGTH_KEY 0x8
39 #define WDT_RST_RELOAD 0x1971
42 #define WDT_MODE_EN (1 << 0)
43 #define WDT_MODE_EXT_POL_LOW (0 << 1)
44 #define WDT_MODE_EXT_POL_HIGH (1 << 1)
45 #define WDT_MODE_EXRST_EN (1 << 2)
46 #define WDT_MODE_IRQ_EN (1 << 3)
47 #define WDT_MODE_AUTO_START (1 << 4)
48 #define WDT_MODE_DUAL_EN (1 << 6)
49 #define WDT_MODE_KEY 0x22000000
51 #define WDT_SWRST 0x14
52 #define WDT_SWRST_KEY 0x1209
54 #define WDT_SWSYSRST 0x18U
55 #define WDT_SWSYS_RST_KEY 0x88000000
57 #define DRV_NAME "mtk-wdt"
58 #define DRV_VERSION "1.0"
60 static bool nowayout
= WATCHDOG_NOWAYOUT
;
61 static unsigned int timeout
;
64 struct watchdog_device wdt_dev
;
65 void __iomem
*wdt_base
;
66 spinlock_t lock
; /* protects WDT_SWSYSRST reg */
67 struct reset_controller_dev rcdev
;
71 int toprgu_sw_rst_num
;
74 static const struct mtk_wdt_data mt2712_data
= {
75 .toprgu_sw_rst_num
= MT2712_TOPRGU_SW_RST_NUM
,
78 static const struct mtk_wdt_data mt8183_data
= {
79 .toprgu_sw_rst_num
= MT8183_TOPRGU_SW_RST_NUM
,
82 static const struct mtk_wdt_data mt8192_data
= {
83 .toprgu_sw_rst_num
= MT8192_TOPRGU_SW_RST_NUM
,
86 static const struct mtk_wdt_data mt8195_data
= {
87 .toprgu_sw_rst_num
= MT8195_TOPRGU_SW_RST_NUM
,
90 static int toprgu_reset_update(struct reset_controller_dev
*rcdev
,
91 unsigned long id
, bool assert)
95 struct mtk_wdt_dev
*data
=
96 container_of(rcdev
, struct mtk_wdt_dev
, rcdev
);
98 spin_lock_irqsave(&data
->lock
, flags
);
100 tmp
= readl(data
->wdt_base
+ WDT_SWSYSRST
);
105 tmp
|= WDT_SWSYS_RST_KEY
;
106 writel(tmp
, data
->wdt_base
+ WDT_SWSYSRST
);
108 spin_unlock_irqrestore(&data
->lock
, flags
);
113 static int toprgu_reset_assert(struct reset_controller_dev
*rcdev
,
116 return toprgu_reset_update(rcdev
, id
, true);
119 static int toprgu_reset_deassert(struct reset_controller_dev
*rcdev
,
122 return toprgu_reset_update(rcdev
, id
, false);
125 static int toprgu_reset(struct reset_controller_dev
*rcdev
,
130 ret
= toprgu_reset_assert(rcdev
, id
);
134 return toprgu_reset_deassert(rcdev
, id
);
137 static const struct reset_control_ops toprgu_reset_ops
= {
138 .assert = toprgu_reset_assert
,
139 .deassert
= toprgu_reset_deassert
,
140 .reset
= toprgu_reset
,
143 static int toprgu_register_reset_controller(struct platform_device
*pdev
,
147 struct mtk_wdt_dev
*mtk_wdt
= platform_get_drvdata(pdev
);
149 spin_lock_init(&mtk_wdt
->lock
);
151 mtk_wdt
->rcdev
.owner
= THIS_MODULE
;
152 mtk_wdt
->rcdev
.nr_resets
= rst_num
;
153 mtk_wdt
->rcdev
.ops
= &toprgu_reset_ops
;
154 mtk_wdt
->rcdev
.of_node
= pdev
->dev
.of_node
;
155 ret
= devm_reset_controller_register(&pdev
->dev
, &mtk_wdt
->rcdev
);
158 "couldn't register wdt reset controller: %d\n", ret
);
162 static int mtk_wdt_restart(struct watchdog_device
*wdt_dev
,
163 unsigned long action
, void *data
)
165 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdt_dev
);
166 void __iomem
*wdt_base
;
168 wdt_base
= mtk_wdt
->wdt_base
;
171 writel(WDT_SWRST_KEY
, wdt_base
+ WDT_SWRST
);
178 static int mtk_wdt_ping(struct watchdog_device
*wdt_dev
)
180 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdt_dev
);
181 void __iomem
*wdt_base
= mtk_wdt
->wdt_base
;
183 iowrite32(WDT_RST_RELOAD
, wdt_base
+ WDT_RST
);
188 static int mtk_wdt_set_timeout(struct watchdog_device
*wdt_dev
,
189 unsigned int timeout
)
191 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdt_dev
);
192 void __iomem
*wdt_base
= mtk_wdt
->wdt_base
;
195 wdt_dev
->timeout
= timeout
;
197 * In dual mode, irq will be triggered at timeout / 2
198 * the real timeout occurs at timeout
200 if (wdt_dev
->pretimeout
)
201 wdt_dev
->pretimeout
= timeout
/ 2;
204 * One bit is the value of 512 ticks
205 * The clock has 32 KHz
207 reg
= WDT_LENGTH_TIMEOUT((timeout
- wdt_dev
->pretimeout
) << 6)
209 iowrite32(reg
, wdt_base
+ WDT_LENGTH
);
211 mtk_wdt_ping(wdt_dev
);
216 static void mtk_wdt_init(struct watchdog_device
*wdt_dev
)
218 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdt_dev
);
219 void __iomem
*wdt_base
;
221 wdt_base
= mtk_wdt
->wdt_base
;
223 if (readl(wdt_base
+ WDT_MODE
) & WDT_MODE_EN
) {
224 set_bit(WDOG_HW_RUNNING
, &wdt_dev
->status
);
225 mtk_wdt_set_timeout(wdt_dev
, wdt_dev
->timeout
);
229 static int mtk_wdt_stop(struct watchdog_device
*wdt_dev
)
231 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdt_dev
);
232 void __iomem
*wdt_base
= mtk_wdt
->wdt_base
;
235 reg
= readl(wdt_base
+ WDT_MODE
);
238 iowrite32(reg
, wdt_base
+ WDT_MODE
);
243 static int mtk_wdt_start(struct watchdog_device
*wdt_dev
)
246 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdt_dev
);
247 void __iomem
*wdt_base
= mtk_wdt
->wdt_base
;
250 ret
= mtk_wdt_set_timeout(wdt_dev
, wdt_dev
->timeout
);
254 reg
= ioread32(wdt_base
+ WDT_MODE
);
255 if (wdt_dev
->pretimeout
)
256 reg
|= (WDT_MODE_IRQ_EN
| WDT_MODE_DUAL_EN
);
258 reg
&= ~(WDT_MODE_IRQ_EN
| WDT_MODE_DUAL_EN
);
259 reg
|= (WDT_MODE_EN
| WDT_MODE_KEY
);
260 iowrite32(reg
, wdt_base
+ WDT_MODE
);
265 static int mtk_wdt_set_pretimeout(struct watchdog_device
*wdd
,
266 unsigned int timeout
)
268 struct mtk_wdt_dev
*mtk_wdt
= watchdog_get_drvdata(wdd
);
269 void __iomem
*wdt_base
= mtk_wdt
->wdt_base
;
270 u32 reg
= ioread32(wdt_base
+ WDT_MODE
);
272 if (timeout
&& !wdd
->pretimeout
) {
273 wdd
->pretimeout
= wdd
->timeout
/ 2;
274 reg
|= (WDT_MODE_IRQ_EN
| WDT_MODE_DUAL_EN
);
275 } else if (!timeout
&& wdd
->pretimeout
) {
277 reg
&= ~(WDT_MODE_IRQ_EN
| WDT_MODE_DUAL_EN
);
283 iowrite32(reg
, wdt_base
+ WDT_MODE
);
285 return mtk_wdt_set_timeout(wdd
, wdd
->timeout
);
288 static irqreturn_t
mtk_wdt_isr(int irq
, void *arg
)
290 struct watchdog_device
*wdd
= arg
;
292 watchdog_notify_pretimeout(wdd
);
297 static const struct watchdog_info mtk_wdt_info
= {
298 .identity
= DRV_NAME
,
299 .options
= WDIOF_SETTIMEOUT
|
300 WDIOF_KEEPALIVEPING
|
304 static const struct watchdog_info mtk_wdt_pt_info
= {
305 .identity
= DRV_NAME
,
306 .options
= WDIOF_SETTIMEOUT
|
308 WDIOF_KEEPALIVEPING
|
312 static const struct watchdog_ops mtk_wdt_ops
= {
313 .owner
= THIS_MODULE
,
314 .start
= mtk_wdt_start
,
315 .stop
= mtk_wdt_stop
,
316 .ping
= mtk_wdt_ping
,
317 .set_timeout
= mtk_wdt_set_timeout
,
318 .set_pretimeout
= mtk_wdt_set_pretimeout
,
319 .restart
= mtk_wdt_restart
,
322 static int mtk_wdt_probe(struct platform_device
*pdev
)
324 struct device
*dev
= &pdev
->dev
;
325 struct mtk_wdt_dev
*mtk_wdt
;
326 const struct mtk_wdt_data
*wdt_data
;
329 mtk_wdt
= devm_kzalloc(dev
, sizeof(*mtk_wdt
), GFP_KERNEL
);
333 platform_set_drvdata(pdev
, mtk_wdt
);
335 mtk_wdt
->wdt_base
= devm_platform_ioremap_resource(pdev
, 0);
336 if (IS_ERR(mtk_wdt
->wdt_base
))
337 return PTR_ERR(mtk_wdt
->wdt_base
);
339 irq
= platform_get_irq(pdev
, 0);
341 err
= devm_request_irq(&pdev
->dev
, irq
, mtk_wdt_isr
, 0, "wdt_bark",
346 mtk_wdt
->wdt_dev
.info
= &mtk_wdt_pt_info
;
347 mtk_wdt
->wdt_dev
.pretimeout
= WDT_MAX_TIMEOUT
/ 2;
349 if (irq
== -EPROBE_DEFER
)
350 return -EPROBE_DEFER
;
352 mtk_wdt
->wdt_dev
.info
= &mtk_wdt_info
;
355 mtk_wdt
->wdt_dev
.ops
= &mtk_wdt_ops
;
356 mtk_wdt
->wdt_dev
.timeout
= WDT_MAX_TIMEOUT
;
357 mtk_wdt
->wdt_dev
.max_hw_heartbeat_ms
= WDT_MAX_TIMEOUT
* 1000;
358 mtk_wdt
->wdt_dev
.min_timeout
= WDT_MIN_TIMEOUT
;
359 mtk_wdt
->wdt_dev
.parent
= dev
;
361 watchdog_init_timeout(&mtk_wdt
->wdt_dev
, timeout
, dev
);
362 watchdog_set_nowayout(&mtk_wdt
->wdt_dev
, nowayout
);
363 watchdog_set_restart_priority(&mtk_wdt
->wdt_dev
, 128);
365 watchdog_set_drvdata(&mtk_wdt
->wdt_dev
, mtk_wdt
);
367 mtk_wdt_init(&mtk_wdt
->wdt_dev
);
369 watchdog_stop_on_reboot(&mtk_wdt
->wdt_dev
);
370 err
= devm_watchdog_register_device(dev
, &mtk_wdt
->wdt_dev
);
374 dev_info(dev
, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
375 mtk_wdt
->wdt_dev
.timeout
, nowayout
);
377 wdt_data
= of_device_get_match_data(dev
);
379 err
= toprgu_register_reset_controller(pdev
,
380 wdt_data
->toprgu_sw_rst_num
);
387 #ifdef CONFIG_PM_SLEEP
388 static int mtk_wdt_suspend(struct device
*dev
)
390 struct mtk_wdt_dev
*mtk_wdt
= dev_get_drvdata(dev
);
392 if (watchdog_active(&mtk_wdt
->wdt_dev
))
393 mtk_wdt_stop(&mtk_wdt
->wdt_dev
);
398 static int mtk_wdt_resume(struct device
*dev
)
400 struct mtk_wdt_dev
*mtk_wdt
= dev_get_drvdata(dev
);
402 if (watchdog_active(&mtk_wdt
->wdt_dev
)) {
403 mtk_wdt_start(&mtk_wdt
->wdt_dev
);
404 mtk_wdt_ping(&mtk_wdt
->wdt_dev
);
411 static const struct of_device_id mtk_wdt_dt_ids
[] = {
412 { .compatible
= "mediatek,mt2712-wdt", .data
= &mt2712_data
},
413 { .compatible
= "mediatek,mt6589-wdt" },
414 { .compatible
= "mediatek,mt8183-wdt", .data
= &mt8183_data
},
415 { .compatible
= "mediatek,mt8192-wdt", .data
= &mt8192_data
},
416 { .compatible
= "mediatek,mt8195-wdt", .data
= &mt8195_data
},
419 MODULE_DEVICE_TABLE(of
, mtk_wdt_dt_ids
);
421 static const struct dev_pm_ops mtk_wdt_pm_ops
= {
422 SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend
,
426 static struct platform_driver mtk_wdt_driver
= {
427 .probe
= mtk_wdt_probe
,
430 .pm
= &mtk_wdt_pm_ops
,
431 .of_match_table
= mtk_wdt_dt_ids
,
435 module_platform_driver(mtk_wdt_driver
);
437 module_param(timeout
, uint
, 0);
438 MODULE_PARM_DESC(timeout
, "Watchdog heartbeat in seconds");
440 module_param(nowayout
, bool, 0);
441 MODULE_PARM_DESC(nowayout
, "Watchdog cannot be stopped once started (default="
442 __MODULE_STRING(WATCHDOG_NOWAYOUT
) ")");
444 MODULE_LICENSE("GPL");
445 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
446 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
447 MODULE_VERSION(DRV_VERSION
);