drivers/watchdog/mtk_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Mediatek Watchdog Driver
   4  *
   5  * Copyright (C) 2014 Matthias Brugger
   6  *
   7  * Matthias Brugger <matthias.bgg@gmail.com>
   8  *
   9  * Based on sunxi_wdt.c
  10  */
  11
  12 #include <dt-bindings/reset-controller/mt2712-resets.h>
  13 #include <dt-bindings/reset-controller/mt8183-resets.h>
  14 #include <dt-bindings/reset-controller/mt8192-resets.h>
  15 #include <dt-bindings/reset/mt8195-resets.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/reset-controller.h>
  27 #include <linux/types.h>
  28 #include <linux/watchdog.h>
  29 #include <linux/interrupt.h>
  30
  31 #define WDT_MAX_TIMEOUT         31
  32 #define WDT_MIN_TIMEOUT         2
  33 #define WDT_LENGTH_TIMEOUT(n)   ((n) << 5)
  34
  35 #define WDT_LENGTH              0x04
  36 #define WDT_LENGTH_KEY          0x8
  37
  38 #define WDT_RST                 0x08
  39 #define WDT_RST_RELOAD          0x1971
  40
  41 #define WDT_MODE                0x00
  42 #define WDT_MODE_EN             (1 << 0)
  43 #define WDT_MODE_EXT_POL_LOW    (0 << 1)
  44 #define WDT_MODE_EXT_POL_HIGH   (1 << 1)
  45 #define WDT_MODE_EXRST_EN       (1 << 2)
  46 #define WDT_MODE_IRQ_EN         (1 << 3)
  47 #define WDT_MODE_AUTO_START     (1 << 4)
  48 #define WDT_MODE_DUAL_EN        (1 << 6)
  49 #define WDT_MODE_KEY            0x22000000
  50
  51 #define WDT_SWRST               0x14
  52 #define WDT_SWRST_KEY           0x1209
  53
  54 #define WDT_SWSYSRST            0x18U
  55 #define WDT_SWSYS_RST_KEY       0x88000000
  56
  57 #define DRV_NAME                "mtk-wdt"
  58 #define DRV_VERSION             "1.0"
  59
  60 static bool nowayout = WATCHDOG_NOWAYOUT;
  61 static unsigned int timeout;
  62
  63 struct mtk_wdt_dev {
  64         struct watchdog_device wdt_dev;
  65         void __iomem *wdt_base;
  66         spinlock_t lock; /* protects WDT_SWSYSRST reg */
  67         struct reset_controller_dev rcdev;
  68 };
  69
  70 struct mtk_wdt_data {
  71         int toprgu_sw_rst_num;
  72 };
  73
  74 static const struct mtk_wdt_data mt2712_data = {
  75         .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
  76 };
  77
  78 static const struct mtk_wdt_data mt8183_data = {
  79         .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
  80 };
  81
  82 static const struct mtk_wdt_data mt8192_data = {
  83         .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
  84 };
  85
  86 static const struct mtk_wdt_data mt8195_data = {
  87         .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
  88 };
  89
  90 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
  91                                unsigned long id, bool assert)
  92 {
  93         unsigned int tmp;
  94         unsigned long flags;
  95         struct mtk_wdt_dev *data =
  96                  container_of(rcdev, struct mtk_wdt_dev, rcdev);
  97
  98         spin_lock_irqsave(&data->lock, flags);
  99
 100         tmp = readl(data->wdt_base + WDT_SWSYSRST);
 101         if (assert)
 102                 tmp |= BIT(id);
 103         else
 104                 tmp &= ~BIT(id);
 105         tmp |= WDT_SWSYS_RST_KEY;
 106         writel(tmp, data->wdt_base + WDT_SWSYSRST);
 107
 108         spin_unlock_irqrestore(&data->lock, flags);
 109
 110         return 0;
 111 }
 112
 113 static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
 114                                unsigned long id)
 115 {
 116         return toprgu_reset_update(rcdev, id, true);
 117 }
 118
 119 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
 120                                  unsigned long id)
 121 {
 122         return toprgu_reset_update(rcdev, id, false);
 123 }
 124
 125 static int toprgu_reset(struct reset_controller_dev *rcdev,
 126                         unsigned long id)
 127 {
 128         int ret;
 129
 130         ret = toprgu_reset_assert(rcdev, id);
 131         if (ret)
 132                 return ret;
 133
 134         return toprgu_reset_deassert(rcdev, id);
 135 }
 136
 137 static const struct reset_control_ops toprgu_reset_ops = {
 138         .assert = toprgu_reset_assert,
 139         .deassert = toprgu_reset_deassert,
 140         .reset = toprgu_reset,
 141 };
 142
 143 static int toprgu_register_reset_controller(struct platform_device *pdev,
 144                                             int rst_num)
 145 {
 146         int ret;
 147         struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
 148
 149         spin_lock_init(&mtk_wdt->lock);
 150
 151         mtk_wdt->rcdev.owner = THIS_MODULE;
 152         mtk_wdt->rcdev.nr_resets = rst_num;
 153         mtk_wdt->rcdev.ops = &toprgu_reset_ops;
 154         mtk_wdt->rcdev.of_node = pdev->dev.of_node;
 155         ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
 156         if (ret != 0)
 157                 dev_err(&pdev->dev,
 158                         "couldn't register wdt reset controller: %d\n", ret);
 159         return ret;
 160 }
 161
 162 static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
 163                            unsigned long action, void *data)
 164 {
 165         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 166         void __iomem *wdt_base;
 167
 168         wdt_base = mtk_wdt->wdt_base;
 169
 170         while (1) {
 171                 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
 172                 mdelay(5);
 173         }
 174
 175         return 0;
 176 }
 177
 178 static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
 179 {
 180         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 181         void __iomem *wdt_base = mtk_wdt->wdt_base;
 182
 183         iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
 184
 185         return 0;
 186 }
 187
 188 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
 189                                 unsigned int timeout)
 190 {
 191         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 192         void __iomem *wdt_base = mtk_wdt->wdt_base;
 193         u32 reg;
 194
 195         wdt_dev->timeout = timeout;
 196         /*
 197          * In dual mode, irq will be triggered at timeout / 2
 198          * the real timeout occurs at timeout
 199          */
 200         if (wdt_dev->pretimeout)
 201                 wdt_dev->pretimeout = timeout / 2;
 202
 203         /*
 204          * One bit is the value of 512 ticks
 205          * The clock has 32 KHz
 206          */
 207         reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
 208                         | WDT_LENGTH_KEY;
 209         iowrite32(reg, wdt_base + WDT_LENGTH);
 210
 211         mtk_wdt_ping(wdt_dev);
 212
 213         return 0;
 214 }
 215
 216 static void mtk_wdt_init(struct watchdog_device *wdt_dev)
 217 {
 218         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 219         void __iomem *wdt_base;
 220
 221         wdt_base = mtk_wdt->wdt_base;
 222
 223         if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
 224                 set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
 225                 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
 226         }
 227 }
 228
 229 static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
 230 {
 231         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 232         void __iomem *wdt_base = mtk_wdt->wdt_base;
 233         u32 reg;
 234
 235         reg = readl(wdt_base + WDT_MODE);
 236         reg &= ~WDT_MODE_EN;
 237         reg |= WDT_MODE_KEY;
 238         iowrite32(reg, wdt_base + WDT_MODE);
 239
 240         return 0;
 241 }
 242
 243 static int mtk_wdt_start(struct watchdog_device *wdt_dev)
 244 {
 245         u32 reg;
 246         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 247         void __iomem *wdt_base = mtk_wdt->wdt_base;
 248         int ret;
 249
 250         ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
 251         if (ret < 0)
 252                 return ret;
 253
 254         reg = ioread32(wdt_base + WDT_MODE);
 255         if (wdt_dev->pretimeout)
 256                 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 257         else
 258                 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 259         reg |= (WDT_MODE_EN | WDT_MODE_KEY);
 260         iowrite32(reg, wdt_base + WDT_MODE);
 261
 262         return 0;
 263 }
 264
 265 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
 266                                   unsigned int timeout)
 267 {
 268         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
 269         void __iomem *wdt_base = mtk_wdt->wdt_base;
 270         u32 reg = ioread32(wdt_base + WDT_MODE);
 271
 272         if (timeout && !wdd->pretimeout) {
 273                 wdd->pretimeout = wdd->timeout / 2;
 274                 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 275         } else if (!timeout && wdd->pretimeout) {
 276                 wdd->pretimeout = 0;
 277                 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 278         } else {
 279                 return 0;
 280         }
 281
 282         reg |= WDT_MODE_KEY;
 283         iowrite32(reg, wdt_base + WDT_MODE);
 284
 285         return mtk_wdt_set_timeout(wdd, wdd->timeout);
 286 }
 287
 288 static irqreturn_t mtk_wdt_isr(int irq, void *arg)
 289 {
 290         struct watchdog_device *wdd = arg;
 291
 292         watchdog_notify_pretimeout(wdd);
 293
 294         return IRQ_HANDLED;
 295 }
 296
 297 static const struct watchdog_info mtk_wdt_info = {
 298         .identity       = DRV_NAME,
 299         .options        = WDIOF_SETTIMEOUT |
 300                           WDIOF_KEEPALIVEPING |
 301                           WDIOF_MAGICCLOSE,
 302 };
 303
 304 static const struct watchdog_info mtk_wdt_pt_info = {
 305         .identity       = DRV_NAME,
 306         .options        = WDIOF_SETTIMEOUT |
 307                           WDIOF_PRETIMEOUT |
 308                           WDIOF_KEEPALIVEPING |
 309                           WDIOF_MAGICCLOSE,
 310 };
 311
 312 static const struct watchdog_ops mtk_wdt_ops = {
 313         .owner          = THIS_MODULE,
 314         .start          = mtk_wdt_start,
 315         .stop           = mtk_wdt_stop,
 316         .ping           = mtk_wdt_ping,
 317         .set_timeout    = mtk_wdt_set_timeout,
 318         .set_pretimeout = mtk_wdt_set_pretimeout,
 319         .restart        = mtk_wdt_restart,
 320 };
 321
 322 static int mtk_wdt_probe(struct platform_device *pdev)
 323 {
 324         struct device *dev = &pdev->dev;
 325         struct mtk_wdt_dev *mtk_wdt;
 326         const struct mtk_wdt_data *wdt_data;
 327         int err, irq;
 328
 329         mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
 330         if (!mtk_wdt)
 331                 return -ENOMEM;
 332
 333         platform_set_drvdata(pdev, mtk_wdt);
 334
 335         mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
 336         if (IS_ERR(mtk_wdt->wdt_base))
 337                 return PTR_ERR(mtk_wdt->wdt_base);
 338
 339         irq = platform_get_irq(pdev, 0);
 340         if (irq > 0) {
 341                 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
 342                                        &mtk_wdt->wdt_dev);
 343                 if (err)
 344                         return err;
 345
 346                 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
 347                 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
 348         } else {
 349                 if (irq == -EPROBE_DEFER)
 350                         return -EPROBE_DEFER;
 351
 352                 mtk_wdt->wdt_dev.info = &mtk_wdt_info;
 353         }
 354
 355         mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
 356         mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
 357         mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
 358         mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
 359         mtk_wdt->wdt_dev.parent = dev;
 360
 361         watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
 362         watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
 363         watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
 364
 365         watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
 366
 367         mtk_wdt_init(&mtk_wdt->wdt_dev);
 368
 369         watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
 370         err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
 371         if (unlikely(err))
 372                 return err;
 373
 374         dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
 375                  mtk_wdt->wdt_dev.timeout, nowayout);
 376
 377         wdt_data = of_device_get_match_data(dev);
 378         if (wdt_data) {
 379                 err = toprgu_register_reset_controller(pdev,
 380                                                        wdt_data->toprgu_sw_rst_num);
 381                 if (err)
 382                         return err;
 383         }
 384         return 0;
 385 }
 386
 387 #ifdef CONFIG_PM_SLEEP
 388 static int mtk_wdt_suspend(struct device *dev)
 389 {
 390         struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
 391
 392         if (watchdog_active(&mtk_wdt->wdt_dev))
 393                 mtk_wdt_stop(&mtk_wdt->wdt_dev);
 394
 395         return 0;
 396 }
 397
 398 static int mtk_wdt_resume(struct device *dev)
 399 {
 400         struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
 401
 402         if (watchdog_active(&mtk_wdt->wdt_dev)) {
 403                 mtk_wdt_start(&mtk_wdt->wdt_dev);
 404                 mtk_wdt_ping(&mtk_wdt->wdt_dev);
 405         }
 406
 407         return 0;
 408 }
 409 #endif
 410
 411 static const struct of_device_id mtk_wdt_dt_ids[] = {
 412         { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
 413         { .compatible = "mediatek,mt6589-wdt" },
 414         { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
 415         { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
 416         { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
 417         { /* sentinel */ }
 418 };
 419 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
 420
 421 static const struct dev_pm_ops mtk_wdt_pm_ops = {
 422         SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
 423                                 mtk_wdt_resume)
 424 };
 425
 426 static struct platform_driver mtk_wdt_driver = {
 427         .probe          = mtk_wdt_probe,
 428         .driver         = {
 429                 .name           = DRV_NAME,
 430                 .pm             = &mtk_wdt_pm_ops,
 431                 .of_match_table = mtk_wdt_dt_ids,
 432         },
 433 };
 434
 435 module_platform_driver(mtk_wdt_driver);
 436
 437 module_param(timeout, uint, 0);
 438 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
 439
 440 module_param(nowayout, bool, 0);
 441 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
 442                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 443
 444 MODULE_LICENSE("GPL");
 445 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
 446 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
 447 MODULE_VERSION(DRV_VERSION);