1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
5 * (C) Copyright 2013 - 2014 Xilinx, Inc.
6 * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
10 #include <linux/err.h>
11 #include <linux/module.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/ioport.h>
15 #include <linux/watchdog.h>
18 #include <linux/of_device.h>
19 #include <linux/of_address.h>
21 /* Register offsets for the Wdt device */
22 #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */
23 #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */
24 #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */
26 /* Control/Status Register Masks */
27 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */
28 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */
29 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
31 /* Control/Status Register 0/1 bits */
32 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
34 /* SelfTest constants */
35 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
36 #define XWT_TIMER_FAILED 0xFFFFFFFF
38 #define WATCHDOG_NAME "Xilinx Watchdog"
44 struct watchdog_device xilinx_wdt_wdd
;
48 static int xilinx_wdt_start(struct watchdog_device
*wdd
)
51 u32 control_status_reg
;
52 struct xwdt_device
*xdev
= watchdog_get_drvdata(wdd
);
54 ret
= clk_enable(xdev
->clk
);
56 dev_err(wdd
->parent
, "Failed to enable clock\n");
60 spin_lock(&xdev
->spinlock
);
62 /* Clean previous status and enable the watchdog timer */
63 control_status_reg
= ioread32(xdev
->base
+ XWT_TWCSR0_OFFSET
);
64 control_status_reg
|= (XWT_CSR0_WRS_MASK
| XWT_CSR0_WDS_MASK
);
66 iowrite32((control_status_reg
| XWT_CSR0_EWDT1_MASK
),
67 xdev
->base
+ XWT_TWCSR0_OFFSET
);
69 iowrite32(XWT_CSRX_EWDT2_MASK
, xdev
->base
+ XWT_TWCSR1_OFFSET
);
71 spin_unlock(&xdev
->spinlock
);
76 static int xilinx_wdt_stop(struct watchdog_device
*wdd
)
78 u32 control_status_reg
;
79 struct xwdt_device
*xdev
= watchdog_get_drvdata(wdd
);
81 spin_lock(&xdev
->spinlock
);
83 control_status_reg
= ioread32(xdev
->base
+ XWT_TWCSR0_OFFSET
);
85 iowrite32((control_status_reg
& ~XWT_CSR0_EWDT1_MASK
),
86 xdev
->base
+ XWT_TWCSR0_OFFSET
);
88 iowrite32(0, xdev
->base
+ XWT_TWCSR1_OFFSET
);
90 spin_unlock(&xdev
->spinlock
);
92 clk_disable(xdev
->clk
);
94 pr_info("Stopped!\n");
99 static int xilinx_wdt_keepalive(struct watchdog_device
*wdd
)
101 u32 control_status_reg
;
102 struct xwdt_device
*xdev
= watchdog_get_drvdata(wdd
);
104 spin_lock(&xdev
->spinlock
);
106 control_status_reg
= ioread32(xdev
->base
+ XWT_TWCSR0_OFFSET
);
107 control_status_reg
|= (XWT_CSR0_WRS_MASK
| XWT_CSR0_WDS_MASK
);
108 iowrite32(control_status_reg
, xdev
->base
+ XWT_TWCSR0_OFFSET
);
110 spin_unlock(&xdev
->spinlock
);
115 static const struct watchdog_info xilinx_wdt_ident
= {
116 .options
= WDIOF_MAGICCLOSE
|
118 .firmware_version
= 1,
119 .identity
= WATCHDOG_NAME
,
122 static const struct watchdog_ops xilinx_wdt_ops
= {
123 .owner
= THIS_MODULE
,
124 .start
= xilinx_wdt_start
,
125 .stop
= xilinx_wdt_stop
,
126 .ping
= xilinx_wdt_keepalive
,
129 static u32
xwdt_selftest(struct xwdt_device
*xdev
)
135 spin_lock(&xdev
->spinlock
);
137 timer_value1
= ioread32(xdev
->base
+ XWT_TBR_OFFSET
);
138 timer_value2
= ioread32(xdev
->base
+ XWT_TBR_OFFSET
);
141 ((i
<= XWT_MAX_SELFTEST_LOOP_COUNT
) &&
142 (timer_value2
== timer_value1
)); i
++) {
143 timer_value2
= ioread32(xdev
->base
+ XWT_TBR_OFFSET
);
146 spin_unlock(&xdev
->spinlock
);
148 if (timer_value2
!= timer_value1
)
149 return ~XWT_TIMER_FAILED
;
151 return XWT_TIMER_FAILED
;
154 static int xwdt_probe(struct platform_device
*pdev
)
157 u32 pfreq
= 0, enable_once
= 0;
158 struct xwdt_device
*xdev
;
159 struct watchdog_device
*xilinx_wdt_wdd
;
161 xdev
= devm_kzalloc(&pdev
->dev
, sizeof(*xdev
), GFP_KERNEL
);
165 xilinx_wdt_wdd
= &xdev
->xilinx_wdt_wdd
;
166 xilinx_wdt_wdd
->info
= &xilinx_wdt_ident
;
167 xilinx_wdt_wdd
->ops
= &xilinx_wdt_ops
;
168 xilinx_wdt_wdd
->parent
= &pdev
->dev
;
170 xdev
->base
= devm_platform_ioremap_resource(pdev
, 0);
171 if (IS_ERR(xdev
->base
))
172 return PTR_ERR(xdev
->base
);
174 rc
= of_property_read_u32(pdev
->dev
.of_node
, "xlnx,wdt-interval",
175 &xdev
->wdt_interval
);
178 "Parameter \"xlnx,wdt-interval\" not found\n");
180 rc
= of_property_read_u32(pdev
->dev
.of_node
, "xlnx,wdt-enable-once",
184 "Parameter \"xlnx,wdt-enable-once\" not found\n");
186 watchdog_set_nowayout(xilinx_wdt_wdd
, enable_once
);
188 xdev
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
189 if (IS_ERR(xdev
->clk
)) {
190 if (PTR_ERR(xdev
->clk
) != -ENOENT
)
191 return PTR_ERR(xdev
->clk
);
194 * Clock framework support is optional, continue on
195 * anyways if we don't find a matching clock.
199 rc
= of_property_read_u32(pdev
->dev
.of_node
, "clock-frequency",
203 "The watchdog clock freq cannot be obtained\n");
205 pfreq
= clk_get_rate(xdev
->clk
);
209 * Twice of the 2^wdt_interval / freq because the first wdt overflow is
210 * ignored (interrupt), reset is only generated at second wdt overflow
212 if (pfreq
&& xdev
->wdt_interval
)
213 xilinx_wdt_wdd
->timeout
= 2 * ((1 << xdev
->wdt_interval
) /
216 spin_lock_init(&xdev
->spinlock
);
217 watchdog_set_drvdata(xilinx_wdt_wdd
, xdev
);
219 rc
= clk_prepare_enable(xdev
->clk
);
221 dev_err(&pdev
->dev
, "unable to enable clock\n");
225 rc
= xwdt_selftest(xdev
);
226 if (rc
== XWT_TIMER_FAILED
) {
227 dev_err(&pdev
->dev
, "SelfTest routine error\n");
228 goto err_clk_disable
;
231 rc
= watchdog_register_device(xilinx_wdt_wdd
);
233 dev_err(&pdev
->dev
, "Cannot register watchdog (err=%d)\n", rc
);
234 goto err_clk_disable
;
237 clk_disable(xdev
->clk
);
239 dev_info(&pdev
->dev
, "Xilinx Watchdog Timer at %p with timeout %ds\n",
240 xdev
->base
, xilinx_wdt_wdd
->timeout
);
242 platform_set_drvdata(pdev
, xdev
);
246 clk_disable_unprepare(xdev
->clk
);
251 static int xwdt_remove(struct platform_device
*pdev
)
253 struct xwdt_device
*xdev
= platform_get_drvdata(pdev
);
255 watchdog_unregister_device(&xdev
->xilinx_wdt_wdd
);
256 clk_disable_unprepare(xdev
->clk
);
262 * xwdt_suspend - Suspend the device.
264 * @dev: handle to the device structure.
267 static int __maybe_unused
xwdt_suspend(struct device
*dev
)
269 struct xwdt_device
*xdev
= dev_get_drvdata(dev
);
271 if (watchdog_active(&xdev
->xilinx_wdt_wdd
))
272 xilinx_wdt_stop(&xdev
->xilinx_wdt_wdd
);
278 * xwdt_resume - Resume the device.
280 * @dev: handle to the device structure.
281 * Return: 0 on success, errno otherwise.
283 static int __maybe_unused
xwdt_resume(struct device
*dev
)
285 struct xwdt_device
*xdev
= dev_get_drvdata(dev
);
288 if (watchdog_active(&xdev
->xilinx_wdt_wdd
))
289 ret
= xilinx_wdt_start(&xdev
->xilinx_wdt_wdd
);
294 static SIMPLE_DEV_PM_OPS(xwdt_pm_ops
, xwdt_suspend
, xwdt_resume
);
296 /* Match table for of_platform binding */
297 static const struct of_device_id xwdt_of_match
[] = {
298 { .compatible
= "xlnx,xps-timebase-wdt-1.00.a", },
299 { .compatible
= "xlnx,xps-timebase-wdt-1.01.a", },
302 MODULE_DEVICE_TABLE(of
, xwdt_of_match
);
304 static struct platform_driver xwdt_driver
= {
306 .remove
= xwdt_remove
,
308 .name
= WATCHDOG_NAME
,
309 .of_match_table
= xwdt_of_match
,
314 module_platform_driver(xwdt_driver
);
316 MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
317 MODULE_DESCRIPTION("Xilinx Watchdog driver");
318 MODULE_LICENSE("GPL");